1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 #ifdef CONFIG_FAULT_INJECTION 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 #else 40 # define should_fail(attr, size) 0 41 #endif 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_gem_address_space; 52 struct msm_gem_vma; 53 struct msm_disp_state; 54 55 #define MAX_CRTCS 8 56 #define MAX_BRIDGES 8 57 58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60 enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66 }; 67 68 enum msm_dsi_controller { 69 MSM_DSI_CONTROLLER_0, 70 MSM_DSI_CONTROLLER_1, 71 MSM_DSI_CONTROLLER_COUNT, 72 }; 73 74 #define MSM_GPU_MAX_RINGS 4 75 #define MAX_H_TILES_PER_DISPLAY 2 76 77 /** 78 * struct msm_display_topology - defines a display topology pipeline 79 * @num_lm: number of layer mixers used 80 * @num_intf: number of interfaces the panel is mounted on 81 * @num_dspp: number of dspp blocks used 82 * @num_dsc: number of Display Stream Compression (DSC) blocks used 83 * @needs_cdm: indicates whether cdm block is needed for this display topology 84 */ 85 struct msm_display_topology { 86 u32 num_lm; 87 u32 num_intf; 88 u32 num_dspp; 89 u32 num_dsc; 90 bool needs_cdm; 91 }; 92 93 /* Commit/Event thread specific structure */ 94 struct msm_drm_thread { 95 struct drm_device *dev; 96 struct kthread_worker *worker; 97 }; 98 99 struct msm_drm_private { 100 101 struct drm_device *dev; 102 103 struct msm_kms *kms; 104 int (*kms_init)(struct drm_device *dev); 105 106 /* subordinate devices, if present: */ 107 struct platform_device *gpu_pdev; 108 109 /* possibly this should be in the kms component, but it is 110 * shared by both mdp4 and mdp5.. 111 */ 112 struct hdmi *hdmi; 113 114 /* DSI is shared by mdp4 and mdp5 */ 115 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 116 117 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 118 119 /* when we have more than one 'msm_gpu' these need to be an array: */ 120 struct msm_gpu *gpu; 121 122 /* gpu is only set on open(), but we need this info earlier */ 123 bool is_a2xx; 124 bool has_cached_coherent; 125 126 struct msm_rd_state *rd; /* debugfs to dump all submits */ 127 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 128 struct msm_perf_state *perf; 129 130 /** 131 * total_mem: Total/global amount of memory backing GEM objects. 132 */ 133 atomic64_t total_mem; 134 135 /** 136 * List of all GEM objects (mainly for debugfs, protected by obj_lock 137 * (acquire before per GEM object lock) 138 */ 139 struct list_head objects; 140 struct mutex obj_lock; 141 142 /** 143 * lru: 144 * 145 * The various LRU's that a GEM object is in at various stages of 146 * it's lifetime. Objects start out in the unbacked LRU. When 147 * pinned (for scannout or permanently mapped GPU buffers, like 148 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 149 * unpinned, it moves into willneed or dontneed LRU depending on 150 * madvise state. When backing pages are evicted (willneed) or 151 * purged (dontneed) it moves back into the unbacked LRU. 152 * 153 * The dontneed LRU is considered by the shrinker for objects 154 * that are candidate for purging, and the willneed LRU is 155 * considered for objects that could be evicted. 156 */ 157 struct { 158 /** 159 * unbacked: 160 * 161 * The LRU for GEM objects without backing pages allocated. 162 * This mostly exists so that objects are always is one 163 * LRU. 164 */ 165 struct drm_gem_lru unbacked; 166 167 /** 168 * pinned: 169 * 170 * The LRU for pinned GEM objects 171 */ 172 struct drm_gem_lru pinned; 173 174 /** 175 * willneed: 176 * 177 * The LRU for unpinned GEM objects which are in madvise 178 * WILLNEED state (ie. can be evicted) 179 */ 180 struct drm_gem_lru willneed; 181 182 /** 183 * dontneed: 184 * 185 * The LRU for unpinned GEM objects which are in madvise 186 * DONTNEED state (ie. can be purged) 187 */ 188 struct drm_gem_lru dontneed; 189 190 /** 191 * lock: 192 * 193 * Protects manipulation of all of the LRUs. 194 */ 195 struct mutex lock; 196 } lru; 197 198 struct workqueue_struct *wq; 199 200 unsigned int num_crtcs; 201 202 struct msm_drm_thread event_thread[MAX_CRTCS]; 203 204 /* VRAM carveout, used when no IOMMU: */ 205 struct { 206 unsigned long size; 207 dma_addr_t paddr; 208 /* NOTE: mm managed at the page level, size is in # of pages 209 * and position mm_node->start is in # of pages: 210 */ 211 struct drm_mm mm; 212 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 213 } vram; 214 215 struct notifier_block vmap_notifier; 216 struct shrinker *shrinker; 217 218 /** 219 * hangcheck_period: For hang detection, in ms 220 * 221 * Note that in practice, a submit/job will get at least two hangcheck 222 * periods, due to checking for progress being implemented as simply 223 * "have the CP position registers changed since last time?" 224 */ 225 unsigned int hangcheck_period; 226 227 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 228 struct devfreq_simple_ondemand_data gpu_devfreq_config; 229 230 /** 231 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 232 */ 233 bool gpu_clamp_to_idle; 234 235 /** 236 * disable_err_irq: 237 * 238 * Disable handling of GPU hw error interrupts, to force fallback to 239 * sw hangcheck timer. Written (via debugfs) by igt tests to test 240 * the sw hangcheck mechanism. 241 */ 242 bool disable_err_irq; 243 }; 244 245 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 246 247 struct msm_pending_timer; 248 249 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 250 struct msm_kms *kms, int crtc_idx); 251 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 252 void msm_atomic_commit_tail(struct drm_atomic_state *state); 253 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 254 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 255 256 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 257 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 258 259 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 260 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 261 262 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 263 bool msm_use_mmu(struct drm_device *dev); 264 265 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 266 struct drm_file *file); 267 268 #ifdef CONFIG_DEBUG_FS 269 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 270 #endif 271 272 int msm_gem_shrinker_init(struct drm_device *dev); 273 void msm_gem_shrinker_cleanup(struct drm_device *dev); 274 275 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 276 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 277 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 278 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 279 struct dma_buf_attachment *attach, struct sg_table *sg); 280 int msm_gem_prime_pin(struct drm_gem_object *obj); 281 void msm_gem_prime_unpin(struct drm_gem_object *obj); 282 283 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 284 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 285 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 286 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 287 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 288 struct msm_gem_address_space *aspace, int plane); 289 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 290 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 291 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 292 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 293 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 294 int w, int h, int p, uint32_t format); 295 296 #ifdef CONFIG_DRM_FBDEV_EMULATION 297 void msm_fbdev_setup(struct drm_device *dev); 298 #else 299 static inline void msm_fbdev_setup(struct drm_device *dev) 300 { 301 } 302 #endif 303 304 struct hdmi; 305 #ifdef CONFIG_DRM_MSM_HDMI 306 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 307 struct drm_encoder *encoder); 308 void __init msm_hdmi_register(void); 309 void __exit msm_hdmi_unregister(void); 310 #else 311 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 312 struct drm_encoder *encoder) 313 { 314 return -EINVAL; 315 } 316 static inline void __init msm_hdmi_register(void) {} 317 static inline void __exit msm_hdmi_unregister(void) {} 318 #endif 319 320 struct msm_dsi; 321 #ifdef CONFIG_DRM_MSM_DSI 322 int dsi_dev_attach(struct platform_device *pdev); 323 void dsi_dev_detach(struct platform_device *pdev); 324 void __init msm_dsi_register(void); 325 void __exit msm_dsi_unregister(void); 326 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 327 struct drm_encoder *encoder); 328 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 329 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 330 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 331 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 332 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 333 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 334 const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); 335 #else 336 static inline void __init msm_dsi_register(void) 337 { 338 } 339 static inline void __exit msm_dsi_unregister(void) 340 { 341 } 342 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 343 struct drm_device *dev, 344 struct drm_encoder *encoder) 345 { 346 return -EINVAL; 347 } 348 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 349 { 350 } 351 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 352 { 353 return false; 354 } 355 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 356 { 357 return false; 358 } 359 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 360 { 361 return false; 362 } 363 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 364 { 365 return false; 366 } 367 368 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 369 { 370 return NULL; 371 } 372 373 static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) 374 { 375 return NULL; 376 } 377 #endif 378 379 #ifdef CONFIG_DRM_MSM_DP 380 int __init msm_dp_register(void); 381 void __exit msm_dp_unregister(void); 382 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 383 struct drm_encoder *encoder, bool yuv_supported); 384 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 385 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 386 const struct drm_display_mode *mode); 387 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 388 const struct drm_display_mode *mode); 389 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 390 391 #else 392 static inline int __init msm_dp_register(void) 393 { 394 return -EINVAL; 395 } 396 static inline void __exit msm_dp_unregister(void) 397 { 398 } 399 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 400 struct drm_device *dev, 401 struct drm_encoder *encoder, 402 bool yuv_supported) 403 { 404 return -EINVAL; 405 } 406 407 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 408 { 409 } 410 411 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 412 const struct drm_display_mode *mode) 413 { 414 return false; 415 } 416 417 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 418 const struct drm_display_mode *mode) 419 { 420 return false; 421 } 422 423 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 424 { 425 return false; 426 } 427 428 #endif 429 430 #ifdef CONFIG_DRM_MSM_MDP4 431 void msm_mdp4_register(void); 432 void msm_mdp4_unregister(void); 433 #else 434 static inline void msm_mdp4_register(void) {} 435 static inline void msm_mdp4_unregister(void) {} 436 #endif 437 438 #ifdef CONFIG_DRM_MSM_MDP5 439 void msm_mdp_register(void); 440 void msm_mdp_unregister(void); 441 #else 442 static inline void msm_mdp_register(void) {} 443 static inline void msm_mdp_unregister(void) {} 444 #endif 445 446 #ifdef CONFIG_DRM_MSM_DPU 447 void msm_dpu_register(void); 448 void msm_dpu_unregister(void); 449 #else 450 static inline void msm_dpu_register(void) {} 451 static inline void msm_dpu_unregister(void) {} 452 #endif 453 454 #ifdef CONFIG_DRM_MSM_MDSS 455 void msm_mdss_register(void); 456 void msm_mdss_unregister(void); 457 #else 458 static inline void msm_mdss_register(void) {} 459 static inline void msm_mdss_unregister(void) {} 460 #endif 461 462 #ifdef CONFIG_DEBUG_FS 463 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 464 int msm_debugfs_late_init(struct drm_device *dev); 465 int msm_rd_debugfs_init(struct drm_minor *minor); 466 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 467 __printf(3, 4) 468 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 469 const char *fmt, ...); 470 int msm_perf_debugfs_init(struct drm_minor *minor); 471 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 472 #else 473 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 474 __printf(3, 4) 475 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 476 struct msm_gem_submit *submit, 477 const char *fmt, ...) {} 478 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 479 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 480 #endif 481 482 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 483 484 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 485 const char *name); 486 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 487 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 488 phys_addr_t *size); 489 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 490 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 491 struct platform_device *dev, 492 const char *name); 493 494 struct icc_path *msm_icc_get(struct device *dev, const char *name); 495 496 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 497 { 498 u32 val = readl(addr); 499 500 val &= ~mask; 501 writel(val | or, addr); 502 } 503 504 /** 505 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 506 * 507 * @timer: hrtimer to control when the kthread work is triggered 508 * @work: the kthread work 509 * @worker: the kthread worker the work will be scheduled on 510 */ 511 struct msm_hrtimer_work { 512 struct hrtimer timer; 513 struct kthread_work work; 514 struct kthread_worker *worker; 515 }; 516 517 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 518 ktime_t wakeup_time, 519 enum hrtimer_mode mode); 520 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 521 struct kthread_worker *worker, 522 kthread_work_func_t fn, 523 clockid_t clock_id, 524 enum hrtimer_mode mode); 525 526 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 527 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 528 529 static inline int align_pitch(int width, int bpp) 530 { 531 int bytespp = (bpp + 7) / 8; 532 /* adreno needs pitch aligned to 32 pixels: */ 533 return bytespp * ALIGN(width, 32); 534 } 535 536 /* for the generated headers: */ 537 #define INVALID_IDX(idx) ({BUG(); 0;}) 538 #define fui(x) ({BUG(); 0;}) 539 #define _mesa_float_to_half(x) ({BUG(); 0;}) 540 541 542 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 543 544 /* for conditionally setting boolean flag(s): */ 545 #define COND(bool, val) ((bool) ? (val) : 0) 546 547 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 548 { 549 ktime_t now = ktime_get(); 550 s64 remaining_jiffies; 551 552 if (ktime_compare(*timeout, now) < 0) { 553 remaining_jiffies = 0; 554 } else { 555 ktime_t rem = ktime_sub(*timeout, now); 556 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 557 } 558 559 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 560 } 561 562 /* Driver helpers */ 563 564 extern const struct component_master_ops msm_drm_ops; 565 566 int msm_kms_pm_prepare(struct device *dev); 567 void msm_kms_pm_complete(struct device *dev); 568 569 int msm_drv_probe(struct device *dev, 570 int (*kms_init)(struct drm_device *dev), 571 struct msm_kms *kms); 572 void msm_kms_shutdown(struct platform_device *pdev); 573 574 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 575 576 #endif /* __MSM_DRV_H__ */ 577