1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * max77693-private.h - Voltage regulator driver for the Maxim 77693 4 * 5 * Copyright (C) 2012 Samsung Electrnoics 6 * SangYoung Son <hello.son@samsung.com> 7 * 8 * This program is not provided / owned by Maxim Integrated Products. 9 */ 10 11 #ifndef __LINUX_MFD_MAX77693_PRIV_H 12 #define __LINUX_MFD_MAX77693_PRIV_H 13 14 #include <linux/i2c.h> 15 16 #define MAX77693_REG_INVALID (0xff) 17 18 /* Slave addr = 0xCC: PMIC, Charger, Flash LED */ 19 enum max77693_pmic_reg { 20 MAX77693_LED_REG_IFLASH1 = 0x00, 21 MAX77693_LED_REG_IFLASH2 = 0x01, 22 MAX77693_LED_REG_ITORCH = 0x02, 23 MAX77693_LED_REG_ITORCHTIMER = 0x03, 24 MAX77693_LED_REG_FLASH_TIMER = 0x04, 25 MAX77693_LED_REG_FLASH_EN = 0x05, 26 MAX77693_LED_REG_MAX_FLASH1 = 0x06, 27 MAX77693_LED_REG_MAX_FLASH2 = 0x07, 28 MAX77693_LED_REG_MAX_FLASH3 = 0x08, 29 MAX77693_LED_REG_MAX_FLASH4 = 0x09, 30 MAX77693_LED_REG_VOUT_CNTL = 0x0A, 31 MAX77693_LED_REG_VOUT_FLASH1 = 0x0B, 32 MAX77693_LED_REG_VOUT_FLASH2 = 0x0C, 33 MAX77693_LED_REG_FLASH_INT = 0x0E, 34 MAX77693_LED_REG_FLASH_INT_MASK = 0x0F, 35 MAX77693_LED_REG_FLASH_STATUS = 0x10, 36 37 MAX77693_PMIC_REG_PMIC_ID1 = 0x20, 38 MAX77693_PMIC_REG_PMIC_ID2 = 0x21, 39 MAX77693_PMIC_REG_INTSRC = 0x22, 40 MAX77693_PMIC_REG_INTSRC_MASK = 0x23, 41 MAX77693_PMIC_REG_TOPSYS_INT = 0x24, 42 MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26, 43 MAX77693_PMIC_REG_TOPSYS_STAT = 0x28, 44 MAX77693_PMIC_REG_MAINCTRL1 = 0x2A, 45 MAX77693_PMIC_REG_LSCNFG = 0x2B, 46 47 MAX77693_CHG_REG_CHG_INT = 0xB0, 48 MAX77693_CHG_REG_CHG_INT_MASK = 0xB1, 49 MAX77693_CHG_REG_CHG_INT_OK = 0xB2, 50 MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3, 51 MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4, 52 MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5, 53 MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6, 54 MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7, 55 MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8, 56 MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9, 57 MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA, 58 MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB, 59 MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC, 60 MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD, 61 MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE, 62 MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF, 63 MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0, 64 MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1, 65 MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2, 66 MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3, 67 MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4, 68 MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5, 69 MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6, 70 71 MAX77693_PMIC_REG_END, 72 }; 73 74 /* MAX77693 ITORCH register */ 75 #define TORCH_IOUT1_SHIFT 0 76 #define TORCH_IOUT2_SHIFT 4 77 #define TORCH_IOUT_MASK(x) (0xf << (x)) 78 #define TORCH_IOUT_MIN 15625 79 #define TORCH_IOUT_MAX 250000 80 #define TORCH_IOUT_STEP 15625 81 82 /* MAX77693 IFLASH1 and IFLASH2 registers */ 83 #define FLASH_IOUT_MIN 15625 84 #define FLASH_IOUT_MAX_1LED 1000000 85 #define FLASH_IOUT_MAX_2LEDS 625000 86 #define FLASH_IOUT_STEP 15625 87 88 /* MAX77693 TORCH_TIMER register */ 89 #define TORCH_TMR_NO_TIMER 0x40 90 #define TORCH_TIMEOUT_MIN 262000 91 #define TORCH_TIMEOUT_MAX 15728000 92 93 /* MAX77693 FLASH_TIMER register */ 94 #define FLASH_TMR_LEVEL 0x80 95 #define FLASH_TIMEOUT_MIN 62500 96 #define FLASH_TIMEOUT_MAX 1000000 97 #define FLASH_TIMEOUT_STEP 62500 98 99 /* MAX77693 FLASH_EN register */ 100 #define FLASH_EN_OFF 0x0 101 #define FLASH_EN_FLASH 0x1 102 #define FLASH_EN_TORCH 0x2 103 #define FLASH_EN_ON 0x3 104 #define FLASH_EN_SHIFT(x) (6 - (x) * 2) 105 #define TORCH_EN_SHIFT(x) (2 - (x) * 2) 106 107 /* MAX77693 MAX_FLASH1 register */ 108 #define MAX_FLASH1_MAX_FL_EN 0x80 109 #define MAX_FLASH1_VSYS_MIN 2400 110 #define MAX_FLASH1_VSYS_MAX 3400 111 #define MAX_FLASH1_VSYS_STEP 33 112 113 /* MAX77693 VOUT_CNTL register */ 114 #define FLASH_BOOST_FIXED 0x04 115 #define FLASH_BOOST_LEDNUM_2 0x80 116 117 /* MAX77693 VOUT_FLASH1 register */ 118 #define FLASH_VOUT_MIN 3300 119 #define FLASH_VOUT_MAX 5500 120 #define FLASH_VOUT_STEP 25 121 #define FLASH_VOUT_RMIN 0x0c 122 123 /* MAX77693 FLASH_STATUS register */ 124 #define FLASH_STATUS_FLASH_ON BIT(3) 125 #define FLASH_STATUS_TORCH_ON BIT(2) 126 127 /* MAX77693 FLASH_INT register */ 128 #define FLASH_INT_FLED2_OPEN BIT(0) 129 #define FLASH_INT_FLED2_SHORT BIT(1) 130 #define FLASH_INT_FLED1_OPEN BIT(2) 131 #define FLASH_INT_FLED1_SHORT BIT(3) 132 #define FLASH_INT_OVER_CURRENT BIT(4) 133 134 /* Fast charge timer in hours */ 135 #define DEFAULT_FAST_CHARGE_TIMER 4 136 /* microamps */ 137 #define DEFAULT_TOP_OFF_THRESHOLD_CURRENT 150000 138 /* minutes */ 139 #define DEFAULT_TOP_OFF_TIMER 30 140 /* microvolts */ 141 #define DEFAULT_CONSTANT_VOLT 4200000 142 /* microvolts */ 143 #define DEFAULT_MIN_SYSTEM_VOLT 3600000 144 /* celsius */ 145 #define DEFAULT_THERMAL_REGULATION_TEMP 100 146 /* microamps */ 147 #define DEFAULT_BATTERY_OVERCURRENT 3500000 148 /* microvolts */ 149 #define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT 4300000 150 151 /* MAX77693_CHG_REG_CHG_INT_OK register */ 152 #define CHG_INT_OK_BYP_SHIFT 0 153 #define CHG_INT_OK_BAT_SHIFT 3 154 #define CHG_INT_OK_CHG_SHIFT 4 155 #define CHG_INT_OK_CHGIN_SHIFT 6 156 #define CHG_INT_OK_DETBAT_SHIFT 7 157 #define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT) 158 #define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT) 159 #define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT) 160 #define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT) 161 #define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT) 162 163 /* MAX77693_CHG_REG_CHG_DETAILS_00 register */ 164 #define CHG_DETAILS_00_CHGIN_SHIFT 5 165 #define CHG_DETAILS_00_CHGIN_MASK (0x3 << CHG_DETAILS_00_CHGIN_SHIFT) 166 167 /* MAX77693_CHG_REG_CHG_DETAILS_01 register */ 168 #define CHG_DETAILS_01_CHG_SHIFT 0 169 #define CHG_DETAILS_01_BAT_SHIFT 4 170 #define CHG_DETAILS_01_TREG_SHIFT 7 171 #define CHG_DETAILS_01_CHG_MASK (0xf << CHG_DETAILS_01_CHG_SHIFT) 172 #define CHG_DETAILS_01_BAT_MASK (0x7 << CHG_DETAILS_01_BAT_SHIFT) 173 #define CHG_DETAILS_01_TREG_MASK BIT(7) 174 175 /* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */ 176 enum max77693_charger_charging_state { 177 MAX77693_CHARGING_PREQUALIFICATION = 0x0, 178 MAX77693_CHARGING_FAST_CONST_CURRENT, 179 MAX77693_CHARGING_FAST_CONST_VOLTAGE, 180 MAX77693_CHARGING_TOP_OFF, 181 MAX77693_CHARGING_DONE, 182 MAX77693_CHARGING_HIGH_TEMP, 183 MAX77693_CHARGING_TIMER_EXPIRED, 184 MAX77693_CHARGING_THERMISTOR_SUSPEND, 185 MAX77693_CHARGING_OFF, 186 MAX77693_CHARGING_RESERVED, 187 MAX77693_CHARGING_OVER_TEMP, 188 MAX77693_CHARGING_WATCHDOG_EXPIRED, 189 }; 190 191 /* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */ 192 enum max77693_charger_battery_state { 193 MAX77693_BATTERY_NOBAT = 0x0, 194 /* Dead-battery or low-battery prequalification */ 195 MAX77693_BATTERY_PREQUALIFICATION, 196 MAX77693_BATTERY_TIMER_EXPIRED, 197 MAX77693_BATTERY_GOOD, 198 MAX77693_BATTERY_LOWVOLTAGE, 199 MAX77693_BATTERY_OVERVOLTAGE, 200 MAX77693_BATTERY_OVERCURRENT, 201 MAX77693_BATTERY_RESERVED, 202 }; 203 204 /* MAX77693_CHG_REG_CHG_DETAILS_02 register */ 205 #define CHG_DETAILS_02_BYP_SHIFT 0 206 #define CHG_DETAILS_02_BYP_MASK (0xf << CHG_DETAILS_02_BYP_SHIFT) 207 208 /* MAX77693 CHG_CNFG_00 register */ 209 #define CHG_CNFG_00_CHG_MASK 0x1 210 #define CHG_CNFG_00_BUCK_MASK 0x4 211 212 /* MAX77693_CHG_REG_CHG_CNFG_01 register */ 213 #define CHG_CNFG_01_FCHGTIME_SHIFT 0 214 #define CHG_CNFG_01_CHGRSTRT_SHIFT 4 215 #define CHG_CNFG_01_PQEN_SHIFT 7 216 #define CHG_CNFG_01_FCHGTIME_MASK (0x7 << CHG_CNFG_01_FCHGTIME_SHIFT) 217 #define CHG_CNFG_01_CHGRSTRT_MASK (0x3 << CHG_CNFG_01_CHGRSTRT_SHIFT) 218 #define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT) 219 220 /* MAX77693_CHG_REG_CHG_CNFG_02 register */ 221 #define CHG_CNFG_02_CC_SHIFT 0 222 #define CHG_CNFG_02_CC_MASK 0x3F 223 224 /* MAX77693_CHG_REG_CHG_CNFG_03 register */ 225 #define CHG_CNFG_03_TOITH_SHIFT 0 226 #define CHG_CNFG_03_TOTIME_SHIFT 3 227 #define CHG_CNFG_03_TOITH_MASK (0x7 << CHG_CNFG_03_TOITH_SHIFT) 228 #define CHG_CNFG_03_TOTIME_MASK (0x7 << CHG_CNFG_03_TOTIME_SHIFT) 229 230 /* MAX77693_CHG_REG_CHG_CNFG_04 register */ 231 #define CHG_CNFG_04_CHGCVPRM_SHIFT 0 232 #define CHG_CNFG_04_MINVSYS_SHIFT 5 233 #define CHG_CNFG_04_CHGCVPRM_MASK (0x1f << CHG_CNFG_04_CHGCVPRM_SHIFT) 234 #define CHG_CNFG_04_MINVSYS_MASK (0x7 << CHG_CNFG_04_MINVSYS_SHIFT) 235 236 /* MAX77693_CHG_REG_CHG_CNFG_06 register */ 237 #define CHG_CNFG_06_CHGPROT_SHIFT 2 238 #define CHG_CNFG_06_CHGPROT_MASK (0x3 << CHG_CNFG_06_CHGPROT_SHIFT) 239 240 /* MAX77693_CHG_REG_CHG_CNFG_07 register */ 241 #define CHG_CNFG_07_REGTEMP_SHIFT 5 242 #define CHG_CNFG_07_REGTEMP_MASK (0x3 << CHG_CNFG_07_REGTEMP_SHIFT) 243 244 /* MAX77693_CHG_REG_CHG_CNFG_12 register */ 245 #define CHG_CNFG_12_B2SOVRC_SHIFT 0 246 #define CHG_CNFG_12_VCHGINREG_SHIFT 3 247 #define CHG_CNFG_12_B2SOVRC_MASK (0x7 << CHG_CNFG_12_B2SOVRC_SHIFT) 248 #define CHG_CNFG_12_VCHGINREG_MASK (0x3 << CHG_CNFG_12_VCHGINREG_SHIFT) 249 250 /* MAX77693 CHG_CNFG_09 Register */ 251 #define CHG_CNFG_09_CHGIN_ILIM_SHIFT 0 252 #define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F 253 254 /* MAX77693 CHG_CTRL Register */ 255 #define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3 256 #define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC 257 #define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40 258 #define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80 259 260 /* Slave addr = 0x4A: MUIC */ 261 enum max77693_muic_reg { 262 MAX77693_MUIC_REG_ID = 0x00, 263 MAX77693_MUIC_REG_INT1 = 0x01, 264 MAX77693_MUIC_REG_INT2 = 0x02, 265 MAX77693_MUIC_REG_INT3 = 0x03, 266 MAX77693_MUIC_REG_STATUS1 = 0x04, 267 MAX77693_MUIC_REG_STATUS2 = 0x05, 268 MAX77693_MUIC_REG_STATUS3 = 0x06, 269 MAX77693_MUIC_REG_INTMASK1 = 0x07, 270 MAX77693_MUIC_REG_INTMASK2 = 0x08, 271 MAX77693_MUIC_REG_INTMASK3 = 0x09, 272 MAX77693_MUIC_REG_CDETCTRL1 = 0x0A, 273 MAX77693_MUIC_REG_CDETCTRL2 = 0x0B, 274 MAX77693_MUIC_REG_CTRL1 = 0x0C, 275 MAX77693_MUIC_REG_CTRL2 = 0x0D, 276 MAX77693_MUIC_REG_CTRL3 = 0x0E, 277 278 MAX77693_MUIC_REG_END, 279 }; 280 281 /* MAX77693 INTMASK1~2 Register */ 282 #define INTMASK1_ADC1K_SHIFT 3 283 #define INTMASK1_ADCERR_SHIFT 2 284 #define INTMASK1_ADCLOW_SHIFT 1 285 #define INTMASK1_ADC_SHIFT 0 286 #define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT) 287 #define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT) 288 #define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT) 289 #define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT) 290 291 #define INTMASK2_VIDRM_SHIFT 5 292 #define INTMASK2_VBVOLT_SHIFT 4 293 #define INTMASK2_DXOVP_SHIFT 3 294 #define INTMASK2_DCDTMR_SHIFT 2 295 #define INTMASK2_CHGDETRUN_SHIFT 1 296 #define INTMASK2_CHGTYP_SHIFT 0 297 #define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT) 298 #define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT) 299 #define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT) 300 #define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT) 301 #define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT) 302 #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT) 303 304 /* MAX77693 MUIC - STATUS1~3 Register */ 305 #define MAX77693_STATUS1_ADC_SHIFT 0 306 #define MAX77693_STATUS1_ADCLOW_SHIFT 5 307 #define MAX77693_STATUS1_ADCERR_SHIFT 6 308 #define MAX77693_STATUS1_ADC1K_SHIFT 7 309 #define MAX77693_STATUS1_ADC_MASK (0x1f << MAX77693_STATUS1_ADC_SHIFT) 310 #define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT) 311 #define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT) 312 #define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT) 313 314 #define MAX77693_STATUS2_CHGTYP_SHIFT 0 315 #define MAX77693_STATUS2_CHGDETRUN_SHIFT 3 316 #define MAX77693_STATUS2_DCDTMR_SHIFT 4 317 #define MAX77693_STATUS2_DXOVP_SHIFT 5 318 #define MAX77693_STATUS2_VBVOLT_SHIFT 6 319 #define MAX77693_STATUS2_VIDRM_SHIFT 7 320 #define MAX77693_STATUS2_CHGTYP_MASK (0x7 << MAX77693_STATUS2_CHGTYP_SHIFT) 321 #define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT) 322 #define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT) 323 #define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT) 324 #define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT) 325 #define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT) 326 327 #define MAX77693_STATUS3_OVP_SHIFT 2 328 #define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT) 329 330 /* MAX77693 CDETCTRL1~2 register */ 331 #define CDETCTRL1_CHGDETEN_SHIFT (0) 332 #define CDETCTRL1_CHGTYPMAN_SHIFT (1) 333 #define CDETCTRL1_DCDEN_SHIFT (2) 334 #define CDETCTRL1_DCD2SCT_SHIFT (3) 335 #define CDETCTRL1_CDDELAY_SHIFT (4) 336 #define CDETCTRL1_DCDCPL_SHIFT (5) 337 #define CDETCTRL1_CDPDET_SHIFT (7) 338 #define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT) 339 #define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT) 340 #define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT) 341 #define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT) 342 #define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT) 343 #define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT) 344 #define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT) 345 346 #define CDETCTRL2_VIDRMEN_SHIFT (1) 347 #define CDETCTRL2_DXOVPEN_SHIFT (3) 348 #define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT) 349 #define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT) 350 351 /* MAX77693 MUIC - CONTROL1~3 register */ 352 #define COMN1SW_SHIFT (0) 353 #define COMP2SW_SHIFT (3) 354 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) 355 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) 356 #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK) 357 #define MAX77693_CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \ 358 | (1 << COMN1SW_SHIFT)) 359 #define MAX77693_CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ 360 | (2 << COMN1SW_SHIFT)) 361 #define MAX77693_CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \ 362 | (3 << COMN1SW_SHIFT)) 363 #define MAX77693_CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ 364 | (0 << COMN1SW_SHIFT)) 365 366 #define MAX77693_CONTROL2_LOWPWR_SHIFT 0 367 #define MAX77693_CONTROL2_ADCEN_SHIFT 1 368 #define MAX77693_CONTROL2_CPEN_SHIFT 2 369 #define MAX77693_CONTROL2_SFOUTASRT_SHIFT 3 370 #define MAX77693_CONTROL2_SFOUTORD_SHIFT 4 371 #define MAX77693_CONTROL2_ACCDET_SHIFT 5 372 #define MAX77693_CONTROL2_USBCPINT_SHIFT 6 373 #define MAX77693_CONTROL2_RCPS_SHIFT 7 374 #define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT) 375 #define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT) 376 #define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT) 377 #define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT) 378 #define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT) 379 #define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT) 380 #define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT) 381 #define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT) 382 383 #define MAX77693_CONTROL3_JIGSET_SHIFT 0 384 #define MAX77693_CONTROL3_BTLDSET_SHIFT 2 385 #define MAX77693_CONTROL3_ADCDBSET_SHIFT 4 386 #define MAX77693_CONTROL3_JIGSET_MASK (0x3 << MAX77693_CONTROL3_JIGSET_SHIFT) 387 #define MAX77693_CONTROL3_BTLDSET_MASK (0x3 << MAX77693_CONTROL3_BTLDSET_SHIFT) 388 #define MAX77693_CONTROL3_ADCDBSET_MASK (0x3 << MAX77693_CONTROL3_ADCDBSET_SHIFT) 389 390 /* Slave addr = 0x90: Haptic */ 391 enum max77693_haptic_reg { 392 MAX77693_HAPTIC_REG_STATUS = 0x00, 393 MAX77693_HAPTIC_REG_CONFIG1 = 0x01, 394 MAX77693_HAPTIC_REG_CONFIG2 = 0x02, 395 MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03, 396 MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04, 397 MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05, 398 MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06, 399 MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07, 400 MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08, 401 MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09, 402 MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A, 403 MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B, 404 MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C, 405 MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D, 406 MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E, 407 MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F, 408 MAX77693_HAPTIC_REG_REV = 0x10, 409 410 MAX77693_HAPTIC_REG_END, 411 }; 412 413 /* max77693-pmic LSCNFG configuration register */ 414 #define MAX77693_PMIC_LOW_SYS_MASK 0x80 415 #define MAX77693_PMIC_LOW_SYS_SHIFT 7 416 417 /* max77693-haptic configuration register */ 418 #define MAX77693_CONFIG2_MODE 7 419 #define MAX77693_CONFIG2_MEN 6 420 #define MAX77693_CONFIG2_HTYP 5 421 422 enum max77693_irq_source { 423 LED_INT = 0, 424 TOPSYS_INT, 425 CHG_INT, 426 MUIC_INT1, 427 MUIC_INT2, 428 MUIC_INT3, 429 430 MAX77693_IRQ_GROUP_NR, 431 }; 432 433 #define SRC_IRQ_CHARGER BIT(0) 434 #define SRC_IRQ_TOP BIT(1) 435 #define SRC_IRQ_FLASH BIT(2) 436 #define SRC_IRQ_MUIC BIT(3) 437 #define SRC_IRQ_ALL (SRC_IRQ_CHARGER | SRC_IRQ_TOP \ 438 | SRC_IRQ_FLASH | SRC_IRQ_MUIC) 439 440 #define LED_IRQ_FLED2_OPEN BIT(0) 441 #define LED_IRQ_FLED2_SHORT BIT(1) 442 #define LED_IRQ_FLED1_OPEN BIT(2) 443 #define LED_IRQ_FLED1_SHORT BIT(3) 444 #define LED_IRQ_MAX_FLASH BIT(4) 445 446 #define TOPSYS_IRQ_T120C_INT BIT(0) 447 #define TOPSYS_IRQ_T140C_INT BIT(1) 448 #define TOPSYS_IRQ_LOWSYS_INT BIT(3) 449 450 #define CHG_IRQ_BYP_I BIT(0) 451 #define CHG_IRQ_THM_I BIT(2) 452 #define CHG_IRQ_BAT_I BIT(3) 453 #define CHG_IRQ_CHG_I BIT(4) 454 #define CHG_IRQ_CHGIN_I BIT(6) 455 456 #define MUIC_IRQ_INT1_ADC BIT(0) 457 #define MUIC_IRQ_INT1_ADC_LOW BIT(1) 458 #define MUIC_IRQ_INT1_ADC_ERR BIT(2) 459 #define MUIC_IRQ_INT1_ADC1K BIT(3) 460 461 #define MUIC_IRQ_INT2_CHGTYP BIT(0) 462 #define MUIC_IRQ_INT2_CHGDETREUN BIT(1) 463 #define MUIC_IRQ_INT2_DCDTMR BIT(2) 464 #define MUIC_IRQ_INT2_DXOVP BIT(3) 465 #define MUIC_IRQ_INT2_VBVOLT BIT(4) 466 #define MUIC_IRQ_INT2_VIDRM BIT(5) 467 468 #define MUIC_IRQ_INT3_EOC BIT(0) 469 #define MUIC_IRQ_INT3_CGMBC BIT(1) 470 #define MUIC_IRQ_INT3_OVP BIT(2) 471 #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3) 472 #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4) 473 #define MUIC_IRQ_INT3_BAT_DET BIT(5) 474 475 enum max77693_irq { 476 /* PMIC - FLASH */ 477 MAX77693_LED_IRQ_FLED2_OPEN, 478 MAX77693_LED_IRQ_FLED2_SHORT, 479 MAX77693_LED_IRQ_FLED1_OPEN, 480 MAX77693_LED_IRQ_FLED1_SHORT, 481 MAX77693_LED_IRQ_MAX_FLASH, 482 483 /* PMIC - TOPSYS */ 484 MAX77693_TOPSYS_IRQ_T120C_INT, 485 MAX77693_TOPSYS_IRQ_T140C_INT, 486 MAX77693_TOPSYS_IRQ_LOWSYS_INT, 487 488 /* PMIC - Charger */ 489 MAX77693_CHG_IRQ_BYP_I, 490 MAX77693_CHG_IRQ_THM_I, 491 MAX77693_CHG_IRQ_BAT_I, 492 MAX77693_CHG_IRQ_CHG_I, 493 MAX77693_CHG_IRQ_CHGIN_I, 494 495 MAX77693_IRQ_NR, 496 }; 497 498 enum max77693_irq_muic { 499 /* MUIC INT1 */ 500 MAX77693_MUIC_IRQ_INT1_ADC, 501 MAX77693_MUIC_IRQ_INT1_ADC_LOW, 502 MAX77693_MUIC_IRQ_INT1_ADC_ERR, 503 MAX77693_MUIC_IRQ_INT1_ADC1K, 504 505 /* MUIC INT2 */ 506 MAX77693_MUIC_IRQ_INT2_CHGTYP, 507 MAX77693_MUIC_IRQ_INT2_CHGDETREUN, 508 MAX77693_MUIC_IRQ_INT2_DCDTMR, 509 MAX77693_MUIC_IRQ_INT2_DXOVP, 510 MAX77693_MUIC_IRQ_INT2_VBVOLT, 511 MAX77693_MUIC_IRQ_INT2_VIDRM, 512 513 /* MUIC INT3 */ 514 MAX77693_MUIC_IRQ_INT3_EOC, 515 MAX77693_MUIC_IRQ_INT3_CGMBC, 516 MAX77693_MUIC_IRQ_INT3_OVP, 517 MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, 518 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, 519 MAX77693_MUIC_IRQ_INT3_BAT_DET, 520 521 MAX77693_MUIC_IRQ_NR, 522 }; 523 524 #endif /* __LINUX_MFD_MAX77693_PRIV_H */ 525