xref: /linux/include/linux/mfd/max77541.h (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef __MFD_MAX77541_H
4 #define __MFD_MAX77541_H
5 
6 #include <linux/bits.h>
7 #include <linux/types.h>
8 
9 /* REGISTERS */
10 #define MAX77541_REG_INT_SRC                    0x00
11 #define MAX77541_REG_INT_SRC_M                  0x01
12 
13 #define MAX77541_BIT_INT_SRC_TOPSYS             BIT(0)
14 #define MAX77541_BIT_INT_SRC_BUCK               BIT(1)
15 
16 #define MAX77541_REG_TOPSYS_INT                 0x02
17 #define MAX77541_REG_TOPSYS_INT_M               0x03
18 
19 #define MAX77541_BIT_TOPSYS_INT_TJ_120C         BIT(0)
20 #define MAX77541_BIT_TOPSYS_INT_TJ_140C         BIT(1)
21 #define MAX77541_BIT_TOPSYS_INT_TSHDN           BIT(2)
22 #define MAX77541_BIT_TOPSYS_INT_UVLO            BIT(3)
23 #define MAX77541_BIT_TOPSYS_INT_ALT_SWO         BIT(4)
24 #define MAX77541_BIT_TOPSYS_INT_EXT_FREQ_DET    BIT(5)
25 
26 /* REGULATORS */
27 #define MAX77541_REG_BUCK_INT                   0x20
28 #define MAX77541_REG_BUCK_INT_M                 0x21
29 
30 #define MAX77541_BIT_BUCK_INT_M1_POK_FLT        BIT(0)
31 #define MAX77541_BIT_BUCK_INT_M2_POK_FLT        BIT(1)
32 #define MAX77541_BIT_BUCK_INT_M1_SCFLT          BIT(4)
33 #define MAX77541_BIT_BUCK_INT_M2_SCFLT          BIT(5)
34 
35 #define MAX77541_REG_EN_CTRL                    0x0B
36 
37 #define MAX77541_BIT_M1_EN                      BIT(0)
38 #define MAX77541_BIT_M2_EN                      BIT(1)
39 
40 #define MAX77541_REG_M1_VOUT                    0x23
41 #define MAX77541_REG_M2_VOUT                    0x33
42 
43 #define MAX77541_BITS_MX_VOUT                   GENMASK(7, 0)
44 
45 #define MAX77541_REG_M1_CFG1                    0x25
46 #define MAX77541_REG_M2_CFG1                    0x35
47 
48 #define MAX77541_BITS_MX_CFG1_RNG               GENMASK(7, 6)
49 
50 /* ADC */
51 #define MAX77541_REG_ADC_INT                    0x70
52 #define MAX77541_REG_ADC_INT_M                  0x71
53 
54 #define MAX77541_BIT_ADC_INT_CH1_I              BIT(0)
55 #define MAX77541_BIT_ADC_INT_CH2_I              BIT(1)
56 #define MAX77541_BIT_ADC_INT_CH3_I              BIT(2)
57 #define MAX77541_BIT_ADC_INT_CH6_I              BIT(5)
58 
59 #define MAX77541_REG_ADC_DATA_CH1               0x72
60 #define MAX77541_REG_ADC_DATA_CH2               0x73
61 #define MAX77541_REG_ADC_DATA_CH3               0x74
62 #define MAX77541_REG_ADC_DATA_CH6               0x77
63 
64 /* INTERRUPT MASKS*/
65 #define MAX77541_REG_INT_SRC_MASK               0x00
66 #define MAX77541_REG_TOPSYS_INT_MASK            0x00
67 #define MAX77541_REG_BUCK_INT_MASK              0x00
68 
69 #define MAX77541_MAX_REGULATORS 2
70 
71 enum max7754x_ids {
72 	MAX77540 = 1,
73 	MAX77541,
74 };
75 
76 struct regmap;
77 struct regmap_irq_chip_data;
78 struct i2c_client;
79 
80 struct max77541 {
81 	struct i2c_client *i2c;
82 	struct regmap *regmap;
83 	enum max7754x_ids id;
84 
85 	struct regmap_irq_chip_data *irq_data;
86 	struct regmap_irq_chip_data *irq_buck;
87 	struct regmap_irq_chip_data *irq_topsys;
88 	struct regmap_irq_chip_data *irq_adc;
89 };
90 
91 #endif /* __MFD_MAX77541_H */
92