1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/slab.h>
18
19 #include <linux/regulator/consumer.h>
20
21 #define USB_PHY_UTMI_CTRL0 (0x3c)
22 #define SLEEPM BIT(0)
23
24 #define USB_PHY_UTMI_CTRL5 (0x50)
25 #define POR BIT(1)
26
27 #define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
28 #define SIDDQ_SEL BIT(1)
29 #define SIDDQ BIT(2)
30 #define FSEL GENMASK(6, 4)
31 #define FSEL_38_4_MHZ_VAL (0x6)
32
33 #define USB_PHY_HS_PHY_CTRL2 (0x64)
34 #define USB2_SUSPEND_N BIT(2)
35 #define USB2_SUSPEND_N_SEL BIT(3)
36
37 #define USB_PHY_CFG0 (0x94)
38 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
39
40 #define USB_PHY_CFG1 (0x154)
41 #define PLL_EN BIT(0)
42
43 #define USB_PHY_FSEL_SEL (0xb8)
44 #define FSEL_SEL BIT(0)
45
46 #define USB_PHY_XCFGI_39_32 (0x16c)
47 #define HSTX_PE GENMASK(3, 2)
48
49 #define USB_PHY_XCFGI_71_64 (0x17c)
50 #define HSTX_SWING GENMASK(3, 0)
51
52 #define USB_PHY_XCFGI_31_24 (0x168)
53 #define HSTX_SLEW GENMASK(2, 0)
54
55 #define USB_PHY_XCFGI_7_0 (0x15c)
56 #define PLL_LOCK_TIME GENMASK(1, 0)
57
58 #define M31_EUSB_PHY_INIT_CFG(o, b, v) \
59 { \
60 .off = o, \
61 .mask = b, \
62 .val = v, \
63 }
64
65 struct m31_phy_tbl_entry {
66 u32 off;
67 u32 mask;
68 u32 val;
69 };
70
71 struct m31_eusb2_priv_data {
72 const struct m31_phy_tbl_entry *setup_seq;
73 unsigned int setup_seq_nregs;
74 const struct m31_phy_tbl_entry *override_seq;
75 unsigned int override_seq_nregs;
76 const struct m31_phy_tbl_entry *reset_seq;
77 unsigned int reset_seq_nregs;
78 unsigned int fsel;
79 };
80
81 static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
82 M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
83 M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
84 M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
85 M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
86 };
87
88 static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = {
89 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0),
90 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7),
91 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0),
92 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, PLL_LOCK_TIME, 0),
93 };
94
95 static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = {
96 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 1),
97 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N, 1),
98 M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, SLEEPM, 1),
99 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ_SEL, 1),
100 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0),
101 M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 0),
102 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0),
103 M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0),
104 };
105
106 static const struct regulator_bulk_data m31_eusb_phy_vregs[] = {
107 { .supply = "vdd" },
108 { .supply = "vdda12" },
109 };
110
111 #define M31_EUSB_NUM_VREGS ARRAY_SIZE(m31_eusb_phy_vregs)
112
113 struct m31eusb2_phy {
114 struct phy *phy;
115 void __iomem *base;
116 const struct m31_eusb2_priv_data *data;
117 enum phy_mode mode;
118
119 struct regulator_bulk_data *vregs;
120 struct clk *clk;
121 struct reset_control *reset;
122
123 struct phy *repeater;
124 };
125
m31eusb2_phy_write_readback(void __iomem * base,u32 offset,const u32 mask,u32 val)126 static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset,
127 const u32 mask, u32 val)
128 {
129 u32 write_val;
130 u32 tmp;
131
132 tmp = readl(base + offset);
133 tmp &= ~mask;
134 write_val = tmp | val;
135
136 writel(write_val, base + offset);
137
138 tmp = readl(base + offset);
139 tmp &= mask;
140
141 if (tmp != val) {
142 pr_err("write: %x to offset: %x FAILED\n", val, offset);
143 return -EINVAL;
144 }
145
146 return 0;
147 }
148
m31eusb2_phy_write_sequence(struct m31eusb2_phy * phy,const struct m31_phy_tbl_entry * tbl,int num)149 static int m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy,
150 const struct m31_phy_tbl_entry *tbl,
151 int num)
152 {
153 int i;
154 int ret;
155
156 for (i = 0 ; i < num; i++, tbl++) {
157 dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x",
158 tbl->off, tbl->mask, tbl->val);
159
160 ret = m31eusb2_phy_write_readback(phy->base,
161 tbl->off, tbl->mask,
162 tbl->val << __ffs(tbl->mask));
163 if (ret < 0)
164 return ret;
165 }
166
167 return 0;
168 }
169
m31eusb2_phy_set_mode(struct phy * uphy,enum phy_mode mode,int submode)170 static int m31eusb2_phy_set_mode(struct phy *uphy, enum phy_mode mode, int submode)
171 {
172 struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
173
174 phy->mode = mode;
175
176 return phy_set_mode_ext(phy->repeater, mode, submode);
177 }
178
m31eusb2_phy_init(struct phy * uphy)179 static int m31eusb2_phy_init(struct phy *uphy)
180 {
181 struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
182 const struct m31_eusb2_priv_data *data = phy->data;
183 int ret;
184
185 ret = regulator_bulk_enable(M31_EUSB_NUM_VREGS, phy->vregs);
186 if (ret) {
187 dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret);
188 return ret;
189 }
190
191 ret = phy_init(phy->repeater);
192 if (ret) {
193 dev_err(&uphy->dev, "repeater init failed. %d\n", ret);
194 goto disable_vreg;
195 }
196
197 ret = clk_prepare_enable(phy->clk);
198 if (ret) {
199 dev_err(&uphy->dev, "failed to enable ref clock, %d\n", ret);
200 goto disable_repeater;
201 }
202
203 /* Perform phy reset */
204 reset_control_assert(phy->reset);
205 udelay(5);
206 reset_control_deassert(phy->reset);
207
208 m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs);
209 m31eusb2_phy_write_readback(phy->base,
210 USB_PHY_HS_PHY_CTRL_COMMON0, FSEL,
211 FIELD_PREP(FSEL, data->fsel));
212 m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_nregs);
213 m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs);
214
215 return 0;
216
217 disable_repeater:
218 phy_exit(phy->repeater);
219 disable_vreg:
220 regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
221
222 return 0;
223 }
224
m31eusb2_phy_exit(struct phy * uphy)225 static int m31eusb2_phy_exit(struct phy *uphy)
226 {
227 struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
228
229 clk_disable_unprepare(phy->clk);
230 regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
231 phy_exit(phy->repeater);
232
233 return 0;
234 }
235
236 static const struct phy_ops m31eusb2_phy_gen_ops = {
237 .init = m31eusb2_phy_init,
238 .exit = m31eusb2_phy_exit,
239 .set_mode = m31eusb2_phy_set_mode,
240 .owner = THIS_MODULE,
241 };
242
m31eusb2_phy_probe(struct platform_device * pdev)243 static int m31eusb2_phy_probe(struct platform_device *pdev)
244 {
245 struct phy_provider *phy_provider;
246 const struct m31_eusb2_priv_data *data;
247 struct device *dev = &pdev->dev;
248 struct m31eusb2_phy *phy;
249 int ret;
250
251 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
252 if (!phy)
253 return -ENOMEM;
254
255 data = device_get_match_data(dev);
256 if (!data)
257 return -EINVAL;
258 phy->data = data;
259
260 phy->base = devm_platform_ioremap_resource(pdev, 0);
261 if (IS_ERR(phy->base))
262 return PTR_ERR(phy->base);
263
264 phy->reset = devm_reset_control_get_exclusive(dev, NULL);
265 if (IS_ERR(phy->reset))
266 return PTR_ERR(phy->reset);
267
268 phy->clk = devm_clk_get(dev, NULL);
269 if (IS_ERR(phy->clk))
270 return dev_err_probe(dev, PTR_ERR(phy->clk),
271 "failed to get clk\n");
272
273 phy->phy = devm_phy_create(dev, NULL, &m31eusb2_phy_gen_ops);
274 if (IS_ERR(phy->phy))
275 return dev_err_probe(dev, PTR_ERR(phy->phy),
276 "failed to create phy\n");
277
278 ret = devm_regulator_bulk_get_const(dev, M31_EUSB_NUM_VREGS,
279 m31_eusb_phy_vregs, &phy->vregs);
280 if (ret)
281 return dev_err_probe(dev, ret,
282 "failed to get regulator supplies\n");
283
284 phy_set_drvdata(phy->phy, phy);
285
286 phy->repeater = devm_of_phy_get_by_index(dev, dev->of_node, 0);
287 if (IS_ERR(phy->repeater))
288 return dev_err_probe(dev, PTR_ERR(phy->repeater),
289 "failed to get repeater\n");
290
291 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
292
293 return PTR_ERR_OR_ZERO(phy_provider);
294 }
295
296 static const struct m31_eusb2_priv_data m31_eusb_v1_data = {
297 .setup_seq = m31_eusb2_setup_tbl,
298 .setup_seq_nregs = ARRAY_SIZE(m31_eusb2_setup_tbl),
299 .override_seq = m31_eusb_phy_override_tbl,
300 .override_seq_nregs = ARRAY_SIZE(m31_eusb_phy_override_tbl),
301 .reset_seq = m31_eusb_phy_reset_tbl,
302 .reset_seq_nregs = ARRAY_SIZE(m31_eusb_phy_reset_tbl),
303 .fsel = FSEL_38_4_MHZ_VAL,
304 };
305
306 static const struct of_device_id m31eusb2_phy_id_table[] = {
307 { .compatible = "qcom,sm8750-m31-eusb2-phy", .data = &m31_eusb_v1_data },
308 { },
309 };
310 MODULE_DEVICE_TABLE(of, m31eusb2_phy_id_table);
311
312 static struct platform_driver m31eusb2_phy_driver = {
313 .probe = m31eusb2_phy_probe,
314 .driver = {
315 .name = "qcom-m31eusb2-phy",
316 .of_match_table = m31eusb2_phy_id_table,
317 },
318 };
319
320 module_platform_driver(m31eusb2_phy_driver);
321
322 MODULE_AUTHOR("Wesley Cheng <quic_wcheng@quicinc.com>");
323 MODULE_DESCRIPTION("eUSB2 Qualcomm M31 HSPHY driver");
324 MODULE_LICENSE("GPL");
325