1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * gfx12: 26 * cpp -DASIC_FAMILY=CHIP_GFX12 cwsr_trap_handler_gfx12.asm -P -o gfx12.sp3 27 * sp3 gfx12.sp3 -hex gfx12.hex 28 */ 29 30#define CHIP_GFX12 37 31 32#define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised 33#define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) 34 35var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK = 0x4 36var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9 37var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK = 0xC00 38var SQ_WAVE_STATE_PRIV_HALT_MASK = 0x4000 39var SQ_WAVE_STATE_PRIV_POISON_ERR_MASK = 0x8000 40var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT = 15 41var SQ_WAVE_STATUS_WAVE64_SHIFT = 29 42var SQ_WAVE_STATUS_WAVE64_SIZE = 1 43var SQ_WAVE_STATUS_NO_VGPRS_SHIFT = 24 44var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK = SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK 45var S_SAVE_PC_HI_TRAP_ID_MASK = 0xF0000000 46 47var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 48var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 49var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 50var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 51var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 52var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 53var SQ_WAVE_LDS_ALLOC_GRANULARITY = 9 54 55var SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK = 0xF 56var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK = 0x10 57var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT = 5 58var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK = 0x20 59var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK = 0x40 60var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT = 6 61var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK = 0x80 62var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT = 7 63var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK = 0x100 64var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT = 8 65var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK = 0x200 66var SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK = 0x800 67var SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK = 0x80 68var SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK = 0x200 69 70var SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK= SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK |\ 71 SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK |\ 72 SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK |\ 73 SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK |\ 74 SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK |\ 75 SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK 76var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT 77var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT 78var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT 79var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT 80var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE = 32 - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT 81var BARRIER_STATE_SIGNAL_OFFSET = 16 82var BARRIER_STATE_VALID_OFFSET = 0 83 84var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 85var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 86 87// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] 88// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 89var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 90var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC 91var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 92var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 93 94var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 95var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 96 97var s_sgpr_save_num = 108 98 99var s_save_spi_init_lo = exec_lo 100var s_save_spi_init_hi = exec_hi 101var s_save_pc_lo = ttmp0 102var s_save_pc_hi = ttmp1 103var s_save_exec_lo = ttmp2 104var s_save_exec_hi = ttmp3 105var s_save_state_priv = ttmp12 106var s_save_excp_flag_priv = ttmp15 107var s_save_xnack_mask = s_save_excp_flag_priv 108var s_wave_size = ttmp7 109var s_save_buf_rsrc0 = ttmp8 110var s_save_buf_rsrc1 = ttmp9 111var s_save_buf_rsrc2 = ttmp10 112var s_save_buf_rsrc3 = ttmp11 113var s_save_mem_offset = ttmp4 114var s_save_alloc_size = s_save_excp_flag_priv 115var s_save_tmp = ttmp14 116var s_save_m0 = ttmp5 117var s_save_ttmps_lo = s_save_tmp 118var s_save_ttmps_hi = s_save_excp_flag_priv 119 120var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 121var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 122 123var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 124var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 125var S_WAVE_SIZE = 25 126 127var s_restore_spi_init_lo = exec_lo 128var s_restore_spi_init_hi = exec_hi 129var s_restore_mem_offset = ttmp12 130var s_restore_alloc_size = ttmp3 131var s_restore_tmp = ttmp2 132var s_restore_mem_offset_save = s_restore_tmp 133var s_restore_m0 = s_restore_alloc_size 134var s_restore_mode = ttmp7 135var s_restore_flat_scratch = s_restore_tmp 136var s_restore_pc_lo = ttmp0 137var s_restore_pc_hi = ttmp1 138var s_restore_exec_lo = ttmp4 139var s_restore_exec_hi = ttmp5 140var s_restore_state_priv = ttmp14 141var s_restore_excp_flag_priv = ttmp15 142var s_restore_xnack_mask = ttmp13 143var s_restore_buf_rsrc0 = ttmp8 144var s_restore_buf_rsrc1 = ttmp9 145var s_restore_buf_rsrc2 = ttmp10 146var s_restore_buf_rsrc3 = ttmp11 147var s_restore_size = ttmp6 148var s_restore_ttmps_lo = s_restore_tmp 149var s_restore_ttmps_hi = s_restore_alloc_size 150var s_restore_spi_init_hi_save = s_restore_exec_hi 151 152shader main 153 asic(DEFAULT) 154 type(CS) 155 wave_size(32) 156 157 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 158 159L_JUMP_TO_RESTORE: 160 s_branch L_RESTORE 161 162L_SKIP_RESTORE: 163 s_getreg_b32 s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV) //save STATUS since we will change SCC 164 165 // Clear SPI_PRIO: do not save with elevated priority. 166 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 167 s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK 168 169 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 170 171 s_and_b32 ttmp2, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK 172 s_cbranch_scc0 L_NOT_HALTED 173 174L_HALTED: 175 // Host trap may occur while wave is halted. 176 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK 177 s_cbranch_scc1 L_FETCH_2ND_TRAP 178 179L_CHECK_SAVE: 180 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK 181 s_cbranch_scc1 L_SAVE 182 183 // Wave is halted but neither host trap nor SAVECTX is raised. 184 // Caused by instruction fetch memory violation. 185 // Spin wait until context saved to prevent interrupt storm. 186 s_sleep 0x10 187 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 188 s_branch L_CHECK_SAVE 189 190L_NOT_HALTED: 191 // Let second-level handle non-SAVECTX exception or trap. 192 // Any concurrent SAVECTX will be handled upon re-entry once halted. 193 194 // Check non-maskable exceptions. memory_violation, illegal_instruction 195 // and xnack_error exceptions always cause the wave to enter the trap 196 // handler. 197 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK 198 s_cbranch_scc1 L_FETCH_2ND_TRAP 199 200 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 201 // Maskable exceptions only cause the wave to enter the trap handler if 202 // their respective bit in mode.excp_en is set. 203 s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) 204 s_and_b32 ttmp3, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK 205 s_cbranch_scc0 L_NOT_ADDR_WATCH 206 s_or_b32 ttmp2, ttmp2, SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK 207 208L_NOT_ADDR_WATCH: 209 s_getreg_b32 ttmp3, hwreg(HW_REG_WAVE_TRAP_CTRL) 210 s_and_b32 ttmp2, ttmp3, ttmp2 211 s_cbranch_scc1 L_FETCH_2ND_TRAP 212 213L_CHECK_TRAP_ID: 214 // Check trap_id != 0 215 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 216 s_cbranch_scc1 L_FETCH_2ND_TRAP 217 218#if SINGLE_STEP_MISSED_WORKAROUND 219 // Prioritize single step exception over context save. 220 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 221 // WAVE_TRAP_CTRL is already in ttmp3. 222 s_and_b32 ttmp3, ttmp3, SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK 223 s_cbranch_scc1 L_FETCH_2ND_TRAP 224#endif 225 226 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK 227 s_cbranch_scc1 L_SAVE 228 229L_FETCH_2ND_TRAP: 230 // Read second-level TBA/TMA from first-level TMA and jump if available. 231 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 232 // ttmp12 holds SQ_WAVE_STATUS 233 s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) 234 s_wait_idle 235 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 236 237 s_bitcmp1_b32 ttmp15, 0xF 238 s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA 239 s_or_b32 ttmp15, ttmp15, 0xFFFF0000 240L_NO_SIGN_EXTEND_TMA: 241 242 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag 243 s_wait_idle 244 s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 245 s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 246 s_or_b32 ttmp11, ttmp11, ttmp2 247 248 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 scope:SCOPE_SYS // second-level TBA 249 s_wait_idle 250 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 scope:SCOPE_SYS // second-level TMA 251 s_wait_idle 252 253 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 254 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 255 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 256 257L_NO_NEXT_TRAP: 258 // If not caused by trap then halt wave to prevent re-entry. 259 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 260 s_cbranch_scc1 L_TRAP_CASE 261 262 // Host trap will not cause trap re-entry. 263 s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 264 s_and_b32 ttmp2, ttmp2, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK 265 s_cbranch_scc1 L_EXIT_TRAP 266 s_or_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK 267 268 // If the PC points to S_ENDPGM then context save will fail if STATE_PRIV.HALT is set. 269 // Rewind the PC to prevent this from occurring. 270 s_sub_u32 ttmp0, ttmp0, 0x8 271 s_subb_u32 ttmp1, ttmp1, 0x0 272 273 s_branch L_EXIT_TRAP 274 275L_TRAP_CASE: 276 // Advance past trap instruction to prevent re-entry. 277 s_add_u32 ttmp0, ttmp0, 0x4 278 s_addc_u32 ttmp1, ttmp1, 0x0 279 280L_EXIT_TRAP: 281 s_and_b32 ttmp1, ttmp1, 0xFFFF 282 283 // Restore SQ_WAVE_STATUS. 284 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 285 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 286 287 // STATE_PRIV.BARRIER_COMPLETE may have changed since we read it. 288 // Only restore fields which the trap handler changes. 289 s_lshr_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT 290 s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \ 291 SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT - SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_state_priv 292 293 s_rfe_b64 [ttmp0, ttmp1] 294 295L_SAVE: 296 // If VGPRs have been deallocated then terminate the wavefront. 297 // It has no remaining program to run and cannot save without VGPRs. 298 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATUS) 299 s_bitcmp1_b32 s_save_tmp, SQ_WAVE_STATUS_NO_VGPRS_SHIFT 300 s_cbranch_scc0 L_HAVE_VGPRS 301 s_endpgm 302L_HAVE_VGPRS: 303 304 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 305 s_mov_b32 s_save_tmp, 0 306 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT, 1), s_save_tmp //clear saveCtx bit 307 308 /* inform SPI the readiness and wait for SPI's go signal */ 309 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 310 s_mov_b32 s_save_exec_hi, exec_hi 311 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 312 313 s_sendmsg_rtn_b64 [exec_lo, exec_hi], sendmsg(MSG_RTN_SAVE_WAVE) 314 s_wait_idle 315 316 // Save first_wave flag so we can clear high bits of save address. 317 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK 318 s_lshl_b32 s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT) 319 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 320 321 // Trap temporaries must be saved via VGPR but all VGPRs are in use. 322 // There is no ttmp space to hold the resource constant for VGPR save. 323 // Save v0 by itself since it requires only two SGPRs. 324 s_mov_b32 s_save_ttmps_lo, exec_lo 325 s_and_b32 s_save_ttmps_hi, exec_hi, 0xFFFF 326 s_mov_b32 exec_lo, 0xFFFFFFFF 327 s_mov_b32 exec_hi, 0xFFFFFFFF 328 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] scope:SCOPE_SYS 329 v_mov_b32 v0, 0x0 330 s_mov_b32 exec_lo, s_save_ttmps_lo 331 s_mov_b32 exec_hi, s_save_ttmps_hi 332 333 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 334 // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 335 get_wave_size2(s_save_ttmps_hi) 336 get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi) 337 get_svgpr_size_bytes(s_save_ttmps_hi) 338 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 339 s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, 0xFFFF 340 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, get_sgpr_size_bytes() 341 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 342 s_addc_u32 s_save_ttmps_hi, s_save_ttmps_hi, 0x0 343 344 v_writelane_b32 v0, ttmp4, 0x4 345 v_writelane_b32 v0, ttmp5, 0x5 346 v_writelane_b32 v0, ttmp6, 0x6 347 v_writelane_b32 v0, ttmp7, 0x7 348 v_writelane_b32 v0, ttmp8, 0x8 349 v_writelane_b32 v0, ttmp9, 0x9 350 v_writelane_b32 v0, ttmp10, 0xA 351 v_writelane_b32 v0, ttmp11, 0xB 352 v_writelane_b32 v0, ttmp13, 0xD 353 v_writelane_b32 v0, exec_lo, 0xE 354 v_writelane_b32 v0, exec_hi, 0xF 355 valu_sgpr_hazard() 356 357 s_mov_b32 exec_lo, 0x3FFF 358 s_mov_b32 exec_hi, 0x0 359 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] offset:0x40 scope:SCOPE_SYS 360 v_readlane_b32 ttmp14, v0, 0xE 361 v_readlane_b32 ttmp15, v0, 0xF 362 s_mov_b32 exec_lo, ttmp14 363 s_mov_b32 exec_hi, ttmp15 364 365 /* setup Resource Contants */ 366 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 367 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 368 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 369 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 370 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 371 372 s_mov_b32 s_save_m0, m0 373 374 /* global mem offset */ 375 s_mov_b32 s_save_mem_offset, 0x0 376 get_wave_size2(s_wave_size) 377 378 /* save first 4 VGPRs, needed for SGPR save */ 379 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 380 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 381 s_and_b32 m0, m0, 1 382 s_cmp_eq_u32 m0, 1 383 s_cbranch_scc1 L_ENABLE_SAVE_4VGPR_EXEC_HI 384 s_mov_b32 exec_hi, 0x00000000 385 s_branch L_SAVE_4VGPR_WAVE32 386L_ENABLE_SAVE_4VGPR_EXEC_HI: 387 s_mov_b32 exec_hi, 0xFFFFFFFF 388 s_branch L_SAVE_4VGPR_WAVE64 389L_SAVE_4VGPR_WAVE32: 390 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 391 392 // VGPR Allocated in 4-GPR granularity 393 394 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128 395 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*2 396 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3 397 s_branch L_SAVE_HWREG 398 399L_SAVE_4VGPR_WAVE64: 400 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 401 402 // VGPR Allocated in 4-GPR granularity 403 404 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256 405 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*2 406 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3 407 408 /* save HW registers */ 409 410L_SAVE_HWREG: 411 // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) 412 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 413 get_svgpr_size_bytes(s_save_tmp) 414 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 415 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 416 417 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 418 419 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource 420 v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource 421 v_mov_b32 v2, 0x0 //Set of SGPRs for TCP store 422 423 // Ensure no further changes to barrier or LDS state. 424 // STATE_PRIV.BARRIER_COMPLETE may change up to this point. 425 s_barrier_signal -2 426 s_barrier_wait -2 427 428 // Re-read final state of BARRIER_COMPLETE field for save. 429 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATE_PRIV) 430 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK 431 s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK 432 s_or_b32 s_save_state_priv, s_save_state_priv, s_save_tmp 433 434 s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 435 v_writelane_b32 v2, s_save_m0, 0x0 436 v_writelane_b32 v2, s_save_pc_lo, 0x1 437 v_writelane_b32 v2, s_save_tmp, 0x2 438 v_writelane_b32 v2, s_save_exec_lo, 0x3 439 v_writelane_b32 v2, s_save_exec_hi, 0x4 440 v_writelane_b32 v2, s_save_state_priv, 0x5 441 v_writelane_b32 v2, s_save_xnack_mask, 0x7 442 valu_sgpr_hazard() 443 444 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 445 v_writelane_b32 v2, s_save_tmp, 0x6 446 447 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_MODE) 448 v_writelane_b32 v2, s_save_tmp, 0x8 449 450 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) 451 v_writelane_b32 v2, s_save_tmp, 0x9 452 453 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) 454 v_writelane_b32 v2, s_save_tmp, 0xA 455 456 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) 457 v_writelane_b32 v2, s_save_tmp, 0xB 458 459 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_TRAP_CTRL) 460 v_writelane_b32 v2, s_save_tmp, 0xC 461 462 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATUS) 463 v_writelane_b32 v2, s_save_tmp, 0xD 464 465 s_get_barrier_state s_save_tmp, -1 466 s_wait_kmcnt (0) 467 v_writelane_b32 v2, s_save_tmp, 0xE 468 valu_sgpr_hazard() 469 470 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 471 s_mov_b32 exec_lo, 0xFFFF 472 s_mov_b32 exec_hi, 0x0 473 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 474 475 // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. 476 s_mov_b32 exec_lo, 0xFFFFFFFF 477 478 /* save SGPRs */ 479 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 480 481 // SGPR SR memory offset : size(VGPR)+size(SVGPR) 482 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 483 get_svgpr_size_bytes(s_save_tmp) 484 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 485 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 486 487 s_mov_b32 ttmp13, 0x0 //next VGPR lane to copy SGPR into 488 489 s_mov_b32 m0, 0x0 //SGPR initial index value =0 490 s_nop 0x0 //Manually inserted wait states 491L_SAVE_SGPR_LOOP: 492 // SGPR is allocated in 16 SGPR granularity 493 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 494 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 495 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 496 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 497 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 498 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 499 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 500 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 501 502 s_cmp_eq_u32 ttmp13, 0x0 503 s_cbranch_scc0 L_WRITE_V2_SECOND_HALF 504 write_16sgpr_to_v2(s0, 0x0) 505 s_branch L_SAVE_SGPR_SKIP_TCP_STORE 506L_WRITE_V2_SECOND_HALF: 507 write_16sgpr_to_v2(s0, 0x10) 508 509 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 510 s_add_u32 s_save_mem_offset, s_save_mem_offset, 0x80 511 s_mov_b32 ttmp13, 0x0 512 v_mov_b32 v2, 0x0 513L_SAVE_SGPR_SKIP_TCP_STORE: 514 515 s_add_u32 m0, m0, 16 //next sgpr index 516 s_cmp_lt_u32 m0, 96 //scc = (m0 < first 96 SGPR) ? 1 : 0 517 s_cbranch_scc1 L_SAVE_SGPR_LOOP //first 96 SGPR save is complete? 518 519 //save the rest 12 SGPR 520 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 521 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 522 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 523 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 524 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 525 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 526 write_12sgpr_to_v2(s0) 527 528 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 529 530 /* save LDS */ 531 532L_SAVE_LDS: 533 // Change EXEC to all threads... 534 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 535 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 536 s_and_b32 m0, m0, 1 537 s_cmp_eq_u32 m0, 1 538 s_cbranch_scc1 L_ENABLE_SAVE_LDS_EXEC_HI 539 s_mov_b32 exec_hi, 0x00000000 540 s_branch L_SAVE_LDS_NORMAL 541L_ENABLE_SAVE_LDS_EXEC_HI: 542 s_mov_b32 exec_hi, 0xFFFFFFFF 543L_SAVE_LDS_NORMAL: 544 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 545 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 546 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 547 548 s_and_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 549 s_cbranch_scc0 L_SAVE_LDS_DONE 550 551 // first wave do LDS save; 552 553 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY 554 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 555 556 // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) 557 // 558 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 559 get_svgpr_size_bytes(s_save_tmp) 560 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 561 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 562 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 563 564 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 565 566 //load 0~63*4(byte address) to vgpr v0 567 v_mbcnt_lo_u32_b32 v0, -1, 0 568 v_mbcnt_hi_u32_b32 v0, -1, v0 569 v_mul_u32_u24 v0, 4, v0 570 571 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 572 s_and_b32 m0, m0, 1 573 s_cmp_eq_u32 m0, 1 574 s_mov_b32 m0, 0x0 575 s_cbranch_scc1 L_SAVE_LDS_W64 576 577L_SAVE_LDS_W32: 578 s_mov_b32 s3, 128 579 s_nop 0 580 s_nop 0 581 s_nop 0 582L_SAVE_LDS_LOOP_W32: 583 ds_read_b32 v1, v0 584 s_wait_idle 585 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 586 587 s_add_u32 m0, m0, s3 //every buffer_store_lds does 128 bytes 588 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 589 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes 590 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 591 s_cbranch_scc1 L_SAVE_LDS_LOOP_W32 //LDS save is complete? 592 593 s_branch L_SAVE_LDS_DONE 594 595L_SAVE_LDS_W64: 596 s_mov_b32 s3, 256 597 s_nop 0 598 s_nop 0 599 s_nop 0 600L_SAVE_LDS_LOOP_W64: 601 ds_read_b32 v1, v0 602 s_wait_idle 603 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 604 605 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 606 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 607 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes 608 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 609 s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 //LDS save is complete? 610 611L_SAVE_LDS_DONE: 612 /* save VGPRs - set the Rest VGPRs */ 613L_SAVE_VGPR: 614 // VGPR SR memory offset: 0 615 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 616 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 617 s_and_b32 m0, m0, 1 618 s_cmp_eq_u32 m0, 1 619 s_cbranch_scc1 L_ENABLE_SAVE_VGPR_EXEC_HI 620 s_mov_b32 s_save_mem_offset, (0+128*4) // for the rest VGPRs 621 s_mov_b32 exec_hi, 0x00000000 622 s_branch L_SAVE_VGPR_NORMAL 623L_ENABLE_SAVE_VGPR_EXEC_HI: 624 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 625 s_mov_b32 exec_hi, 0xFFFFFFFF 626L_SAVE_VGPR_NORMAL: 627 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 628 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 629 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 630 //determine it is wave32 or wave64 631 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 632 s_and_b32 m0, m0, 1 633 s_cmp_eq_u32 m0, 1 634 s_cbranch_scc1 L_SAVE_VGPR_WAVE64 635 636 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 637 638 // VGPR Allocated in 4-GPR granularity 639 640 // VGPR store using dw burst 641 s_mov_b32 m0, 0x4 //VGPR initial index value =4 642 s_cmp_lt_u32 m0, s_save_alloc_size 643 s_cbranch_scc0 L_SAVE_VGPR_END 644 645L_SAVE_VGPR_W32_LOOP: 646 v_movrels_b32 v0, v0 //v0 = v[0+m0] 647 v_movrels_b32 v1, v1 //v1 = v[1+m0] 648 v_movrels_b32 v2, v2 //v2 = v[2+m0] 649 v_movrels_b32 v3, v3 //v3 = v[3+m0] 650 651 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 652 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128 653 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*2 654 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3 655 656 s_add_u32 m0, m0, 4 //next vgpr index 657 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128*4 //every buffer_store_dword does 128 bytes 658 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 659 s_cbranch_scc1 L_SAVE_VGPR_W32_LOOP //VGPR save is complete? 660 661 s_branch L_SAVE_VGPR_END 662 663L_SAVE_VGPR_WAVE64: 664 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 665 666 // VGPR store using dw burst 667 s_mov_b32 m0, 0x4 //VGPR initial index value =4 668 s_cmp_lt_u32 m0, s_save_alloc_size 669 s_cbranch_scc0 L_SAVE_SHARED_VGPR 670 671L_SAVE_VGPR_W64_LOOP: 672 v_movrels_b32 v0, v0 //v0 = v[0+m0] 673 v_movrels_b32 v1, v1 //v1 = v[1+m0] 674 v_movrels_b32 v2, v2 //v2 = v[2+m0] 675 v_movrels_b32 v3, v3 //v3 = v[3+m0] 676 677 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 678 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256 679 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*2 680 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3 681 682 s_add_u32 m0, m0, 4 //next vgpr index 683 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 684 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 685 s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? 686 687L_SAVE_SHARED_VGPR: 688 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 689 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? 690 s_cbranch_scc0 L_SAVE_VGPR_END //no shared_vgpr used? jump to L_SAVE_LDS 691 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) 692 //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. 693 //save shared_vgpr will start from the index of m0 694 s_add_u32 s_save_alloc_size, s_save_alloc_size, m0 695 s_mov_b32 exec_lo, 0xFFFFFFFF 696 s_mov_b32 exec_hi, 0x00000000 697 698L_SAVE_SHARED_VGPR_WAVE64_LOOP: 699 v_movrels_b32 v0, v0 //v0 = v[0+m0] 700 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS 701 s_add_u32 m0, m0, 1 //next vgpr index 702 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 703 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 704 s_cbranch_scc1 L_SAVE_SHARED_VGPR_WAVE64_LOOP //SHARED_VGPR save is complete? 705 706L_SAVE_VGPR_END: 707 s_branch L_END_PGM 708 709L_RESTORE: 710 /* Setup Resource Contants */ 711 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 712 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 713 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 714 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 715 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 716 717 // Save s_restore_spi_init_hi for later use. 718 s_mov_b32 s_restore_spi_init_hi_save, s_restore_spi_init_hi 719 720 //determine it is wave32 or wave64 721 get_wave_size2(s_restore_size) 722 723 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 724 s_cbranch_scc0 L_RESTORE_VGPR 725 726 /* restore LDS */ 727L_RESTORE_LDS: 728 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 729 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 730 s_and_b32 m0, m0, 1 731 s_cmp_eq_u32 m0, 1 732 s_cbranch_scc1 L_ENABLE_RESTORE_LDS_EXEC_HI 733 s_mov_b32 exec_hi, 0x00000000 734 s_branch L_RESTORE_LDS_NORMAL 735L_ENABLE_RESTORE_LDS_EXEC_HI: 736 s_mov_b32 exec_hi, 0xFFFFFFFF 737L_RESTORE_LDS_NORMAL: 738 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 739 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 740 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 741 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY 742 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 743 744 // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) 745 // 746 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 747 get_svgpr_size_bytes(s_restore_tmp) 748 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 749 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 750 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() 751 752 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 753 754 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 755 s_and_b32 m0, m0, 1 756 s_cmp_eq_u32 m0, 1 757 s_mov_b32 m0, 0x0 758 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 759 760L_RESTORE_LDS_LOOP_W32: 761 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 762 s_wait_idle 763 ds_store_addtid_b32 v0 764 s_add_u32 m0, m0, 128 // 128 DW 765 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW 766 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 767 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W32 //LDS restore is complete? 768 s_branch L_RESTORE_VGPR 769 770L_RESTORE_LDS_LOOP_W64: 771 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 772 s_wait_idle 773 ds_store_addtid_b32 v0 774 s_add_u32 m0, m0, 256 // 256 DW 775 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW 776 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 777 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 //LDS restore is complete? 778 779 /* restore VGPRs */ 780L_RESTORE_VGPR: 781 // VGPR SR memory offset : 0 782 s_mov_b32 s_restore_mem_offset, 0x0 783 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 784 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 785 s_and_b32 m0, m0, 1 786 s_cmp_eq_u32 m0, 1 787 s_cbranch_scc1 L_ENABLE_RESTORE_VGPR_EXEC_HI 788 s_mov_b32 exec_hi, 0x00000000 789 s_branch L_RESTORE_VGPR_NORMAL 790L_ENABLE_RESTORE_VGPR_EXEC_HI: 791 s_mov_b32 exec_hi, 0xFFFFFFFF 792L_RESTORE_VGPR_NORMAL: 793 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 794 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 795 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 796 //determine it is wave32 or wave64 797 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 798 s_and_b32 m0, m0, 1 799 s_cmp_eq_u32 m0, 1 800 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 801 802 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 803 804 // VGPR load using dw burst 805 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 806 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 807 s_mov_b32 m0, 4 //VGPR initial index value = 4 808 s_cmp_lt_u32 m0, s_restore_alloc_size 809 s_cbranch_scc0 L_RESTORE_SGPR 810 811L_RESTORE_VGPR_WAVE32_LOOP: 812 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS 813 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128 814 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*2 815 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*3 816 s_wait_idle 817 v_movreld_b32 v0, v0 //v[0+m0] = v0 818 v_movreld_b32 v1, v1 819 v_movreld_b32 v2, v2 820 v_movreld_b32 v3, v3 821 s_add_u32 m0, m0, 4 //next vgpr index 822 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 //every buffer_load_dword does 128 bytes 823 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 824 s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? 825 826 /* VGPR restore on v0 */ 827 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS 828 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128 829 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128*2 830 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128*3 831 s_wait_idle 832 833 s_branch L_RESTORE_SGPR 834 835L_RESTORE_VGPR_WAVE64: 836 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 837 838 // VGPR load using dw burst 839 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last 840 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 841 s_mov_b32 m0, 4 //VGPR initial index value = 4 842 s_cmp_lt_u32 m0, s_restore_alloc_size 843 s_cbranch_scc0 L_RESTORE_SHARED_VGPR 844 845L_RESTORE_VGPR_WAVE64_LOOP: 846 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS 847 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256 848 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*2 849 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*3 850 s_wait_idle 851 v_movreld_b32 v0, v0 //v[0+m0] = v0 852 v_movreld_b32 v1, v1 853 v_movreld_b32 v2, v2 854 v_movreld_b32 v3, v3 855 s_add_u32 m0, m0, 4 //next vgpr index 856 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 857 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 858 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 859 860L_RESTORE_SHARED_VGPR: 861 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size 862 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? 863 s_cbranch_scc0 L_RESTORE_V0 //no shared_vgpr used? 864 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) 865 //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. 866 //restore shared_vgpr will start from the index of m0 867 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, m0 868 s_mov_b32 exec_lo, 0xFFFFFFFF 869 s_mov_b32 exec_hi, 0x00000000 870L_RESTORE_SHARED_VGPR_WAVE64_LOOP: 871 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS 872 s_wait_idle 873 v_movreld_b32 v0, v0 //v[0+m0] = v0 874 s_add_u32 m0, m0, 1 //next vgpr index 875 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 876 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 877 s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 878 879 s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!! 880 881 /* VGPR restore on v0 */ 882L_RESTORE_V0: 883 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS 884 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256 885 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256*2 886 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256*3 887 s_wait_idle 888 889 /* restore SGPRs */ 890 //will be 2+8+16*6 891 // SGPR SR memory offset : size(VGPR)+size(SVGPR) 892L_RESTORE_SGPR: 893 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 894 get_svgpr_size_bytes(s_restore_tmp) 895 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 896 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 897 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 20*4 //s108~s127 is not saved 898 899 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 900 901 s_mov_b32 m0, s_sgpr_save_num 902 903 read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 904 s_wait_idle 905 906 s_sub_u32 m0, m0, 4 // Restore from S[0] to S[104] 907 s_nop 0 // hazard SALU M0=> S_MOVREL 908 909 s_movreld_b64 s0, s0 //s[0+m0] = s0 910 s_movreld_b64 s2, s2 911 912 read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 913 s_wait_idle 914 915 s_sub_u32 m0, m0, 8 // Restore from S[0] to S[96] 916 s_nop 0 // hazard SALU M0=> S_MOVREL 917 918 s_movreld_b64 s0, s0 //s[0+m0] = s0 919 s_movreld_b64 s2, s2 920 s_movreld_b64 s4, s4 921 s_movreld_b64 s6, s6 922 923 L_RESTORE_SGPR_LOOP: 924 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 925 s_wait_idle 926 927 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 928 s_nop 0 // hazard SALU M0=> S_MOVREL 929 930 s_movreld_b64 s0, s0 //s[0+m0] = s0 931 s_movreld_b64 s2, s2 932 s_movreld_b64 s4, s4 933 s_movreld_b64 s6, s6 934 s_movreld_b64 s8, s8 935 s_movreld_b64 s10, s10 936 s_movreld_b64 s12, s12 937 s_movreld_b64 s14, s14 938 939 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0 940 s_cbranch_scc0 L_RESTORE_SGPR_LOOP 941 942 // s_barrier with STATE_PRIV.TRAP_AFTER_INST=1, STATUS.PRIV=1 incorrectly asserts debug exception. 943 // Clear DEBUG_EN before and restore MODE after the barrier. 944 s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE), 0 945 946 /* restore HW registers */ 947L_RESTORE_HWREG: 948 // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) 949 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 950 get_svgpr_size_bytes(s_restore_tmp) 951 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 952 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 953 954 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 955 956 // Restore s_restore_spi_init_hi before the saved value gets clobbered. 957 s_mov_b32 s_restore_spi_init_hi, s_restore_spi_init_hi_save 958 959 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) 960 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) 961 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 962 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) 963 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 964 read_hwreg_from_mem(s_restore_state_priv, s_restore_buf_rsrc0, s_restore_mem_offset) 965 read_hwreg_from_mem(s_restore_excp_flag_priv, s_restore_buf_rsrc0, s_restore_mem_offset) 966 read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset) 967 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) 968 read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) 969 s_wait_idle 970 971 s_setreg_b32 hwreg(HW_REG_WAVE_SCRATCH_BASE_LO), s_restore_flat_scratch 972 973 read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) 974 s_wait_idle 975 976 s_setreg_b32 hwreg(HW_REG_WAVE_SCRATCH_BASE_HI), s_restore_flat_scratch 977 978 read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset) 979 s_wait_idle 980 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_USER), s_restore_tmp 981 982 read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset) 983 s_wait_idle 984 s_setreg_b32 hwreg(HW_REG_WAVE_TRAP_CTRL), s_restore_tmp 985 986 // Only the first wave needs to restore the workgroup barrier. 987 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 988 s_cbranch_scc0 L_SKIP_BARRIER_RESTORE 989 990 // Skip over WAVE_STATUS, since there is no state to restore from it 991 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 4 992 993 read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset) 994 s_wait_idle 995 996 s_bitcmp1_b32 s_restore_tmp, BARRIER_STATE_VALID_OFFSET 997 s_cbranch_scc0 L_SKIP_BARRIER_RESTORE 998 999 // extract the saved signal count from s_restore_tmp 1000 s_lshr_b32 s_restore_tmp, s_restore_tmp, BARRIER_STATE_SIGNAL_OFFSET 1001 1002 // We need to call s_barrier_signal repeatedly to restore the signal 1003 // count of the work group barrier. The member count is already 1004 // initialized with the number of waves in the work group. 1005L_BARRIER_RESTORE_LOOP: 1006 s_and_b32 s_restore_tmp, s_restore_tmp, s_restore_tmp 1007 s_cbranch_scc0 L_SKIP_BARRIER_RESTORE 1008 s_barrier_signal -1 1009 s_add_i32 s_restore_tmp, s_restore_tmp, -1 1010 s_branch L_BARRIER_RESTORE_LOOP 1011 1012L_SKIP_BARRIER_RESTORE: 1013 1014 s_mov_b32 m0, s_restore_m0 1015 s_mov_b32 exec_lo, s_restore_exec_lo 1016 s_mov_b32 exec_hi, s_restore_exec_hi 1017 1018 // EXCP_FLAG_PRIV.SAVE_CONTEXT and HOST_TRAP may have changed. 1019 // Only restore the other fields to avoid clobbering them. 1020 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, 0, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE), s_restore_excp_flag_priv 1021 s_lshr_b32 s_restore_excp_flag_priv, s_restore_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT 1022 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE), s_restore_excp_flag_priv 1023 s_lshr_b32 s_restore_excp_flag_priv, s_restore_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT 1024 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE), s_restore_excp_flag_priv 1025 1026 s_setreg_b32 hwreg(HW_REG_WAVE_MODE), s_restore_mode 1027 1028 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1029 // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 1030 get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size) 1031 get_svgpr_size_bytes(s_restore_ttmps_hi) 1032 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1033 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, get_sgpr_size_bytes() 1034 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1035 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1036 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1037 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 scope:SCOPE_SYS 1038 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 scope:SCOPE_SYS 1039 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 scope:SCOPE_SYS 1040 s_wait_idle 1041 1042 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1043 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1044 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1045 1046 s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV), s_restore_state_priv // SCC is included, which is changed by previous salu 1047 1048 // Make barrier and LDS state visible to all waves in the group. 1049 // STATE_PRIV.BARRIER_COMPLETE may change after this point. 1050 s_barrier_signal -2 1051 s_barrier_wait -2 1052 1053 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1054 1055L_END_PGM: 1056 // Make sure that no wave of the workgroup can exit the trap handler 1057 // before the workgroup barrier state is saved. 1058 s_barrier_signal -2 1059 s_barrier_wait -2 1060 s_endpgm_saved 1061end 1062 1063function write_16sgpr_to_v2(s, lane_offset) 1064 // Copy into VGPR for later TCP store. 1065 for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++ 1066 v_writelane_b32 v2, s[sgpr_idx], sgpr_idx + lane_offset 1067 end 1068 valu_sgpr_hazard() 1069 s_add_u32 ttmp13, ttmp13, 0x10 1070end 1071 1072function write_12sgpr_to_v2(s) 1073 // Copy into VGPR for later TCP store. 1074 for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++ 1075 v_writelane_b32 v2, s[sgpr_idx], sgpr_idx 1076 end 1077 valu_sgpr_hazard() 1078end 1079 1080function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1081 s_buffer_load_dword s, s_rsrc, s_mem_offset scope:SCOPE_SYS 1082 s_add_u32 s_mem_offset, s_mem_offset, 4 1083end 1084 1085function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1086 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1087 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset scope:SCOPE_SYS 1088end 1089 1090function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset) 1091 s_sub_u32 s_mem_offset, s_mem_offset, 4*8 1092 s_buffer_load_dwordx8 s, s_rsrc, s_mem_offset scope:SCOPE_SYS 1093end 1094 1095function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset) 1096 s_sub_u32 s_mem_offset, s_mem_offset, 4*4 1097 s_buffer_load_dwordx4 s, s_rsrc, s_mem_offset scope:SCOPE_SYS 1098end 1099 1100function get_vgpr_size_bytes(s_vgpr_size_byte, s_size) 1101 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1102 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1103 s_bitcmp1_b32 s_size, S_WAVE_SIZE 1104 s_cbranch_scc1 L_ENABLE_SHIFT_W64 1105 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+7) //Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4 (non-zero value) 1106 s_branch L_SHIFT_DONE 1107L_ENABLE_SHIFT_W64: 1108 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) 1109L_SHIFT_DONE: 1110end 1111 1112function get_svgpr_size_bytes(s_svgpr_size_byte) 1113 s_getreg_b32 s_svgpr_size_byte, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 1114 s_lshl_b32 s_svgpr_size_byte, s_svgpr_size_byte, (3+7) 1115end 1116 1117function get_sgpr_size_bytes 1118 return 512 1119end 1120 1121function get_hwreg_size_bytes 1122 return 128 1123end 1124 1125function get_wave_size2(s_reg) 1126 s_getreg_b32 s_reg, hwreg(HW_REG_WAVE_STATUS,SQ_WAVE_STATUS_WAVE64_SHIFT,SQ_WAVE_STATUS_WAVE64_SIZE) 1127 s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE 1128end 1129 1130function valu_sgpr_hazard 1131#if HAVE_VALU_SGPR_HAZARD 1132 for var rep = 0; rep < 8; rep ++ 1133 ds_nop 1134 end 1135#endif 1136end 1137