1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * nct7904.c - driver for Nuvoton NCT7904D. 4 * 5 * Copyright (c) 2015 Kontron 6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru> 7 * 8 * Copyright (c) 2019 Advantech 9 * Author: Amy.Shih <amy.shih@advantech.com.tw> 10 * 11 * Copyright (c) 2020 Advantech 12 * Author: Yuechao Zhao <yuechao.zhao@advantech.com.cn> 13 * 14 * Supports the following chips: 15 * 16 * Chip #vin #fan #pwm #temp #dts chip ID 17 * nct7904d 20 12 4 5 8 0xc5 18 */ 19 20 #include <linux/module.h> 21 #include <linux/device.h> 22 #include <linux/init.h> 23 #include <linux/i2c.h> 24 #include <linux/hwmon.h> 25 #include <linux/watchdog.h> 26 27 #define VENDOR_ID_REG 0x7A /* Any bank */ 28 #define NUVOTON_ID 0x50 29 #define CHIP_ID_REG 0x7B /* Any bank */ 30 #define NCT7904_ID 0xC5 31 #define DEVICE_ID_REG 0x7C /* Any bank */ 32 33 #define BANK_SEL_REG 0xFF 34 #define BANK_0 0x00 35 #define BANK_1 0x01 36 #define BANK_2 0x02 37 #define BANK_3 0x03 38 #define BANK_4 0x04 39 #define BANK_MAX 0x04 40 41 #define FANIN_MAX 12 /* Counted from 1 */ 42 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB, 43 LTD (not a voltage), VSEN17..19 */ 44 #define FANCTL_MAX 4 /* Counted from 1 */ 45 #define TCPU_MAX 8 /* Counted from 1 */ 46 #define TEMP_MAX 4 /* Counted from 1 */ 47 #define SMI_STS_MAX 10 /* Counted from 1 */ 48 49 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */ 50 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */ 51 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */ 52 #define FANIN_CTRL0_REG 0x24 53 #define FANIN_CTRL1_REG 0x25 54 #define DTS_T_CTRL0_REG 0x26 55 #define DTS_T_CTRL1_REG 0x27 56 #define VT_ADC_MD_REG 0x2E 57 58 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */ 59 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */ 60 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */ 61 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */ 62 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */ 63 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */ 64 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */ 65 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */ 66 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */ 67 68 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */ 69 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */ 70 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */ 71 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */ 72 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */ 73 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */ 74 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */ 75 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */ 76 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */ 77 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */ 78 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */ 79 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */ 80 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */ 81 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */ 82 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */ 83 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */ 84 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */ 85 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */ 86 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */ 87 88 #define PRTS_REG 0x03 /* Bank 2 */ 89 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */ 90 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */ 91 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */ 92 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */ 93 94 #define WDT_LOCK_REG 0xE0 /* W/O Lock Watchdog Register */ 95 #define WDT_EN_REG 0xE1 /* R/O Watchdog Enable Register */ 96 #define WDT_STS_REG 0xE2 /* R/O Watchdog Status Register */ 97 #define WDT_TIMER_REG 0xE3 /* R/W Watchdog Timer Register */ 98 #define WDT_SOFT_EN 0x55 /* Enable soft watchdog timer */ 99 #define WDT_SOFT_DIS 0xAA /* Disable soft watchdog timer */ 100 101 #define VOLT_MONITOR_MODE 0x0 102 #define THERMAL_DIODE_MODE 0x1 103 #define THERMISTOR_MODE 0x3 104 105 #define ENABLE_TSI BIT(1) 106 107 #define WATCHDOG_TIMEOUT 1 /* 1 minute default timeout */ 108 109 /*The timeout range is 1-255 minutes*/ 110 #define MIN_TIMEOUT (1 * 60) 111 #define MAX_TIMEOUT (255 * 60) 112 113 static int timeout; 114 module_param(timeout, int, 0); 115 MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes. 1 <= timeout <= 255, default=" 116 __MODULE_STRING(WATCHDOG_TIMEOUT) "."); 117 118 static bool nowayout = WATCHDOG_NOWAYOUT; 119 module_param(nowayout, bool, 0); 120 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 121 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 122 123 static const unsigned short normal_i2c[] = { 124 0x2d, 0x2e, I2C_CLIENT_END 125 }; 126 127 struct nct7904_data { 128 struct i2c_client *client; 129 struct watchdog_device wdt; 130 int bank_sel; 131 u32 fanin_mask; 132 u32 vsen_mask; 133 u32 tcpu_mask; 134 u8 fan_mode[FANCTL_MAX]; 135 u8 enable_dts; 136 u8 has_dts; 137 u8 temp_mode; /* 0: TR mode, 1: TD mode */ 138 u8 fan_alarm[2]; 139 u8 vsen_alarm[3]; 140 }; 141 142 /* Access functions */ 143 static int nct7904_bank_select(struct nct7904_data *data, unsigned int bank) 144 { 145 int ret; 146 147 if (data->bank_sel == bank) 148 return 0; 149 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank); 150 if (ret < 0) { 151 data->bank_sel = -1; 152 return ret; 153 } 154 data->bank_sel = bank; 155 return 0; 156 } 157 158 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */ 159 static int nct7904_read_reg(struct nct7904_data *data, 160 unsigned int bank, unsigned int reg) 161 { 162 struct i2c_client *client = data->client; 163 int ret; 164 165 ret = nct7904_bank_select(data, bank); 166 if (ret < 0) 167 return ret; 168 return i2c_smbus_read_byte_data(client, reg); 169 } 170 171 /* 172 * Read 2-byte register. Returns register in big-endian format or 173 * -ERRNO on error. 174 */ 175 static int nct7904_read_reg16(struct nct7904_data *data, 176 unsigned int bank, unsigned int reg) 177 { 178 struct i2c_client *client = data->client; 179 int ret, hi; 180 181 ret = nct7904_bank_select(data, bank); 182 if (ret < 0) 183 return ret; 184 hi = i2c_smbus_read_byte_data(client, reg); 185 if (hi < 0) 186 return hi; 187 ret = i2c_smbus_read_byte_data(client, reg + 1); 188 if (ret < 0) 189 return ret; 190 return ret | (hi << 8); 191 } 192 193 /* Write 1-byte register. Returns 0 or -ERRNO on error. */ 194 static int nct7904_write_reg(struct nct7904_data *data, 195 unsigned int bank, unsigned int reg, u8 val) 196 { 197 struct i2c_client *client = data->client; 198 int ret; 199 200 ret = nct7904_bank_select(data, bank); 201 if (ret < 0) 202 return ret; 203 return i2c_smbus_write_byte_data(client, reg, val); 204 } 205 206 static int nct7904_read_fan(struct device *dev, u32 attr, int channel, 207 long *val) 208 { 209 struct nct7904_data *data = dev_get_drvdata(dev); 210 unsigned int cnt, rpm; 211 int ret; 212 213 switch (attr) { 214 case hwmon_fan_input: 215 ret = nct7904_read_reg16(data, BANK_0, 216 FANIN1_HV_REG + channel * 2); 217 if (ret < 0) 218 return ret; 219 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 220 if (cnt == 0 || cnt == 0x1fff) 221 rpm = 0; 222 else 223 rpm = 1350000 / cnt; 224 *val = rpm; 225 return 0; 226 case hwmon_fan_min: 227 ret = nct7904_read_reg16(data, BANK_1, 228 FANIN1_HV_HL_REG + channel * 2); 229 if (ret < 0) 230 return ret; 231 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 232 if (cnt == 0 || cnt == 0x1fff) 233 rpm = 0; 234 else 235 rpm = 1350000 / cnt; 236 *val = rpm; 237 return 0; 238 case hwmon_fan_alarm: 239 ret = nct7904_read_reg(data, BANK_0, 240 SMI_STS5_REG + (channel >> 3)); 241 if (ret < 0) 242 return ret; 243 if (!data->fan_alarm[channel >> 3]) 244 data->fan_alarm[channel >> 3] = ret & 0xff; 245 else 246 /* If there is new alarm showing up */ 247 data->fan_alarm[channel >> 3] |= (ret & 0xff); 248 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1; 249 /* Needs to clean the alarm if alarm existing */ 250 if (*val) 251 data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07); 252 return 0; 253 default: 254 return -EOPNOTSUPP; 255 } 256 } 257 258 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel) 259 { 260 const struct nct7904_data *data = _data; 261 262 switch (attr) { 263 case hwmon_fan_input: 264 case hwmon_fan_alarm: 265 if (data->fanin_mask & (1 << channel)) 266 return 0444; 267 break; 268 case hwmon_fan_min: 269 if (data->fanin_mask & (1 << channel)) 270 return 0644; 271 break; 272 default: 273 break; 274 } 275 276 return 0; 277 } 278 279 static u8 nct7904_chan_to_index[] = { 280 0, /* Not used */ 281 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 282 18, 19, 20, 16 283 }; 284 285 static int nct7904_read_in(struct device *dev, u32 attr, int channel, 286 long *val) 287 { 288 struct nct7904_data *data = dev_get_drvdata(dev); 289 int ret, volt, index; 290 291 index = nct7904_chan_to_index[channel]; 292 293 switch (attr) { 294 case hwmon_in_input: 295 ret = nct7904_read_reg16(data, BANK_0, 296 VSEN1_HV_REG + index * 2); 297 if (ret < 0) 298 return ret; 299 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 300 if (index < 14) 301 volt *= 2; /* 0.002V scale */ 302 else 303 volt *= 6; /* 0.006V scale */ 304 *val = volt; 305 return 0; 306 case hwmon_in_min: 307 ret = nct7904_read_reg16(data, BANK_1, 308 VSEN1_HV_LL_REG + index * 4); 309 if (ret < 0) 310 return ret; 311 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 312 if (index < 14) 313 volt *= 2; /* 0.002V scale */ 314 else 315 volt *= 6; /* 0.006V scale */ 316 *val = volt; 317 return 0; 318 case hwmon_in_max: 319 ret = nct7904_read_reg16(data, BANK_1, 320 VSEN1_HV_HL_REG + index * 4); 321 if (ret < 0) 322 return ret; 323 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 324 if (index < 14) 325 volt *= 2; /* 0.002V scale */ 326 else 327 volt *= 6; /* 0.006V scale */ 328 *val = volt; 329 return 0; 330 case hwmon_in_alarm: 331 ret = nct7904_read_reg(data, BANK_0, 332 SMI_STS1_REG + (index >> 3)); 333 if (ret < 0) 334 return ret; 335 if (!data->vsen_alarm[index >> 3]) 336 data->vsen_alarm[index >> 3] = ret & 0xff; 337 else 338 /* If there is new alarm showing up */ 339 data->vsen_alarm[index >> 3] |= (ret & 0xff); 340 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1; 341 /* Needs to clean the alarm if alarm existing */ 342 if (*val) 343 data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07); 344 return 0; 345 default: 346 return -EOPNOTSUPP; 347 } 348 } 349 350 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel) 351 { 352 const struct nct7904_data *data = _data; 353 int index = nct7904_chan_to_index[channel]; 354 355 switch (attr) { 356 case hwmon_in_input: 357 case hwmon_in_alarm: 358 if (channel > 0 && (data->vsen_mask & BIT(index))) 359 return 0444; 360 break; 361 case hwmon_in_min: 362 case hwmon_in_max: 363 if (channel > 0 && (data->vsen_mask & BIT(index))) 364 return 0644; 365 break; 366 default: 367 break; 368 } 369 370 return 0; 371 } 372 373 static int nct7904_read_temp(struct device *dev, u32 attr, int channel, 374 long *val) 375 { 376 struct nct7904_data *data = dev_get_drvdata(dev); 377 int ret, temp; 378 unsigned int reg1, reg2, reg3; 379 s8 temps; 380 381 switch (attr) { 382 case hwmon_temp_input: 383 if (channel == 4) 384 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG); 385 else if (channel < 5) 386 ret = nct7904_read_reg16(data, BANK_0, 387 TEMP_CH1_HV_REG + channel * 4); 388 else 389 ret = nct7904_read_reg16(data, BANK_0, 390 T_CPU1_HV_REG + (channel - 5) 391 * 2); 392 if (ret < 0) 393 return ret; 394 temp = ((ret & 0xff00) >> 5) | (ret & 0x7); 395 *val = sign_extend32(temp, 10) * 125; 396 return 0; 397 case hwmon_temp_alarm: 398 if (channel == 4) { 399 ret = nct7904_read_reg(data, BANK_0, 400 SMI_STS3_REG); 401 if (ret < 0) 402 return ret; 403 *val = (ret >> 1) & 1; 404 } else if (channel < 4) { 405 ret = nct7904_read_reg(data, BANK_0, 406 SMI_STS1_REG); 407 if (ret < 0) 408 return ret; 409 *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1; 410 } else { 411 if ((channel - 5) < 4) { 412 ret = nct7904_read_reg(data, BANK_0, 413 SMI_STS7_REG + 414 ((channel - 5) >> 3)); 415 if (ret < 0) 416 return ret; 417 *val = (ret >> ((channel - 5) & 0x07)) & 1; 418 } else { 419 ret = nct7904_read_reg(data, BANK_0, 420 SMI_STS8_REG + 421 ((channel - 5) >> 3)); 422 if (ret < 0) 423 return ret; 424 *val = (ret >> (((channel - 5) & 0x07) - 4)) 425 & 1; 426 } 427 } 428 return 0; 429 case hwmon_temp_type: 430 if (channel < 5) { 431 if ((data->tcpu_mask >> channel) & 0x01) { 432 if ((data->temp_mode >> channel) & 0x01) 433 *val = 3; /* TD */ 434 else 435 *val = 4; /* TR */ 436 } else { 437 *val = 0; 438 } 439 } else { 440 if ((data->has_dts >> (channel - 5)) & 0x01) { 441 if (data->enable_dts & ENABLE_TSI) 442 *val = 5; /* TSI */ 443 else 444 *val = 6; /* PECI */ 445 } else { 446 *val = 0; 447 } 448 } 449 return 0; 450 case hwmon_temp_max: 451 reg1 = LTD_HV_LL_REG; 452 reg2 = TEMP_CH1_W_REG; 453 reg3 = DTS_T_CPU1_W_REG; 454 break; 455 case hwmon_temp_max_hyst: 456 reg1 = LTD_LV_LL_REG; 457 reg2 = TEMP_CH1_WH_REG; 458 reg3 = DTS_T_CPU1_WH_REG; 459 break; 460 case hwmon_temp_crit: 461 reg1 = LTD_HV_HL_REG; 462 reg2 = TEMP_CH1_C_REG; 463 reg3 = DTS_T_CPU1_C_REG; 464 break; 465 case hwmon_temp_crit_hyst: 466 reg1 = LTD_LV_HL_REG; 467 reg2 = TEMP_CH1_CH_REG; 468 reg3 = DTS_T_CPU1_CH_REG; 469 break; 470 default: 471 return -EOPNOTSUPP; 472 } 473 474 if (channel == 4) 475 ret = nct7904_read_reg(data, BANK_1, reg1); 476 else if (channel < 5) 477 ret = nct7904_read_reg(data, BANK_1, 478 reg2 + channel * 8); 479 else 480 ret = nct7904_read_reg(data, BANK_1, 481 reg3 + (channel - 5) * 4); 482 483 if (ret < 0) 484 return ret; 485 temps = ret; 486 *val = temps * 1000; 487 return 0; 488 } 489 490 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel) 491 { 492 const struct nct7904_data *data = _data; 493 494 switch (attr) { 495 case hwmon_temp_input: 496 case hwmon_temp_alarm: 497 case hwmon_temp_type: 498 if (channel < 5) { 499 if (data->tcpu_mask & BIT(channel)) 500 return 0444; 501 } else { 502 if (data->has_dts & BIT(channel - 5)) 503 return 0444; 504 } 505 break; 506 case hwmon_temp_max: 507 case hwmon_temp_max_hyst: 508 case hwmon_temp_crit: 509 case hwmon_temp_crit_hyst: 510 if (channel < 5) { 511 if (data->tcpu_mask & BIT(channel)) 512 return 0644; 513 } else { 514 if (data->has_dts & BIT(channel - 5)) 515 return 0644; 516 } 517 break; 518 default: 519 break; 520 } 521 522 return 0; 523 } 524 525 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel, 526 long *val) 527 { 528 struct nct7904_data *data = dev_get_drvdata(dev); 529 int ret; 530 531 switch (attr) { 532 case hwmon_pwm_input: 533 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel); 534 if (ret < 0) 535 return ret; 536 *val = ret; 537 return 0; 538 case hwmon_pwm_enable: 539 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel); 540 if (ret < 0) 541 return ret; 542 543 *val = ret ? 2 : 1; 544 return 0; 545 default: 546 return -EOPNOTSUPP; 547 } 548 } 549 550 static int nct7904_write_temp(struct device *dev, u32 attr, int channel, 551 long val) 552 { 553 struct nct7904_data *data = dev_get_drvdata(dev); 554 int ret; 555 unsigned int reg1, reg2, reg3; 556 557 val = clamp_val(val / 1000, -128, 127); 558 559 switch (attr) { 560 case hwmon_temp_max: 561 reg1 = LTD_HV_LL_REG; 562 reg2 = TEMP_CH1_W_REG; 563 reg3 = DTS_T_CPU1_W_REG; 564 break; 565 case hwmon_temp_max_hyst: 566 reg1 = LTD_LV_LL_REG; 567 reg2 = TEMP_CH1_WH_REG; 568 reg3 = DTS_T_CPU1_WH_REG; 569 break; 570 case hwmon_temp_crit: 571 reg1 = LTD_HV_HL_REG; 572 reg2 = TEMP_CH1_C_REG; 573 reg3 = DTS_T_CPU1_C_REG; 574 break; 575 case hwmon_temp_crit_hyst: 576 reg1 = LTD_LV_HL_REG; 577 reg2 = TEMP_CH1_CH_REG; 578 reg3 = DTS_T_CPU1_CH_REG; 579 break; 580 default: 581 return -EOPNOTSUPP; 582 } 583 if (channel == 4) 584 ret = nct7904_write_reg(data, BANK_1, reg1, val); 585 else if (channel < 5) 586 ret = nct7904_write_reg(data, BANK_1, 587 reg2 + channel * 8, val); 588 else 589 ret = nct7904_write_reg(data, BANK_1, 590 reg3 + (channel - 5) * 4, val); 591 592 return ret; 593 } 594 595 static int nct7904_write_fan(struct device *dev, u32 attr, int channel, 596 long val) 597 { 598 struct nct7904_data *data = dev_get_drvdata(dev); 599 int ret; 600 u8 tmp; 601 602 switch (attr) { 603 case hwmon_fan_min: 604 if (val <= 0) 605 return -EINVAL; 606 607 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff); 608 tmp = (val >> 5) & 0xff; 609 ret = nct7904_write_reg(data, BANK_1, 610 FANIN1_HV_HL_REG + channel * 2, tmp); 611 if (ret < 0) 612 return ret; 613 tmp = val & 0x1f; 614 ret = nct7904_write_reg(data, BANK_1, 615 FANIN1_LV_HL_REG + channel * 2, tmp); 616 return ret; 617 default: 618 return -EOPNOTSUPP; 619 } 620 } 621 622 static int nct7904_write_in(struct device *dev, u32 attr, int channel, 623 long val) 624 { 625 struct nct7904_data *data = dev_get_drvdata(dev); 626 int ret, index, tmp; 627 628 index = nct7904_chan_to_index[channel]; 629 630 if (index < 14) 631 val = val / 2; /* 0.002V scale */ 632 else 633 val = val / 6; /* 0.006V scale */ 634 635 val = clamp_val(val, 0, 0x7ff); 636 637 switch (attr) { 638 case hwmon_in_min: 639 tmp = nct7904_read_reg(data, BANK_1, 640 VSEN1_LV_LL_REG + index * 4); 641 if (tmp < 0) 642 return tmp; 643 tmp &= ~0x7; 644 tmp |= val & 0x7; 645 ret = nct7904_write_reg(data, BANK_1, 646 VSEN1_LV_LL_REG + index * 4, tmp); 647 if (ret < 0) 648 return ret; 649 tmp = nct7904_read_reg(data, BANK_1, 650 VSEN1_HV_LL_REG + index * 4); 651 if (tmp < 0) 652 return tmp; 653 tmp = (val >> 3) & 0xff; 654 ret = nct7904_write_reg(data, BANK_1, 655 VSEN1_HV_LL_REG + index * 4, tmp); 656 return ret; 657 case hwmon_in_max: 658 tmp = nct7904_read_reg(data, BANK_1, 659 VSEN1_LV_HL_REG + index * 4); 660 if (tmp < 0) 661 return tmp; 662 tmp &= ~0x7; 663 tmp |= val & 0x7; 664 ret = nct7904_write_reg(data, BANK_1, 665 VSEN1_LV_HL_REG + index * 4, tmp); 666 if (ret < 0) 667 return ret; 668 tmp = nct7904_read_reg(data, BANK_1, 669 VSEN1_HV_HL_REG + index * 4); 670 if (tmp < 0) 671 return tmp; 672 tmp = (val >> 3) & 0xff; 673 ret = nct7904_write_reg(data, BANK_1, 674 VSEN1_HV_HL_REG + index * 4, tmp); 675 return ret; 676 default: 677 return -EOPNOTSUPP; 678 } 679 } 680 681 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel, 682 long val) 683 { 684 struct nct7904_data *data = dev_get_drvdata(dev); 685 int ret; 686 687 switch (attr) { 688 case hwmon_pwm_input: 689 if (val < 0 || val > 255) 690 return -EINVAL; 691 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel, 692 val); 693 return ret; 694 case hwmon_pwm_enable: 695 if (val < 1 || val > 2 || 696 (val == 2 && !data->fan_mode[channel])) 697 return -EINVAL; 698 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel, 699 val == 2 ? data->fan_mode[channel] : 0); 700 return ret; 701 default: 702 return -EOPNOTSUPP; 703 } 704 } 705 706 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel) 707 { 708 switch (attr) { 709 case hwmon_pwm_input: 710 case hwmon_pwm_enable: 711 return 0644; 712 default: 713 return 0; 714 } 715 } 716 717 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type, 718 u32 attr, int channel, long *val) 719 { 720 switch (type) { 721 case hwmon_in: 722 return nct7904_read_in(dev, attr, channel, val); 723 case hwmon_fan: 724 return nct7904_read_fan(dev, attr, channel, val); 725 case hwmon_pwm: 726 return nct7904_read_pwm(dev, attr, channel, val); 727 case hwmon_temp: 728 return nct7904_read_temp(dev, attr, channel, val); 729 default: 730 return -EOPNOTSUPP; 731 } 732 } 733 734 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type, 735 u32 attr, int channel, long val) 736 { 737 switch (type) { 738 case hwmon_in: 739 return nct7904_write_in(dev, attr, channel, val); 740 case hwmon_fan: 741 return nct7904_write_fan(dev, attr, channel, val); 742 case hwmon_pwm: 743 return nct7904_write_pwm(dev, attr, channel, val); 744 case hwmon_temp: 745 return nct7904_write_temp(dev, attr, channel, val); 746 default: 747 return -EOPNOTSUPP; 748 } 749 } 750 751 static umode_t nct7904_is_visible(const void *data, 752 enum hwmon_sensor_types type, 753 u32 attr, int channel) 754 { 755 switch (type) { 756 case hwmon_in: 757 return nct7904_in_is_visible(data, attr, channel); 758 case hwmon_fan: 759 return nct7904_fan_is_visible(data, attr, channel); 760 case hwmon_pwm: 761 return nct7904_pwm_is_visible(data, attr, channel); 762 case hwmon_temp: 763 return nct7904_temp_is_visible(data, attr, channel); 764 default: 765 return 0; 766 } 767 } 768 769 /* Return 0 if detection is successful, -ENODEV otherwise */ 770 static int nct7904_detect(struct i2c_client *client, 771 struct i2c_board_info *info) 772 { 773 struct i2c_adapter *adapter = client->adapter; 774 775 if (!i2c_check_functionality(adapter, 776 I2C_FUNC_SMBUS_READ_BYTE | 777 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 778 return -ENODEV; 779 780 /* Determine the chip type. */ 781 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID || 782 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID || 783 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 || 784 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00) 785 return -ENODEV; 786 787 strscpy(info->type, "nct7904", I2C_NAME_SIZE); 788 789 return 0; 790 } 791 792 static const struct hwmon_channel_info * const nct7904_info[] = { 793 HWMON_CHANNEL_INFO(in, 794 /* dummy, skipped in is_visible */ 795 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 796 HWMON_I_ALARM, 797 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 798 HWMON_I_ALARM, 799 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 800 HWMON_I_ALARM, 801 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 802 HWMON_I_ALARM, 803 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 804 HWMON_I_ALARM, 805 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 806 HWMON_I_ALARM, 807 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 808 HWMON_I_ALARM, 809 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 810 HWMON_I_ALARM, 811 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 812 HWMON_I_ALARM, 813 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 814 HWMON_I_ALARM, 815 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 816 HWMON_I_ALARM, 817 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 818 HWMON_I_ALARM, 819 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 820 HWMON_I_ALARM, 821 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 822 HWMON_I_ALARM, 823 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 824 HWMON_I_ALARM, 825 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 826 HWMON_I_ALARM, 827 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 828 HWMON_I_ALARM, 829 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 830 HWMON_I_ALARM, 831 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 832 HWMON_I_ALARM, 833 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 834 HWMON_I_ALARM, 835 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 836 HWMON_I_ALARM), 837 HWMON_CHANNEL_INFO(fan, 838 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 839 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 840 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 841 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 842 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 843 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 844 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 845 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 846 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 847 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 848 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 849 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM), 850 HWMON_CHANNEL_INFO(pwm, 851 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 852 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 853 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 854 HWMON_PWM_INPUT | HWMON_PWM_ENABLE), 855 HWMON_CHANNEL_INFO(temp, 856 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 857 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 858 HWMON_T_CRIT_HYST, 859 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 860 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 861 HWMON_T_CRIT_HYST, 862 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 863 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 864 HWMON_T_CRIT_HYST, 865 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 866 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 867 HWMON_T_CRIT_HYST, 868 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 869 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 870 HWMON_T_CRIT_HYST, 871 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 872 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 873 HWMON_T_CRIT_HYST, 874 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 875 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 876 HWMON_T_CRIT_HYST, 877 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 878 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 879 HWMON_T_CRIT_HYST, 880 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 881 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 882 HWMON_T_CRIT_HYST, 883 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 884 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 885 HWMON_T_CRIT_HYST, 886 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 887 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 888 HWMON_T_CRIT_HYST, 889 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 890 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 891 HWMON_T_CRIT_HYST, 892 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 893 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 894 HWMON_T_CRIT_HYST), 895 NULL 896 }; 897 898 static const struct hwmon_ops nct7904_hwmon_ops = { 899 .is_visible = nct7904_is_visible, 900 .read = nct7904_read, 901 .write = nct7904_write, 902 }; 903 904 static const struct hwmon_chip_info nct7904_chip_info = { 905 .ops = &nct7904_hwmon_ops, 906 .info = nct7904_info, 907 }; 908 909 /* 910 * Watchdog Function 911 */ 912 static int nct7904_wdt_start(struct watchdog_device *wdt) 913 { 914 struct nct7904_data *data = watchdog_get_drvdata(wdt); 915 916 /* Enable soft watchdog timer */ 917 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN); 918 } 919 920 static int nct7904_wdt_stop(struct watchdog_device *wdt) 921 { 922 struct nct7904_data *data = watchdog_get_drvdata(wdt); 923 924 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS); 925 } 926 927 static int nct7904_wdt_set_timeout(struct watchdog_device *wdt, 928 unsigned int timeout) 929 { 930 struct nct7904_data *data = watchdog_get_drvdata(wdt); 931 /* 932 * The NCT7904 is very special in watchdog function. 933 * Its minimum unit is minutes. And wdt->timeout needs 934 * to match the actual timeout selected. So, this needs 935 * to be: wdt->timeout = timeout / 60 * 60. 936 * For example, if the user configures a timeout of 937 * 119 seconds, the actual timeout will be 60 seconds. 938 * So, wdt->timeout must then be set to 60 seconds. 939 */ 940 wdt->timeout = timeout / 60 * 60; 941 942 return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, 943 wdt->timeout / 60); 944 } 945 946 static int nct7904_wdt_ping(struct watchdog_device *wdt) 947 { 948 /* 949 * Note: 950 * NCT7904 does not support refreshing WDT_TIMER_REG register when 951 * the watchdog is active. Please disable watchdog before feeding 952 * the watchdog and enable it again. 953 */ 954 struct nct7904_data *data = watchdog_get_drvdata(wdt); 955 int ret; 956 957 /* Disable soft watchdog timer */ 958 ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS); 959 if (ret < 0) 960 return ret; 961 962 /* feed watchdog */ 963 ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60); 964 if (ret < 0) 965 return ret; 966 967 /* Enable soft watchdog timer */ 968 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN); 969 } 970 971 static unsigned int nct7904_wdt_get_timeleft(struct watchdog_device *wdt) 972 { 973 struct nct7904_data *data = watchdog_get_drvdata(wdt); 974 int ret; 975 976 ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG); 977 if (ret < 0) 978 return 0; 979 980 return ret * 60; 981 } 982 983 static const struct watchdog_info nct7904_wdt_info = { 984 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | 985 WDIOF_MAGICCLOSE, 986 .identity = "nct7904 watchdog", 987 }; 988 989 static const struct watchdog_ops nct7904_wdt_ops = { 990 .owner = THIS_MODULE, 991 .start = nct7904_wdt_start, 992 .stop = nct7904_wdt_stop, 993 .ping = nct7904_wdt_ping, 994 .set_timeout = nct7904_wdt_set_timeout, 995 .get_timeleft = nct7904_wdt_get_timeleft, 996 }; 997 998 static int nct7904_probe(struct i2c_client *client) 999 { 1000 struct nct7904_data *data; 1001 struct device *hwmon_dev; 1002 struct device *dev = &client->dev; 1003 int ret, i; 1004 u32 mask; 1005 u8 val, bit; 1006 1007 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL); 1008 if (!data) 1009 return -ENOMEM; 1010 1011 data->client = client; 1012 data->bank_sel = -1; 1013 1014 /* Setup sensor groups. */ 1015 /* FANIN attributes */ 1016 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG); 1017 if (ret < 0) 1018 return ret; 1019 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8); 1020 1021 /* 1022 * VSEN attributes 1023 * 1024 * Note: voltage sensors overlap with external temperature 1025 * sensors. So, if we ever decide to support the latter 1026 * we will have to adjust 'vsen_mask' accordingly. 1027 */ 1028 mask = 0; 1029 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG); 1030 if (ret >= 0) 1031 mask = (ret >> 8) | ((ret & 0xff) << 8); 1032 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 1033 if (ret >= 0) 1034 mask |= (ret << 16); 1035 data->vsen_mask = mask; 1036 1037 /* CPU_TEMP attributes */ 1038 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG); 1039 if (ret < 0) 1040 return ret; 1041 1042 if ((ret & 0x6) == 0x6) 1043 data->tcpu_mask |= 1; /* TR1 */ 1044 if ((ret & 0x18) == 0x18) 1045 data->tcpu_mask |= 2; /* TR2 */ 1046 if ((ret & 0x20) == 0x20) 1047 data->tcpu_mask |= 4; /* TR3 */ 1048 if ((ret & 0x80) == 0x80) 1049 data->tcpu_mask |= 8; /* TR4 */ 1050 1051 /* LTD */ 1052 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 1053 if (ret < 0) 1054 return ret; 1055 if ((ret & 0x02) == 0x02) 1056 data->tcpu_mask |= 0x10; 1057 1058 /* Multi-Function detecting for Volt and TR/TD */ 1059 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG); 1060 if (ret < 0) 1061 return ret; 1062 1063 data->temp_mode = 0; 1064 for (i = 0; i < 4; i++) { 1065 val = (ret >> (i * 2)) & 0x03; 1066 bit = (1 << i); 1067 if (val == VOLT_MONITOR_MODE) { 1068 data->tcpu_mask &= ~bit; 1069 } else if (val == THERMAL_DIODE_MODE && i < 2) { 1070 data->temp_mode |= bit; 1071 data->vsen_mask &= ~(0x06 << (i * 2)); 1072 } else if (val == THERMISTOR_MODE) { 1073 data->vsen_mask &= ~(0x02 << (i * 2)); 1074 } else { 1075 /* Reserved */ 1076 data->tcpu_mask &= ~bit; 1077 data->vsen_mask &= ~(0x06 << (i * 2)); 1078 } 1079 } 1080 1081 /* PECI */ 1082 ret = nct7904_read_reg(data, BANK_2, PFE_REG); 1083 if (ret < 0) 1084 return ret; 1085 if (ret & 0x80) { 1086 data->enable_dts = 1; /* Enable DTS & PECI */ 1087 } else { 1088 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG); 1089 if (ret < 0) 1090 return ret; 1091 if (ret & 0x80) 1092 data->enable_dts = 0x3; /* Enable DTS & TSI */ 1093 } 1094 1095 /* Check DTS enable status */ 1096 if (data->enable_dts) { 1097 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG); 1098 if (ret < 0) 1099 return ret; 1100 data->has_dts = ret & 0xF; 1101 if (data->enable_dts & ENABLE_TSI) { 1102 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG); 1103 if (ret < 0) 1104 return ret; 1105 data->has_dts |= (ret & 0xF) << 4; 1106 } 1107 } 1108 1109 for (i = 0; i < FANCTL_MAX; i++) { 1110 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i); 1111 if (ret < 0) 1112 return ret; 1113 data->fan_mode[i] = ret; 1114 } 1115 1116 /* Read all of SMI status register to clear alarms */ 1117 for (i = 0; i < SMI_STS_MAX; i++) { 1118 ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i); 1119 if (ret < 0) 1120 return ret; 1121 } 1122 1123 hwmon_dev = 1124 devm_hwmon_device_register_with_info(dev, client->name, data, 1125 &nct7904_chip_info, NULL); 1126 ret = PTR_ERR_OR_ZERO(hwmon_dev); 1127 if (ret) 1128 return ret; 1129 1130 /* Watchdog initialization */ 1131 data->wdt.ops = &nct7904_wdt_ops; 1132 data->wdt.info = &nct7904_wdt_info; 1133 1134 data->wdt.timeout = WATCHDOG_TIMEOUT * 60; /* Set default timeout */ 1135 data->wdt.min_timeout = MIN_TIMEOUT; 1136 data->wdt.max_timeout = MAX_TIMEOUT; 1137 data->wdt.parent = &client->dev; 1138 1139 watchdog_init_timeout(&data->wdt, timeout * 60, &client->dev); 1140 watchdog_set_nowayout(&data->wdt, nowayout); 1141 watchdog_set_drvdata(&data->wdt, data); 1142 1143 watchdog_stop_on_unregister(&data->wdt); 1144 1145 return devm_watchdog_register_device(dev, &data->wdt); 1146 } 1147 1148 static const struct i2c_device_id nct7904_id[] = { 1149 {"nct7904"}, 1150 {} 1151 }; 1152 MODULE_DEVICE_TABLE(i2c, nct7904_id); 1153 1154 static struct i2c_driver nct7904_driver = { 1155 .class = I2C_CLASS_HWMON, 1156 .driver = { 1157 .name = "nct7904", 1158 }, 1159 .probe = nct7904_probe, 1160 .id_table = nct7904_id, 1161 .detect = nct7904_detect, 1162 .address_list = normal_i2c, 1163 }; 1164 1165 module_i2c_driver(nct7904_driver); 1166 1167 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>"); 1168 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904"); 1169 MODULE_LICENSE("GPL"); 1170