1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __QCOM_TSENS_H__ 7 #define __QCOM_TSENS_H__ 8 9 #define NO_PT_CALIB 0x0 10 #define ONE_PT_CALIB 0x1 11 #define ONE_PT_CALIB2 0x2 12 #define TWO_PT_CALIB 0x3 13 #define ONE_PT_CALIB2_NO_OFFSET 0x6 14 #define TWO_PT_CALIB_NO_OFFSET 0x7 15 #define CAL_DEGC_PT1 30 16 #define CAL_DEGC_PT2 120 17 #define SLOPE_FACTOR 1000 18 #define SLOPE_DEFAULT 3200 19 #define TIMEOUT_US 100 20 #define THRESHOLD_MAX_ADC_CODE 0x3ff 21 #define THRESHOLD_MIN_ADC_CODE 0x0 22 23 #define MAX_SENSORS 16 24 #define MAX_READ_RETRY 3 25 26 #include <linux/interrupt.h> 27 #include <linux/thermal.h> 28 #include <linux/regmap.h> 29 #include <linux/slab.h> 30 31 struct tsens_priv; 32 33 /* IP version numbers in ascending order */ 34 enum tsens_ver { 35 VER_0 = 0, 36 VER_0_1, 37 VER_1_X, 38 VER_1_X_NO_RPM, 39 VER_2_X, 40 VER_2_X_NO_RPM, 41 }; 42 43 enum tsens_irq_type { 44 LOWER, 45 UPPER, 46 CRITICAL, 47 }; 48 49 /** 50 * struct tsens_sensor - data for each sensor connected to the tsens device 51 * @priv: tsens device instance that this sensor is connected to 52 * @tzd: pointer to the thermal zone that this sensor is in 53 * @offset: offset of temperature adjustment curve 54 * @hw_id: HW ID can be used in case of platform-specific IDs 55 * @slope: slope of temperature adjustment curve 56 * @status: 8960-specific variable to track 8960 and 8660 status register offset 57 */ 58 struct tsens_sensor { 59 struct tsens_priv *priv; 60 struct thermal_zone_device *tzd; 61 int offset; 62 unsigned int hw_id; 63 int slope; 64 u32 status; 65 int p1_calib_offset; 66 int p2_calib_offset; 67 }; 68 69 /** 70 * struct tsens_ops - operations as supported by the tsens device 71 * @init: Function to initialize the tsens device 72 * @calibrate: Function to calibrate the tsens device 73 * @get_temp: Function which returns the temp in millidegC 74 * @enable: Function to enable (clocks/power) tsens device 75 * @disable: Function to disable the tsens device 76 * @suspend: Function to suspend the tsens device 77 * @resume: Function to resume the tsens device 78 */ 79 struct tsens_ops { 80 /* mandatory callbacks */ 81 int (*init)(struct tsens_priv *priv); 82 int (*calibrate)(struct tsens_priv *priv); 83 int (*get_temp)(const struct tsens_sensor *s, int *temp); 84 /* optional callbacks */ 85 int (*enable)(struct tsens_priv *priv, int i); 86 void (*disable)(struct tsens_priv *priv); 87 int (*suspend)(struct tsens_priv *priv); 88 int (*resume)(struct tsens_priv *priv); 89 }; 90 91 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ 92 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \ 93 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \ 94 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \ 95 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \ 96 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \ 97 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \ 98 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \ 99 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \ 100 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \ 101 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \ 102 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit) 103 104 #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \ 105 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \ 106 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \ 107 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \ 108 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \ 109 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \ 110 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \ 111 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \ 112 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \ 113 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \ 114 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \ 115 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \ 116 [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \ 117 [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \ 118 [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \ 119 [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ 120 [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) 121 122 #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ 123 [_name##_##0] = REG_FIELD(_offset, 0, 0), \ 124 [_name##_##1] = REG_FIELD(_offset, 1, 1), \ 125 [_name##_##2] = REG_FIELD(_offset, 2, 2), \ 126 [_name##_##3] = REG_FIELD(_offset, 3, 3), \ 127 [_name##_##4] = REG_FIELD(_offset, 4, 4), \ 128 [_name##_##5] = REG_FIELD(_offset, 5, 5), \ 129 [_name##_##6] = REG_FIELD(_offset, 6, 6), \ 130 [_name##_##7] = REG_FIELD(_offset, 7, 7), \ 131 [_name##_##8] = REG_FIELD(_offset, 8, 8), \ 132 [_name##_##9] = REG_FIELD(_offset, 9, 9), \ 133 [_name##_##10] = REG_FIELD(_offset, 10, 10), \ 134 [_name##_##11] = REG_FIELD(_offset, 11, 11), \ 135 [_name##_##12] = REG_FIELD(_offset, 12, 12), \ 136 [_name##_##13] = REG_FIELD(_offset, 13, 13), \ 137 [_name##_##14] = REG_FIELD(_offset, 14, 14), \ 138 [_name##_##15] = REG_FIELD(_offset, 15, 15) 139 140 #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ 141 [_name##_##0] = REG_FIELD(_offset, 16, 16), \ 142 [_name##_##1] = REG_FIELD(_offset, 17, 17), \ 143 [_name##_##2] = REG_FIELD(_offset, 18, 18), \ 144 [_name##_##3] = REG_FIELD(_offset, 19, 19), \ 145 [_name##_##4] = REG_FIELD(_offset, 20, 20), \ 146 [_name##_##5] = REG_FIELD(_offset, 21, 21), \ 147 [_name##_##6] = REG_FIELD(_offset, 22, 22), \ 148 [_name##_##7] = REG_FIELD(_offset, 23, 23), \ 149 [_name##_##8] = REG_FIELD(_offset, 24, 24), \ 150 [_name##_##9] = REG_FIELD(_offset, 25, 25), \ 151 [_name##_##10] = REG_FIELD(_offset, 26, 26), \ 152 [_name##_##11] = REG_FIELD(_offset, 27, 27), \ 153 [_name##_##12] = REG_FIELD(_offset, 28, 28), \ 154 [_name##_##13] = REG_FIELD(_offset, 29, 29), \ 155 [_name##_##14] = REG_FIELD(_offset, 30, 30), \ 156 [_name##_##15] = REG_FIELD(_offset, 31, 31) 157 158 /* 159 * reg_field IDs to use as an index into an array 160 * If you change the order of the entries, check the devm_regmap_field_alloc() 161 * calls in init_common() 162 */ 163 enum regfield_ids { 164 /* ----- SROT ------ */ 165 /* HW_VER */ 166 VER_MAJOR, 167 VER_MINOR, 168 VER_STEP, 169 /* CTRL_OFFSET */ 170 TSENS_EN, 171 TSENS_SW_RST, 172 SENSOR_EN, 173 CODE_OR_TEMP, 174 MAIN_MEASURE_PERIOD, 175 176 /* ----- TM ------ */ 177 /* TRDY */ 178 TRDY, 179 /* INTERRUPT ENABLE */ 180 INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ 181 /* STATUS */ 182 LAST_TEMP_0, /* Last temperature reading */ 183 LAST_TEMP_1, 184 LAST_TEMP_2, 185 LAST_TEMP_3, 186 LAST_TEMP_4, 187 LAST_TEMP_5, 188 LAST_TEMP_6, 189 LAST_TEMP_7, 190 LAST_TEMP_8, 191 LAST_TEMP_9, 192 LAST_TEMP_10, 193 LAST_TEMP_11, 194 LAST_TEMP_12, 195 LAST_TEMP_13, 196 LAST_TEMP_14, 197 LAST_TEMP_15, 198 VALID_0, /* VALID reading or not */ 199 VALID_1, 200 VALID_2, 201 VALID_3, 202 VALID_4, 203 VALID_5, 204 VALID_6, 205 VALID_7, 206 VALID_8, 207 VALID_9, 208 VALID_10, 209 VALID_11, 210 VALID_12, 211 VALID_13, 212 VALID_14, 213 VALID_15, 214 LOWER_STATUS_0, /* LOWER threshold violated */ 215 LOWER_STATUS_1, 216 LOWER_STATUS_2, 217 LOWER_STATUS_3, 218 LOWER_STATUS_4, 219 LOWER_STATUS_5, 220 LOWER_STATUS_6, 221 LOWER_STATUS_7, 222 LOWER_STATUS_8, 223 LOWER_STATUS_9, 224 LOWER_STATUS_10, 225 LOWER_STATUS_11, 226 LOWER_STATUS_12, 227 LOWER_STATUS_13, 228 LOWER_STATUS_14, 229 LOWER_STATUS_15, 230 LOW_INT_STATUS_0, /* LOWER interrupt status */ 231 LOW_INT_STATUS_1, 232 LOW_INT_STATUS_2, 233 LOW_INT_STATUS_3, 234 LOW_INT_STATUS_4, 235 LOW_INT_STATUS_5, 236 LOW_INT_STATUS_6, 237 LOW_INT_STATUS_7, 238 LOW_INT_STATUS_8, 239 LOW_INT_STATUS_9, 240 LOW_INT_STATUS_10, 241 LOW_INT_STATUS_11, 242 LOW_INT_STATUS_12, 243 LOW_INT_STATUS_13, 244 LOW_INT_STATUS_14, 245 LOW_INT_STATUS_15, 246 LOW_INT_CLEAR_0, /* LOWER interrupt clear */ 247 LOW_INT_CLEAR_1, 248 LOW_INT_CLEAR_2, 249 LOW_INT_CLEAR_3, 250 LOW_INT_CLEAR_4, 251 LOW_INT_CLEAR_5, 252 LOW_INT_CLEAR_6, 253 LOW_INT_CLEAR_7, 254 LOW_INT_CLEAR_8, 255 LOW_INT_CLEAR_9, 256 LOW_INT_CLEAR_10, 257 LOW_INT_CLEAR_11, 258 LOW_INT_CLEAR_12, 259 LOW_INT_CLEAR_13, 260 LOW_INT_CLEAR_14, 261 LOW_INT_CLEAR_15, 262 LOW_INT_MASK_0, /* LOWER interrupt mask */ 263 LOW_INT_MASK_1, 264 LOW_INT_MASK_2, 265 LOW_INT_MASK_3, 266 LOW_INT_MASK_4, 267 LOW_INT_MASK_5, 268 LOW_INT_MASK_6, 269 LOW_INT_MASK_7, 270 LOW_INT_MASK_8, 271 LOW_INT_MASK_9, 272 LOW_INT_MASK_10, 273 LOW_INT_MASK_11, 274 LOW_INT_MASK_12, 275 LOW_INT_MASK_13, 276 LOW_INT_MASK_14, 277 LOW_INT_MASK_15, 278 LOW_THRESH_0, /* LOWER threshold values */ 279 LOW_THRESH_1, 280 LOW_THRESH_2, 281 LOW_THRESH_3, 282 LOW_THRESH_4, 283 LOW_THRESH_5, 284 LOW_THRESH_6, 285 LOW_THRESH_7, 286 LOW_THRESH_8, 287 LOW_THRESH_9, 288 LOW_THRESH_10, 289 LOW_THRESH_11, 290 LOW_THRESH_12, 291 LOW_THRESH_13, 292 LOW_THRESH_14, 293 LOW_THRESH_15, 294 UPPER_STATUS_0, /* UPPER threshold violated */ 295 UPPER_STATUS_1, 296 UPPER_STATUS_2, 297 UPPER_STATUS_3, 298 UPPER_STATUS_4, 299 UPPER_STATUS_5, 300 UPPER_STATUS_6, 301 UPPER_STATUS_7, 302 UPPER_STATUS_8, 303 UPPER_STATUS_9, 304 UPPER_STATUS_10, 305 UPPER_STATUS_11, 306 UPPER_STATUS_12, 307 UPPER_STATUS_13, 308 UPPER_STATUS_14, 309 UPPER_STATUS_15, 310 UP_INT_STATUS_0, /* UPPER interrupt status */ 311 UP_INT_STATUS_1, 312 UP_INT_STATUS_2, 313 UP_INT_STATUS_3, 314 UP_INT_STATUS_4, 315 UP_INT_STATUS_5, 316 UP_INT_STATUS_6, 317 UP_INT_STATUS_7, 318 UP_INT_STATUS_8, 319 UP_INT_STATUS_9, 320 UP_INT_STATUS_10, 321 UP_INT_STATUS_11, 322 UP_INT_STATUS_12, 323 UP_INT_STATUS_13, 324 UP_INT_STATUS_14, 325 UP_INT_STATUS_15, 326 UP_INT_CLEAR_0, /* UPPER interrupt clear */ 327 UP_INT_CLEAR_1, 328 UP_INT_CLEAR_2, 329 UP_INT_CLEAR_3, 330 UP_INT_CLEAR_4, 331 UP_INT_CLEAR_5, 332 UP_INT_CLEAR_6, 333 UP_INT_CLEAR_7, 334 UP_INT_CLEAR_8, 335 UP_INT_CLEAR_9, 336 UP_INT_CLEAR_10, 337 UP_INT_CLEAR_11, 338 UP_INT_CLEAR_12, 339 UP_INT_CLEAR_13, 340 UP_INT_CLEAR_14, 341 UP_INT_CLEAR_15, 342 UP_INT_MASK_0, /* UPPER interrupt mask */ 343 UP_INT_MASK_1, 344 UP_INT_MASK_2, 345 UP_INT_MASK_3, 346 UP_INT_MASK_4, 347 UP_INT_MASK_5, 348 UP_INT_MASK_6, 349 UP_INT_MASK_7, 350 UP_INT_MASK_8, 351 UP_INT_MASK_9, 352 UP_INT_MASK_10, 353 UP_INT_MASK_11, 354 UP_INT_MASK_12, 355 UP_INT_MASK_13, 356 UP_INT_MASK_14, 357 UP_INT_MASK_15, 358 UP_THRESH_0, /* UPPER threshold values */ 359 UP_THRESH_1, 360 UP_THRESH_2, 361 UP_THRESH_3, 362 UP_THRESH_4, 363 UP_THRESH_5, 364 UP_THRESH_6, 365 UP_THRESH_7, 366 UP_THRESH_8, 367 UP_THRESH_9, 368 UP_THRESH_10, 369 UP_THRESH_11, 370 UP_THRESH_12, 371 UP_THRESH_13, 372 UP_THRESH_14, 373 UP_THRESH_15, 374 CRITICAL_STATUS_0, /* CRITICAL threshold violated */ 375 CRITICAL_STATUS_1, 376 CRITICAL_STATUS_2, 377 CRITICAL_STATUS_3, 378 CRITICAL_STATUS_4, 379 CRITICAL_STATUS_5, 380 CRITICAL_STATUS_6, 381 CRITICAL_STATUS_7, 382 CRITICAL_STATUS_8, 383 CRITICAL_STATUS_9, 384 CRITICAL_STATUS_10, 385 CRITICAL_STATUS_11, 386 CRITICAL_STATUS_12, 387 CRITICAL_STATUS_13, 388 CRITICAL_STATUS_14, 389 CRITICAL_STATUS_15, 390 CRIT_INT_STATUS_0, /* CRITICAL interrupt status */ 391 CRIT_INT_STATUS_1, 392 CRIT_INT_STATUS_2, 393 CRIT_INT_STATUS_3, 394 CRIT_INT_STATUS_4, 395 CRIT_INT_STATUS_5, 396 CRIT_INT_STATUS_6, 397 CRIT_INT_STATUS_7, 398 CRIT_INT_STATUS_8, 399 CRIT_INT_STATUS_9, 400 CRIT_INT_STATUS_10, 401 CRIT_INT_STATUS_11, 402 CRIT_INT_STATUS_12, 403 CRIT_INT_STATUS_13, 404 CRIT_INT_STATUS_14, 405 CRIT_INT_STATUS_15, 406 CRIT_INT_CLEAR_0, /* CRITICAL interrupt clear */ 407 CRIT_INT_CLEAR_1, 408 CRIT_INT_CLEAR_2, 409 CRIT_INT_CLEAR_3, 410 CRIT_INT_CLEAR_4, 411 CRIT_INT_CLEAR_5, 412 CRIT_INT_CLEAR_6, 413 CRIT_INT_CLEAR_7, 414 CRIT_INT_CLEAR_8, 415 CRIT_INT_CLEAR_9, 416 CRIT_INT_CLEAR_10, 417 CRIT_INT_CLEAR_11, 418 CRIT_INT_CLEAR_12, 419 CRIT_INT_CLEAR_13, 420 CRIT_INT_CLEAR_14, 421 CRIT_INT_CLEAR_15, 422 CRIT_INT_MASK_0, /* CRITICAL interrupt mask */ 423 CRIT_INT_MASK_1, 424 CRIT_INT_MASK_2, 425 CRIT_INT_MASK_3, 426 CRIT_INT_MASK_4, 427 CRIT_INT_MASK_5, 428 CRIT_INT_MASK_6, 429 CRIT_INT_MASK_7, 430 CRIT_INT_MASK_8, 431 CRIT_INT_MASK_9, 432 CRIT_INT_MASK_10, 433 CRIT_INT_MASK_11, 434 CRIT_INT_MASK_12, 435 CRIT_INT_MASK_13, 436 CRIT_INT_MASK_14, 437 CRIT_INT_MASK_15, 438 CRIT_THRESH_0, /* CRITICAL threshold values */ 439 CRIT_THRESH_1, 440 CRIT_THRESH_2, 441 CRIT_THRESH_3, 442 CRIT_THRESH_4, 443 CRIT_THRESH_5, 444 CRIT_THRESH_6, 445 CRIT_THRESH_7, 446 CRIT_THRESH_8, 447 CRIT_THRESH_9, 448 CRIT_THRESH_10, 449 CRIT_THRESH_11, 450 CRIT_THRESH_12, 451 CRIT_THRESH_13, 452 CRIT_THRESH_14, 453 CRIT_THRESH_15, 454 455 /* WATCHDOG */ 456 WDOG_BARK_STATUS, 457 WDOG_BARK_CLEAR, 458 WDOG_BARK_MASK, 459 WDOG_BARK_COUNT, 460 461 /* CYCLE COMPLETION MONITOR */ 462 CC_MON_STATUS, 463 CC_MON_CLEAR, 464 CC_MON_MASK, 465 466 MIN_STATUS_0, /* MIN threshold violated */ 467 MIN_STATUS_1, 468 MIN_STATUS_2, 469 MIN_STATUS_3, 470 MIN_STATUS_4, 471 MIN_STATUS_5, 472 MIN_STATUS_6, 473 MIN_STATUS_7, 474 MIN_STATUS_8, 475 MIN_STATUS_9, 476 MIN_STATUS_10, 477 MIN_STATUS_11, 478 MIN_STATUS_12, 479 MIN_STATUS_13, 480 MIN_STATUS_14, 481 MIN_STATUS_15, 482 MAX_STATUS_0, /* MAX threshold violated */ 483 MAX_STATUS_1, 484 MAX_STATUS_2, 485 MAX_STATUS_3, 486 MAX_STATUS_4, 487 MAX_STATUS_5, 488 MAX_STATUS_6, 489 MAX_STATUS_7, 490 MAX_STATUS_8, 491 MAX_STATUS_9, 492 MAX_STATUS_10, 493 MAX_STATUS_11, 494 MAX_STATUS_12, 495 MAX_STATUS_13, 496 MAX_STATUS_14, 497 MAX_STATUS_15, 498 499 /* Keep last */ 500 MAX_REGFIELDS 501 }; 502 503 /** 504 * struct tsens_features - Features supported by the IP 505 * @ver_major: Major number of IP version 506 * @crit_int: does the IP support critical interrupts? 507 * @combo_int: does the IP use one IRQ for up, low and critical thresholds? 508 * @adc: do the sensors only output adc code (instead of temperature)? 509 * @srot_split: does the IP neatly splits the register space into SROT and TM, 510 * with SROT only being available to secure boot firmware? 511 * @has_watchdog: does this IP support watchdog functionality? 512 * @max_sensors: maximum sensors supported by this version of the IP 513 * @trip_min_temp: minimum trip temperature supported by this version of the IP 514 * @trip_max_temp: maximum trip temperature supported by this version of the IP 515 */ 516 struct tsens_features { 517 unsigned int ver_major; 518 unsigned int crit_int:1; 519 unsigned int combo_int:1; 520 unsigned int adc:1; 521 unsigned int srot_split:1; 522 unsigned int has_watchdog:1; 523 unsigned int max_sensors; 524 int trip_min_temp; 525 int trip_max_temp; 526 }; 527 528 /** 529 * struct tsens_plat_data - tsens compile-time platform data 530 * @num_sensors: Number of sensors supported by platform 531 * @ops: operations the tsens instance supports 532 * @hw_ids: Subset of sensors ids supported by platform, if not the first n 533 * @feat: features of the IP 534 * @fields: bitfield locations 535 * @no_irq_wake: if set, TSENS interrupts will not be configured as wakeup sources 536 */ 537 struct tsens_plat_data { 538 const u32 num_sensors; 539 const struct tsens_ops *ops; 540 unsigned int *hw_ids; 541 struct tsens_features *feat; 542 const struct reg_field *fields; 543 bool no_irq_wake; 544 }; 545 546 /** 547 * struct tsens_context - Registers to be saved/restored across a context loss 548 * @threshold: Threshold register value 549 * @control: Control register value 550 */ 551 struct tsens_context { 552 int threshold; 553 int control; 554 }; 555 556 /** 557 * struct tsens_priv - private data for each instance of the tsens IP 558 * @dev: pointer to struct device 559 * @num_sensors: number of sensors enabled on this device 560 * @tm_map: pointer to TM register address space 561 * @srot_map: pointer to SROT register address space 562 * @tm_offset: deal with old device trees that don't address TM and SROT 563 * address space separately 564 * @ul_lock: lock while processing upper/lower threshold interrupts 565 * @crit_lock: lock while processing critical threshold interrupts 566 * @rf: array of regmap_fields used to store value of the field 567 * @ctx: registers to be saved and restored during suspend/resume 568 * @feat: features of the IP 569 * @fields: bitfield locations 570 * @ops: pointer to list of callbacks supported by this device 571 * @debug_root: pointer to debugfs dentry for all tsens 572 * @debug: pointer to debugfs dentry for tsens controller 573 * @uplow_irq: IRQ number for uplow (upper/lower) threshold interrupts 574 * @crit_irq: IRQ number for critical threshold interrupts 575 * @combined_irq: IRQ number for combined threshold interrupts 576 * @sensor: list of sensors attached to this device 577 */ 578 struct tsens_priv { 579 struct device *dev; 580 u32 num_sensors; 581 struct regmap *tm_map; 582 struct regmap *srot_map; 583 u32 tm_offset; 584 585 /* lock for upper/lower threshold interrupts */ 586 spinlock_t ul_lock; 587 588 struct regmap_field *rf[MAX_REGFIELDS]; 589 struct tsens_context ctx; 590 struct tsens_features *feat; 591 const struct reg_field *fields; 592 const struct tsens_ops *ops; 593 594 struct dentry *debug_root; 595 struct dentry *debug; 596 597 int uplow_irq; 598 int crit_irq; 599 int combined_irq; 600 601 struct tsens_sensor sensor[] __counted_by(num_sensors); 602 }; 603 604 /** 605 * struct tsens_single_value - internal representation of a single field inside nvmem calibration data 606 * @idx: index into the u32 data array 607 * @shift: the shift of the first bit in the value 608 * @blob: index of the data blob to use for this cell 609 */ 610 struct tsens_single_value { 611 u8 idx; 612 u8 shift; 613 u8 blob; 614 }; 615 616 /** 617 * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob 618 * @base_len: the length of the base fields inside calibration data 619 * @base_shift: the shift to be applied to base data 620 * @sp_len: the length of the sN_pM fields inside calibration data 621 * @mode: descriptor of the calibration mode field 622 * @invalid: descriptor of the calibration mode invalid field 623 * @base: descriptors of the base0 and base1 fields 624 * @sp: descriptors of the sN_pM fields 625 */ 626 struct tsens_legacy_calibration_format { 627 unsigned int base_len; 628 unsigned int base_shift; 629 unsigned int sp_len; 630 /* just two bits */ 631 struct tsens_single_value mode; 632 /* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */ 633 struct tsens_single_value invalid; 634 struct tsens_single_value base[2]; 635 struct tsens_single_value sp[][2]; 636 }; 637 638 char *qfprom_read(struct device *dev, const char *cname); 639 int tsens_read_calibration_legacy(struct tsens_priv *priv, 640 const struct tsens_legacy_calibration_format *format, 641 u32 *p1, u32 *p2, 642 u32 *cdata, u32 *csel); 643 int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup); 644 int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); 645 int tsens_calibrate_common(struct tsens_priv *priv); 646 void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); 647 int init_common(struct tsens_priv *priv); 648 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp); 649 int get_temp_common(const struct tsens_sensor *s, int *temp); 650 #ifdef CONFIG_SUSPEND 651 int tsens_resume_common(struct tsens_priv *priv); 652 int tsens_suspend_common(struct tsens_priv *priv); 653 #else 654 static inline int tsens_resume_common(struct tsens_priv *priv) 655 { 656 return 0; 657 } 658 659 static inline int tsens_suspend_common(struct tsens_priv *priv) 660 { 661 return 0; 662 } 663 #endif 664 665 /* TSENS target */ 666 extern struct tsens_plat_data data_8960; 667 668 /* TSENS v0.1 targets */ 669 extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607; 670 671 /* TSENS v1 targets */ 672 extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956; 673 674 /* TSENS v1 with no RPM targets */ 675 extern const struct tsens_plat_data data_ipq5018; 676 677 /* TSENS v2 targets */ 678 extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; 679 extern const struct tsens_plat_data data_ipq5332, data_ipq5424; 680 681 /* TSENS automotive targets */ 682 extern struct tsens_plat_data data_automotive_v2; 683 684 #endif /* __QCOM_TSENS_H__ */ 685