1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_LOONGARCH_H 6 #define _ASM_LOONGARCH_H 7 8 #include <linux/bits.h> 9 #include <linux/linkage.h> 10 #include <linux/types.h> 11 12 #ifndef __ASSEMBLER__ 13 #include <larchintrin.h> 14 15 /* CPUCFG */ 16 #define read_cpucfg(reg) __cpucfg(reg) 17 18 #endif /* !__ASSEMBLER__ */ 19 20 #ifdef __ASSEMBLER__ 21 22 /* LoongArch Registers */ 23 #define REG_ZERO 0x0 24 #define REG_RA 0x1 25 #define REG_TP 0x2 26 #define REG_SP 0x3 27 #define REG_A0 0x4 /* Reused as V0 for return value */ 28 #define REG_A1 0x5 /* Reused as V1 for return value */ 29 #define REG_A2 0x6 30 #define REG_A3 0x7 31 #define REG_A4 0x8 32 #define REG_A5 0x9 33 #define REG_A6 0xa 34 #define REG_A7 0xb 35 #define REG_T0 0xc 36 #define REG_T1 0xd 37 #define REG_T2 0xe 38 #define REG_T3 0xf 39 #define REG_T4 0x10 40 #define REG_T5 0x11 41 #define REG_T6 0x12 42 #define REG_T7 0x13 43 #define REG_T8 0x14 44 #define REG_U0 0x15 /* Kernel uses it as percpu base */ 45 #define REG_FP 0x16 46 #define REG_S0 0x17 47 #define REG_S1 0x18 48 #define REG_S2 0x19 49 #define REG_S3 0x1a 50 #define REG_S4 0x1b 51 #define REG_S5 0x1c 52 #define REG_S6 0x1d 53 #define REG_S7 0x1e 54 #define REG_S8 0x1f 55 56 #endif /* __ASSEMBLER__ */ 57 58 /* Bit fields for CPUCFG registers */ 59 #define LOONGARCH_CPUCFG0 0x0 60 #define CPUCFG0_PRID GENMASK(31, 0) 61 62 #define LOONGARCH_CPUCFG1 0x1 63 #define CPUCFG1_ISGR32 BIT(0) 64 #define CPUCFG1_ISGR64 BIT(1) 65 #define CPUCFG1_ISA GENMASK(1, 0) 66 #define CPUCFG1_PAGING BIT(2) 67 #define CPUCFG1_IOCSR BIT(3) 68 #define CPUCFG1_PABITS GENMASK(11, 4) 69 #define CPUCFG1_VABITS GENMASK(19, 12) 70 #define CPUCFG1_UAL BIT(20) 71 #define CPUCFG1_RI BIT(21) 72 #define CPUCFG1_EP BIT(22) 73 #define CPUCFG1_RPLV BIT(23) 74 #define CPUCFG1_HUGEPG BIT(24) 75 #define CPUCFG1_CRC32 BIT(25) 76 #define CPUCFG1_MSGINT BIT(26) 77 78 #define LOONGARCH_CPUCFG2 0x2 79 #define CPUCFG2_FP BIT(0) 80 #define CPUCFG2_FPSP BIT(1) 81 #define CPUCFG2_FPDP BIT(2) 82 #define CPUCFG2_FPVERS GENMASK(5, 3) 83 #define CPUCFG2_LSX BIT(6) 84 #define CPUCFG2_LASX BIT(7) 85 #define CPUCFG2_COMPLEX BIT(8) 86 #define CPUCFG2_CRYPTO BIT(9) 87 #define CPUCFG2_LVZP BIT(10) 88 #define CPUCFG2_LVZVER GENMASK(13, 11) 89 #define CPUCFG2_LLFTP BIT(14) 90 #define CPUCFG2_LLFTPREV GENMASK(17, 15) 91 #define CPUCFG2_X86BT BIT(18) 92 #define CPUCFG2_ARMBT BIT(19) 93 #define CPUCFG2_MIPSBT BIT(20) 94 #define CPUCFG2_LSPW BIT(21) 95 #define CPUCFG2_LAM BIT(22) 96 #define CPUCFG2_PTW BIT(24) 97 #define CPUCFG2_FRECIPE BIT(25) 98 #define CPUCFG2_DIV32 BIT(26) 99 #define CPUCFG2_LAM_BH BIT(27) 100 #define CPUCFG2_LAMCAS BIT(28) 101 #define CPUCFG2_LLACQ_SCREL BIT(29) 102 #define CPUCFG2_SCQ BIT(30) 103 104 #define LOONGARCH_CPUCFG3 0x3 105 #define CPUCFG3_CCDMA BIT(0) 106 #define CPUCFG3_SFB BIT(1) 107 #define CPUCFG3_UCACC BIT(2) 108 #define CPUCFG3_LLEXC BIT(3) 109 #define CPUCFG3_SCDLY BIT(4) 110 #define CPUCFG3_LLDBAR BIT(5) 111 #define CPUCFG3_ITLBT BIT(6) 112 #define CPUCFG3_ICACHET BIT(7) 113 #define CPUCFG3_SPW_LVL GENMASK(10, 8) 114 #define CPUCFG3_SPW_HG_HF BIT(11) 115 #define CPUCFG3_RVA BIT(12) 116 #define CPUCFG3_RVAMAX GENMASK(16, 13) 117 #define CPUCFG3_DBAR_HINTS BIT(17) 118 #define CPUCFG3_ALDORDER_CAP BIT(18) /* All address load ordered, capability */ 119 #define CPUCFG3_ASTORDER_CAP BIT(19) /* All address store ordered, capability */ 120 #define CPUCFG3_ALDORDER_STA BIT(20) /* All address load ordered, status */ 121 #define CPUCFG3_ASTORDER_STA BIT(21) /* All address store ordered, status */ 122 #define CPUCFG3_SLDORDER_CAP BIT(22) /* Same address load ordered, capability */ 123 #define CPUCFG3_SLDORDER_STA BIT(23) /* Same address load ordered, status */ 124 125 #define LOONGARCH_CPUCFG4 0x4 126 #define CPUCFG4_CCFREQ GENMASK(31, 0) 127 128 #define LOONGARCH_CPUCFG5 0x5 129 #define CPUCFG5_CCMUL GENMASK(15, 0) 130 #define CPUCFG5_CCDIV GENMASK(31, 16) 131 132 #define LOONGARCH_CPUCFG6 0x6 133 #define CPUCFG6_PMP BIT(0) 134 #define CPUCFG6_PAMVER GENMASK(3, 1) 135 #define CPUCFG6_PMNUM GENMASK(7, 4) 136 #define CPUCFG6_PMNUM_SHIFT 4 137 #define CPUCFG6_PMBITS GENMASK(13, 8) 138 #define CPUCFG6_PMBITS_SHIFT 8 139 #define CPUCFG6_UPM BIT(14) 140 141 #define LOONGARCH_CPUCFG16 0x10 142 #define CPUCFG16_L1_IUPRE BIT(0) 143 #define CPUCFG16_L1_IUUNIFY BIT(1) 144 #define CPUCFG16_L1_DPRE BIT(2) 145 #define CPUCFG16_L2_IUPRE BIT(3) 146 #define CPUCFG16_L2_IUUNIFY BIT(4) 147 #define CPUCFG16_L2_IUPRIV BIT(5) 148 #define CPUCFG16_L2_IUINCL BIT(6) 149 #define CPUCFG16_L2_DPRE BIT(7) 150 #define CPUCFG16_L2_DPRIV BIT(8) 151 #define CPUCFG16_L2_DINCL BIT(9) 152 #define CPUCFG16_L3_IUPRE BIT(10) 153 #define CPUCFG16_L3_IUUNIFY BIT(11) 154 #define CPUCFG16_L3_IUPRIV BIT(12) 155 #define CPUCFG16_L3_IUINCL BIT(13) 156 #define CPUCFG16_L3_DPRE BIT(14) 157 #define CPUCFG16_L3_DPRIV BIT(15) 158 #define CPUCFG16_L3_DINCL BIT(16) 159 160 #define LOONGARCH_CPUCFG17 0x11 161 #define LOONGARCH_CPUCFG18 0x12 162 #define LOONGARCH_CPUCFG19 0x13 163 #define LOONGARCH_CPUCFG20 0x14 164 #define CPUCFG_CACHE_WAYS_M GENMASK(15, 0) 165 #define CPUCFG_CACHE_SETS_M GENMASK(23, 16) 166 #define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24) 167 #define CPUCFG_CACHE_WAYS 0 168 #define CPUCFG_CACHE_SETS 16 169 #define CPUCFG_CACHE_LSIZE 24 170 171 #define LOONGARCH_CPUCFG48 0x30 172 #define CPUCFG48_MCSR_LCK BIT(0) 173 #define CPUCFG48_NAP_EN BIT(1) 174 #define CPUCFG48_VFPU_CG BIT(2) 175 #define CPUCFG48_RAM_CG BIT(3) 176 177 /* 178 * CPUCFG index area: 0x40000000 -- 0x400000ff 179 * SW emulation for KVM hypervirsor, see arch/loongarch/include/uapi/asm/kvm_para.h 180 */ 181 182 #ifndef __ASSEMBLER__ 183 184 /* CSR */ 185 #define csr_read32(reg) __csrrd_w(reg) 186 #define csr_read64(reg) __csrrd_d(reg) 187 #define csr_write32(val, reg) __csrwr_w(val, reg) 188 #define csr_write64(val, reg) __csrwr_d(val, reg) 189 #define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg) 190 #define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg) 191 192 #ifdef CONFIG_32BIT 193 #define csr_read(reg) csr_read32(reg) 194 #define csr_write(val, reg) csr_write32(val, reg) 195 #define csr_xchg(val, mask, reg) csr_xchg32(val, mask, reg) 196 #else 197 #define csr_read(reg) csr_read64(reg) 198 #define csr_write(val, reg) csr_write64(val, reg) 199 #define csr_xchg(val, mask, reg) csr_xchg64(val, mask, reg) 200 #endif 201 202 /* IOCSR */ 203 #define iocsr_read32(reg) __iocsrrd_w(reg) 204 #define iocsr_read64(reg) __iocsrrd_d(reg) 205 #define iocsr_write32(val, reg) __iocsrwr_w(val, reg) 206 #define iocsr_write64(val, reg) __iocsrwr_d(val, reg) 207 208 #endif /* !__ASSEMBLER__ */ 209 210 /* CSR register number */ 211 212 /* Basic CSR registers */ 213 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 214 #define CSR_CRMD_WE_SHIFT 9 215 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT) 216 #define CSR_CRMD_DACM_SHIFT 7 217 #define CSR_CRMD_DACM_WIDTH 2 218 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT) 219 #define CSR_CRMD_DACF_SHIFT 5 220 #define CSR_CRMD_DACF_WIDTH 2 221 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT) 222 #define CSR_CRMD_PG_SHIFT 4 223 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT) 224 #define CSR_CRMD_DA_SHIFT 3 225 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT) 226 #define CSR_CRMD_IE_SHIFT 2 227 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT) 228 #define CSR_CRMD_PLV_SHIFT 0 229 #define CSR_CRMD_PLV_WIDTH 2 230 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT) 231 232 #define PLV_KERN 0 233 #define PLV_USER 3 234 #define PLV_MASK 0x3 235 236 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 237 #define CSR_PRMD_PWE_SHIFT 3 238 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT) 239 #define CSR_PRMD_PIE_SHIFT 2 240 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT) 241 #define CSR_PRMD_PPLV_SHIFT 0 242 #define CSR_PRMD_PPLV_WIDTH 2 243 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT) 244 245 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */ 246 #define CSR_EUEN_LBTEN_SHIFT 3 247 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT) 248 #define CSR_EUEN_LASXEN_SHIFT 2 249 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT) 250 #define CSR_EUEN_LSXEN_SHIFT 1 251 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT) 252 #define CSR_EUEN_FPEN_SHIFT 0 253 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT) 254 255 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */ 256 257 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ 258 #define CSR_ECFG_VS_SHIFT 16 259 #define CSR_ECFG_VS_WIDTH 3 260 #define CSR_ECFG_VS_SHIFT_END (CSR_ECFG_VS_SHIFT + CSR_ECFG_VS_WIDTH - 1) 261 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT) 262 #define CSR_ECFG_IM_SHIFT 0 263 #define CSR_ECFG_IM_WIDTH 14 264 #define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT) 265 266 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 267 #define CSR_ESTAT_ESUBCODE_SHIFT 22 268 #define CSR_ESTAT_ESUBCODE_WIDTH 9 269 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT) 270 #define CSR_ESTAT_EXC_SHIFT 16 271 #define CSR_ESTAT_EXC_WIDTH 6 272 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT) 273 #define CSR_ESTAT_IS_SHIFT 0 274 #define CSR_ESTAT_IS_WIDTH 15 275 #define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT) 276 277 #define LOONGARCH_CSR_ERA 0x6 /* Exception return address */ 278 279 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 280 281 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */ 282 283 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */ 284 285 /* TLB related CSR registers */ 286 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */ 287 #define CSR_TLBIDX_EHINV_SHIFT 31 288 #define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT) 289 #define CSR_TLBIDX_PS_SHIFT 24 290 #define CSR_TLBIDX_PS_WIDTH 6 291 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT) 292 #define CSR_TLBIDX_IDX_SHIFT 0 293 #define CSR_TLBIDX_IDX_WIDTH 12 294 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT) 295 #define CSR_TLBIDX_SIZEM 0x3f000000 296 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT 297 #define CSR_TLBIDX_IDXM 0xfff 298 #define CSR_INVALID_ENTRY(e) (CSR_TLBIDX_EHINV | e) 299 300 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ 301 302 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ 303 #define CSR_TLBLO0_RPLV_SHIFT 63 304 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT) 305 #define CSR_TLBLO0_NX_SHIFT 62 306 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT) 307 #define CSR_TLBLO0_NR_SHIFT 61 308 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT) 309 #define CSR_TLBLO0_PFN_SHIFT 12 310 #define CSR_TLBLO0_PFN_WIDTH 36 311 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT) 312 #define CSR_TLBLO0_GLOBAL_SHIFT 6 313 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT) 314 #define CSR_TLBLO0_CCA_SHIFT 4 315 #define CSR_TLBLO0_CCA_WIDTH 2 316 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT) 317 #define CSR_TLBLO0_PLV_SHIFT 2 318 #define CSR_TLBLO0_PLV_WIDTH 2 319 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT) 320 #define CSR_TLBLO0_WE_SHIFT 1 321 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT) 322 #define CSR_TLBLO0_V_SHIFT 0 323 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT) 324 325 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ 326 #define CSR_TLBLO1_RPLV_SHIFT 63 327 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT) 328 #define CSR_TLBLO1_NX_SHIFT 62 329 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT) 330 #define CSR_TLBLO1_NR_SHIFT 61 331 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT) 332 #define CSR_TLBLO1_PFN_SHIFT 12 333 #define CSR_TLBLO1_PFN_WIDTH 36 334 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT) 335 #define CSR_TLBLO1_GLOBAL_SHIFT 6 336 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT) 337 #define CSR_TLBLO1_CCA_SHIFT 4 338 #define CSR_TLBLO1_CCA_WIDTH 2 339 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT) 340 #define CSR_TLBLO1_PLV_SHIFT 2 341 #define CSR_TLBLO1_PLV_WIDTH 2 342 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT) 343 #define CSR_TLBLO1_WE_SHIFT 1 344 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT) 345 #define CSR_TLBLO1_V_SHIFT 0 346 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT) 347 348 #define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */ 349 #define CSR_GTLBC_TGID_SHIFT 16 350 #define CSR_GTLBC_TGID_WIDTH 8 351 #define CSR_GTLBC_TGID_SHIFT_END (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1) 352 #define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT) 353 #define CSR_GTLBC_TOTI_SHIFT 13 354 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT) 355 #define CSR_GTLBC_USETGID_SHIFT 12 356 #define CSR_GTLBC_USETGID (_ULCAST_(0x1) << CSR_GTLBC_USETGID_SHIFT) 357 #define CSR_GTLBC_GMTLBSZ_SHIFT 0 358 #define CSR_GTLBC_GMTLBSZ_WIDTH 6 359 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT) 360 361 #define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */ 362 #define CSR_TRGP_RID_SHIFT 16 363 #define CSR_TRGP_RID_WIDTH 8 364 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT) 365 #define CSR_TRGP_GTLB_SHIFT 0 366 #define CSR_TRGP_GTLB (1 << CSR_TRGP_GTLB_SHIFT) 367 368 #define LOONGARCH_CSR_ASID 0x18 /* ASID */ 369 #define CSR_ASID_BIT_SHIFT 16 /* ASIDBits */ 370 #define CSR_ASID_BIT_WIDTH 8 371 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT) 372 #define CSR_ASID_ASID_SHIFT 0 373 #define CSR_ASID_ASID_WIDTH 10 374 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT) 375 376 #define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */ 377 378 #define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */ 379 380 #define LOONGARCH_CSR_PGD 0x1b /* Page table base */ 381 382 #define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */ 383 #define CSR_PWCTL0_PTEW_SHIFT 30 384 #define CSR_PWCTL0_PTEW_WIDTH 2 385 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT) 386 #define CSR_PWCTL0_DIR1WIDTH_SHIFT 25 387 #define CSR_PWCTL0_DIR1WIDTH_WIDTH 5 388 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT) 389 #define CSR_PWCTL0_DIR1BASE_SHIFT 20 390 #define CSR_PWCTL0_DIR1BASE_WIDTH 5 391 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT) 392 #define CSR_PWCTL0_DIR0WIDTH_SHIFT 15 393 #define CSR_PWCTL0_DIR0WIDTH_WIDTH 5 394 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT) 395 #define CSR_PWCTL0_DIR0BASE_SHIFT 10 396 #define CSR_PWCTL0_DIR0BASE_WIDTH 5 397 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT) 398 #define CSR_PWCTL0_PTWIDTH_SHIFT 5 399 #define CSR_PWCTL0_PTWIDTH_WIDTH 5 400 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT) 401 #define CSR_PWCTL0_PTBASE_SHIFT 0 402 #define CSR_PWCTL0_PTBASE_WIDTH 5 403 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT) 404 405 #define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */ 406 #define CSR_PWCTL1_PTW_SHIFT 24 407 #define CSR_PWCTL1_PTW_WIDTH 1 408 #define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT) 409 #define CSR_PWCTL1_DIR3WIDTH_SHIFT 18 410 #define CSR_PWCTL1_DIR3WIDTH_WIDTH 5 411 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT) 412 #define CSR_PWCTL1_DIR3BASE_SHIFT 12 413 #define CSR_PWCTL1_DIR3BASE_WIDTH 5 414 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT) 415 #define CSR_PWCTL1_DIR2WIDTH_SHIFT 6 416 #define CSR_PWCTL1_DIR2WIDTH_WIDTH 5 417 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT) 418 #define CSR_PWCTL1_DIR2BASE_SHIFT 0 419 #define CSR_PWCTL1_DIR2BASE_WIDTH 5 420 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT) 421 422 #define LOONGARCH_CSR_STLBPGSIZE 0x1e 423 #define CSR_STLBPGSIZE_PS_WIDTH 6 424 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f)) 425 426 #define LOONGARCH_CSR_RVACFG 0x1f 427 #define CSR_RVACFG_RDVA_WIDTH 4 428 #define CSR_RVACFG_RDVA (_ULCAST_(0xf)) 429 430 /* Config CSR registers */ 431 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */ 432 #define CSR_CPUID_COREID_WIDTH 11 433 #define CSR_CPUID_COREID _ULCAST_(0x7ff) 434 435 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */ 436 #define CSR_CONF1_VSMAX_SHIFT 12 437 #define CSR_CONF1_VSMAX_WIDTH 3 438 #define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT) 439 #define CSR_CONF1_TMRBITS_SHIFT 4 440 #define CSR_CONF1_TMRBITS_WIDTH 8 441 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT) 442 #define CSR_CONF1_KSNUM_WIDTH 4 443 #define CSR_CONF1_KSNUM _ULCAST_(0xf) 444 445 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */ 446 #define CSR_CONF2_PGMASK_SUPP 0x3ffff000 447 448 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */ 449 #define CSR_CONF3_STLBIDX_SHIFT 20 450 #define CSR_CONF3_STLBIDX_WIDTH 6 451 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT) 452 #define CSR_CONF3_STLBWAYS_SHIFT 12 453 #define CSR_CONF3_STLBWAYS_WIDTH 8 454 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT) 455 #define CSR_CONF3_MTLBSIZE_SHIFT 4 456 #define CSR_CONF3_MTLBSIZE_WIDTH 8 457 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT) 458 #define CSR_CONF3_TLBTYPE_SHIFT 0 459 #define CSR_CONF3_TLBTYPE_WIDTH 4 460 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT) 461 462 /* KSave registers */ 463 #define LOONGARCH_CSR_KS0 0x30 464 #define LOONGARCH_CSR_KS1 0x31 465 #define LOONGARCH_CSR_KS2 0x32 466 #define LOONGARCH_CSR_KS3 0x33 467 #define LOONGARCH_CSR_KS4 0x34 468 #define LOONGARCH_CSR_KS5 0x35 469 #define LOONGARCH_CSR_KS6 0x36 470 #define LOONGARCH_CSR_KS7 0x37 471 #define LOONGARCH_CSR_KS8 0x38 472 #define LOONGARCH_CSR_KS9 0x39 473 #define LOONGARCH_CSR_KS10 0x3a 474 #define LOONGARCH_CSR_KS11 0x3b 475 #define LOONGARCH_CSR_KS12 0x3c 476 #define LOONGARCH_CSR_KS13 0x3d 477 #define LOONGARCH_CSR_KS14 0x3e 478 #define LOONGARCH_CSR_KS15 0x3f 479 480 /* Exception allocated KS0, KS1 and KS2 statically */ 481 #define EXCEPTION_KS0 LOONGARCH_CSR_KS0 482 #define EXCEPTION_KS1 LOONGARCH_CSR_KS1 483 #define EXCEPTION_KS2 LOONGARCH_CSR_KS2 484 #define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2) 485 486 /* Percpu-data base allocated KS3 statically */ 487 #define PERCPU_BASE_KS LOONGARCH_CSR_KS3 488 #define PERCPU_KSAVE_MASK (1 << 3) 489 490 /* KVM allocated KS4 and KS5 statically */ 491 #define KVM_VCPU_KS LOONGARCH_CSR_KS4 492 #define KVM_TEMP_KS LOONGARCH_CSR_KS5 493 #define KVM_KSAVE_MASK (1 << 4 | 1 << 5) 494 495 /* Timer registers */ 496 #define LOONGARCH_CSR_TMID 0x40 /* Timer ID */ 497 498 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ 499 #define CSR_TCFG_VAL_SHIFT 2 500 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT) 501 #define CSR_TCFG_PERIOD_SHIFT 1 502 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT) 503 #define CSR_TCFG_EN (_ULCAST_(0x1)) 504 505 #define LOONGARCH_CSR_TVAL 0x42 /* Timer value */ 506 507 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */ 508 509 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */ 510 #define CSR_TINTCLR_TI_SHIFT 0 511 #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT) 512 513 /* Guest registers */ 514 #define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */ 515 #define CSR_GSTAT_GID_SHIFT 16 516 #define CSR_GSTAT_GID_WIDTH 8 517 #define CSR_GSTAT_GID_SHIFT_END (CSR_GSTAT_GID_SHIFT + CSR_GSTAT_GID_WIDTH - 1) 518 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT) 519 #define CSR_GSTAT_GIDBIT_SHIFT 4 520 #define CSR_GSTAT_GIDBIT_WIDTH 6 521 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT) 522 #define CSR_GSTAT_PVM_SHIFT 1 523 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT) 524 #define CSR_GSTAT_VM_SHIFT 0 525 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT) 526 527 #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ 528 #define CSR_GCFG_GPERF_SHIFT 24 529 #define CSR_GCFG_GPERF_WIDTH 3 530 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) 531 #define CSR_GCFG_GPMP_SHIFT 23 532 #define CSR_GCFG_GPMP (_ULCAST_(0x1) << CSR_GCFG_GPMP_SHIFT) 533 #define CSR_GCFG_GCI_SHIFT 20 534 #define CSR_GCFG_GCI_WIDTH 2 535 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) 536 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) 537 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) 538 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) 539 #define CSR_GCFG_GCIP_SHIFT 16 540 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) 541 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) 542 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) 543 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) 544 #define CSR_GCFG_TORU_SHIFT 15 545 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) 546 #define CSR_GCFG_TORUP_SHIFT 14 547 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) 548 #define CSR_GCFG_TOP_SHIFT 13 549 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) 550 #define CSR_GCFG_TOPP_SHIFT 12 551 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) 552 #define CSR_GCFG_TOE_SHIFT 11 553 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) 554 #define CSR_GCFG_TOEP_SHIFT 10 555 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) 556 #define CSR_GCFG_TIT_SHIFT 9 557 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) 558 #define CSR_GCFG_TITP_SHIFT 8 559 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) 560 #define CSR_GCFG_SIT_SHIFT 7 561 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) 562 #define CSR_GCFG_SITP_SHIFT 6 563 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) 564 #define CSR_GCFG_MATC_SHITF 4 565 #define CSR_GCFG_MATC_WIDTH 2 566 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) 567 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) 568 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) 569 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) 570 #define CSR_GCFG_MATP_NEST_SHIFT 2 571 #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) 572 #define CSR_GCFG_MATP_ROOT_SHIFT 1 573 #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) 574 #define CSR_GCFG_MATP_GUEST_SHIFT 0 575 #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) 576 577 #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ 578 #define CSR_GINTC_HC_SHIFT 16 579 #define CSR_GINTC_HC_WIDTH 8 580 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT) 581 #define CSR_GINTC_PIP_SHIFT 8 582 #define CSR_GINTC_PIP_WIDTH 8 583 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT) 584 #define CSR_GINTC_VIP_SHIFT 0 585 #define CSR_GINTC_VIP_WIDTH 8 586 #define CSR_GINTC_VIP (_ULCAST_(0xff)) 587 588 #define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */ 589 590 /* LLBCTL register */ 591 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */ 592 #define CSR_LLBCTL_ROLLB_SHIFT 0 593 #define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT) 594 #define CSR_LLBCTL_WCLLB_SHIFT 1 595 #define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT) 596 #define CSR_LLBCTL_KLO_SHIFT 2 597 #define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT) 598 599 /* Implement dependent */ 600 #define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */ 601 #define CSR_LDSTORDER_SHIFT 28 602 #define CSR_LDSTORDER_WIDTH 3 603 #define CSR_LDSTORDER_MASK (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT) 604 #define CSR_LDSTORDER_NLD_NST (_ULCAST_(0x0) << CSR_LDSTORDER_SHIFT) /* 000 = No Load No Store */ 605 #define CSR_LDSTORDER_ALD_NST (_ULCAST_(0x1) << CSR_LDSTORDER_SHIFT) /* 001 = All Load No Store */ 606 #define CSR_LDSTORDER_SLD_NST (_ULCAST_(0x3) << CSR_LDSTORDER_SHIFT) /* 011 = Same Load No Store */ 607 #define CSR_LDSTORDER_NLD_AST (_ULCAST_(0x4) << CSR_LDSTORDER_SHIFT) /* 100 = No Load All Store */ 608 #define CSR_LDSTORDER_ALD_AST (_ULCAST_(0x5) << CSR_LDSTORDER_SHIFT) /* 101 = All Load All Store */ 609 #define CSR_LDSTORDER_SLD_AST (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT) /* 111 = Same Load All Store */ 610 #define CSR_MISPEC_SHIFT 20 611 #define CSR_MISPEC_WIDTH 8 612 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT) 613 #define CSR_SSEN_SHIFT 18 614 #define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT) 615 #define CSR_SCRAND_SHIFT 17 616 #define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT) 617 #define CSR_LLEXCL_SHIFT 16 618 #define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT) 619 #define CSR_DISVC_SHIFT 15 620 #define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT) 621 #define CSR_VCLRU_SHIFT 14 622 #define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT) 623 #define CSR_DCLRU_SHIFT 13 624 #define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT) 625 #define CSR_FASTLDQ_SHIFT 12 626 #define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT) 627 #define CSR_USERCAC_SHIFT 11 628 #define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT) 629 #define CSR_ANTI_MISPEC_SHIFT 10 630 #define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT) 631 #define CSR_AUTO_FLUSHSFB_SHIFT 9 632 #define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT) 633 #define CSR_STFILL_SHIFT 8 634 #define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT) 635 #define CSR_LIFEP_SHIFT 7 636 #define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT) 637 #define CSR_LLSYNC_SHIFT 6 638 #define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT) 639 #define CSR_BRBTDIS_SHIFT 5 640 #define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT) 641 #define CSR_RASDIS_SHIFT 4 642 #define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT) 643 #define CSR_STPRE_SHIFT 2 644 #define CSR_STPRE_WIDTH 2 645 #define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT) 646 #define CSR_INSTPRE_SHIFT 1 647 #define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT) 648 #define CSR_DATAPRE_SHIFT 0 649 #define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT) 650 651 #define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */ 652 #define CSR_FLUSH_MTLB_SHIFT 0 653 #define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT) 654 #define CSR_FLUSH_STLB_SHIFT 1 655 #define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT) 656 #define CSR_FLUSH_DTLB_SHIFT 2 657 #define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT) 658 #define CSR_FLUSH_ITLB_SHIFT 3 659 #define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT) 660 #define CSR_FLUSH_BTAC_SHIFT 4 661 #define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT) 662 663 #define LOONGARCH_CSR_GNMI 0x82 664 665 /* TLB Refill registers */ 666 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */ 667 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */ 668 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */ 669 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */ 670 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */ 671 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ 672 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ 673 #define CSR_TLBREHI_PS_SHIFT 0 674 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT) 675 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ 676 677 /* Machine Error registers */ 678 #define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */ 679 #define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */ 680 #define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */ 681 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */ 682 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */ 683 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */ 684 685 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ 686 687 #define LOONGARCH_CSR_ISR0 0xa0 688 #define LOONGARCH_CSR_ISR1 0xa1 689 #define LOONGARCH_CSR_ISR2 0xa2 690 #define LOONGARCH_CSR_ISR3 0xa3 691 692 #define LOONGARCH_CSR_IRR 0xa4 693 #define LOONGARCH_CSR_IPR 0xa5 694 695 #define LOONGARCH_CSR_PRID 0xc0 696 697 /* Shadow MCSR : 0xc0 ~ 0xff */ 698 #define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */ 699 #define MCSR0_INT_IMPL_SHIFT 58 700 #define MCSR0_INT_IMPL 0 701 #define MCSR0_IOCSR_BRD_SHIFT 57 702 #define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT) 703 #define MCSR0_HUGEPG_SHIFT 56 704 #define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT) 705 #define MCSR0_RPLMTLB_SHIFT 55 706 #define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT) 707 #define MCSR0_EP_SHIFT 54 708 #define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT) 709 #define MCSR0_RI_SHIFT 53 710 #define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT) 711 #define MCSR0_UAL_SHIFT 52 712 #define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT) 713 #define MCSR0_VABIT_SHIFT 44 714 #define MCSR0_VABIT_WIDTH 8 715 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT) 716 #define VABIT_DEFAULT 0x2f 717 #define MCSR0_PABIT_SHIFT 36 718 #define MCSR0_PABIT_WIDTH 8 719 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT) 720 #define PABIT_DEFAULT 0x2f 721 #define MCSR0_IOCSR_SHIFT 35 722 #define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT) 723 #define MCSR0_PAGING_SHIFT 34 724 #define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT) 725 #define MCSR0_GR64_SHIFT 33 726 #define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT) 727 #define GR64_DEFAULT 1 728 #define MCSR0_GR32_SHIFT 32 729 #define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT) 730 #define GR32_DEFAULT 0 731 #define MCSR0_PRID_WIDTH 32 732 #define MCSR0_PRID 0x14C010 733 734 #define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */ 735 #define MCSR1_HPFOLD_SHIFT 43 736 #define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT) 737 #define MCSR1_SPW_LVL_SHIFT 40 738 #define MCSR1_SPW_LVL_WIDTH 3 739 #define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT) 740 #define MCSR1_ICACHET_SHIFT 39 741 #define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT) 742 #define MCSR1_ITLBT_SHIFT 38 743 #define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT) 744 #define MCSR1_LLDBAR_SHIFT 37 745 #define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT) 746 #define MCSR1_SCDLY_SHIFT 36 747 #define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT) 748 #define MCSR1_LLEXC_SHIFT 35 749 #define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT) 750 #define MCSR1_UCACC_SHIFT 34 751 #define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT) 752 #define MCSR1_SFB_SHIFT 33 753 #define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT) 754 #define MCSR1_CCDMA_SHIFT 32 755 #define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT) 756 #define MCSR1_LAMO_SHIFT 22 757 #define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT) 758 #define MCSR1_LSPW_SHIFT 21 759 #define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT) 760 #define MCSR1_MIPSBT_SHIFT 20 761 #define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT) 762 #define MCSR1_ARMBT_SHIFT 19 763 #define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT) 764 #define MCSR1_X86BT_SHIFT 18 765 #define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT) 766 #define MCSR1_LLFTPVERS_SHIFT 15 767 #define MCSR1_LLFTPVERS_WIDTH 3 768 #define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT) 769 #define MCSR1_LLFTP_SHIFT 14 770 #define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT) 771 #define MCSR1_VZVERS_SHIFT 11 772 #define MCSR1_VZVERS_WIDTH 3 773 #define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT) 774 #define MCSR1_VZ_SHIFT 10 775 #define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT) 776 #define MCSR1_CRYPTO_SHIFT 9 777 #define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT) 778 #define MCSR1_COMPLEX_SHIFT 8 779 #define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT) 780 #define MCSR1_LASX_SHIFT 7 781 #define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT) 782 #define MCSR1_LSX_SHIFT 6 783 #define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT) 784 #define MCSR1_FPVERS_SHIFT 3 785 #define MCSR1_FPVERS_WIDTH 3 786 #define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT) 787 #define MCSR1_FPDP_SHIFT 2 788 #define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT) 789 #define MCSR1_FPSP_SHIFT 1 790 #define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT) 791 #define MCSR1_FP_SHIFT 0 792 #define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT) 793 794 #define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */ 795 #define MCSR2_CCDIV_SHIFT 48 796 #define MCSR2_CCDIV_WIDTH 16 797 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT) 798 #define MCSR2_CCMUL_SHIFT 32 799 #define MCSR2_CCMUL_WIDTH 16 800 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT) 801 #define MCSR2_CCFREQ_WIDTH 32 802 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff)) 803 #define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */ 804 805 #define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */ 806 #define MCSR3_UPM_SHIFT 14 807 #define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT) 808 #define MCSR3_PMBITS_SHIFT 8 809 #define MCSR3_PMBITS_WIDTH 6 810 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT) 811 #define PMBITS_DEFAULT 0x40 812 #define MCSR3_PMNUM_SHIFT 4 813 #define MCSR3_PMNUM_WIDTH 4 814 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT) 815 #define MCSR3_PAMVER_SHIFT 1 816 #define MCSR3_PAMVER_WIDTH 3 817 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT) 818 #define MCSR3_PMP_SHIFT 0 819 #define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT) 820 821 #define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */ 822 #define MCSR8_L1I_SIZE_SHIFT 56 823 #define MCSR8_L1I_SIZE_WIDTH 7 824 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT) 825 #define MCSR8_L1I_IDX_SHIFT 48 826 #define MCSR8_L1I_IDX_WIDTH 8 827 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT) 828 #define MCSR8_L1I_WAY_SHIFT 32 829 #define MCSR8_L1I_WAY_WIDTH 16 830 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT) 831 #define MCSR8_L3DINCL_SHIFT 16 832 #define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT) 833 #define MCSR8_L3DPRIV_SHIFT 15 834 #define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT) 835 #define MCSR8_L3DPRE_SHIFT 14 836 #define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT) 837 #define MCSR8_L3IUINCL_SHIFT 13 838 #define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT) 839 #define MCSR8_L3IUPRIV_SHIFT 12 840 #define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT) 841 #define MCSR8_L3IUUNIFY_SHIFT 11 842 #define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT) 843 #define MCSR8_L3IUPRE_SHIFT 10 844 #define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT) 845 #define MCSR8_L2DINCL_SHIFT 9 846 #define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT) 847 #define MCSR8_L2DPRIV_SHIFT 8 848 #define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT) 849 #define MCSR8_L2DPRE_SHIFT 7 850 #define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT) 851 #define MCSR8_L2IUINCL_SHIFT 6 852 #define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT) 853 #define MCSR8_L2IUPRIV_SHIFT 5 854 #define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT) 855 #define MCSR8_L2IUUNIFY_SHIFT 4 856 #define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT) 857 #define MCSR8_L2IUPRE_SHIFT 3 858 #define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT) 859 #define MCSR8_L1DPRE_SHIFT 2 860 #define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT) 861 #define MCSR8_L1IUUNIFY_SHIFT 1 862 #define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT) 863 #define MCSR8_L1IUPRE_SHIFT 0 864 #define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT) 865 866 #define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */ 867 #define MCSR9_L2U_SIZE_SHIFT 56 868 #define MCSR9_L2U_SIZE_WIDTH 7 869 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT) 870 #define MCSR9_L2U_IDX_SHIFT 48 871 #define MCSR9_L2U_IDX_WIDTH 8 872 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT) 873 #define MCSR9_L2U_WAY_SHIFT 32 874 #define MCSR9_L2U_WAY_WIDTH 16 875 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT) 876 #define MCSR9_L1D_SIZE_SHIFT 24 877 #define MCSR9_L1D_SIZE_WIDTH 7 878 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT) 879 #define MCSR9_L1D_IDX_SHIFT 16 880 #define MCSR9_L1D_IDX_WIDTH 8 881 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT) 882 #define MCSR9_L1D_WAY_SHIFT 0 883 #define MCSR9_L1D_WAY_WIDTH 16 884 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT) 885 886 #define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */ 887 #define MCSR10_L3U_SIZE_SHIFT 24 888 #define MCSR10_L3U_SIZE_WIDTH 7 889 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT) 890 #define MCSR10_L3U_IDX_SHIFT 16 891 #define MCSR10_L3U_IDX_WIDTH 8 892 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT) 893 #define MCSR10_L3U_WAY_SHIFT 0 894 #define MCSR10_L3U_WAY_WIDTH 16 895 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT) 896 897 #define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */ 898 #define MCSR24_RAMCG_SHIFT 3 899 #define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT) 900 #define MCSR24_VFPUCG_SHIFT 2 901 #define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT) 902 #define MCSR24_NAPEN_SHIFT 1 903 #define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT) 904 #define MCSR24_MCSRLOCK_SHIFT 0 905 #define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT) 906 907 /* Uncached accelerate windows registers */ 908 #define LOONGARCH_CSR_UCAWIN 0x100 909 #define LOONGARCH_CSR_UCAWIN0_LO 0x102 910 #define LOONGARCH_CSR_UCAWIN0_HI 0x103 911 #define LOONGARCH_CSR_UCAWIN1_LO 0x104 912 #define LOONGARCH_CSR_UCAWIN1_HI 0x105 913 #define LOONGARCH_CSR_UCAWIN2_LO 0x106 914 #define LOONGARCH_CSR_UCAWIN2_HI 0x107 915 #define LOONGARCH_CSR_UCAWIN3_LO 0x108 916 #define LOONGARCH_CSR_UCAWIN3_HI 0x109 917 918 /* Direct Map windows registers */ 919 #define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */ 920 #define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */ 921 #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */ 922 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */ 923 924 /* Direct Map window 0/1/2/3 */ 925 926 #ifdef CONFIG_32BIT 927 928 #define CSR_DMW0_PLV0 (1 << 0) 929 #define CSR_DMW0_VSEG (0x4) 930 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) 931 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0) 932 933 #define CSR_DMW1_PLV0 (1 << 0) 934 #define CSR_DMW1_MAT (1 << 4) 935 #define CSR_DMW1_VSEG (0x5) 936 #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) 937 #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) 938 939 #define CSR_DMW2_INIT 0x0 940 941 #define CSR_DMW3_INIT 0x0 942 943 #else 944 945 #define CSR_DMW0_PLV0 _CONST64_(1 << 0) 946 #define CSR_DMW0_VSEG _CONST64_(0x8000) 947 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) 948 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0) 949 950 #define CSR_DMW1_PLV0 _CONST64_(1 << 0) 951 #define CSR_DMW1_MAT _CONST64_(1 << 4) 952 #define CSR_DMW1_VSEG _CONST64_(0x9000) 953 #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) 954 #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) 955 956 #define CSR_DMW2_PLV0 _CONST64_(1 << 0) 957 #define CSR_DMW2_MAT _CONST64_(2 << 4) 958 #define CSR_DMW2_VSEG _CONST64_(0xa000) 959 #define CSR_DMW2_BASE (CSR_DMW2_VSEG << DMW_PABITS) 960 #define CSR_DMW2_INIT (CSR_DMW2_BASE | CSR_DMW2_MAT | CSR_DMW2_PLV0) 961 962 #define CSR_DMW3_INIT 0x0 963 964 #endif 965 966 /* Performance Counter registers */ 967 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */ 968 #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */ 969 #define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */ 970 #define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */ 971 #define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */ 972 #define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */ 973 #define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */ 974 #define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */ 975 #define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16) 976 #define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17) 977 #define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18) 978 #define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19) 979 #define CSR_PERFCTRL_IE (_ULCAST_(1) << 20) 980 #define CSR_PERFCTRL_EVENT 0x3ff 981 982 /* Debug registers */ 983 #define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */ 984 #define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */ 985 986 #define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */ 987 #define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */ 988 #define LOONGARCH_CSR_DB0CTRL 0x312 /* data breakpoint 0 control */ 989 #define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */ 990 991 #define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */ 992 #define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */ 993 #define LOONGARCH_CSR_DB1CTRL 0x31a /* data breakpoint 1 control */ 994 #define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */ 995 996 #define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */ 997 #define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */ 998 #define LOONGARCH_CSR_DB2CTRL 0x322 /* data breakpoint 2 control */ 999 #define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */ 1000 1001 #define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */ 1002 #define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */ 1003 #define LOONGARCH_CSR_DB3CTRL 0x32a /* data breakpoint 3 control */ 1004 #define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */ 1005 1006 #define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */ 1007 #define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */ 1008 #define LOONGARCH_CSR_DB4CTRL 0x332 /* data breakpoint 4 control */ 1009 #define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */ 1010 1011 #define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */ 1012 #define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */ 1013 #define LOONGARCH_CSR_DB5CTRL 0x33a /* data breakpoint 5 control */ 1014 #define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */ 1015 1016 #define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */ 1017 #define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */ 1018 #define LOONGARCH_CSR_DB6CTRL 0x342 /* data breakpoint 6 control */ 1019 #define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */ 1020 1021 #define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */ 1022 #define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */ 1023 #define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */ 1024 #define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */ 1025 1026 #define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */ 1027 #define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */ 1028 #define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */ 1029 #define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */ 1030 1031 #define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */ 1032 #define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */ 1033 #define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */ 1034 #define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */ 1035 1036 #define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */ 1037 #define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */ 1038 #define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */ 1039 #define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */ 1040 1041 #define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */ 1042 #define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */ 1043 #define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */ 1044 #define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */ 1045 1046 #define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */ 1047 #define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */ 1048 #define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */ 1049 #define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */ 1050 1051 #define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */ 1052 #define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */ 1053 #define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */ 1054 #define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */ 1055 1056 #define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */ 1057 #define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */ 1058 1059 #define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */ 1060 #define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */ 1061 #define LOONGARCH_CSR_IB0CTRL 0x392 /* inst breakpoint 0 control */ 1062 #define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */ 1063 1064 #define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */ 1065 #define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */ 1066 #define LOONGARCH_CSR_IB1CTRL 0x39a /* inst breakpoint 1 control */ 1067 #define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */ 1068 1069 #define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */ 1070 #define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */ 1071 #define LOONGARCH_CSR_IB2CTRL 0x3a2 /* inst breakpoint 2 control */ 1072 #define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */ 1073 1074 #define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */ 1075 #define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */ 1076 #define LOONGARCH_CSR_IB3CTRL 0x3aa /* inst breakpoint 3 control */ 1077 #define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */ 1078 1079 #define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */ 1080 #define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */ 1081 #define LOONGARCH_CSR_IB4CTRL 0x3b2 /* inst breakpoint 4 control */ 1082 #define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */ 1083 1084 #define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */ 1085 #define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */ 1086 #define LOONGARCH_CSR_IB5CTRL 0x3ba /* inst breakpoint 5 control */ 1087 #define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */ 1088 1089 #define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */ 1090 #define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */ 1091 #define LOONGARCH_CSR_IB6CTRL 0x3c2 /* inst breakpoint 6 control */ 1092 #define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */ 1093 1094 #define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */ 1095 #define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */ 1096 #define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */ 1097 #define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */ 1098 1099 #define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */ 1100 #define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */ 1101 #define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */ 1102 #define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */ 1103 1104 #define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */ 1105 #define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */ 1106 #define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */ 1107 #define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */ 1108 1109 #define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */ 1110 #define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */ 1111 #define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */ 1112 #define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */ 1113 1114 #define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */ 1115 #define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */ 1116 #define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */ 1117 #define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */ 1118 1119 #define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */ 1120 #define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */ 1121 #define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */ 1122 #define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */ 1123 1124 #define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */ 1125 #define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */ 1126 #define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */ 1127 #define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */ 1128 1129 #define LOONGARCH_CSR_DEBUG 0x500 /* debug config */ 1130 #define LOONGARCH_CSR_DERA 0x501 /* debug era */ 1131 #define LOONGARCH_CSR_DESAVE 0x502 /* debug save */ 1132 1133 #define CSR_FWPC_SKIP_SHIFT 16 1134 #define CSR_FWPC_SKIP (_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT) 1135 1136 /* 1137 * CSR_ECFG IM 1138 */ 1139 #define ECFG0_IM 0x00005fff 1140 #define ECFGB_SIP0 0 1141 #define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0) 1142 #define ECFGB_SIP1 1 1143 #define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1) 1144 #define ECFGB_IP0 2 1145 #define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0) 1146 #define ECFGB_IP1 3 1147 #define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1) 1148 #define ECFGB_IP2 4 1149 #define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2) 1150 #define ECFGB_IP3 5 1151 #define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3) 1152 #define ECFGB_IP4 6 1153 #define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4) 1154 #define ECFGB_IP5 7 1155 #define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5) 1156 #define ECFGB_IP6 8 1157 #define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6) 1158 #define ECFGB_IP7 9 1159 #define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7) 1160 #define ECFGB_PMC 10 1161 #define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC) 1162 #define ECFGB_TIMER 11 1163 #define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER) 1164 #define ECFGB_IPI 12 1165 #define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI) 1166 #define ECFGF(hwirq) (_ULCAST_(1) << hwirq) 1167 1168 #define ESTATF_IP 0x00003fff 1169 1170 #define LOONGARCH_IOCSR_FEATURES 0x8 1171 #define IOCSRF_TEMP BIT_ULL(0) 1172 #define IOCSRF_NODECNT BIT_ULL(1) 1173 #define IOCSRF_MSI BIT_ULL(2) 1174 #define IOCSRF_EXTIOI BIT_ULL(3) 1175 #define IOCSRF_CSRIPI BIT_ULL(4) 1176 #define IOCSRF_FREQCSR BIT_ULL(5) 1177 #define IOCSRF_FREQSCALE BIT_ULL(6) 1178 #define IOCSRF_DVFSV1 BIT_ULL(7) 1179 #define IOCSRF_EIODECODE BIT_ULL(9) 1180 #define IOCSRF_FLATMODE BIT_ULL(10) 1181 #define IOCSRF_VM BIT_ULL(11) 1182 #define IOCSRF_AVEC BIT_ULL(15) 1183 #define IOCSRF_REDIRECT BIT_ULL(16) 1184 1185 #define LOONGARCH_IOCSR_VENDOR 0x10 1186 1187 #define LOONGARCH_IOCSR_CPUNAME 0x20 1188 1189 #define LOONGARCH_IOCSR_NODECNT 0x408 1190 1191 #define LOONGARCH_IOCSR_MISC_FUNC 0x420 1192 #define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10) 1193 #define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21) 1194 #define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48) 1195 #define IOCSR_MISC_FUNC_AVEC_EN BIT_ULL(51) 1196 1197 #define LOONGARCH_IOCSR_CPUTEMP 0x428 1198 1199 #define LOONGARCH_IOCSR_SMCMBX 0x51c 1200 1201 /* PerCore CSR, only accessible by local cores */ 1202 #define LOONGARCH_IOCSR_IPI_STATUS 0x1000 1203 #define LOONGARCH_IOCSR_IPI_EN 0x1004 1204 #define LOONGARCH_IOCSR_IPI_SET 0x1008 1205 #define LOONGARCH_IOCSR_IPI_CLEAR 0x100c 1206 #define LOONGARCH_IOCSR_MBUF0 0x1020 1207 #define LOONGARCH_IOCSR_MBUF1 0x1028 1208 #define LOONGARCH_IOCSR_MBUF2 0x1030 1209 #define LOONGARCH_IOCSR_MBUF3 0x1038 1210 1211 #define LOONGARCH_IOCSR_IPI_SEND 0x1040 1212 #define IOCSR_IPI_SEND_IP_SHIFT 0 1213 #define IOCSR_IPI_SEND_CPU_SHIFT 16 1214 #define IOCSR_IPI_SEND_BLOCKING BIT(31) 1215 1216 #define LOONGARCH_IOCSR_MBUF_SEND 0x1048 1217 #define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31) 1218 #define IOCSR_MBUF_SEND_BOX_SHIFT 2 1219 #define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1) 1220 #define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1) 1221 #define IOCSR_MBUF_SEND_CPU_SHIFT 16 1222 #define IOCSR_MBUF_SEND_BUF_SHIFT 32 1223 #define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1224 1225 #define LOONGARCH_IOCSR_ANY_SEND 0x1158 1226 #define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31) 1227 #define IOCSR_ANY_SEND_CPU_SHIFT 16 1228 #define IOCSR_ANY_SEND_MASK_SHIFT 27 1229 #define IOCSR_ANY_SEND_BUF_SHIFT 32 1230 #define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1231 1232 /* Register offset and bit definition for CSR access */ 1233 #define LOONGARCH_IOCSR_TIMER_CFG 0x1060 1234 #define LOONGARCH_IOCSR_TIMER_TICK 0x1070 1235 #define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63) 1236 #define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62) 1237 #define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61) 1238 #define IOCSR_TIMER_MASK 0x0ffffffffffffULL 1239 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48) 1240 1241 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0 1242 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0 1243 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600 1244 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680 1245 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800 1246 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00 1247 #define IOCSR_EXTIOI_VECTOR_NUM 256 1248 1249 #ifndef __ASSEMBLER__ 1250 1251 #ifdef CONFIG_32BIT 1252 1253 static __always_inline u32 rdtime_h(void) 1254 { 1255 u32 val = 0; 1256 1257 __asm__ __volatile__( 1258 "rdtimeh.w %0, $zero\n\t" 1259 : "=r"(val) 1260 : 1261 ); 1262 return val; 1263 } 1264 1265 static __always_inline u32 rdtime_l(void) 1266 { 1267 u32 val = 0; 1268 1269 __asm__ __volatile__( 1270 "rdtimel.w %0, $zero\n\t" 1271 : "=r"(val) 1272 : 1273 ); 1274 return val; 1275 } 1276 1277 #else 1278 1279 static __always_inline u64 rdtime_d(void) 1280 { 1281 u64 val = 0; 1282 1283 __asm__ __volatile__( 1284 "rdtime.d %0, $zero\n\t" 1285 : "=r"(val) 1286 : 1287 ); 1288 return val; 1289 } 1290 1291 #endif 1292 1293 static inline unsigned int get_csr_cpuid(void) 1294 { 1295 return csr_read32(LOONGARCH_CSR_CPUID); 1296 } 1297 1298 #ifdef CONFIG_64BIT 1299 static inline void csr_any_send(unsigned int addr, unsigned int data, 1300 unsigned int data_mask, unsigned int cpu) 1301 { 1302 uint64_t val = 0; 1303 1304 val = IOCSR_ANY_SEND_BLOCKING | addr; 1305 val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT); 1306 val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT); 1307 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT); 1308 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND); 1309 } 1310 #endif 1311 1312 static inline unsigned int read_csr_excode(void) 1313 { 1314 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 1315 } 1316 1317 static inline void write_csr_index(unsigned int idx) 1318 { 1319 csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX); 1320 } 1321 1322 static inline unsigned int read_csr_pagesize(void) 1323 { 1324 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE; 1325 } 1326 1327 static inline void write_csr_pagesize(unsigned int size) 1328 { 1329 csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX); 1330 } 1331 1332 static inline unsigned int read_csr_tlbrefill_pagesize(void) 1333 { 1334 return (csr_read(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT; 1335 } 1336 1337 static inline void write_csr_tlbrefill_pagesize(unsigned int size) 1338 { 1339 csr_xchg(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI); 1340 } 1341 1342 #define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID) 1343 #define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID) 1344 #define read_csr_entryhi() csr_read(LOONGARCH_CSR_TLBEHI) 1345 #define write_csr_entryhi(val) csr_write(val, LOONGARCH_CSR_TLBEHI) 1346 #define read_csr_entrylo0() csr_read(LOONGARCH_CSR_TLBELO0) 1347 #define write_csr_entrylo0(val) csr_write(val, LOONGARCH_CSR_TLBELO0) 1348 #define read_csr_entrylo1() csr_read(LOONGARCH_CSR_TLBELO1) 1349 #define write_csr_entrylo1(val) csr_write(val, LOONGARCH_CSR_TLBELO1) 1350 #define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG) 1351 #define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG) 1352 #define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT) 1353 #define write_csr_estat(val) csr_write32(val, LOONGARCH_CSR_ESTAT) 1354 #define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX) 1355 #define write_csr_tlbidx(val) csr_write32(val, LOONGARCH_CSR_TLBIDX) 1356 #define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN) 1357 #define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN) 1358 #define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID) 1359 #define read_csr_prcfg1() csr_read(LOONGARCH_CSR_PRCFG1) 1360 #define write_csr_prcfg1(val) csr_write(val, LOONGARCH_CSR_PRCFG1) 1361 #define read_csr_prcfg2() csr_read(LOONGARCH_CSR_PRCFG2) 1362 #define write_csr_prcfg2(val) csr_write(val, LOONGARCH_CSR_PRCFG2) 1363 #define read_csr_prcfg3() csr_read(LOONGARCH_CSR_PRCFG3) 1364 #define write_csr_prcfg3(val) csr_write(val, LOONGARCH_CSR_PRCFG3) 1365 #define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE) 1366 #define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE) 1367 #define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG) 1368 #define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG) 1369 #define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR) 1370 #define read_csr_impctl1() csr_read(LOONGARCH_CSR_IMPCTL1) 1371 #define write_csr_impctl1(val) csr_write(val, LOONGARCH_CSR_IMPCTL1) 1372 #define write_csr_impctl2(val) csr_write(val, LOONGARCH_CSR_IMPCTL2) 1373 1374 #define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0) 1375 #define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0) 1376 #define read_csr_perfctrl1() csr_read64(LOONGARCH_CSR_PERFCTRL1) 1377 #define read_csr_perfcntr1() csr_read64(LOONGARCH_CSR_PERFCNTR1) 1378 #define read_csr_perfctrl2() csr_read64(LOONGARCH_CSR_PERFCTRL2) 1379 #define read_csr_perfcntr2() csr_read64(LOONGARCH_CSR_PERFCNTR2) 1380 #define read_csr_perfctrl3() csr_read64(LOONGARCH_CSR_PERFCTRL3) 1381 #define read_csr_perfcntr3() csr_read64(LOONGARCH_CSR_PERFCNTR3) 1382 #define write_csr_perfctrl0(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL0) 1383 #define write_csr_perfcntr0(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR0) 1384 #define write_csr_perfctrl1(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL1) 1385 #define write_csr_perfcntr1(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR1) 1386 #define write_csr_perfctrl2(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL2) 1387 #define write_csr_perfcntr2(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR2) 1388 #define write_csr_perfctrl3(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL3) 1389 #define write_csr_perfcntr3(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR3) 1390 1391 /* 1392 * Manipulate bits in a register. 1393 */ 1394 #define __BUILD_CSR_COMMON(name) \ 1395 static inline unsigned long \ 1396 set_##name(unsigned long set) \ 1397 { \ 1398 unsigned long res, new; \ 1399 \ 1400 res = read_##name(); \ 1401 new = res | set; \ 1402 write_##name(new); \ 1403 \ 1404 return res; \ 1405 } \ 1406 \ 1407 static inline unsigned long \ 1408 clear_##name(unsigned long clear) \ 1409 { \ 1410 unsigned long res, new; \ 1411 \ 1412 res = read_##name(); \ 1413 new = res & ~clear; \ 1414 write_##name(new); \ 1415 \ 1416 return res; \ 1417 } \ 1418 \ 1419 static inline unsigned long \ 1420 change_##name(unsigned long change, unsigned long val) \ 1421 { \ 1422 unsigned long res, new; \ 1423 \ 1424 res = read_##name(); \ 1425 new = res & ~change; \ 1426 new |= (val & change); \ 1427 write_##name(new); \ 1428 \ 1429 return res; \ 1430 } 1431 1432 #define __BUILD_CSR_OP(name) __BUILD_CSR_COMMON(csr_##name) 1433 1434 __BUILD_CSR_OP(euen) 1435 __BUILD_CSR_OP(ecfg) 1436 __BUILD_CSR_OP(tlbidx) 1437 1438 #define set_csr_estat(val) \ 1439 csr_xchg32(val, val, LOONGARCH_CSR_ESTAT) 1440 #define clear_csr_estat(val) \ 1441 csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT) 1442 1443 #endif /* __ASSEMBLER__ */ 1444 1445 /* Generic EntryLo bit definitions */ 1446 #define ENTRYLO_V (_ULCAST_(1) << 0) 1447 #define ENTRYLO_D (_ULCAST_(1) << 1) 1448 #define ENTRYLO_PLV_SHIFT 2 1449 #define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT) 1450 #define ENTRYLO_C_SHIFT 4 1451 #define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT) 1452 #define ENTRYLO_G (_ULCAST_(1) << 6) 1453 #ifdef CONFIG_64BIT 1454 #define ENTRYLO_NR (_ULCAST_(1) << 61) 1455 #define ENTRYLO_NX (_ULCAST_(1) << 62) 1456 #endif 1457 1458 /* Values for PageSize register */ 1459 #define PS_4K 0x0000000c 1460 #define PS_8K 0x0000000d 1461 #define PS_16K 0x0000000e 1462 #define PS_32K 0x0000000f 1463 #define PS_64K 0x00000010 1464 #define PS_128K 0x00000011 1465 #define PS_256K 0x00000012 1466 #define PS_512K 0x00000013 1467 #define PS_1M 0x00000014 1468 #define PS_2M 0x00000015 1469 #define PS_4M 0x00000016 1470 #define PS_8M 0x00000017 1471 #define PS_16M 0x00000018 1472 #define PS_32M 0x00000019 1473 #define PS_64M 0x0000001a 1474 #define PS_128M 0x0000001b 1475 #define PS_256M 0x0000001c 1476 #define PS_512M 0x0000001d 1477 #define PS_1G 0x0000001e 1478 1479 /* Default page size for a given kernel configuration */ 1480 #ifdef CONFIG_PAGE_SIZE_4KB 1481 #define PS_DEFAULT_SIZE PS_4K 1482 #elif defined(CONFIG_PAGE_SIZE_16KB) 1483 #define PS_DEFAULT_SIZE PS_16K 1484 #elif defined(CONFIG_PAGE_SIZE_64KB) 1485 #define PS_DEFAULT_SIZE PS_64K 1486 #else 1487 #error Bad page size configuration! 1488 #endif 1489 1490 /* Default huge tlb size for a given kernel configuration */ 1491 #ifdef CONFIG_PAGE_SIZE_4KB 1492 #define PS_HUGE_SIZE PS_1M 1493 #elif defined(CONFIG_PAGE_SIZE_16KB) 1494 #define PS_HUGE_SIZE PS_16M 1495 #elif defined(CONFIG_PAGE_SIZE_64KB) 1496 #define PS_HUGE_SIZE PS_256M 1497 #else 1498 #error Bad page size configuration for hugetlbfs! 1499 #endif 1500 1501 /* ExStatus.ExcCode */ 1502 #define EXCCODE_RSV 0 /* Reserved */ 1503 #define EXCCODE_TLBL 1 /* TLB miss on a load */ 1504 #define EXCCODE_TLBS 2 /* TLB miss on a store */ 1505 #define EXCCODE_TLBI 3 /* TLB miss on a ifetch */ 1506 #define EXCCODE_TLBM 4 /* TLB modified fault */ 1507 #define EXCCODE_TLBNR 5 /* TLB Read-Inhibit exception */ 1508 #define EXCCODE_TLBNX 6 /* TLB Execution-Inhibit exception */ 1509 #define EXCCODE_TLBPE 7 /* TLB Privilege Error */ 1510 #define EXCCODE_ADE 8 /* Address Error */ 1511 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */ 1512 #define EXSUBCODE_ADEM 1 /* Access Memory*/ 1513 #define EXCCODE_ALE 9 /* Unalign Access */ 1514 #define EXCCODE_BCE 10 /* Bounds Check Error */ 1515 #define EXCCODE_SYS 11 /* System call */ 1516 #define EXCCODE_BP 12 /* Breakpoint */ 1517 #define EXCCODE_INE 13 /* Inst. Not Exist */ 1518 #define EXCCODE_IPE 14 /* Inst. Privileged Error */ 1519 #define EXCCODE_FPDIS 15 /* FPU Disabled */ 1520 #define EXCCODE_LSXDIS 16 /* LSX Disabled */ 1521 #define EXCCODE_LASXDIS 17 /* LASX Disabled */ 1522 #define EXCCODE_FPE 18 /* Floating Point Exception */ 1523 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */ 1524 #define EXCSUBCODE_VFPE 1 /* Vector Exception */ 1525 #define EXCCODE_WATCH 19 /* WatchPoint Exception */ 1526 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */ 1527 #define EXCSUBCODE_WPEM 1 /* ... on Memory Accesses */ 1528 #define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */ 1529 #define EXCCODE_BTE 21 /* Binary Trans. Exception */ 1530 #define EXCCODE_GSPR 22 /* Guest Privileged Error */ 1531 #define EXCCODE_HVC 23 /* Hypercall */ 1532 #define EXCCODE_GCM 24 /* Guest CSR modified */ 1533 #define EXCSUBCODE_GCSC 0 /* Software caused */ 1534 #define EXCSUBCODE_GCHC 1 /* Hardware caused */ 1535 #define EXCCODE_SE 25 /* Security */ 1536 1537 /* Interrupt numbers */ 1538 #define INT_SWI0 0 /* Software Interrupts */ 1539 #define INT_SWI1 1 1540 #define INT_HWI0 2 /* Hardware Interrupts */ 1541 #define INT_HWI1 3 1542 #define INT_HWI2 4 1543 #define INT_HWI3 5 1544 #define INT_HWI4 6 1545 #define INT_HWI5 7 1546 #define INT_HWI6 8 1547 #define INT_HWI7 9 1548 #define INT_PCOV 10 /* Performance Counter Overflow */ 1549 #define INT_TI 11 /* Timer */ 1550 #define INT_IPI 12 1551 #define INT_NMI 13 1552 #define INT_AVEC 14 1553 1554 /* ExcCodes corresponding to interrupts */ 1555 #define EXCCODE_INT_NUM (INT_AVEC + 1) 1556 #define EXCCODE_INT_START 64 1557 #define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1) 1558 1559 /* FPU Status Register Names */ 1560 #ifndef CONFIG_AS_HAS_FCSR_CLASS 1561 #define LOONGARCH_FCSR0 $r0 1562 #define LOONGARCH_FCSR1 $r1 1563 #define LOONGARCH_FCSR2 $r2 1564 #define LOONGARCH_FCSR3 $r3 1565 #else 1566 #define LOONGARCH_FCSR0 $fcsr0 1567 #define LOONGARCH_FCSR1 $fcsr1 1568 #define LOONGARCH_FCSR2 $fcsr2 1569 #define LOONGARCH_FCSR3 $fcsr3 1570 #endif 1571 1572 /* FPU Status Register Values */ 1573 #define FPU_CSR_RSVD 0xe0e0fce0 1574 1575 /* 1576 * X the exception cause indicator 1577 * E the exception enable 1578 * S the sticky/flag bit 1579 */ 1580 #define FPU_CSR_ALL_X 0x1f000000 1581 #define FPU_CSR_INV_X 0x10000000 1582 #define FPU_CSR_DIV_X 0x08000000 1583 #define FPU_CSR_OVF_X 0x04000000 1584 #define FPU_CSR_UDF_X 0x02000000 1585 #define FPU_CSR_INE_X 0x01000000 1586 1587 #define FPU_CSR_ALL_S 0x001f0000 1588 #define FPU_CSR_INV_S 0x00100000 1589 #define FPU_CSR_DIV_S 0x00080000 1590 #define FPU_CSR_OVF_S 0x00040000 1591 #define FPU_CSR_UDF_S 0x00020000 1592 #define FPU_CSR_INE_S 0x00010000 1593 1594 #define FPU_CSR_ALL_E 0x0000001f 1595 #define FPU_CSR_INV_E 0x00000010 1596 #define FPU_CSR_DIV_E 0x00000008 1597 #define FPU_CSR_OVF_E 0x00000004 1598 #define FPU_CSR_UDF_E 0x00000002 1599 #define FPU_CSR_INE_E 0x00000001 1600 1601 /* Bits 8 and 9 of FPU Status Register specify the rounding mode */ 1602 #define FPU_CSR_RM 0x300 1603 #define FPU_CSR_RN 0x000 /* nearest */ 1604 #define FPU_CSR_RZ 0x100 /* towards zero */ 1605 #define FPU_CSR_RU 0x200 /* towards +Infinity */ 1606 #define FPU_CSR_RD 0x300 /* towards -Infinity */ 1607 1608 /* Bit 6 of FPU Status Register specify the LBT TOP simulation mode */ 1609 #define FPU_CSR_TM_SHIFT 0x6 1610 #define FPU_CSR_TM (_ULCAST_(1) << FPU_CSR_TM_SHIFT) 1611 1612 #define read_fcsr(source) \ 1613 ({ \ 1614 unsigned int __res; \ 1615 \ 1616 __asm__ __volatile__( \ 1617 " movfcsr2gr %0, "__stringify(source)" \n" \ 1618 : "=r" (__res)); \ 1619 __res; \ 1620 }) 1621 1622 #define write_fcsr(dest, val) \ 1623 do { \ 1624 __asm__ __volatile__( \ 1625 " movgr2fcsr "__stringify(dest)", %0 \n" \ 1626 : : "r" (val)); \ 1627 } while (0) 1628 1629 #endif /* _ASM_LOONGARCH_H */ 1630