1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5 #ifndef _ASM_LOONGARCH_H
6 #define _ASM_LOONGARCH_H
7
8 #include <linux/bits.h>
9 #include <linux/linkage.h>
10 #include <linux/types.h>
11
12 #ifndef __ASSEMBLER__
13 #include <larchintrin.h>
14
15 /* CPUCFG */
16 #define read_cpucfg(reg) __cpucfg(reg)
17
18 #endif /* !__ASSEMBLER__ */
19
20 #ifdef __ASSEMBLER__
21
22 /* LoongArch Registers */
23 #define REG_ZERO 0x0
24 #define REG_RA 0x1
25 #define REG_TP 0x2
26 #define REG_SP 0x3
27 #define REG_A0 0x4 /* Reused as V0 for return value */
28 #define REG_A1 0x5 /* Reused as V1 for return value */
29 #define REG_A2 0x6
30 #define REG_A3 0x7
31 #define REG_A4 0x8
32 #define REG_A5 0x9
33 #define REG_A6 0xa
34 #define REG_A7 0xb
35 #define REG_T0 0xc
36 #define REG_T1 0xd
37 #define REG_T2 0xe
38 #define REG_T3 0xf
39 #define REG_T4 0x10
40 #define REG_T5 0x11
41 #define REG_T6 0x12
42 #define REG_T7 0x13
43 #define REG_T8 0x14
44 #define REG_U0 0x15 /* Kernel uses it as percpu base */
45 #define REG_FP 0x16
46 #define REG_S0 0x17
47 #define REG_S1 0x18
48 #define REG_S2 0x19
49 #define REG_S3 0x1a
50 #define REG_S4 0x1b
51 #define REG_S5 0x1c
52 #define REG_S6 0x1d
53 #define REG_S7 0x1e
54 #define REG_S8 0x1f
55
56 #endif /* __ASSEMBLER__ */
57
58 /* Bit fields for CPUCFG registers */
59 #define LOONGARCH_CPUCFG0 0x0
60 #define CPUCFG0_PRID GENMASK(31, 0)
61
62 #define LOONGARCH_CPUCFG1 0x1
63 #define CPUCFG1_ISGR32 BIT(0)
64 #define CPUCFG1_ISGR64 BIT(1)
65 #define CPUCFG1_ISA GENMASK(1, 0)
66 #define CPUCFG1_PAGING BIT(2)
67 #define CPUCFG1_IOCSR BIT(3)
68 #define CPUCFG1_PABITS GENMASK(11, 4)
69 #define CPUCFG1_VABITS GENMASK(19, 12)
70 #define CPUCFG1_UAL BIT(20)
71 #define CPUCFG1_RI BIT(21)
72 #define CPUCFG1_EP BIT(22)
73 #define CPUCFG1_RPLV BIT(23)
74 #define CPUCFG1_HUGEPG BIT(24)
75 #define CPUCFG1_CRC32 BIT(25)
76 #define CPUCFG1_MSGINT BIT(26)
77
78 #define LOONGARCH_CPUCFG2 0x2
79 #define CPUCFG2_FP BIT(0)
80 #define CPUCFG2_FPSP BIT(1)
81 #define CPUCFG2_FPDP BIT(2)
82 #define CPUCFG2_FPVERS GENMASK(5, 3)
83 #define CPUCFG2_LSX BIT(6)
84 #define CPUCFG2_LASX BIT(7)
85 #define CPUCFG2_COMPLEX BIT(8)
86 #define CPUCFG2_CRYPTO BIT(9)
87 #define CPUCFG2_LVZP BIT(10)
88 #define CPUCFG2_LVZVER GENMASK(13, 11)
89 #define CPUCFG2_LLFTP BIT(14)
90 #define CPUCFG2_LLFTPREV GENMASK(17, 15)
91 #define CPUCFG2_X86BT BIT(18)
92 #define CPUCFG2_ARMBT BIT(19)
93 #define CPUCFG2_MIPSBT BIT(20)
94 #define CPUCFG2_LSPW BIT(21)
95 #define CPUCFG2_LAM BIT(22)
96 #define CPUCFG2_PTW BIT(24)
97
98 #define LOONGARCH_CPUCFG3 0x3
99 #define CPUCFG3_CCDMA BIT(0)
100 #define CPUCFG3_SFB BIT(1)
101 #define CPUCFG3_UCACC BIT(2)
102 #define CPUCFG3_LLEXC BIT(3)
103 #define CPUCFG3_SCDLY BIT(4)
104 #define CPUCFG3_LLDBAR BIT(5)
105 #define CPUCFG3_ITLBT BIT(6)
106 #define CPUCFG3_ICACHET BIT(7)
107 #define CPUCFG3_SPW_LVL GENMASK(10, 8)
108 #define CPUCFG3_SPW_HG_HF BIT(11)
109 #define CPUCFG3_RVA BIT(12)
110 #define CPUCFG3_RVAMAX GENMASK(16, 13)
111 #define CPUCFG3_ALDORDER_CAP BIT(18) /* All address load ordered, capability */
112 #define CPUCFG3_ASTORDER_CAP BIT(19) /* All address store ordered, capability */
113 #define CPUCFG3_ALDORDER_STA BIT(20) /* All address load ordered, status */
114 #define CPUCFG3_ASTORDER_STA BIT(21) /* All address store ordered, status */
115 #define CPUCFG3_SLDORDER_CAP BIT(22) /* Same address load ordered, capability */
116 #define CPUCFG3_SLDORDER_STA BIT(23) /* Same address load ordered, status */
117
118 #define LOONGARCH_CPUCFG4 0x4
119 #define CPUCFG4_CCFREQ GENMASK(31, 0)
120
121 #define LOONGARCH_CPUCFG5 0x5
122 #define CPUCFG5_CCMUL GENMASK(15, 0)
123 #define CPUCFG5_CCDIV GENMASK(31, 16)
124
125 #define LOONGARCH_CPUCFG6 0x6
126 #define CPUCFG6_PMP BIT(0)
127 #define CPUCFG6_PAMVER GENMASK(3, 1)
128 #define CPUCFG6_PMNUM GENMASK(7, 4)
129 #define CPUCFG6_PMNUM_SHIFT 4
130 #define CPUCFG6_PMBITS GENMASK(13, 8)
131 #define CPUCFG6_PMBITS_SHIFT 8
132 #define CPUCFG6_UPM BIT(14)
133
134 #define LOONGARCH_CPUCFG16 0x10
135 #define CPUCFG16_L1_IUPRE BIT(0)
136 #define CPUCFG16_L1_IUUNIFY BIT(1)
137 #define CPUCFG16_L1_DPRE BIT(2)
138 #define CPUCFG16_L2_IUPRE BIT(3)
139 #define CPUCFG16_L2_IUUNIFY BIT(4)
140 #define CPUCFG16_L2_IUPRIV BIT(5)
141 #define CPUCFG16_L2_IUINCL BIT(6)
142 #define CPUCFG16_L2_DPRE BIT(7)
143 #define CPUCFG16_L2_DPRIV BIT(8)
144 #define CPUCFG16_L2_DINCL BIT(9)
145 #define CPUCFG16_L3_IUPRE BIT(10)
146 #define CPUCFG16_L3_IUUNIFY BIT(11)
147 #define CPUCFG16_L3_IUPRIV BIT(12)
148 #define CPUCFG16_L3_IUINCL BIT(13)
149 #define CPUCFG16_L3_DPRE BIT(14)
150 #define CPUCFG16_L3_DPRIV BIT(15)
151 #define CPUCFG16_L3_DINCL BIT(16)
152
153 #define LOONGARCH_CPUCFG17 0x11
154 #define LOONGARCH_CPUCFG18 0x12
155 #define LOONGARCH_CPUCFG19 0x13
156 #define LOONGARCH_CPUCFG20 0x14
157 #define CPUCFG_CACHE_WAYS_M GENMASK(15, 0)
158 #define CPUCFG_CACHE_SETS_M GENMASK(23, 16)
159 #define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24)
160 #define CPUCFG_CACHE_WAYS 0
161 #define CPUCFG_CACHE_SETS 16
162 #define CPUCFG_CACHE_LSIZE 24
163
164 #define LOONGARCH_CPUCFG48 0x30
165 #define CPUCFG48_MCSR_LCK BIT(0)
166 #define CPUCFG48_NAP_EN BIT(1)
167 #define CPUCFG48_VFPU_CG BIT(2)
168 #define CPUCFG48_RAM_CG BIT(3)
169
170 /*
171 * CPUCFG index area: 0x40000000 -- 0x400000ff
172 * SW emulation for KVM hypervirsor, see arch/loongarch/include/uapi/asm/kvm_para.h
173 */
174
175 #ifndef __ASSEMBLER__
176
177 /* CSR */
178 #define csr_read32(reg) __csrrd_w(reg)
179 #define csr_read64(reg) __csrrd_d(reg)
180 #define csr_write32(val, reg) __csrwr_w(val, reg)
181 #define csr_write64(val, reg) __csrwr_d(val, reg)
182 #define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg)
183 #define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg)
184
185 #ifdef CONFIG_32BIT
186 #define csr_read(reg) csr_read32(reg)
187 #define csr_write(val, reg) csr_write32(val, reg)
188 #define csr_xchg(val, mask, reg) csr_xchg32(val, mask, reg)
189 #else
190 #define csr_read(reg) csr_read64(reg)
191 #define csr_write(val, reg) csr_write64(val, reg)
192 #define csr_xchg(val, mask, reg) csr_xchg64(val, mask, reg)
193 #endif
194
195 /* IOCSR */
196 #define iocsr_read32(reg) __iocsrrd_w(reg)
197 #define iocsr_read64(reg) __iocsrrd_d(reg)
198 #define iocsr_write32(val, reg) __iocsrwr_w(val, reg)
199 #define iocsr_write64(val, reg) __iocsrwr_d(val, reg)
200
201 #endif /* !__ASSEMBLER__ */
202
203 /* CSR register number */
204
205 /* Basic CSR registers */
206 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
207 #define CSR_CRMD_WE_SHIFT 9
208 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT)
209 #define CSR_CRMD_DACM_SHIFT 7
210 #define CSR_CRMD_DACM_WIDTH 2
211 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT)
212 #define CSR_CRMD_DACF_SHIFT 5
213 #define CSR_CRMD_DACF_WIDTH 2
214 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT)
215 #define CSR_CRMD_PG_SHIFT 4
216 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT)
217 #define CSR_CRMD_DA_SHIFT 3
218 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT)
219 #define CSR_CRMD_IE_SHIFT 2
220 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT)
221 #define CSR_CRMD_PLV_SHIFT 0
222 #define CSR_CRMD_PLV_WIDTH 2
223 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT)
224
225 #define PLV_KERN 0
226 #define PLV_USER 3
227 #define PLV_MASK 0x3
228
229 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
230 #define CSR_PRMD_PWE_SHIFT 3
231 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT)
232 #define CSR_PRMD_PIE_SHIFT 2
233 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT)
234 #define CSR_PRMD_PPLV_SHIFT 0
235 #define CSR_PRMD_PPLV_WIDTH 2
236 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
237
238 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
239 #define CSR_EUEN_LBTEN_SHIFT 3
240 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
241 #define CSR_EUEN_LASXEN_SHIFT 2
242 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
243 #define CSR_EUEN_LSXEN_SHIFT 1
244 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
245 #define CSR_EUEN_FPEN_SHIFT 0
246 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
247
248 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */
249
250 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
251 #define CSR_ECFG_VS_SHIFT 16
252 #define CSR_ECFG_VS_WIDTH 3
253 #define CSR_ECFG_VS_SHIFT_END (CSR_ECFG_VS_SHIFT + CSR_ECFG_VS_WIDTH - 1)
254 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
255 #define CSR_ECFG_IM_SHIFT 0
256 #define CSR_ECFG_IM_WIDTH 14
257 #define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
258
259 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
260 #define CSR_ESTAT_ESUBCODE_SHIFT 22
261 #define CSR_ESTAT_ESUBCODE_WIDTH 9
262 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
263 #define CSR_ESTAT_EXC_SHIFT 16
264 #define CSR_ESTAT_EXC_WIDTH 6
265 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
266 #define CSR_ESTAT_IS_SHIFT 0
267 #define CSR_ESTAT_IS_WIDTH 15
268 #define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
269
270 #define LOONGARCH_CSR_ERA 0x6 /* Exception return address */
271
272 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
273
274 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
275
276 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */
277
278 /* TLB related CSR registers */
279 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
280 #define CSR_TLBIDX_EHINV_SHIFT 31
281 #define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT)
282 #define CSR_TLBIDX_PS_SHIFT 24
283 #define CSR_TLBIDX_PS_WIDTH 6
284 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT)
285 #define CSR_TLBIDX_IDX_SHIFT 0
286 #define CSR_TLBIDX_IDX_WIDTH 12
287 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT)
288 #define CSR_TLBIDX_SIZEM 0x3f000000
289 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
290 #define CSR_TLBIDX_IDXM 0xfff
291 #define CSR_INVALID_ENTRY(e) (CSR_TLBIDX_EHINV | e)
292
293 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
294
295 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
296 #define CSR_TLBLO0_RPLV_SHIFT 63
297 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT)
298 #define CSR_TLBLO0_NX_SHIFT 62
299 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT)
300 #define CSR_TLBLO0_NR_SHIFT 61
301 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT)
302 #define CSR_TLBLO0_PFN_SHIFT 12
303 #define CSR_TLBLO0_PFN_WIDTH 36
304 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT)
305 #define CSR_TLBLO0_GLOBAL_SHIFT 6
306 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT)
307 #define CSR_TLBLO0_CCA_SHIFT 4
308 #define CSR_TLBLO0_CCA_WIDTH 2
309 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT)
310 #define CSR_TLBLO0_PLV_SHIFT 2
311 #define CSR_TLBLO0_PLV_WIDTH 2
312 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT)
313 #define CSR_TLBLO0_WE_SHIFT 1
314 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT)
315 #define CSR_TLBLO0_V_SHIFT 0
316 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT)
317
318 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
319 #define CSR_TLBLO1_RPLV_SHIFT 63
320 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT)
321 #define CSR_TLBLO1_NX_SHIFT 62
322 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT)
323 #define CSR_TLBLO1_NR_SHIFT 61
324 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT)
325 #define CSR_TLBLO1_PFN_SHIFT 12
326 #define CSR_TLBLO1_PFN_WIDTH 36
327 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT)
328 #define CSR_TLBLO1_GLOBAL_SHIFT 6
329 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT)
330 #define CSR_TLBLO1_CCA_SHIFT 4
331 #define CSR_TLBLO1_CCA_WIDTH 2
332 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT)
333 #define CSR_TLBLO1_PLV_SHIFT 2
334 #define CSR_TLBLO1_PLV_WIDTH 2
335 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT)
336 #define CSR_TLBLO1_WE_SHIFT 1
337 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT)
338 #define CSR_TLBLO1_V_SHIFT 0
339 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
340
341 #define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */
342 #define CSR_GTLBC_TGID_SHIFT 16
343 #define CSR_GTLBC_TGID_WIDTH 8
344 #define CSR_GTLBC_TGID_SHIFT_END (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
345 #define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
346 #define CSR_GTLBC_TOTI_SHIFT 13
347 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
348 #define CSR_GTLBC_USETGID_SHIFT 12
349 #define CSR_GTLBC_USETGID (_ULCAST_(0x1) << CSR_GTLBC_USETGID_SHIFT)
350 #define CSR_GTLBC_GMTLBSZ_SHIFT 0
351 #define CSR_GTLBC_GMTLBSZ_WIDTH 6
352 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
353
354 #define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */
355 #define CSR_TRGP_RID_SHIFT 16
356 #define CSR_TRGP_RID_WIDTH 8
357 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT)
358 #define CSR_TRGP_GTLB_SHIFT 0
359 #define CSR_TRGP_GTLB (1 << CSR_TRGP_GTLB_SHIFT)
360
361 #define LOONGARCH_CSR_ASID 0x18 /* ASID */
362 #define CSR_ASID_BIT_SHIFT 16 /* ASIDBits */
363 #define CSR_ASID_BIT_WIDTH 8
364 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT)
365 #define CSR_ASID_ASID_SHIFT 0
366 #define CSR_ASID_ASID_WIDTH 10
367 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT)
368
369 #define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */
370
371 #define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */
372
373 #define LOONGARCH_CSR_PGD 0x1b /* Page table base */
374
375 #define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */
376 #define CSR_PWCTL0_PTEW_SHIFT 30
377 #define CSR_PWCTL0_PTEW_WIDTH 2
378 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT)
379 #define CSR_PWCTL0_DIR1WIDTH_SHIFT 25
380 #define CSR_PWCTL0_DIR1WIDTH_WIDTH 5
381 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT)
382 #define CSR_PWCTL0_DIR1BASE_SHIFT 20
383 #define CSR_PWCTL0_DIR1BASE_WIDTH 5
384 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT)
385 #define CSR_PWCTL0_DIR0WIDTH_SHIFT 15
386 #define CSR_PWCTL0_DIR0WIDTH_WIDTH 5
387 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT)
388 #define CSR_PWCTL0_DIR0BASE_SHIFT 10
389 #define CSR_PWCTL0_DIR0BASE_WIDTH 5
390 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT)
391 #define CSR_PWCTL0_PTWIDTH_SHIFT 5
392 #define CSR_PWCTL0_PTWIDTH_WIDTH 5
393 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT)
394 #define CSR_PWCTL0_PTBASE_SHIFT 0
395 #define CSR_PWCTL0_PTBASE_WIDTH 5
396 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)
397
398 #define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */
399 #define CSR_PWCTL1_PTW_SHIFT 24
400 #define CSR_PWCTL1_PTW_WIDTH 1
401 #define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT)
402 #define CSR_PWCTL1_DIR3WIDTH_SHIFT 18
403 #define CSR_PWCTL1_DIR3WIDTH_WIDTH 5
404 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)
405 #define CSR_PWCTL1_DIR3BASE_SHIFT 12
406 #define CSR_PWCTL1_DIR3BASE_WIDTH 5
407 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT)
408 #define CSR_PWCTL1_DIR2WIDTH_SHIFT 6
409 #define CSR_PWCTL1_DIR2WIDTH_WIDTH 5
410 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT)
411 #define CSR_PWCTL1_DIR2BASE_SHIFT 0
412 #define CSR_PWCTL1_DIR2BASE_WIDTH 5
413 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT)
414
415 #define LOONGARCH_CSR_STLBPGSIZE 0x1e
416 #define CSR_STLBPGSIZE_PS_WIDTH 6
417 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f))
418
419 #define LOONGARCH_CSR_RVACFG 0x1f
420 #define CSR_RVACFG_RDVA_WIDTH 4
421 #define CSR_RVACFG_RDVA (_ULCAST_(0xf))
422
423 /* Config CSR registers */
424 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
425 #define CSR_CPUID_COREID_WIDTH 11
426 #define CSR_CPUID_COREID _ULCAST_(0x7ff)
427
428 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
429 #define CSR_CONF1_VSMAX_SHIFT 12
430 #define CSR_CONF1_VSMAX_WIDTH 3
431 #define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT)
432 #define CSR_CONF1_TMRBITS_SHIFT 4
433 #define CSR_CONF1_TMRBITS_WIDTH 8
434 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT)
435 #define CSR_CONF1_KSNUM_WIDTH 4
436 #define CSR_CONF1_KSNUM _ULCAST_(0xf)
437
438 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
439 #define CSR_CONF2_PGMASK_SUPP 0x3ffff000
440
441 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
442 #define CSR_CONF3_STLBIDX_SHIFT 20
443 #define CSR_CONF3_STLBIDX_WIDTH 6
444 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT)
445 #define CSR_CONF3_STLBWAYS_SHIFT 12
446 #define CSR_CONF3_STLBWAYS_WIDTH 8
447 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT)
448 #define CSR_CONF3_MTLBSIZE_SHIFT 4
449 #define CSR_CONF3_MTLBSIZE_WIDTH 8
450 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT)
451 #define CSR_CONF3_TLBTYPE_SHIFT 0
452 #define CSR_CONF3_TLBTYPE_WIDTH 4
453 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT)
454
455 /* KSave registers */
456 #define LOONGARCH_CSR_KS0 0x30
457 #define LOONGARCH_CSR_KS1 0x31
458 #define LOONGARCH_CSR_KS2 0x32
459 #define LOONGARCH_CSR_KS3 0x33
460 #define LOONGARCH_CSR_KS4 0x34
461 #define LOONGARCH_CSR_KS5 0x35
462 #define LOONGARCH_CSR_KS6 0x36
463 #define LOONGARCH_CSR_KS7 0x37
464 #define LOONGARCH_CSR_KS8 0x38
465 #define LOONGARCH_CSR_KS9 0x39
466 #define LOONGARCH_CSR_KS10 0x3a
467 #define LOONGARCH_CSR_KS11 0x3b
468 #define LOONGARCH_CSR_KS12 0x3c
469 #define LOONGARCH_CSR_KS13 0x3d
470 #define LOONGARCH_CSR_KS14 0x3e
471 #define LOONGARCH_CSR_KS15 0x3f
472
473 /* Exception allocated KS0, KS1 and KS2 statically */
474 #define EXCEPTION_KS0 LOONGARCH_CSR_KS0
475 #define EXCEPTION_KS1 LOONGARCH_CSR_KS1
476 #define EXCEPTION_KS2 LOONGARCH_CSR_KS2
477 #define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2)
478
479 /* Percpu-data base allocated KS3 statically */
480 #define PERCPU_BASE_KS LOONGARCH_CSR_KS3
481 #define PERCPU_KSAVE_MASK (1 << 3)
482
483 /* KVM allocated KS4 and KS5 statically */
484 #define KVM_VCPU_KS LOONGARCH_CSR_KS4
485 #define KVM_TEMP_KS LOONGARCH_CSR_KS5
486 #define KVM_KSAVE_MASK (1 << 4 | 1 << 5)
487
488 /* Timer registers */
489 #define LOONGARCH_CSR_TMID 0x40 /* Timer ID */
490
491 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
492 #define CSR_TCFG_VAL_SHIFT 2
493 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
494 #define CSR_TCFG_PERIOD_SHIFT 1
495 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
496 #define CSR_TCFG_EN (_ULCAST_(0x1))
497
498 #define LOONGARCH_CSR_TVAL 0x42 /* Timer value */
499
500 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
501
502 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
503 #define CSR_TINTCLR_TI_SHIFT 0
504 #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT)
505
506 /* Guest registers */
507 #define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */
508 #define CSR_GSTAT_GID_SHIFT 16
509 #define CSR_GSTAT_GID_WIDTH 8
510 #define CSR_GSTAT_GID_SHIFT_END (CSR_GSTAT_GID_SHIFT + CSR_GSTAT_GID_WIDTH - 1)
511 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
512 #define CSR_GSTAT_GIDBIT_SHIFT 4
513 #define CSR_GSTAT_GIDBIT_WIDTH 6
514 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT)
515 #define CSR_GSTAT_PVM_SHIFT 1
516 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT)
517 #define CSR_GSTAT_VM_SHIFT 0
518 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT)
519
520 #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */
521 #define CSR_GCFG_GPERF_SHIFT 24
522 #define CSR_GCFG_GPERF_WIDTH 3
523 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)
524 #define CSR_GCFG_GPMP_SHIFT 23
525 #define CSR_GCFG_GPMP (_ULCAST_(0x1) << CSR_GCFG_GPMP_SHIFT)
526 #define CSR_GCFG_GCI_SHIFT 20
527 #define CSR_GCFG_GCI_WIDTH 2
528 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)
529 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT)
530 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT)
531 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT)
532 #define CSR_GCFG_GCIP_SHIFT 16
533 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT)
534 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT)
535 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1))
536 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2))
537 #define CSR_GCFG_TORU_SHIFT 15
538 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT)
539 #define CSR_GCFG_TORUP_SHIFT 14
540 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT)
541 #define CSR_GCFG_TOP_SHIFT 13
542 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT)
543 #define CSR_GCFG_TOPP_SHIFT 12
544 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT)
545 #define CSR_GCFG_TOE_SHIFT 11
546 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT)
547 #define CSR_GCFG_TOEP_SHIFT 10
548 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT)
549 #define CSR_GCFG_TIT_SHIFT 9
550 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT)
551 #define CSR_GCFG_TITP_SHIFT 8
552 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT)
553 #define CSR_GCFG_SIT_SHIFT 7
554 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT)
555 #define CSR_GCFG_SITP_SHIFT 6
556 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT)
557 #define CSR_GCFG_MATC_SHITF 4
558 #define CSR_GCFG_MATC_WIDTH 2
559 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF)
560 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
561 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
562 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
563 #define CSR_GCFG_MATP_NEST_SHIFT 2
564 #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT)
565 #define CSR_GCFG_MATP_ROOT_SHIFT 1
566 #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT)
567 #define CSR_GCFG_MATP_GUEST_SHIFT 0
568 #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT)
569
570 #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */
571 #define CSR_GINTC_HC_SHIFT 16
572 #define CSR_GINTC_HC_WIDTH 8
573 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT)
574 #define CSR_GINTC_PIP_SHIFT 8
575 #define CSR_GINTC_PIP_WIDTH 8
576 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT)
577 #define CSR_GINTC_VIP_SHIFT 0
578 #define CSR_GINTC_VIP_WIDTH 8
579 #define CSR_GINTC_VIP (_ULCAST_(0xff))
580
581 #define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */
582
583 /* LLBCTL register */
584 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
585 #define CSR_LLBCTL_ROLLB_SHIFT 0
586 #define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT)
587 #define CSR_LLBCTL_WCLLB_SHIFT 1
588 #define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT)
589 #define CSR_LLBCTL_KLO_SHIFT 2
590 #define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT)
591
592 /* Implement dependent */
593 #define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */
594 #define CSR_LDSTORDER_SHIFT 28
595 #define CSR_LDSTORDER_WIDTH 3
596 #define CSR_LDSTORDER_MASK (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT)
597 #define CSR_LDSTORDER_NLD_NST (_ULCAST_(0x0) << CSR_LDSTORDER_SHIFT) /* 000 = No Load No Store */
598 #define CSR_LDSTORDER_ALD_NST (_ULCAST_(0x1) << CSR_LDSTORDER_SHIFT) /* 001 = All Load No Store */
599 #define CSR_LDSTORDER_SLD_NST (_ULCAST_(0x3) << CSR_LDSTORDER_SHIFT) /* 011 = Same Load No Store */
600 #define CSR_LDSTORDER_NLD_AST (_ULCAST_(0x4) << CSR_LDSTORDER_SHIFT) /* 100 = No Load All Store */
601 #define CSR_LDSTORDER_ALD_AST (_ULCAST_(0x5) << CSR_LDSTORDER_SHIFT) /* 101 = All Load All Store */
602 #define CSR_LDSTORDER_SLD_AST (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT) /* 111 = Same Load All Store */
603 #define CSR_MISPEC_SHIFT 20
604 #define CSR_MISPEC_WIDTH 8
605 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
606 #define CSR_SSEN_SHIFT 18
607 #define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT)
608 #define CSR_SCRAND_SHIFT 17
609 #define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT)
610 #define CSR_LLEXCL_SHIFT 16
611 #define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT)
612 #define CSR_DISVC_SHIFT 15
613 #define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT)
614 #define CSR_VCLRU_SHIFT 14
615 #define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT)
616 #define CSR_DCLRU_SHIFT 13
617 #define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT)
618 #define CSR_FASTLDQ_SHIFT 12
619 #define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT)
620 #define CSR_USERCAC_SHIFT 11
621 #define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT)
622 #define CSR_ANTI_MISPEC_SHIFT 10
623 #define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT)
624 #define CSR_AUTO_FLUSHSFB_SHIFT 9
625 #define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT)
626 #define CSR_STFILL_SHIFT 8
627 #define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT)
628 #define CSR_LIFEP_SHIFT 7
629 #define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT)
630 #define CSR_LLSYNC_SHIFT 6
631 #define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT)
632 #define CSR_BRBTDIS_SHIFT 5
633 #define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT)
634 #define CSR_RASDIS_SHIFT 4
635 #define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT)
636 #define CSR_STPRE_SHIFT 2
637 #define CSR_STPRE_WIDTH 2
638 #define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT)
639 #define CSR_INSTPRE_SHIFT 1
640 #define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT)
641 #define CSR_DATAPRE_SHIFT 0
642 #define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT)
643
644 #define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */
645 #define CSR_FLUSH_MTLB_SHIFT 0
646 #define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT)
647 #define CSR_FLUSH_STLB_SHIFT 1
648 #define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT)
649 #define CSR_FLUSH_DTLB_SHIFT 2
650 #define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT)
651 #define CSR_FLUSH_ITLB_SHIFT 3
652 #define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT)
653 #define CSR_FLUSH_BTAC_SHIFT 4
654 #define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT)
655
656 #define LOONGARCH_CSR_GNMI 0x82
657
658 /* TLB Refill registers */
659 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */
660 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
661 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
662 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */
663 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
664 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
665 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
666 #define CSR_TLBREHI_PS_SHIFT 0
667 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT)
668 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
669
670 /* Machine Error registers */
671 #define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */
672 #define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */
673 #define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */
674 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */
675 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */
676 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */
677
678 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
679
680 #define LOONGARCH_CSR_ISR0 0xa0
681 #define LOONGARCH_CSR_ISR1 0xa1
682 #define LOONGARCH_CSR_ISR2 0xa2
683 #define LOONGARCH_CSR_ISR3 0xa3
684
685 #define LOONGARCH_CSR_IRR 0xa4
686
687 #define LOONGARCH_CSR_PRID 0xc0
688
689 /* Shadow MCSR : 0xc0 ~ 0xff */
690 #define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */
691 #define MCSR0_INT_IMPL_SHIFT 58
692 #define MCSR0_INT_IMPL 0
693 #define MCSR0_IOCSR_BRD_SHIFT 57
694 #define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT)
695 #define MCSR0_HUGEPG_SHIFT 56
696 #define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT)
697 #define MCSR0_RPLMTLB_SHIFT 55
698 #define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT)
699 #define MCSR0_EP_SHIFT 54
700 #define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT)
701 #define MCSR0_RI_SHIFT 53
702 #define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT)
703 #define MCSR0_UAL_SHIFT 52
704 #define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT)
705 #define MCSR0_VABIT_SHIFT 44
706 #define MCSR0_VABIT_WIDTH 8
707 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT)
708 #define VABIT_DEFAULT 0x2f
709 #define MCSR0_PABIT_SHIFT 36
710 #define MCSR0_PABIT_WIDTH 8
711 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT)
712 #define PABIT_DEFAULT 0x2f
713 #define MCSR0_IOCSR_SHIFT 35
714 #define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT)
715 #define MCSR0_PAGING_SHIFT 34
716 #define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT)
717 #define MCSR0_GR64_SHIFT 33
718 #define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT)
719 #define GR64_DEFAULT 1
720 #define MCSR0_GR32_SHIFT 32
721 #define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT)
722 #define GR32_DEFAULT 0
723 #define MCSR0_PRID_WIDTH 32
724 #define MCSR0_PRID 0x14C010
725
726 #define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */
727 #define MCSR1_HPFOLD_SHIFT 43
728 #define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT)
729 #define MCSR1_SPW_LVL_SHIFT 40
730 #define MCSR1_SPW_LVL_WIDTH 3
731 #define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT)
732 #define MCSR1_ICACHET_SHIFT 39
733 #define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT)
734 #define MCSR1_ITLBT_SHIFT 38
735 #define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT)
736 #define MCSR1_LLDBAR_SHIFT 37
737 #define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT)
738 #define MCSR1_SCDLY_SHIFT 36
739 #define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT)
740 #define MCSR1_LLEXC_SHIFT 35
741 #define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT)
742 #define MCSR1_UCACC_SHIFT 34
743 #define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT)
744 #define MCSR1_SFB_SHIFT 33
745 #define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT)
746 #define MCSR1_CCDMA_SHIFT 32
747 #define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT)
748 #define MCSR1_LAMO_SHIFT 22
749 #define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT)
750 #define MCSR1_LSPW_SHIFT 21
751 #define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT)
752 #define MCSR1_MIPSBT_SHIFT 20
753 #define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT)
754 #define MCSR1_ARMBT_SHIFT 19
755 #define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT)
756 #define MCSR1_X86BT_SHIFT 18
757 #define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT)
758 #define MCSR1_LLFTPVERS_SHIFT 15
759 #define MCSR1_LLFTPVERS_WIDTH 3
760 #define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT)
761 #define MCSR1_LLFTP_SHIFT 14
762 #define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT)
763 #define MCSR1_VZVERS_SHIFT 11
764 #define MCSR1_VZVERS_WIDTH 3
765 #define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT)
766 #define MCSR1_VZ_SHIFT 10
767 #define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT)
768 #define MCSR1_CRYPTO_SHIFT 9
769 #define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT)
770 #define MCSR1_COMPLEX_SHIFT 8
771 #define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT)
772 #define MCSR1_LASX_SHIFT 7
773 #define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT)
774 #define MCSR1_LSX_SHIFT 6
775 #define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT)
776 #define MCSR1_FPVERS_SHIFT 3
777 #define MCSR1_FPVERS_WIDTH 3
778 #define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT)
779 #define MCSR1_FPDP_SHIFT 2
780 #define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT)
781 #define MCSR1_FPSP_SHIFT 1
782 #define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT)
783 #define MCSR1_FP_SHIFT 0
784 #define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT)
785
786 #define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */
787 #define MCSR2_CCDIV_SHIFT 48
788 #define MCSR2_CCDIV_WIDTH 16
789 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT)
790 #define MCSR2_CCMUL_SHIFT 32
791 #define MCSR2_CCMUL_WIDTH 16
792 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT)
793 #define MCSR2_CCFREQ_WIDTH 32
794 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff))
795 #define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */
796
797 #define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */
798 #define MCSR3_UPM_SHIFT 14
799 #define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT)
800 #define MCSR3_PMBITS_SHIFT 8
801 #define MCSR3_PMBITS_WIDTH 6
802 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT)
803 #define PMBITS_DEFAULT 0x40
804 #define MCSR3_PMNUM_SHIFT 4
805 #define MCSR3_PMNUM_WIDTH 4
806 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT)
807 #define MCSR3_PAMVER_SHIFT 1
808 #define MCSR3_PAMVER_WIDTH 3
809 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT)
810 #define MCSR3_PMP_SHIFT 0
811 #define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT)
812
813 #define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */
814 #define MCSR8_L1I_SIZE_SHIFT 56
815 #define MCSR8_L1I_SIZE_WIDTH 7
816 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT)
817 #define MCSR8_L1I_IDX_SHIFT 48
818 #define MCSR8_L1I_IDX_WIDTH 8
819 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT)
820 #define MCSR8_L1I_WAY_SHIFT 32
821 #define MCSR8_L1I_WAY_WIDTH 16
822 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT)
823 #define MCSR8_L3DINCL_SHIFT 16
824 #define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT)
825 #define MCSR8_L3DPRIV_SHIFT 15
826 #define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT)
827 #define MCSR8_L3DPRE_SHIFT 14
828 #define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT)
829 #define MCSR8_L3IUINCL_SHIFT 13
830 #define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT)
831 #define MCSR8_L3IUPRIV_SHIFT 12
832 #define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT)
833 #define MCSR8_L3IUUNIFY_SHIFT 11
834 #define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT)
835 #define MCSR8_L3IUPRE_SHIFT 10
836 #define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT)
837 #define MCSR8_L2DINCL_SHIFT 9
838 #define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT)
839 #define MCSR8_L2DPRIV_SHIFT 8
840 #define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT)
841 #define MCSR8_L2DPRE_SHIFT 7
842 #define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT)
843 #define MCSR8_L2IUINCL_SHIFT 6
844 #define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT)
845 #define MCSR8_L2IUPRIV_SHIFT 5
846 #define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT)
847 #define MCSR8_L2IUUNIFY_SHIFT 4
848 #define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT)
849 #define MCSR8_L2IUPRE_SHIFT 3
850 #define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT)
851 #define MCSR8_L1DPRE_SHIFT 2
852 #define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT)
853 #define MCSR8_L1IUUNIFY_SHIFT 1
854 #define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT)
855 #define MCSR8_L1IUPRE_SHIFT 0
856 #define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT)
857
858 #define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */
859 #define MCSR9_L2U_SIZE_SHIFT 56
860 #define MCSR9_L2U_SIZE_WIDTH 7
861 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT)
862 #define MCSR9_L2U_IDX_SHIFT 48
863 #define MCSR9_L2U_IDX_WIDTH 8
864 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT)
865 #define MCSR9_L2U_WAY_SHIFT 32
866 #define MCSR9_L2U_WAY_WIDTH 16
867 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT)
868 #define MCSR9_L1D_SIZE_SHIFT 24
869 #define MCSR9_L1D_SIZE_WIDTH 7
870 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT)
871 #define MCSR9_L1D_IDX_SHIFT 16
872 #define MCSR9_L1D_IDX_WIDTH 8
873 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT)
874 #define MCSR9_L1D_WAY_SHIFT 0
875 #define MCSR9_L1D_WAY_WIDTH 16
876 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT)
877
878 #define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */
879 #define MCSR10_L3U_SIZE_SHIFT 24
880 #define MCSR10_L3U_SIZE_WIDTH 7
881 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT)
882 #define MCSR10_L3U_IDX_SHIFT 16
883 #define MCSR10_L3U_IDX_WIDTH 8
884 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT)
885 #define MCSR10_L3U_WAY_SHIFT 0
886 #define MCSR10_L3U_WAY_WIDTH 16
887 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT)
888
889 #define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */
890 #define MCSR24_RAMCG_SHIFT 3
891 #define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT)
892 #define MCSR24_VFPUCG_SHIFT 2
893 #define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT)
894 #define MCSR24_NAPEN_SHIFT 1
895 #define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT)
896 #define MCSR24_MCSRLOCK_SHIFT 0
897 #define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT)
898
899 /* Uncached accelerate windows registers */
900 #define LOONGARCH_CSR_UCAWIN 0x100
901 #define LOONGARCH_CSR_UCAWIN0_LO 0x102
902 #define LOONGARCH_CSR_UCAWIN0_HI 0x103
903 #define LOONGARCH_CSR_UCAWIN1_LO 0x104
904 #define LOONGARCH_CSR_UCAWIN1_HI 0x105
905 #define LOONGARCH_CSR_UCAWIN2_LO 0x106
906 #define LOONGARCH_CSR_UCAWIN2_HI 0x107
907 #define LOONGARCH_CSR_UCAWIN3_LO 0x108
908 #define LOONGARCH_CSR_UCAWIN3_HI 0x109
909
910 /* Direct Map windows registers */
911 #define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */
912 #define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */
913 #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */
914 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */
915
916 /* Direct Map window 0/1/2/3 */
917
918 #ifdef CONFIG_32BIT
919
920 #define CSR_DMW0_PLV0 (1 << 0)
921 #define CSR_DMW0_VSEG (0x4)
922 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS)
923 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0)
924
925 #define CSR_DMW1_PLV0 (1 << 0)
926 #define CSR_DMW1_MAT (1 << 4)
927 #define CSR_DMW1_VSEG (0x5)
928 #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS)
929 #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0)
930
931 #define CSR_DMW2_INIT 0x0
932
933 #define CSR_DMW3_INIT 0x0
934
935 #else
936
937 #define CSR_DMW0_PLV0 _CONST64_(1 << 0)
938 #define CSR_DMW0_VSEG _CONST64_(0x8000)
939 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS)
940 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0)
941
942 #define CSR_DMW1_PLV0 _CONST64_(1 << 0)
943 #define CSR_DMW1_MAT _CONST64_(1 << 4)
944 #define CSR_DMW1_VSEG _CONST64_(0x9000)
945 #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS)
946 #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0)
947
948 #define CSR_DMW2_PLV0 _CONST64_(1 << 0)
949 #define CSR_DMW2_MAT _CONST64_(2 << 4)
950 #define CSR_DMW2_VSEG _CONST64_(0xa000)
951 #define CSR_DMW2_BASE (CSR_DMW2_VSEG << DMW_PABITS)
952 #define CSR_DMW2_INIT (CSR_DMW2_BASE | CSR_DMW2_MAT | CSR_DMW2_PLV0)
953
954 #define CSR_DMW3_INIT 0x0
955
956 #endif
957
958 /* Performance Counter registers */
959 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */
960 #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */
961 #define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */
962 #define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */
963 #define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */
964 #define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */
965 #define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */
966 #define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */
967 #define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16)
968 #define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17)
969 #define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18)
970 #define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19)
971 #define CSR_PERFCTRL_IE (_ULCAST_(1) << 20)
972 #define CSR_PERFCTRL_EVENT 0x3ff
973
974 /* Debug registers */
975 #define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */
976 #define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */
977
978 #define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */
979 #define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */
980 #define LOONGARCH_CSR_DB0CTRL 0x312 /* data breakpoint 0 control */
981 #define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */
982
983 #define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */
984 #define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */
985 #define LOONGARCH_CSR_DB1CTRL 0x31a /* data breakpoint 1 control */
986 #define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */
987
988 #define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */
989 #define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */
990 #define LOONGARCH_CSR_DB2CTRL 0x322 /* data breakpoint 2 control */
991 #define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */
992
993 #define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */
994 #define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */
995 #define LOONGARCH_CSR_DB3CTRL 0x32a /* data breakpoint 3 control */
996 #define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */
997
998 #define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */
999 #define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */
1000 #define LOONGARCH_CSR_DB4CTRL 0x332 /* data breakpoint 4 control */
1001 #define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */
1002
1003 #define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */
1004 #define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */
1005 #define LOONGARCH_CSR_DB5CTRL 0x33a /* data breakpoint 5 control */
1006 #define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */
1007
1008 #define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */
1009 #define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */
1010 #define LOONGARCH_CSR_DB6CTRL 0x342 /* data breakpoint 6 control */
1011 #define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */
1012
1013 #define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */
1014 #define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */
1015 #define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
1016 #define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
1017
1018 #define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */
1019 #define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */
1020 #define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */
1021 #define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */
1022
1023 #define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */
1024 #define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */
1025 #define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */
1026 #define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */
1027
1028 #define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */
1029 #define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */
1030 #define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */
1031 #define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */
1032
1033 #define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */
1034 #define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */
1035 #define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */
1036 #define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */
1037
1038 #define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */
1039 #define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */
1040 #define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */
1041 #define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */
1042
1043 #define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */
1044 #define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */
1045 #define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */
1046 #define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */
1047
1048 #define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
1049 #define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
1050
1051 #define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */
1052 #define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */
1053 #define LOONGARCH_CSR_IB0CTRL 0x392 /* inst breakpoint 0 control */
1054 #define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */
1055
1056 #define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */
1057 #define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */
1058 #define LOONGARCH_CSR_IB1CTRL 0x39a /* inst breakpoint 1 control */
1059 #define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */
1060
1061 #define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */
1062 #define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */
1063 #define LOONGARCH_CSR_IB2CTRL 0x3a2 /* inst breakpoint 2 control */
1064 #define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */
1065
1066 #define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */
1067 #define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */
1068 #define LOONGARCH_CSR_IB3CTRL 0x3aa /* inst breakpoint 3 control */
1069 #define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */
1070
1071 #define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */
1072 #define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */
1073 #define LOONGARCH_CSR_IB4CTRL 0x3b2 /* inst breakpoint 4 control */
1074 #define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */
1075
1076 #define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */
1077 #define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */
1078 #define LOONGARCH_CSR_IB5CTRL 0x3ba /* inst breakpoint 5 control */
1079 #define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */
1080
1081 #define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */
1082 #define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */
1083 #define LOONGARCH_CSR_IB6CTRL 0x3c2 /* inst breakpoint 6 control */
1084 #define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */
1085
1086 #define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */
1087 #define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */
1088 #define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
1089 #define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
1090
1091 #define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */
1092 #define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */
1093 #define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */
1094 #define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */
1095
1096 #define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */
1097 #define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */
1098 #define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */
1099 #define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */
1100
1101 #define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */
1102 #define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */
1103 #define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */
1104 #define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */
1105
1106 #define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */
1107 #define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */
1108 #define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */
1109 #define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */
1110
1111 #define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */
1112 #define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */
1113 #define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */
1114 #define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */
1115
1116 #define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */
1117 #define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */
1118 #define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */
1119 #define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */
1120
1121 #define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
1122 #define LOONGARCH_CSR_DERA 0x501 /* debug era */
1123 #define LOONGARCH_CSR_DESAVE 0x502 /* debug save */
1124
1125 #define CSR_FWPC_SKIP_SHIFT 16
1126 #define CSR_FWPC_SKIP (_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT)
1127
1128 /*
1129 * CSR_ECFG IM
1130 */
1131 #define ECFG0_IM 0x00005fff
1132 #define ECFGB_SIP0 0
1133 #define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0)
1134 #define ECFGB_SIP1 1
1135 #define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1)
1136 #define ECFGB_IP0 2
1137 #define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0)
1138 #define ECFGB_IP1 3
1139 #define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1)
1140 #define ECFGB_IP2 4
1141 #define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2)
1142 #define ECFGB_IP3 5
1143 #define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3)
1144 #define ECFGB_IP4 6
1145 #define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4)
1146 #define ECFGB_IP5 7
1147 #define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5)
1148 #define ECFGB_IP6 8
1149 #define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6)
1150 #define ECFGB_IP7 9
1151 #define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7)
1152 #define ECFGB_PMC 10
1153 #define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC)
1154 #define ECFGB_TIMER 11
1155 #define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER)
1156 #define ECFGB_IPI 12
1157 #define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI)
1158 #define ECFGF(hwirq) (_ULCAST_(1) << hwirq)
1159
1160 #define ESTATF_IP 0x00003fff
1161
1162 #define LOONGARCH_IOCSR_FEATURES 0x8
1163 #define IOCSRF_TEMP BIT_ULL(0)
1164 #define IOCSRF_NODECNT BIT_ULL(1)
1165 #define IOCSRF_MSI BIT_ULL(2)
1166 #define IOCSRF_EXTIOI BIT_ULL(3)
1167 #define IOCSRF_CSRIPI BIT_ULL(4)
1168 #define IOCSRF_FREQCSR BIT_ULL(5)
1169 #define IOCSRF_FREQSCALE BIT_ULL(6)
1170 #define IOCSRF_DVFSV1 BIT_ULL(7)
1171 #define IOCSRF_EIODECODE BIT_ULL(9)
1172 #define IOCSRF_FLATMODE BIT_ULL(10)
1173 #define IOCSRF_VM BIT_ULL(11)
1174 #define IOCSRF_AVEC BIT_ULL(15)
1175 #define IOCSRF_REDIRECT BIT_ULL(16)
1176
1177 #define LOONGARCH_IOCSR_VENDOR 0x10
1178
1179 #define LOONGARCH_IOCSR_CPUNAME 0x20
1180
1181 #define LOONGARCH_IOCSR_NODECNT 0x408
1182
1183 #define LOONGARCH_IOCSR_MISC_FUNC 0x420
1184 #define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10)
1185 #define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21)
1186 #define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48)
1187 #define IOCSR_MISC_FUNC_AVEC_EN BIT_ULL(51)
1188
1189 #define LOONGARCH_IOCSR_CPUTEMP 0x428
1190
1191 #define LOONGARCH_IOCSR_SMCMBX 0x51c
1192
1193 /* PerCore CSR, only accessible by local cores */
1194 #define LOONGARCH_IOCSR_IPI_STATUS 0x1000
1195 #define LOONGARCH_IOCSR_IPI_EN 0x1004
1196 #define LOONGARCH_IOCSR_IPI_SET 0x1008
1197 #define LOONGARCH_IOCSR_IPI_CLEAR 0x100c
1198 #define LOONGARCH_IOCSR_MBUF0 0x1020
1199 #define LOONGARCH_IOCSR_MBUF1 0x1028
1200 #define LOONGARCH_IOCSR_MBUF2 0x1030
1201 #define LOONGARCH_IOCSR_MBUF3 0x1038
1202
1203 #define LOONGARCH_IOCSR_IPI_SEND 0x1040
1204 #define IOCSR_IPI_SEND_IP_SHIFT 0
1205 #define IOCSR_IPI_SEND_CPU_SHIFT 16
1206 #define IOCSR_IPI_SEND_BLOCKING BIT(31)
1207
1208 #define LOONGARCH_IOCSR_MBUF_SEND 0x1048
1209 #define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31)
1210 #define IOCSR_MBUF_SEND_BOX_SHIFT 2
1211 #define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1)
1212 #define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1)
1213 #define IOCSR_MBUF_SEND_CPU_SHIFT 16
1214 #define IOCSR_MBUF_SEND_BUF_SHIFT 32
1215 #define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1216
1217 #define LOONGARCH_IOCSR_ANY_SEND 0x1158
1218 #define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31)
1219 #define IOCSR_ANY_SEND_CPU_SHIFT 16
1220 #define IOCSR_ANY_SEND_MASK_SHIFT 27
1221 #define IOCSR_ANY_SEND_BUF_SHIFT 32
1222 #define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1223
1224 /* Register offset and bit definition for CSR access */
1225 #define LOONGARCH_IOCSR_TIMER_CFG 0x1060
1226 #define LOONGARCH_IOCSR_TIMER_TICK 0x1070
1227 #define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63)
1228 #define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62)
1229 #define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61)
1230 #define IOCSR_TIMER_MASK 0x0ffffffffffffULL
1231 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48)
1232
1233 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0
1234 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0
1235 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600
1236 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680
1237 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800
1238 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00
1239 #define IOCSR_EXTIOI_VECTOR_NUM 256
1240
1241 #ifndef __ASSEMBLER__
1242
1243 #ifdef CONFIG_32BIT
1244
rdtime_h(void)1245 static __always_inline u32 rdtime_h(void)
1246 {
1247 u32 val = 0;
1248
1249 __asm__ __volatile__(
1250 "rdtimeh.w %0, $zero\n\t"
1251 : "=r"(val)
1252 :
1253 );
1254 return val;
1255 }
1256
rdtime_l(void)1257 static __always_inline u32 rdtime_l(void)
1258 {
1259 u32 val = 0;
1260
1261 __asm__ __volatile__(
1262 "rdtimel.w %0, $zero\n\t"
1263 : "=r"(val)
1264 :
1265 );
1266 return val;
1267 }
1268
1269 #else
1270
rdtime_d(void)1271 static __always_inline u64 rdtime_d(void)
1272 {
1273 u64 val = 0;
1274
1275 __asm__ __volatile__(
1276 "rdtime.d %0, $zero\n\t"
1277 : "=r"(val)
1278 :
1279 );
1280 return val;
1281 }
1282
1283 #endif
1284
get_csr_cpuid(void)1285 static inline unsigned int get_csr_cpuid(void)
1286 {
1287 return csr_read32(LOONGARCH_CSR_CPUID);
1288 }
1289
1290 #ifdef CONFIG_64BIT
csr_any_send(unsigned int addr,unsigned int data,unsigned int data_mask,unsigned int cpu)1291 static inline void csr_any_send(unsigned int addr, unsigned int data,
1292 unsigned int data_mask, unsigned int cpu)
1293 {
1294 uint64_t val = 0;
1295
1296 val = IOCSR_ANY_SEND_BLOCKING | addr;
1297 val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT);
1298 val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT);
1299 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT);
1300 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND);
1301 }
1302 #endif
1303
read_csr_excode(void)1304 static inline unsigned int read_csr_excode(void)
1305 {
1306 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
1307 }
1308
write_csr_index(unsigned int idx)1309 static inline void write_csr_index(unsigned int idx)
1310 {
1311 csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX);
1312 }
1313
read_csr_pagesize(void)1314 static inline unsigned int read_csr_pagesize(void)
1315 {
1316 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE;
1317 }
1318
write_csr_pagesize(unsigned int size)1319 static inline void write_csr_pagesize(unsigned int size)
1320 {
1321 csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX);
1322 }
1323
read_csr_tlbrefill_pagesize(void)1324 static inline unsigned int read_csr_tlbrefill_pagesize(void)
1325 {
1326 return (csr_read(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT;
1327 }
1328
write_csr_tlbrefill_pagesize(unsigned int size)1329 static inline void write_csr_tlbrefill_pagesize(unsigned int size)
1330 {
1331 csr_xchg(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI);
1332 }
1333
1334 #define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID)
1335 #define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID)
1336 #define read_csr_entryhi() csr_read(LOONGARCH_CSR_TLBEHI)
1337 #define write_csr_entryhi(val) csr_write(val, LOONGARCH_CSR_TLBEHI)
1338 #define read_csr_entrylo0() csr_read(LOONGARCH_CSR_TLBELO0)
1339 #define write_csr_entrylo0(val) csr_write(val, LOONGARCH_CSR_TLBELO0)
1340 #define read_csr_entrylo1() csr_read(LOONGARCH_CSR_TLBELO1)
1341 #define write_csr_entrylo1(val) csr_write(val, LOONGARCH_CSR_TLBELO1)
1342 #define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG)
1343 #define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG)
1344 #define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT)
1345 #define write_csr_estat(val) csr_write32(val, LOONGARCH_CSR_ESTAT)
1346 #define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX)
1347 #define write_csr_tlbidx(val) csr_write32(val, LOONGARCH_CSR_TLBIDX)
1348 #define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN)
1349 #define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN)
1350 #define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID)
1351 #define read_csr_prcfg1() csr_read(LOONGARCH_CSR_PRCFG1)
1352 #define write_csr_prcfg1(val) csr_write(val, LOONGARCH_CSR_PRCFG1)
1353 #define read_csr_prcfg2() csr_read(LOONGARCH_CSR_PRCFG2)
1354 #define write_csr_prcfg2(val) csr_write(val, LOONGARCH_CSR_PRCFG2)
1355 #define read_csr_prcfg3() csr_read(LOONGARCH_CSR_PRCFG3)
1356 #define write_csr_prcfg3(val) csr_write(val, LOONGARCH_CSR_PRCFG3)
1357 #define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE)
1358 #define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE)
1359 #define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG)
1360 #define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG)
1361 #define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR)
1362 #define read_csr_impctl1() csr_read(LOONGARCH_CSR_IMPCTL1)
1363 #define write_csr_impctl1(val) csr_write(val, LOONGARCH_CSR_IMPCTL1)
1364 #define write_csr_impctl2(val) csr_write(val, LOONGARCH_CSR_IMPCTL2)
1365
1366 #define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0)
1367 #define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0)
1368 #define read_csr_perfctrl1() csr_read64(LOONGARCH_CSR_PERFCTRL1)
1369 #define read_csr_perfcntr1() csr_read64(LOONGARCH_CSR_PERFCNTR1)
1370 #define read_csr_perfctrl2() csr_read64(LOONGARCH_CSR_PERFCTRL2)
1371 #define read_csr_perfcntr2() csr_read64(LOONGARCH_CSR_PERFCNTR2)
1372 #define read_csr_perfctrl3() csr_read64(LOONGARCH_CSR_PERFCTRL3)
1373 #define read_csr_perfcntr3() csr_read64(LOONGARCH_CSR_PERFCNTR3)
1374 #define write_csr_perfctrl0(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL0)
1375 #define write_csr_perfcntr0(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR0)
1376 #define write_csr_perfctrl1(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL1)
1377 #define write_csr_perfcntr1(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR1)
1378 #define write_csr_perfctrl2(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL2)
1379 #define write_csr_perfcntr2(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR2)
1380 #define write_csr_perfctrl3(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL3)
1381 #define write_csr_perfcntr3(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR3)
1382
1383 /*
1384 * Manipulate bits in a register.
1385 */
1386 #define __BUILD_CSR_COMMON(name) \
1387 static inline unsigned long \
1388 set_##name(unsigned long set) \
1389 { \
1390 unsigned long res, new; \
1391 \
1392 res = read_##name(); \
1393 new = res | set; \
1394 write_##name(new); \
1395 \
1396 return res; \
1397 } \
1398 \
1399 static inline unsigned long \
1400 clear_##name(unsigned long clear) \
1401 { \
1402 unsigned long res, new; \
1403 \
1404 res = read_##name(); \
1405 new = res & ~clear; \
1406 write_##name(new); \
1407 \
1408 return res; \
1409 } \
1410 \
1411 static inline unsigned long \
1412 change_##name(unsigned long change, unsigned long val) \
1413 { \
1414 unsigned long res, new; \
1415 \
1416 res = read_##name(); \
1417 new = res & ~change; \
1418 new |= (val & change); \
1419 write_##name(new); \
1420 \
1421 return res; \
1422 }
1423
1424 #define __BUILD_CSR_OP(name) __BUILD_CSR_COMMON(csr_##name)
1425
1426 __BUILD_CSR_OP(euen)
1427 __BUILD_CSR_OP(ecfg)
1428 __BUILD_CSR_OP(tlbidx)
1429
1430 #define set_csr_estat(val) \
1431 csr_xchg32(val, val, LOONGARCH_CSR_ESTAT)
1432 #define clear_csr_estat(val) \
1433 csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT)
1434
1435 #endif /* __ASSEMBLER__ */
1436
1437 /* Generic EntryLo bit definitions */
1438 #define ENTRYLO_V (_ULCAST_(1) << 0)
1439 #define ENTRYLO_D (_ULCAST_(1) << 1)
1440 #define ENTRYLO_PLV_SHIFT 2
1441 #define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT)
1442 #define ENTRYLO_C_SHIFT 4
1443 #define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT)
1444 #define ENTRYLO_G (_ULCAST_(1) << 6)
1445 #ifdef CONFIG_64BIT
1446 #define ENTRYLO_NR (_ULCAST_(1) << 61)
1447 #define ENTRYLO_NX (_ULCAST_(1) << 62)
1448 #endif
1449
1450 /* Values for PageSize register */
1451 #define PS_4K 0x0000000c
1452 #define PS_8K 0x0000000d
1453 #define PS_16K 0x0000000e
1454 #define PS_32K 0x0000000f
1455 #define PS_64K 0x00000010
1456 #define PS_128K 0x00000011
1457 #define PS_256K 0x00000012
1458 #define PS_512K 0x00000013
1459 #define PS_1M 0x00000014
1460 #define PS_2M 0x00000015
1461 #define PS_4M 0x00000016
1462 #define PS_8M 0x00000017
1463 #define PS_16M 0x00000018
1464 #define PS_32M 0x00000019
1465 #define PS_64M 0x0000001a
1466 #define PS_128M 0x0000001b
1467 #define PS_256M 0x0000001c
1468 #define PS_512M 0x0000001d
1469 #define PS_1G 0x0000001e
1470
1471 /* Default page size for a given kernel configuration */
1472 #ifdef CONFIG_PAGE_SIZE_4KB
1473 #define PS_DEFAULT_SIZE PS_4K
1474 #elif defined(CONFIG_PAGE_SIZE_16KB)
1475 #define PS_DEFAULT_SIZE PS_16K
1476 #elif defined(CONFIG_PAGE_SIZE_64KB)
1477 #define PS_DEFAULT_SIZE PS_64K
1478 #else
1479 #error Bad page size configuration!
1480 #endif
1481
1482 /* Default huge tlb size for a given kernel configuration */
1483 #ifdef CONFIG_PAGE_SIZE_4KB
1484 #define PS_HUGE_SIZE PS_1M
1485 #elif defined(CONFIG_PAGE_SIZE_16KB)
1486 #define PS_HUGE_SIZE PS_16M
1487 #elif defined(CONFIG_PAGE_SIZE_64KB)
1488 #define PS_HUGE_SIZE PS_256M
1489 #else
1490 #error Bad page size configuration for hugetlbfs!
1491 #endif
1492
1493 /* ExStatus.ExcCode */
1494 #define EXCCODE_RSV 0 /* Reserved */
1495 #define EXCCODE_TLBL 1 /* TLB miss on a load */
1496 #define EXCCODE_TLBS 2 /* TLB miss on a store */
1497 #define EXCCODE_TLBI 3 /* TLB miss on a ifetch */
1498 #define EXCCODE_TLBM 4 /* TLB modified fault */
1499 #define EXCCODE_TLBNR 5 /* TLB Read-Inhibit exception */
1500 #define EXCCODE_TLBNX 6 /* TLB Execution-Inhibit exception */
1501 #define EXCCODE_TLBPE 7 /* TLB Privilege Error */
1502 #define EXCCODE_ADE 8 /* Address Error */
1503 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */
1504 #define EXSUBCODE_ADEM 1 /* Access Memory*/
1505 #define EXCCODE_ALE 9 /* Unalign Access */
1506 #define EXCCODE_BCE 10 /* Bounds Check Error */
1507 #define EXCCODE_SYS 11 /* System call */
1508 #define EXCCODE_BP 12 /* Breakpoint */
1509 #define EXCCODE_INE 13 /* Inst. Not Exist */
1510 #define EXCCODE_IPE 14 /* Inst. Privileged Error */
1511 #define EXCCODE_FPDIS 15 /* FPU Disabled */
1512 #define EXCCODE_LSXDIS 16 /* LSX Disabled */
1513 #define EXCCODE_LASXDIS 17 /* LASX Disabled */
1514 #define EXCCODE_FPE 18 /* Floating Point Exception */
1515 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */
1516 #define EXCSUBCODE_VFPE 1 /* Vector Exception */
1517 #define EXCCODE_WATCH 19 /* WatchPoint Exception */
1518 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */
1519 #define EXCSUBCODE_WPEM 1 /* ... on Memory Accesses */
1520 #define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */
1521 #define EXCCODE_BTE 21 /* Binary Trans. Exception */
1522 #define EXCCODE_GSPR 22 /* Guest Privileged Error */
1523 #define EXCCODE_HVC 23 /* Hypercall */
1524 #define EXCCODE_GCM 24 /* Guest CSR modified */
1525 #define EXCSUBCODE_GCSC 0 /* Software caused */
1526 #define EXCSUBCODE_GCHC 1 /* Hardware caused */
1527 #define EXCCODE_SE 25 /* Security */
1528
1529 /* Interrupt numbers */
1530 #define INT_SWI0 0 /* Software Interrupts */
1531 #define INT_SWI1 1
1532 #define INT_HWI0 2 /* Hardware Interrupts */
1533 #define INT_HWI1 3
1534 #define INT_HWI2 4
1535 #define INT_HWI3 5
1536 #define INT_HWI4 6
1537 #define INT_HWI5 7
1538 #define INT_HWI6 8
1539 #define INT_HWI7 9
1540 #define INT_PCOV 10 /* Performance Counter Overflow */
1541 #define INT_TI 11 /* Timer */
1542 #define INT_IPI 12
1543 #define INT_NMI 13
1544 #define INT_AVEC 14
1545
1546 /* ExcCodes corresponding to interrupts */
1547 #define EXCCODE_INT_NUM (INT_AVEC + 1)
1548 #define EXCCODE_INT_START 64
1549 #define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
1550
1551 /* FPU Status Register Names */
1552 #ifndef CONFIG_AS_HAS_FCSR_CLASS
1553 #define LOONGARCH_FCSR0 $r0
1554 #define LOONGARCH_FCSR1 $r1
1555 #define LOONGARCH_FCSR2 $r2
1556 #define LOONGARCH_FCSR3 $r3
1557 #else
1558 #define LOONGARCH_FCSR0 $fcsr0
1559 #define LOONGARCH_FCSR1 $fcsr1
1560 #define LOONGARCH_FCSR2 $fcsr2
1561 #define LOONGARCH_FCSR3 $fcsr3
1562 #endif
1563
1564 /* FPU Status Register Values */
1565 #define FPU_CSR_RSVD 0xe0e0fce0
1566
1567 /*
1568 * X the exception cause indicator
1569 * E the exception enable
1570 * S the sticky/flag bit
1571 */
1572 #define FPU_CSR_ALL_X 0x1f000000
1573 #define FPU_CSR_INV_X 0x10000000
1574 #define FPU_CSR_DIV_X 0x08000000
1575 #define FPU_CSR_OVF_X 0x04000000
1576 #define FPU_CSR_UDF_X 0x02000000
1577 #define FPU_CSR_INE_X 0x01000000
1578
1579 #define FPU_CSR_ALL_S 0x001f0000
1580 #define FPU_CSR_INV_S 0x00100000
1581 #define FPU_CSR_DIV_S 0x00080000
1582 #define FPU_CSR_OVF_S 0x00040000
1583 #define FPU_CSR_UDF_S 0x00020000
1584 #define FPU_CSR_INE_S 0x00010000
1585
1586 #define FPU_CSR_ALL_E 0x0000001f
1587 #define FPU_CSR_INV_E 0x00000010
1588 #define FPU_CSR_DIV_E 0x00000008
1589 #define FPU_CSR_OVF_E 0x00000004
1590 #define FPU_CSR_UDF_E 0x00000002
1591 #define FPU_CSR_INE_E 0x00000001
1592
1593 /* Bits 8 and 9 of FPU Status Register specify the rounding mode */
1594 #define FPU_CSR_RM 0x300
1595 #define FPU_CSR_RN 0x000 /* nearest */
1596 #define FPU_CSR_RZ 0x100 /* towards zero */
1597 #define FPU_CSR_RU 0x200 /* towards +Infinity */
1598 #define FPU_CSR_RD 0x300 /* towards -Infinity */
1599
1600 /* Bit 6 of FPU Status Register specify the LBT TOP simulation mode */
1601 #define FPU_CSR_TM_SHIFT 0x6
1602 #define FPU_CSR_TM (_ULCAST_(1) << FPU_CSR_TM_SHIFT)
1603
1604 #define read_fcsr(source) \
1605 ({ \
1606 unsigned int __res; \
1607 \
1608 __asm__ __volatile__( \
1609 " movfcsr2gr %0, "__stringify(source)" \n" \
1610 : "=r" (__res)); \
1611 __res; \
1612 })
1613
1614 #define write_fcsr(dest, val) \
1615 do { \
1616 __asm__ __volatile__( \
1617 " movgr2fcsr "__stringify(dest)", %0 \n" \
1618 : : "r" (val)); \
1619 } while (0)
1620
1621 #endif /* _ASM_LOONGARCH_H */
1622