xref: /linux/drivers/gpu/drm/logicvc/logicvc_regs.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2019-2022 Bootlin
4  * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
5  *
6  * Copyright (C) 2014 Xylon d.o.o.
7  * Author: Davor Joja <davor.joja@logicbricks.com>
8  */
9 
10 #ifndef _LOGICVC_REGS_H_
11 #define _LOGICVC_REGS_H_
12 
13 #define LOGICVC_DIMENSIONS_MAX		(BIT(16) - 1)
14 
15 #define LOGICVC_HSYNC_FRONT_PORCH_REG	0x00
16 #define LOGICVC_HSYNC_REG		0x08
17 #define LOGICVC_HSYNC_BACK_PORCH_REG	0x10
18 #define LOGICVC_HRES_REG		0x18
19 #define LOGICVC_VSYNC_FRONT_PORCH_REG	0x20
20 #define LOGICVC_VSYNC_REG		0x28
21 #define LOGICVC_VSYNC_BACK_PORCH_REG	0x30
22 #define LOGICVC_VRES_REG		0x38
23 
24 #define LOGICVC_CTRL_REG		0x40
25 #define LOGICVC_CTRL_CLOCK_INVERT	BIT(8)
26 #define LOGICVC_CTRL_PIXEL_INVERT	BIT(7)
27 #define LOGICVC_CTRL_DE_INVERT		BIT(5)
28 #define LOGICVC_CTRL_DE_ENABLE		BIT(4)
29 #define LOGICVC_CTRL_VSYNC_INVERT	BIT(3)
30 #define LOGICVC_CTRL_VSYNC_ENABLE	BIT(2)
31 #define LOGICVC_CTRL_HSYNC_INVERT	BIT(1)
32 #define LOGICVC_CTRL_HSYNC_ENABLE	BIT(0)
33 
34 #define LOGICVC_DTYPE_REG		0x48
35 #define LOGICVC_BACKGROUND_COLOR_REG	0x50
36 
37 #define LOGICVC_BUFFER_SEL_REG		0x58
38 #define LOGICVC_BUFFER_SEL_VALUE(i, v) \
39 	(BIT(10 + (i)) | ((v) << (2 * (i))))
40 #define LOGICVC_BUFFER_SEL_MAX		2
41 
42 #define LOGICVC_DOUBLE_CLUT_REG		0x60
43 
44 #define LOGICVC_INT_STAT_REG		0x68
45 #define LOGICVC_INT_STAT_V_SYNC		BIT(5)
46 
47 #define LOGICVC_INT_MASK_REG		0x70
48 #define LOGICVC_INT_MASK_V_SYNC		BIT(5)
49 
50 #define LOGICVC_POWER_CTRL_REG		0x78
51 #define LOGICVC_POWER_CTRL_BACKLIGHT_ENABLE	BIT(0)
52 #define LOGICVC_POWER_CTRL_VDD_ENABLE		BIT(1)
53 #define LOGICVC_POWER_CTRL_VEE_ENABLE		BIT(2)
54 #define LOGICVC_POWER_CTRL_VIDEO_ENABLE		BIT(3)
55 
56 #define LOGICVC_IP_VERSION_REG		0xf8
57 #define LOGICVC_IP_VERSION_MAJOR_MASK	GENMASK(16, 11)
58 #define LOGICVC_IP_VERSION_MINOR_MASK	GENMASK(10, 5)
59 #define LOGICVC_IP_VERSION_LEVEL_MASK	GENMASK(4, 0)
60 
61 #define LOGICVC_LAYER_ADDRESS_REG(i)	(0x100 + (i) * 0x80)
62 #define LOGICVC_LAYER_HOFFSET_REG(i)	(0x100 + (i) * 0x80)
63 
64 #define LOGICVC_LAYER_VOFFSET_REG(i)	(0x108 + (i) * 0x80)
65 #define LOGICVC_LAYER_VOFFSET_MAX	4095
66 
67 #define LOGICVC_LAYER_HPOSITION_REG(i)	(0x110 + (i) * 0x80)
68 #define LOGICVC_LAYER_VPOSITION_REG(i)	(0x118 + (i) * 0x80)
69 #define LOGICVC_LAYER_WIDTH_REG(i)	(0x120 + (i) * 0x80)
70 #define LOGICVC_LAYER_HEIGHT_REG(i)	(0x128 + (i) * 0x80)
71 #define LOGICVC_LAYER_ALPHA_REG(i)	(0x130 + (i) * 0x80)
72 
73 #define LOGICVC_LAYER_CTRL_REG(i)	(0x138 + (i) * 0x80)
74 #define LOGICVC_LAYER_CTRL_ENABLE	BIT(0)
75 #define LOGICVC_LAYER_CTRL_COLOR_KEY_DISABLE	BIT(1)
76 #define LOGICVC_LAYER_CTRL_PIXEL_FORMAT_INVERT	BIT(4)
77 
78 #define LOGICVC_LAYER_COLOR_KEY_REG(i)	(0x140 + (i) * 0x80)
79 
80 #endif
81