1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_REGS_H_ 7 #define _XE_GT_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset 13 * for the media GT. xe_mmio and xe_gt_mcr functions will automatically 14 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. 15 */ 16 #define MEDIA_GT_GSI_OFFSET 0x380000 17 #define MEDIA_GT_GSI_LENGTH 0x40000 18 19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) 21 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 22 #define MTL_CC_MASK REG_GENMASK(12, 9) 23 #define MTL_CRST 0xf 24 25 /* RPM unit config (Gen8+) */ 26 #define RPM_CONFIG0 XE_REG(0xd00) 27 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 28 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 29 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 30 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 31 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 32 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 33 34 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4) 35 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4) 36 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84) 37 38 #define GMD_ID XE_REG(0xd8c) 39 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 40 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 41 /* 42 * Spec defines these bits as "Reserved", but then make them assume some 43 * meaning that depends on the ARCH. To avoid any confusion, call them 44 * SUBIP_FLAG_MASK. 45 */ 46 #define GMD_ID_SUBIP_FLAG_MASK REG_GENMASK(13, 6) 47 #define GMD_ID_REVID REG_GENMASK(5, 0) 48 49 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) 50 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) 51 52 #define STEER_SEMAPHORE XE_REG(0xfd0) 53 #define MTL_MCR_SELECTOR XE_REG(0xfd4) 54 #define SF_MCR_SELECTOR XE_REG(0xfd8) 55 #define MCR_SELECTOR XE_REG(0xfdc) 56 #define GAM_MCR_SELECTOR XE_REG(0xfe0) 57 #define MCR_MULTICAST REG_BIT(31) 58 #define MCR_SLICE_MASK REG_GENMASK(30, 27) 59 #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) 60 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) 61 #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) 62 #define MTL_MCR_GROUPID REG_GENMASK(12, 8) 63 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 64 65 #define PS_INVOCATION_COUNT XE_REG(0x2348) 66 67 #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) 68 #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4) 69 #define LE_SSE_MASK REG_GENMASK(18, 17) 70 #define LE_SSE(value) REG_FIELD_PREP(LE_SSE_MASK, value) 71 #define LE_COS_MASK REG_GENMASK(16, 15) 72 #define LE_SCF_MASK REG_BIT(14) 73 #define LE_SCF(value) REG_FIELD_PREP(LE_SCF_MASK, value) 74 #define LE_PFM_MASK REG_GENMASK(13, 11) 75 #define LE_PFM(value) REG_FIELD_PREP(LE_PFM_MASK, value) 76 #define LE_SCC_MASK REG_GENMASK(10, 8) 77 #define LE_SCC(value) REG_FIELD_PREP(LE_SCC_MASK, value) 78 #define LE_RSC_MASK REG_BIT(7) 79 #define LE_RSC(value) REG_FIELD_PREP(LE_RSC_MASK, value) 80 #define LE_AOM_MASK REG_BIT(6) 81 #define LE_AOM(value) REG_FIELD_PREP(LE_AOM_MASK, value) 82 #define LE_LRUM_MASK REG_GENMASK(5, 4) 83 #define LE_LRUM(value) REG_FIELD_PREP(LE_LRUM_MASK, value) 84 #define LE_TGT_CACHE_MASK REG_GENMASK(3, 2) 85 #define LE_TGT_CACHE(value) REG_FIELD_PREP(LE_TGT_CACHE_MASK, value) 86 #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) 87 #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) 88 89 #define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148) 90 #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) 91 92 #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194) 93 #define EN_CMP_1WCOH REG_BIT(15) 94 #define CG_DIS_CNTLBUS REG_BIT(6) 95 96 #define CCS_AUX_INV XE_REG(0x4208) 97 98 #define VD0_AUX_INV XE_REG(0x4218) 99 #define VE0_AUX_INV XE_REG(0x4238) 100 101 #define VE1_AUX_INV XE_REG(0x42b8) 102 #define AUX_INV REG_BIT(0) 103 104 #define GAMSTLB_CTRL XE_REG_MCR(0x477c) 105 #define DIS_PEND_GPA_LINK REG_BIT(13) 106 107 #define GAMSTLB_CTRL2 XE_REG_MCR(0x4788) 108 #define STLB_SINGLE_BANK_MODE REG_BIT(11) 109 110 #define XE2_LMEM_CFG XE_REG(0x48b0) 111 112 #define XE2_GAMWALK_CTRL 0x47e4 113 #define XE2_GAMWALK_CTRL_MEDIA XE_REG(XE2_GAMWALK_CTRL + MEDIA_GT_GSI_OFFSET) 114 #define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL) 115 #define EN_CMP_1WCOH_GW REG_BIT(14) 116 117 #define MMIOATSREQLIMIT_GAM_WALK_3D XE_REG_MCR(0x47f8) 118 #define DIS_ATS_WRONLY_PG REG_BIT(18) 119 120 #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) 121 #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8) 122 123 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) 124 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) 125 126 #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED) 127 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 128 #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6) 129 130 #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) 131 #define TBIMR_FAST_CLIP REG_BIT(5) 132 133 #define FF_MODE XE_REG_MCR(0x6210) 134 #define DIS_TE_AUTOSTRIP REG_BIT(31) 135 #define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20) 136 #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16) 137 #define DIS_MESH_AUTOSTRIP REG_BIT(15) 138 #define DIS_TE_PATCH_CTRL REG_BIT(4) 139 140 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED) 141 #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9) 142 #define DIS_AUTOSTRIP REG_BIT(6) 143 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 144 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 145 146 #define FF_MODE2 XE_REG(0x6604) 147 #define XEHP_FF_MODE2 XE_REG_MCR(0x6604) 148 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 149 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 150 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 151 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 152 153 #define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c) 154 155 #define CACHE_MODE_1 XE_REG_MCR(0x7004, XE_REG_OPTION_MASKED) 156 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 157 158 #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED) 159 #define XEHP_COMMON_SLICE_CHICKEN1 XE_REG_MCR(0x7010, XE_REG_OPTION_MASKED) 160 #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST REG_BIT(14) 161 162 #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) 163 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 164 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 165 166 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) 167 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 168 169 #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) 170 #define FLSH_IGNORES_PSD REG_BIT(10) 171 #define FD_END_COLLECT REG_BIT(5) 172 173 #define SC_INSTDONE XE_REG(0x7100) 174 #define SC_INSTDONE_EXTRA XE_REG(0x7104) 175 #define SC_INSTDONE_EXTRA2 XE_REG(0x7108) 176 177 #define XEHPG_SC_INSTDONE XE_REG_MCR(0x7100) 178 #define XEHPG_SC_INSTDONE_EXTRA XE_REG_MCR(0x7104) 179 #define XEHPG_SC_INSTDONE_EXTRA2 XE_REG_MCR(0x7108) 180 181 #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) 182 #define XEHP_COMMON_SLICE_CHICKEN4 XE_REG_MCR(0x7300, XE_REG_OPTION_MASKED) 183 #define SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE REG_BIT(12) 184 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 185 #define HW_FILTERING REG_BIT(5) 186 187 #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED) 188 #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED) 189 #define DISABLE_STATE_CACHE_PERF_FIX REG_BIT(13) 190 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 191 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 192 #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 193 #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 194 195 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 196 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 197 #define FAST_CLEAR_VALIGN_FIX REG_BIT(13) 198 199 #define MSG_IDLE_CS XE_REG(0x8000) 200 #define MSG_IDLE_VCS0 XE_REG(0x8004) 201 #define MSG_IDLE_VCS1 XE_REG(0x8008) 202 #define MSG_IDLE_VCS2 XE_REG(0x80C0) 203 #define MSG_IDLE_VCS3 XE_REG(0x80C4) 204 #define MSG_IDLE_VCS4 XE_REG(0x80C8) 205 #define MSG_IDLE_VCS5 XE_REG(0x80CC) 206 #define MSG_IDLE_VCS6 XE_REG(0x80D0) 207 #define MSG_IDLE_VCS7 XE_REG(0x80D4) 208 #define MSG_IDLE_VECS0 XE_REG(0x8010) 209 #define MSG_IDLE_VECS1 XE_REG(0x80D8) 210 #define MSG_IDLE_VECS2 XE_REG(0x80DC) 211 #define MSG_IDLE_VECS3 XE_REG(0x80E0) 212 #define MSG_IDLE_BCS0 XE_REG(0x800C) 213 #define MSG_IDLE_BCS1 XE_REG(0x8680) 214 #define MSG_IDLE_BCS2 XE_REG(0x8684) 215 #define MSG_IDLE_BCS3 XE_REG(0x8688) 216 #define MSG_IDLE_BCS4 XE_REG(0x868C) 217 #define MSG_IDLE_BCS5 XE_REG(0x8690) 218 #define MSG_IDLE_BCS6 XE_REG(0x8694) 219 #define MSG_IDLE_BCS7 XE_REG(0x8698) 220 #define MSG_IDLE_BCS8 XE_REG(0x869C) 221 #define MSG_IDLE_GSCCS0 XE_REG(0xA62C) 222 #define MSG_IDLE_INDICATION REG_BIT(0) 223 #define MSG_IDLE_C6_ALLOWED REG_BIT(1) 224 #define MSG_IDLE_FW_REQ REG_GENMASK(13, 9) 225 226 #define XE2LPM_CCCHKNREG1 XE_REG(0x82a8) 227 228 #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED) 229 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 230 231 #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED) 232 #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13) 233 234 #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED) 235 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 236 237 #define SQCNT1 XE_REG_MCR(0x8718) 238 #define XELPMP_SQCNT1 XE_REG(0x8718) 239 #define SQCNT1_PMON_ENABLE REG_BIT(30) 240 #define SQCNT1_OABPC REG_BIT(29) 241 #define ENFORCE_RAR REG_BIT(23) 242 243 #define XEHP_SQCM XE_REG_MCR(0x8724) 244 #define EN_32B_ACCESS REG_BIT(30) 245 246 #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) 247 #define XE2_FLAT_CCS_ENABLE REG_BIT(0) 248 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6) 249 250 #define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804) 251 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0) 252 253 #define GSCPSMI_BASE XE_REG(0x880c) 254 255 #define CCCHKNREG1 XE_REG_MCR(0x8828) 256 #define L3CMPCTRL REG_BIT(23) 257 #define ENCOMPPERFFIX REG_BIT(18) 258 259 /* Fuse readout registers for GT */ 260 #define XEHP_FUSE4 XE_REG(0x9114) 261 #define CFEG_WMTP_DISABLE REG_BIT(20) 262 #define CCS_EN_MASK REG_GENMASK(19, 16) 263 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 264 265 #define MIRROR_FUSE3 XE_REG(0x9118) 266 #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) 267 #define L3BANK_PAIR_COUNT 4 268 #define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4) 269 #define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4) 270 #define L3BANK_MASK REG_GENMASK(3, 0) 271 #define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0) 272 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 273 #define MAX_MSLICES 4 274 #define MEML3_EN_MASK REG_GENMASK(3, 0) 275 276 #define MIRROR_FUSE1 XE_REG(0x911c) 277 278 #define FUSE2 XE_REG(0x9120) 279 #define PRODUCTION_HW REG_BIT(2) 280 281 #define MIRROR_L3BANK_ENABLE XE_REG(0x9130) 282 #define XE3_L3BANK_ENABLE REG_GENMASK(31, 0) 283 284 #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 285 #define XELP_EU_MASK REG_GENMASK(7, 0) 286 #define XELP_GT_SLICE_ENABLE XE_REG(0x9138) 287 #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) 288 289 #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) 290 #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 291 #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 292 293 #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) 294 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) 295 #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) 296 #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) 297 #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) 298 #define XE3P_XPC_GT_GEOMETRY_DSS_3 XE_REG(0x915c) 299 #define XE3P_XPC_GT_COMPUTE_DSS_3 XE_REG(0x9160) 300 301 #define SERVICE_COPY_ENABLE XE_REG(0x9170) 302 #define FUSE_SERVICE_COPY_ENABLE_MASK REG_GENMASK(7, 0) 303 304 #define GDRST XE_REG(0x941c) 305 #define GRDOM_GUC REG_BIT(3) 306 #define GRDOM_FULL REG_BIT(0) 307 308 #define MISCCPCTL XE_REG(0x9424) 309 #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 310 311 #define UNSLCGCTL9430 XE_REG(0x9430) 312 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 313 314 #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434) 315 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 316 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 317 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 318 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 319 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 320 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 321 322 #define UNSLCGCTL9440 XE_REG(0x9440) 323 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 324 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 325 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 326 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 327 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 328 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 329 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 330 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 331 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 332 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 333 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 334 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 335 336 #define UNSLCGCTL9444 XE_REG(0x9444) 337 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 338 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 339 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 340 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 341 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 342 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 343 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 344 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 345 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 346 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 347 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 348 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 349 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 350 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 351 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 352 #define LTCDD_CLKGATE_DIS REG_BIT(10) 353 354 #define UNSLCGCTL9454 XE_REG(0x9454) 355 #define LSCFE_CLKGATE_DIS REG_BIT(4) 356 357 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4) 358 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 359 #define L3_CLKGATE_DIS REG_BIT(16) 360 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 361 #define MSCUNIT_CLKGATE_DIS REG_BIT(10) 362 #define RCCUNIT_CLKGATE_DIS REG_BIT(7) 363 #define SARBUNIT_CLKGATE_DIS REG_BIT(5) 364 #define SBEUNIT_CLKGATE_DIS REG_BIT(4) 365 366 #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4) 367 #define VSUNIT_CLKGATE2_DIS REG_BIT(19) 368 369 #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524) 370 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 371 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 372 373 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528) 374 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 375 376 #define SSMCGCTL9530 XE_REG_MCR(0x9530) 377 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 378 379 #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550) 380 #define DFR_DISABLE REG_BIT(9) 381 382 #define RPNSWREQ XE_REG(0xa008) 383 #define REQ_RATIO_MASK REG_GENMASK(31, 23) 384 385 #define RP_CONTROL XE_REG(0xa024) 386 #define RPSWCTL_MASK REG_GENMASK(10, 9) 387 #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) 388 #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) 389 #define RC_CONTROL XE_REG(0xa090) 390 #define RC_CTL_HW_ENABLE REG_BIT(31) 391 #define RC_CTL_TO_MODE REG_BIT(28) 392 #define RC_CTL_RC6_ENABLE REG_BIT(18) 393 #define RC_STATE XE_REG(0xa094) 394 #define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) 395 #define MEDIA_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c4) 396 #define RENDER_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c8) 397 398 #define PMINTRMSK XE_REG(0xa168) 399 #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) 400 #define ARAT_EXPIRED_INTRMSK REG_BIT(9) 401 402 #define FORCEWAKE_GT XE_REG(0xa188) 403 404 #define POWERGATE_ENABLE XE_REG(0xa210) 405 #define RENDER_POWERGATE_ENABLE REG_BIT(0) 406 #define MEDIA_POWERGATE_ENABLE REG_BIT(1) 407 #define MEDIA_SAMPLERS_POWERGATE_ENABLE REG_BIT(2) 408 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 409 #define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 410 411 #define FORCEWAKE_RENDER XE_REG(0xa278) 412 413 #define POWERGATE_DOMAIN_STATUS XE_REG(0xa2a0) 414 #define GSC_AWAKE_STATUS REG_BIT(8) 415 #define MEDIA_SLICE3_AWAKE_STATUS REG_BIT(4) 416 #define MEDIA_SLICE2_AWAKE_STATUS REG_BIT(3) 417 #define MEDIA_SLICE1_AWAKE_STATUS REG_BIT(2) 418 #define RENDER_AWAKE_STATUS REG_BIT(1) 419 #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0) 420 421 #define MISC_STATUS_0 XE_REG(0xa500) 422 423 #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) 424 #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) 425 #define FORCEWAKE_GSC XE_REG(0xa618) 426 427 #define XELP_GARBCNTL XE_REG(0xb004) 428 #define XELP_BUS_HASH_CTL_BIT_EXC REG_BIT(7) 429 430 #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) 431 #define XEHPC_OVRLSCCC REG_BIT(0) 432 433 #define LNCFCMOCS_REG_COUNT 32 434 #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) 435 #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) 436 #define L3_UPPER_LKUP_MASK REG_BIT(23) 437 #define L3_UPPER_GLBGO_MASK REG_BIT(22) 438 #define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20) 439 #define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17) 440 #define L3_UPPER_IDX_ESC_MASK REG_BIT(16) 441 #define L3_LKUP_MASK REG_BIT(7) 442 #define L3_LKUP(value) REG_FIELD_PREP(L3_LKUP_MASK, value) 443 #define L3_GLBGO_MASK REG_BIT(6) 444 #define L3_GLBGO(value) REG_FIELD_PREP(L3_GLBGO_MASK, value) 445 #define L3_CACHEABILITY_MASK REG_GENMASK(5, 4) 446 #define L3_CACHEABILITY(value) REG_FIELD_PREP(L3_CACHEABILITY_MASK, value) 447 #define L3_SCC_MASK REG_GENMASK(3, 1) 448 #define L3_SCC(value) REG_FIELD_PREP(L3_SCC_MASK, value) 449 #define L3_ESC_MASK REG_BIT(0) 450 #define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value) 451 452 #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) 453 #define XEHP_LNESPARE REG_BIT(19) 454 455 #define LSN_VC_REG2 XE_REG_MCR(0xb0c8) 456 #define LSN_LNI_WGT_MASK REG_GENMASK(31, 28) 457 #define LSN_LNI_WGT(value) REG_FIELD_PREP(LSN_LNI_WGT_MASK, value) 458 #define LSN_LNE_WGT_MASK REG_GENMASK(27, 24) 459 #define LSN_LNE_WGT(value) REG_FIELD_PREP(LSN_LNE_WGT_MASK, value) 460 #define LSN_DIM_X_WGT_MASK REG_GENMASK(23, 20) 461 #define LSN_DIM_X_WGT(value) REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value) 462 #define LSN_DIM_Y_WGT_MASK REG_GENMASK(19, 16) 463 #define LSN_DIM_Y_WGT(value) REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value) 464 #define LSN_DIM_Z_WGT_MASK REG_GENMASK(15, 12) 465 #define LSN_DIM_Z_WGT(value) REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value) 466 467 #define L3SQCREG2 XE_REG_MCR(0xb104) 468 #define L3_SQ_DISABLE_COAMA_2WAY_COH REG_BIT(30) 469 #define L3_SQ_DISABLE_COAMA REG_BIT(22) 470 #define COMPMEMRD256BOVRFETCHEN REG_BIT(20) 471 #define NONCOMPMEMRD256BOVRFETCHEN REG_BIT(14) 472 473 #define L3SQCREG3 XE_REG_MCR(0xb108) 474 #define COMPPWOVERFETCHEN REG_BIT(28) 475 476 #define SCRATCH3_LBCF XE_REG_MCR(0xb154) 477 #define RWFLUSHALLEN REG_BIT(17) 478 479 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) 480 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 481 482 #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188) 483 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 484 485 #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) 486 487 #define L2COMPUTESIDECTRL XE_REG_MCR(0xb1c0) 488 #define CECTRL REG_GENMASK(2, 1) 489 #define CECTRL_CENODATA_ALWAYS REG_FIELD_PREP(CECTRL, 0x0) 490 491 #define XE2_GLOBAL_INVAL XE_REG(0xb404) 492 493 #define XE2LPM_L3SQCREG2 XE_REG_MCR(0xb604) 494 495 #define XE2LPM_L3SQCREG3 XE_REG_MCR(0xb608) 496 497 #define XE2LPM_SCRATCH3_LBCF XE_REG_MCR(0xb654) 498 499 #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) 500 501 #define XE2_TDF_CTRL XE_REG(0xb418) 502 #define TRANSIENT_FLUSH_REQUEST REG_BIT(0) 503 504 #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) 505 #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) 506 #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) 507 #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34) 508 #define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34) 509 #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38) 510 #define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38) 511 #define FORCE_MISS_FTLB REG_BIT(3) 512 513 #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c) 514 #define BANK_HASH_MODE REG_GENMASK(27, 26) 515 #define BANK_HASH_4KB_MODE REG_FIELD_PREP(BANK_HASH_MODE, 0x3) 516 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 517 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 518 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 519 520 #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54) 521 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 522 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 523 524 #define LMEM_CFG XE_REG(0xcf58) 525 #define LMEM_EN REG_BIT(31) 526 #define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */ 527 528 #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) 529 #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) 530 531 #define SAMPLER_INSTDONE XE_REG_MCR(0xe160) 532 #define ROW_INSTDONE XE_REG_MCR(0xe164) 533 534 #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED) 535 #define ENABLE_SMALLPL REG_BIT(15) 536 #define SMP_WAIT_FETCH_MERGING_COUNTER REG_GENMASK(11, 10) 537 #define SMP_FORCE_128B_OVERFETCH REG_FIELD_PREP(SMP_WAIT_FETCH_MERGING_COUNTER, 1) 538 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 539 #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 540 #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 541 542 #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) 543 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 544 #define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6) 545 546 #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) 547 #define DISABLE_ECC REG_BIT(5) 548 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 549 550 #define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED) 551 #define DISABLE_GRF_CLEAR REG_BIT(13) 552 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 553 #define DISABLE_TDL_PUSH REG_BIT(9) 554 #define DIS_PICK_2ND_EU REG_BIT(7) 555 #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 556 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 557 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 558 559 #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) 560 #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) 561 #define DIS_EU_GRF_POISON_TO_LSC REG_BIT(13) 562 #define DIS_FIX_EOT1_FLUSH REG_BIT(9) 563 564 #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) 565 #define STK_ID_RESTRICT REG_BIT(12) 566 #define SLM_WMTP_RESTORE REG_BIT(11) 567 #define RES_CHK_SPR_DIS REG_BIT(6) 568 569 #define TDL_TSL_CHICKEN2 XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED) 570 #define TILEY_LOCALID REG_BIT(2) 571 572 #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) 573 #define UGM_BACKUP_MODE REG_BIT(13) 574 #define MDQ_ARBITRATION_MODE REG_BIT(12) 575 #define STALL_DOP_GATING_DISABLE REG_BIT(5) 576 #define EARLY_EOT_DIS REG_BIT(1) 577 578 #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED) 579 #define DISABLE_READ_SUPPRESSION REG_BIT(15) 580 #define DISABLE_EARLY_READ REG_BIT(14) 581 #define ENABLE_LARGE_GRF_MODE REG_BIT(12) 582 #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 583 #define DISABLE_TDL_SVHS_GATING REG_BIT(1) 584 #define DISABLE_DOP_GATING REG_BIT(0) 585 586 #define RT_CTRL XE_REG_MCR(0xe530) 587 #define DIS_NULL_QUERY REG_BIT(10) 588 589 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) 590 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) 591 592 #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) 593 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 594 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 595 596 #define TDL_CHICKEN XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED) 597 #define BIT_APQ_OPT_DIS REG_BIT(14) 598 #define QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE REG_BIT(12) 599 #define EUSTALL_PERF_SAMPLING_DISABLE REG_BIT(5) 600 601 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) 602 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 603 #define WR_REQ_CHAINING_DIS REG_BIT(26) 604 #define TGM_WRITE_EOM_FORCE REG_BIT(17) 605 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 606 #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) 607 608 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) 609 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) 610 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 611 #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32) 612 #define SAMPLER_LD_LSC_DISABLE REG_BIT(45 - 32) 613 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 614 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 615 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 616 #define L3_128B_256B_WRT_DIS REG_BIT(40 - 32) 617 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 618 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 619 #define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32) 620 621 #define ROW_CHICKEN5 XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED) 622 #define CPSS_AWARE_DIS REG_BIT(3) 623 624 #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) 625 #define COMP_CKN_IN REG_GENMASK(30, 29) 626 627 #define MAIN_GAMCTRL_MODE XE_REG(0xef00) 628 #define MAIN_GAMCTRL_QUEUE_SELECT REG_BIT(0) 629 630 #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED) 631 #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 632 #define RCU_MODE_CCS_ENABLE REG_BIT(0) 633 634 /* 635 * Total of 4 cslices, where each cslice is in the form: 636 * [0-3] CCS ID 637 * [4-6] RSVD 638 * [7] Disabled 639 */ 640 #define CCS_MODE XE_REG(0x14804) 641 #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ 642 #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ 643 #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) 644 #define CCS_MODE_CSLICE(cslice, ccs) \ 645 ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH)) 646 647 #define FORCEWAKE_ACK_GT XE_REG(0x130044) 648 649 /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */ 650 #define FORCEWAKE_KERNEL 0 651 #define FORCEWAKE_MT(bit) BIT(bit) 652 #define FORCEWAKE_MT_MASK(bit) BIT((bit) + 16) 653 654 #define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) 655 #define MTL_MEDIA_MC6 XE_REG(0x138048) 656 657 #define GT_CORE_STATUS XE_REG(0x138060) 658 #define RCN_MASK REG_GENMASK(2, 0) 659 #define GT_C0 0 660 #define GT_C6 3 661 662 #define GT_GFX_RC6_LOCKED XE_REG(0x138104) 663 #define GT_GFX_RC6 XE_REG(0x138108) 664 665 #define GT_IA_PERF_BIAS_REG XE_REG(0x138158) 666 #define GT_BIAS REG_GENMASK(31, 16) 667 #define IA_BIAS REG_GENMASK(15, 0) 668 #define GT_BIAS_DEFAULT 0x10 669 #define IA_BIAS_DEFAULT 0x10 670 671 #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) 672 /* Common performance limit reason bits - available on all platforms */ 673 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 674 #define PROCHOT_MASK REG_BIT(0) 675 #define THERMAL_LIMIT_MASK REG_BIT(1) 676 #define RATL_MASK REG_BIT(5) 677 #define VR_THERMALERT_MASK REG_BIT(6) 678 #define VR_TDC_MASK REG_BIT(7) 679 #define POWER_LIMIT_4_MASK REG_BIT(8) 680 #define POWER_LIMIT_1_MASK REG_BIT(10) 681 #define POWER_LIMIT_2_MASK REG_BIT(11) 682 /* Platform-specific performance limit reason bits - for Crescent Island */ 683 #define CRI_PERF_LIMIT_REASONS_MASK 0xfdff 684 #define SOC_THERMAL_LIMIT_MASK REG_BIT(1) 685 #define MEM_THERMAL_MASK REG_BIT(2) 686 #define VR_THERMAL_MASK REG_BIT(3) 687 #define ICCMAX_MASK REG_BIT(4) 688 #define PWRBRK_MASK REG_BIT(5) 689 #define SOC_AVG_THERMAL_MASK REG_BIT(6) 690 #define FASTVMODE_MASK REG_BIT(7) 691 #define PSYS_PL1_MASK REG_BIT(12) 692 #define PSYS_PL2_MASK REG_BIT(13) 693 #define P0_FREQ_MASK REG_BIT(14) 694 #define PSYS_CRIT_MASK REG_BIT(15) 695 696 #define GT_PERF_STATUS XE_REG(0x1381b4) 697 #define VOLTAGE_MASK REG_GENMASK(10, 0) 698 699 #define SFC_DONE(n) XE_REG(0x1cc000 + (n) * 0x1000) 700 701 #endif 702