1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 #include <net/phy/realtek_phy.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 60 #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" 61 #define FIRMWARE_8125K_1 "rtl_nic/rtl8125k-1.fw" 62 #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" 63 #define FIRMWARE_8125CP_1 "rtl_nic/rtl8125cp-1.fw" 64 #define FIRMWARE_9151A_1 "rtl_nic/rtl9151a-1.fw" 65 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 66 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 67 #define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw" 68 69 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 70 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 71 72 #define R8169_REGS_SIZE 256 73 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 74 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 75 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 76 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 77 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 78 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 79 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 80 81 #define OCP_STD_PHY_BASE 0xa400 82 83 #define RTL_CFG_NO_GBIT 1 84 85 /* write/read MMIO register */ 86 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 87 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 88 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 89 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 90 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 91 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 92 93 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 94 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 95 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 96 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 97 #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) 98 99 static const struct rtl_chip_info { 100 u32 mask; 101 u32 val; 102 enum mac_version mac_version; 103 const char *name; 104 const char *fw_name; 105 } rtl_chip_infos[] = { 106 /* 8127A family. */ 107 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 }, 108 109 /* 8126A family. */ 110 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, 111 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, 112 113 /* 8125BP family. */ 114 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, 115 116 /* 8125CP family*/ 117 { 0x7cf, 0x708, RTL_GIGA_MAC_VER_65, "RTL8125CP", FIRMWARE_8125CP_1 }, 118 119 /* 8125D family. */ 120 { 0x7cf, 0x68b, RTL_GIGA_MAC_VER_64, "RTL9151A", FIRMWARE_9151A_1 }, 121 { 0x7cf, 0x68a, RTL_GIGA_MAC_VER_64, "RTL8125K", FIRMWARE_8125K_1 }, 122 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 }, 123 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, 124 125 /* 8125B family. */ 126 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 }, 127 128 /* 8125A family. */ 129 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, 130 131 /* RTL8117 */ 132 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" }, 133 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", 134 FIRMWARE_8168FP_3 }, 135 136 /* 8168EP family. */ 137 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" }, 138 139 /* 8168H family. */ 140 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h", 141 FIRMWARE_8168H_2 }, 142 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 143 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 }, 144 145 /* 8168G family. */ 146 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 }, 147 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu", 148 FIRMWARE_8168G_3 }, 149 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g", 150 FIRMWARE_8168G_2 }, 151 152 /* 8168F family. */ 153 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 }, 154 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f", 155 FIRMWARE_8168F_2 }, 156 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f", 157 FIRMWARE_8168F_1 }, 158 159 /* 8168E family. */ 160 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl", 161 FIRMWARE_8168E_3 }, 162 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e", 163 FIRMWARE_8168E_1 }, 164 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e", 165 FIRMWARE_8168E_2 }, 166 167 /* 8168D family. */ 168 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d", 169 FIRMWARE_8168D_1 }, 170 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d", 171 FIRMWARE_8168D_2 }, 172 173 /* 8168DP family. */ 174 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" }, 175 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" }, 176 177 /* 8168C family. */ 178 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" }, 179 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" }, 180 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" }, 181 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" }, 182 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" }, 183 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" }, 184 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" }, 185 186 /* 8168B family. */ 187 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" }, 188 /* This one is very old and rare, support has been removed. 189 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, 190 */ 191 192 /* 8101 family. */ 193 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 }, 194 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 }, 195 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 }, 196 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 }, 197 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 198 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 199 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 200 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 201 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" }, 202 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 203 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 204 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" }, 205 206 /* 8110 family. */ 207 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" }, 208 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" }, 209 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" }, 210 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" }, 211 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" }, 212 213 /* extended chip version*/ 214 { 0x7cf, 0x7c8, RTL_GIGA_MAC_VER_EXTENDED }, 215 216 /* Catch-all */ 217 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 218 }; 219 220 static const struct rtl_chip_info rtl_chip_infos_extended[] = { 221 { 0x7fffffff, 0x00000000, RTL_GIGA_MAC_VER_64, "RTL9151AS", 222 FIRMWARE_9151A_1}, 223 224 /* Catch-all */ 225 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } 226 }; 227 228 static const struct pci_device_id rtl8169_pci_tbl[] = { 229 { PCI_VDEVICE(REALTEK, 0x2502) }, 230 { PCI_VDEVICE(REALTEK, 0x2600) }, 231 { PCI_VDEVICE(REALTEK, 0x8129) }, 232 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 233 { PCI_VDEVICE(REALTEK, 0x8161) }, 234 { PCI_VDEVICE(REALTEK, 0x8162) }, 235 { PCI_VDEVICE(REALTEK, 0x8167) }, 236 { PCI_VDEVICE(REALTEK, 0x8168) }, 237 { PCI_VDEVICE(NCUBE, 0x8168) }, 238 { PCI_VDEVICE(REALTEK, 0x8169) }, 239 { PCI_VDEVICE(DLINK, 0x4300) }, 240 { PCI_VDEVICE(DLINK, 0x4302) }, 241 { PCI_VDEVICE(AT, 0xc107) }, 242 { PCI_VDEVICE(USR, 0x0116) }, 243 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 244 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 245 { PCI_VDEVICE(REALTEK, 0x8125) }, 246 { PCI_VDEVICE(REALTEK, 0x8126) }, 247 { PCI_VDEVICE(REALTEK, 0x8127) }, 248 { PCI_VDEVICE(REALTEK, 0x3000) }, 249 { PCI_VDEVICE(REALTEK, 0x5000) }, 250 { PCI_VDEVICE(REALTEK, 0x0e10) }, 251 {} 252 }; 253 254 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 255 256 enum rtl_registers { 257 MAC0 = 0, /* Ethernet hardware address. */ 258 MAC4 = 4, 259 MAR0 = 8, /* Multicast filter. */ 260 CounterAddrLow = 0x10, 261 CounterAddrHigh = 0x14, 262 TxDescStartAddrLow = 0x20, 263 TxDescStartAddrHigh = 0x24, 264 TxHDescStartAddrLow = 0x28, 265 TxHDescStartAddrHigh = 0x2c, 266 FLASH = 0x30, 267 ERSR = 0x36, 268 ChipCmd = 0x37, 269 TxPoll = 0x38, 270 IntrMask = 0x3c, 271 IntrStatus = 0x3e, 272 273 TxConfig = 0x40, 274 /* Extended chip version id */ 275 TX_CONFIG_V2 = 0x60b0, 276 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 277 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 278 279 RxConfig = 0x44, 280 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 281 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 282 #define RXCFG_FIFO_SHIFT 13 283 /* No threshold before first PCI xfer */ 284 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 285 #define RX_EARLY_OFF (1 << 11) 286 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 287 #define RXCFG_DMA_SHIFT 8 288 /* Unlimited maximum PCI burst. */ 289 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 290 291 Cfg9346 = 0x50, 292 Config0 = 0x51, 293 Config1 = 0x52, 294 Config2 = 0x53, 295 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 296 297 Config3 = 0x54, 298 Config4 = 0x55, 299 Config5 = 0x56, 300 PHYAR = 0x60, 301 PHYstatus = 0x6c, 302 RxMaxSize = 0xda, 303 CPlusCmd = 0xe0, 304 IntrMitigate = 0xe2, 305 306 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 307 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 308 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 309 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 310 311 #define RTL_COALESCE_T_MAX 0x0fU 312 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 313 314 RxDescAddrLow = 0xe4, 315 RxDescAddrHigh = 0xe8, 316 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 317 318 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 319 320 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 321 322 #define TxPacketMax (8064 >> 7) 323 #define EarlySize 0x27 324 325 FuncEvent = 0xf0, 326 FuncEventMask = 0xf4, 327 FuncPresetState = 0xf8, 328 IBCR0 = 0xf8, 329 IBCR2 = 0xf9, 330 IBIMR0 = 0xfa, 331 IBISR0 = 0xfb, 332 FuncForceEvent = 0xfc, 333 334 ALDPS_LTR = 0xe0a2, 335 LTR_OBFF_LOCK = 0xe032, 336 LTR_SNOOP = 0xe034, 337 338 #define ALDPS_LTR_EN BIT(0) 339 #define LTR_OBFF_LOCK_EN BIT(0) 340 #define LINK_SPEED_CHANGE_EN BIT(14) 341 #define LTR_SNOOP_EN GENMASK(15, 14) 342 }; 343 344 enum rtl8168_8101_registers { 345 CSIDR = 0x64, 346 CSIAR = 0x68, 347 #define CSIAR_FLAG 0x80000000 348 #define CSIAR_WRITE_CMD 0x80000000 349 #define CSIAR_BYTE_ENABLE 0x0000f000 350 #define CSIAR_ADDR_MASK 0x00000fff 351 PMCH = 0x6f, 352 #define D3COLD_NO_PLL_DOWN BIT(7) 353 #define D3HOT_NO_PLL_DOWN BIT(6) 354 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 355 EPHYAR = 0x80, 356 #define EPHYAR_FLAG 0x80000000 357 #define EPHYAR_WRITE_CMD 0x80000000 358 #define EPHYAR_REG_MASK 0x1f 359 #define EPHYAR_REG_SHIFT 16 360 #define EPHYAR_DATA_MASK 0xffff 361 DLLPR = 0xd0, 362 #define PFM_EN (1 << 6) 363 #define TX_10M_PS_EN (1 << 7) 364 DBG_REG = 0xd1, 365 #define FIX_NAK_1 (1 << 4) 366 #define FIX_NAK_2 (1 << 3) 367 TWSI = 0xd2, 368 MCU = 0xd3, 369 #define NOW_IS_OOB (1 << 7) 370 #define TX_EMPTY (1 << 5) 371 #define RX_EMPTY (1 << 4) 372 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 373 #define EN_NDP (1 << 3) 374 #define EN_OOB_RESET (1 << 2) 375 #define LINK_LIST_RDY (1 << 1) 376 EFUSEAR = 0xdc, 377 #define EFUSEAR_FLAG 0x80000000 378 #define EFUSEAR_WRITE_CMD 0x80000000 379 #define EFUSEAR_READ_CMD 0x00000000 380 #define EFUSEAR_REG_MASK 0x03ff 381 #define EFUSEAR_REG_SHIFT 8 382 #define EFUSEAR_DATA_MASK 0xff 383 MISC_1 = 0xf2, 384 #define PFM_D3COLD_EN (1 << 6) 385 }; 386 387 enum rtl8168_registers { 388 LED_CTRL = 0x18, 389 LED_FREQ = 0x1a, 390 EEE_LED = 0x1b, 391 ERIDR = 0x70, 392 ERIAR = 0x74, 393 #define ERIAR_FLAG 0x80000000 394 #define ERIAR_WRITE_CMD 0x80000000 395 #define ERIAR_READ_CMD 0x00000000 396 #define ERIAR_ADDR_BYTE_ALIGN 4 397 #define ERIAR_TYPE_SHIFT 16 398 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 399 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 400 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 401 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 402 #define ERIAR_MASK_SHIFT 12 403 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 404 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 405 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 406 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 407 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 408 EPHY_RXER_NUM = 0x7c, 409 OCPDR = 0xb0, /* OCP GPHY access */ 410 #define OCPDR_WRITE_CMD 0x80000000 411 #define OCPDR_READ_CMD 0x00000000 412 #define OCPDR_REG_MASK 0x7f 413 #define OCPDR_GPHY_REG_SHIFT 16 414 #define OCPDR_DATA_MASK 0xffff 415 OCPAR = 0xb4, 416 #define OCPAR_FLAG 0x80000000 417 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 418 #define OCPAR_GPHY_READ_CMD 0x0000f060 419 GPHY_OCP = 0xb8, 420 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 421 MISC = 0xf0, /* 8168e only. */ 422 #define TXPLA_RST (1 << 29) 423 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 424 #define PWM_EN (1 << 22) 425 #define RXDV_GATED_EN (1 << 19) 426 #define EARLY_TALLY_EN (1 << 16) 427 COMBO_LTR_EXTEND = 0xb6, 428 #define COMBO_LTR_EXTEND_EN BIT(0) 429 }; 430 431 enum rtl8125_registers { 432 LEDSEL0 = 0x18, 433 INT_CFG0_8125 = 0x34, 434 #define INT_CFG0_ENABLE_8125 BIT(0) 435 #define INT_CFG0_CLKREQEN BIT(3) 436 IntrMask_8125 = 0x38, 437 IntrStatus_8125 = 0x3c, 438 INT_CFG1_8125 = 0x7a, 439 LEDSEL2 = 0x84, 440 LEDSEL1 = 0x86, 441 TxPoll_8125 = 0x90, 442 LEDSEL3 = 0x96, 443 MAC0_BKP = 0x19e0, 444 RSS_CTRL_8125 = 0x4500, 445 Q_NUM_CTRL_8125 = 0x4800, 446 EEE_TXIDLE_TIMER_8125 = 0x6048, 447 }; 448 449 #define LEDSEL_MASK_8125 0x23f 450 451 #define RX_VLAN_INNER_8125 BIT(22) 452 #define RX_VLAN_OUTER_8125 BIT(23) 453 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 454 455 #define RX_FETCH_DFLT_8125 (8 << 27) 456 457 enum rtl_register_content { 458 /* InterruptStatusBits */ 459 SYSErr = 0x8000, 460 PCSTimeout = 0x4000, 461 SWInt = 0x0100, 462 TxDescUnavail = 0x0080, 463 RxFIFOOver = 0x0040, 464 LinkChg = 0x0020, 465 RxOverflow = 0x0010, 466 TxErr = 0x0008, 467 TxOK = 0x0004, 468 RxErr = 0x0002, 469 RxOK = 0x0001, 470 471 /* RxStatusDesc */ 472 RxRWT = (1 << 22), 473 RxRES = (1 << 21), 474 RxRUNT = (1 << 20), 475 RxCRC = (1 << 19), 476 477 /* ChipCmdBits */ 478 StopReq = 0x80, 479 CmdReset = 0x10, 480 CmdRxEnb = 0x08, 481 CmdTxEnb = 0x04, 482 RxBufEmpty = 0x01, 483 484 /* TXPoll register p.5 */ 485 HPQ = 0x80, /* Poll cmd on the high prio queue */ 486 NPQ = 0x40, /* Poll cmd on the low prio queue */ 487 FSWInt = 0x01, /* Forced software interrupt */ 488 489 /* Cfg9346Bits */ 490 Cfg9346_Lock = 0x00, 491 Cfg9346_Unlock = 0xc0, 492 493 /* rx_mode_bits */ 494 AcceptErr = 0x20, 495 AcceptRunt = 0x10, 496 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 497 AcceptBroadcast = 0x08, 498 AcceptMulticast = 0x04, 499 AcceptMyPhys = 0x02, 500 AcceptAllPhys = 0x01, 501 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 502 #define RX_CONFIG_ACCEPT_MASK 0x3f 503 504 /* TxConfigBits */ 505 TxInterFrameGapShift = 24, 506 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 507 508 /* Config1 register p.24 */ 509 LEDS1 = (1 << 7), 510 LEDS0 = (1 << 6), 511 Speed_down = (1 << 4), 512 MEMMAP = (1 << 3), 513 IOMAP = (1 << 2), 514 VPD = (1 << 1), 515 PMEnable = (1 << 0), /* Power Management Enable */ 516 517 /* Config2 register p. 25 */ 518 ClkReqEn = (1 << 7), /* Clock Request Enable */ 519 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 520 PCI_Clock_66MHz = 0x01, 521 PCI_Clock_33MHz = 0x00, 522 523 /* Config3 register p.25 */ 524 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 525 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 526 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 527 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 528 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 529 530 /* Config4 register */ 531 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 532 533 /* Config5 register p.27 */ 534 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 535 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 536 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 537 Spi_en = (1 << 3), 538 LanWake = (1 << 1), /* LanWake enable/disable */ 539 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 540 ASPM_en = (1 << 0), /* ASPM enable */ 541 542 /* CPlusCmd p.31 */ 543 EnableBist = (1 << 15), // 8168 8101 544 Mac_dbgo_oe = (1 << 14), // 8168 8101 545 EnAnaPLL = (1 << 14), // 8169 546 Normal_mode = (1 << 13), // unused 547 Force_half_dup = (1 << 12), // 8168 8101 548 Force_rxflow_en = (1 << 11), // 8168 8101 549 Force_txflow_en = (1 << 10), // 8168 8101 550 Cxpl_dbg_sel = (1 << 9), // 8168 8101 551 ASF = (1 << 8), // 8168 8101 552 PktCntrDisable = (1 << 7), // 8168 8101 553 Mac_dbgo_sel = 0x001c, // 8168 554 RxVlan = (1 << 6), 555 RxChkSum = (1 << 5), 556 PCIDAC = (1 << 4), 557 PCIMulRW = (1 << 3), 558 #define INTT_MASK GENMASK(1, 0) 559 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 560 561 /* rtl8169_PHYstatus */ 562 TBI_Enable = 0x80, 563 TxFlowCtrl = 0x40, 564 RxFlowCtrl = 0x20, 565 _1000bpsF = 0x10, 566 _100bps = 0x08, 567 _10bps = 0x04, 568 LinkStatus = 0x02, 569 FullDup = 0x01, 570 571 /* ResetCounterCommand */ 572 CounterReset = 0x1, 573 574 /* DumpCounterCommand */ 575 CounterDump = 0x8, 576 577 /* magic enable v2 */ 578 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 579 }; 580 581 enum rtl_desc_bit { 582 /* First doubleword. */ 583 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 584 RingEnd = (1 << 30), /* End of descriptor ring */ 585 FirstFrag = (1 << 29), /* First segment of a packet */ 586 LastFrag = (1 << 28), /* Final segment of a packet */ 587 }; 588 589 /* Generic case. */ 590 enum rtl_tx_desc_bit { 591 /* First doubleword. */ 592 TD_LSO = (1 << 27), /* Large Send Offload */ 593 #define TD_MSS_MAX 0x07ffu /* MSS value */ 594 595 /* Second doubleword. */ 596 TxVlanTag = (1 << 17), /* Add VLAN tag */ 597 }; 598 599 /* 8169, 8168b and 810x except 8102e. */ 600 enum rtl_tx_desc_bit_0 { 601 /* First doubleword. */ 602 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 603 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 604 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 605 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 606 }; 607 608 /* 8102e, 8168c and beyond. */ 609 enum rtl_tx_desc_bit_1 { 610 /* First doubleword. */ 611 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 612 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 613 #define GTTCPHO_SHIFT 18 614 #define GTTCPHO_MAX 0x7f 615 616 /* Second doubleword. */ 617 #define TCPHO_SHIFT 18 618 #define TCPHO_MAX 0x3ff 619 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 620 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 621 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 622 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 623 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 624 }; 625 626 enum rtl_rx_desc_bit { 627 /* Rx private */ 628 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 629 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 630 631 #define RxProtoUDP (PID1) 632 #define RxProtoTCP (PID0) 633 #define RxProtoIP (PID1 | PID0) 634 #define RxProtoMask RxProtoIP 635 636 IPFail = (1 << 16), /* IP checksum failed */ 637 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 638 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 639 640 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 641 642 RxVlanTag = (1 << 16), /* VLAN tag available */ 643 }; 644 645 #define RTL_GSO_MAX_SIZE_V1 32000 646 #define RTL_GSO_MAX_SEGS_V1 24 647 #define RTL_GSO_MAX_SIZE_V2 64000 648 #define RTL_GSO_MAX_SEGS_V2 64 649 650 struct TxDesc { 651 __le32 opts1; 652 __le32 opts2; 653 __le64 addr; 654 }; 655 656 struct RxDesc { 657 __le32 opts1; 658 __le32 opts2; 659 __le64 addr; 660 }; 661 662 struct ring_info { 663 struct sk_buff *skb; 664 u32 len; 665 }; 666 667 struct rtl8169_counters { 668 __le64 tx_packets; 669 __le64 rx_packets; 670 __le64 tx_errors; 671 __le32 rx_errors; 672 __le16 rx_missed; 673 __le16 align_errors; 674 __le32 tx_one_collision; 675 __le32 tx_multi_collision; 676 __le64 rx_unicast; 677 __le64 rx_broadcast; 678 __le32 rx_multicast; 679 __le16 tx_aborted; 680 __le16 tx_underrun; 681 /* new since RTL8125 */ 682 __le64 tx_octets; 683 __le64 rx_octets; 684 __le64 rx_multicast64; 685 __le64 tx_unicast64; 686 __le64 tx_broadcast64; 687 __le64 tx_multicast64; 688 __le32 tx_pause_on; 689 __le32 tx_pause_off; 690 __le32 tx_pause_all; 691 __le32 tx_deferred; 692 __le32 tx_late_collision; 693 __le32 tx_all_collision; 694 __le32 tx_aborted32; 695 __le32 align_errors32; 696 __le32 rx_frame_too_long; 697 __le32 rx_runt; 698 __le32 rx_pause_on; 699 __le32 rx_pause_off; 700 __le32 rx_pause_all; 701 __le32 rx_unknown_opcode; 702 __le32 rx_mac_error; 703 __le32 tx_underrun32; 704 __le32 rx_mac_missed; 705 __le32 rx_tcam_dropped; 706 __le32 tdu; 707 __le32 rdu; 708 }; 709 710 struct rtl8169_tc_offsets { 711 bool inited; 712 __le64 tx_errors; 713 __le32 tx_multi_collision; 714 __le16 tx_aborted; 715 __le16 rx_missed; 716 }; 717 718 enum rtl_flag { 719 RTL_FLAG_TASK_RESET_PENDING, 720 RTL_FLAG_TASK_TX_TIMEOUT, 721 RTL_FLAG_MAX 722 }; 723 724 enum rtl_dash_type { 725 RTL_DASH_NONE, 726 RTL_DASH_DP, 727 RTL_DASH_EP, 728 RTL_DASH_25_BP, 729 }; 730 731 struct rtl8169_private { 732 void __iomem *mmio_addr; /* memory map physical address */ 733 struct pci_dev *pci_dev; 734 struct net_device *dev; 735 struct phy_device *phydev; 736 struct napi_struct napi; 737 enum mac_version mac_version; 738 enum rtl_dash_type dash_type; 739 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 740 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 741 u32 dirty_tx; 742 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 743 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 744 dma_addr_t TxPhyAddr; 745 dma_addr_t RxPhyAddr; 746 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 747 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 748 u16 cp_cmd; 749 u16 tx_lpi_timer; 750 u32 irq_mask; 751 int irq; 752 struct clk *clk; 753 754 struct { 755 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 756 struct work_struct work; 757 } wk; 758 759 raw_spinlock_t mac_ocp_lock; 760 struct mutex led_lock; /* serialize LED ctrl RMW access */ 761 762 unsigned supports_gmii:1; 763 unsigned aspm_manageable:1; 764 unsigned dash_enabled:1; 765 bool sfp_mode:1; 766 dma_addr_t counters_phys_addr; 767 struct rtl8169_counters *counters; 768 struct rtl8169_tc_offsets tc_offset; 769 u32 saved_wolopts; 770 771 const char *fw_name; 772 struct rtl_fw *rtl_fw; 773 774 struct r8169_led_classdev *leds; 775 776 u32 ocp_base; 777 }; 778 779 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 780 781 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 782 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 783 MODULE_SOFTDEP("pre: realtek"); 784 MODULE_LICENSE("GPL"); 785 MODULE_FIRMWARE(FIRMWARE_8168D_1); 786 MODULE_FIRMWARE(FIRMWARE_8168D_2); 787 MODULE_FIRMWARE(FIRMWARE_8168E_1); 788 MODULE_FIRMWARE(FIRMWARE_8168E_2); 789 MODULE_FIRMWARE(FIRMWARE_8168E_3); 790 MODULE_FIRMWARE(FIRMWARE_8105E_1); 791 MODULE_FIRMWARE(FIRMWARE_8168F_1); 792 MODULE_FIRMWARE(FIRMWARE_8168F_2); 793 MODULE_FIRMWARE(FIRMWARE_8402_1); 794 MODULE_FIRMWARE(FIRMWARE_8411_1); 795 MODULE_FIRMWARE(FIRMWARE_8411_2); 796 MODULE_FIRMWARE(FIRMWARE_8106E_1); 797 MODULE_FIRMWARE(FIRMWARE_8106E_2); 798 MODULE_FIRMWARE(FIRMWARE_8168G_2); 799 MODULE_FIRMWARE(FIRMWARE_8168G_3); 800 MODULE_FIRMWARE(FIRMWARE_8168H_2); 801 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 802 MODULE_FIRMWARE(FIRMWARE_8107E_2); 803 MODULE_FIRMWARE(FIRMWARE_8125A_3); 804 MODULE_FIRMWARE(FIRMWARE_8125B_2); 805 MODULE_FIRMWARE(FIRMWARE_8125D_1); 806 MODULE_FIRMWARE(FIRMWARE_8125D_2); 807 MODULE_FIRMWARE(FIRMWARE_8125K_1); 808 MODULE_FIRMWARE(FIRMWARE_8125BP_2); 809 MODULE_FIRMWARE(FIRMWARE_8125CP_1); 810 MODULE_FIRMWARE(FIRMWARE_9151A_1); 811 MODULE_FIRMWARE(FIRMWARE_8126A_2); 812 MODULE_FIRMWARE(FIRMWARE_8126A_3); 813 MODULE_FIRMWARE(FIRMWARE_8127A_1); 814 815 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 816 { 817 return &tp->pci_dev->dev; 818 } 819 820 static void rtl_lock_config_regs(struct rtl8169_private *tp) 821 { 822 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 823 } 824 825 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 826 { 827 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 828 } 829 830 static void rtl_pci_commit(struct rtl8169_private *tp) 831 { 832 /* Read an arbitrary register to commit a preceding PCI write */ 833 RTL_R8(tp, ChipCmd); 834 } 835 836 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 837 { 838 u8 val; 839 840 val = RTL_R8(tp, Config2); 841 RTL_W8(tp, Config2, (val & ~clear) | set); 842 } 843 844 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 845 { 846 u8 val; 847 848 val = RTL_R8(tp, Config5); 849 RTL_W8(tp, Config5, (val & ~clear) | set); 850 } 851 852 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 853 u8 bits, bool cond) 854 { 855 u8 val, old_val; 856 857 old_val = RTL_R8(tp, reg); 858 if (cond) 859 val = old_val | bits; 860 else 861 val = old_val & ~bits; 862 if (val != old_val) 863 RTL_W8(tp, reg, val); 864 } 865 866 static bool rtl_is_8125(struct rtl8169_private *tp) 867 { 868 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 869 } 870 871 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 872 { 873 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 874 tp->mac_version != RTL_GIGA_MAC_VER_39 && 875 tp->mac_version <= RTL_GIGA_MAC_VER_52; 876 } 877 878 static bool rtl_supports_eee(struct rtl8169_private *tp) 879 { 880 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 881 tp->mac_version != RTL_GIGA_MAC_VER_37 && 882 tp->mac_version != RTL_GIGA_MAC_VER_39; 883 } 884 885 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 886 { 887 int i; 888 889 for (i = 0; i < ETH_ALEN; i++) 890 mac[i] = RTL_R8(tp, reg + i); 891 } 892 893 struct rtl_cond { 894 bool (*check)(struct rtl8169_private *); 895 const char *msg; 896 }; 897 898 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 899 unsigned long usecs, int n, bool high) 900 { 901 int i; 902 903 for (i = 0; i < n; i++) { 904 if (c->check(tp) == high) 905 return true; 906 fsleep(usecs); 907 } 908 909 if (net_ratelimit()) 910 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 911 c->msg, !high, n, usecs); 912 return false; 913 } 914 915 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 916 const struct rtl_cond *c, 917 unsigned long d, int n) 918 { 919 return rtl_loop_wait(tp, c, d, n, true); 920 } 921 922 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 923 const struct rtl_cond *c, 924 unsigned long d, int n) 925 { 926 return rtl_loop_wait(tp, c, d, n, false); 927 } 928 929 #define DECLARE_RTL_COND(name) \ 930 static bool name ## _check(struct rtl8169_private *); \ 931 \ 932 static const struct rtl_cond name = { \ 933 .check = name ## _check, \ 934 .msg = #name \ 935 }; \ 936 \ 937 static bool name ## _check(struct rtl8169_private *tp) 938 939 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 940 { 941 struct device *dev = tp_to_dev(tp); 942 int ret; 943 944 ret = pm_runtime_resume_and_get(dev); 945 if (ret < 0) 946 return ret; 947 948 mutex_lock(&tp->led_lock); 949 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 950 mutex_unlock(&tp->led_lock); 951 952 pm_runtime_put_sync(dev); 953 954 return 0; 955 } 956 957 int rtl8168_get_led_mode(struct rtl8169_private *tp) 958 { 959 struct device *dev = tp_to_dev(tp); 960 int ret; 961 962 ret = pm_runtime_resume_and_get(dev); 963 if (ret < 0) 964 return ret; 965 966 ret = RTL_R16(tp, LED_CTRL); 967 968 pm_runtime_put_sync(dev); 969 970 return ret; 971 } 972 973 static int rtl8125_get_led_reg(int index) 974 { 975 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 976 977 return led_regs[index]; 978 } 979 980 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 981 { 982 int reg = rtl8125_get_led_reg(index); 983 struct device *dev = tp_to_dev(tp); 984 int ret; 985 u16 val; 986 987 ret = pm_runtime_resume_and_get(dev); 988 if (ret < 0) 989 return ret; 990 991 mutex_lock(&tp->led_lock); 992 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 993 RTL_W16(tp, reg, val | mode); 994 mutex_unlock(&tp->led_lock); 995 996 pm_runtime_put_sync(dev); 997 998 return 0; 999 } 1000 1001 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 1002 { 1003 int reg = rtl8125_get_led_reg(index); 1004 struct device *dev = tp_to_dev(tp); 1005 int ret; 1006 1007 ret = pm_runtime_resume_and_get(dev); 1008 if (ret < 0) 1009 return ret; 1010 1011 ret = RTL_R16(tp, reg); 1012 1013 pm_runtime_put_sync(dev); 1014 1015 return ret; 1016 } 1017 1018 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 1019 char *buf, int buf_len) 1020 { 1021 struct pci_dev *pdev = tp->pci_dev; 1022 char pdom[8], pfun[8]; 1023 int domain; 1024 1025 domain = pci_domain_nr(pdev->bus); 1026 if (domain) 1027 snprintf(pdom, sizeof(pdom), "P%d", domain); 1028 else 1029 pdom[0] = '\0'; 1030 1031 if (pdev->multifunction) 1032 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 1033 else 1034 pfun[0] = '\0'; 1035 1036 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 1037 PCI_SLOT(pdev->devfn), pfun, idx); 1038 } 1039 1040 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1041 { 1042 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1043 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52) 1044 *cmd |= 0xf70 << 18; 1045 } 1046 1047 DECLARE_RTL_COND(rtl_eriar_cond) 1048 { 1049 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1050 } 1051 1052 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1053 u32 val, int type) 1054 { 1055 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1056 1057 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 1058 return; 1059 1060 RTL_W32(tp, ERIDR, val); 1061 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1062 RTL_W32(tp, ERIAR, cmd); 1063 1064 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1065 } 1066 1067 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1068 u32 val) 1069 { 1070 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1071 } 1072 1073 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1074 { 1075 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1076 1077 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1078 RTL_W32(tp, ERIAR, cmd); 1079 1080 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1081 RTL_R32(tp, ERIDR) : ~0; 1082 } 1083 1084 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1085 { 1086 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1087 } 1088 1089 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1090 { 1091 u32 val = rtl_eri_read(tp, addr); 1092 1093 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1094 } 1095 1096 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1097 { 1098 rtl_w0w1_eri(tp, addr, p, 0); 1099 } 1100 1101 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1102 { 1103 rtl_w0w1_eri(tp, addr, 0, m); 1104 } 1105 1106 static bool rtl_ocp_reg_failure(u32 reg) 1107 { 1108 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1109 } 1110 1111 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1112 { 1113 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1114 } 1115 1116 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1117 { 1118 if (rtl_ocp_reg_failure(reg)) 1119 return; 1120 1121 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1122 1123 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1124 } 1125 1126 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1127 { 1128 if (rtl_ocp_reg_failure(reg)) 1129 return 0; 1130 1131 /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ 1132 if (tp->sfp_mode && reg == (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) 1133 return PHY_ID_RTL_DUMMY_SFP & 0xffff; 1134 1135 RTL_W32(tp, GPHY_OCP, reg << 15); 1136 1137 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1138 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1139 } 1140 1141 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1142 { 1143 if (rtl_ocp_reg_failure(reg)) 1144 return; 1145 1146 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1147 } 1148 1149 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1150 { 1151 unsigned long flags; 1152 1153 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1154 __r8168_mac_ocp_write(tp, reg, data); 1155 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1156 } 1157 1158 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1159 { 1160 if (rtl_ocp_reg_failure(reg)) 1161 return 0; 1162 1163 RTL_W32(tp, OCPDR, reg << 15); 1164 1165 return RTL_R32(tp, OCPDR); 1166 } 1167 1168 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1169 { 1170 unsigned long flags; 1171 u16 val; 1172 1173 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1174 val = __r8168_mac_ocp_read(tp, reg); 1175 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1176 1177 return val; 1178 } 1179 1180 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1181 u16 set) 1182 { 1183 unsigned long flags; 1184 u16 data; 1185 1186 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1187 data = __r8168_mac_ocp_read(tp, reg); 1188 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1189 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1190 } 1191 1192 static void r8127_sfp_sds_phy_reset(struct rtl8169_private *tp) 1193 { 1194 RTL_W8(tp, 0x2350, RTL_R8(tp, 0x2350) & ~BIT(0)); 1195 udelay(1); 1196 1197 RTL_W16(tp, 0x233a, 0x801f); 1198 RTL_W8(tp, 0x2350, RTL_R8(tp, 0x2350) | BIT(0)); 1199 usleep_range(10, 20); 1200 } 1201 1202 static void r8127_sfp_init_10g(struct rtl8169_private *tp) 1203 { 1204 int val; 1205 1206 r8127_sfp_sds_phy_reset(tp); 1207 1208 RTL_W16(tp, 0x233a, 0x801a); 1209 RTL_W16(tp, 0x233e, (RTL_R16(tp, 0x233e) & ~0x3003) | 0x1000); 1210 1211 r8168_phy_ocp_write(tp, 0xc40a, 0x0000); 1212 r8168_phy_ocp_write(tp, 0xc466, 0x0003); 1213 r8168_phy_ocp_write(tp, 0xc808, 0x0000); 1214 r8168_phy_ocp_write(tp, 0xc80a, 0x0000); 1215 1216 val = r8168_phy_ocp_read(tp, 0xc804); 1217 r8168_phy_ocp_write(tp, 0xc804, (val & ~0x000f) | 0x000c); 1218 } 1219 1220 static void rtl_sfp_init(struct rtl8169_private *tp) 1221 { 1222 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 1223 r8127_sfp_init_10g(tp); 1224 } 1225 1226 static void rtl_sfp_reset(struct rtl8169_private *tp) 1227 { 1228 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 1229 r8127_sfp_sds_phy_reset(tp); 1230 } 1231 1232 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1233 * PHY MCU interrupts before PHY power-down. 1234 */ 1235 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1236 { 1237 switch (tp->mac_version) { 1238 case RTL_GIGA_MAC_VER_40: 1239 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1240 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1241 else 1242 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1243 break; 1244 default: 1245 break; 1246 } 1247 }; 1248 1249 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1250 { 1251 if (reg == 0x1f) { 1252 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1253 return; 1254 } 1255 1256 if (tp->ocp_base != OCP_STD_PHY_BASE) 1257 reg -= 0x10; 1258 1259 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1260 rtl8168g_phy_suspend_quirk(tp, value); 1261 1262 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1263 } 1264 1265 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1266 { 1267 if (reg == 0x1f) 1268 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1269 1270 if (tp->ocp_base != OCP_STD_PHY_BASE) 1271 reg -= 0x10; 1272 1273 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1274 } 1275 1276 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1277 { 1278 if (reg == 0x1f) { 1279 tp->ocp_base = value << 4; 1280 return; 1281 } 1282 1283 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1284 } 1285 1286 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1287 { 1288 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1289 } 1290 1291 DECLARE_RTL_COND(rtl_phyar_cond) 1292 { 1293 return RTL_R32(tp, PHYAR) & 0x80000000; 1294 } 1295 1296 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1297 { 1298 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1299 1300 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1301 /* 1302 * According to hardware specs a 20us delay is required after write 1303 * complete indication, but before sending next command. 1304 */ 1305 udelay(20); 1306 } 1307 1308 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1309 { 1310 int value; 1311 1312 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1313 1314 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1315 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1316 1317 /* 1318 * According to hardware specs a 20us delay is required after read 1319 * complete indication, but before sending next command. 1320 */ 1321 udelay(20); 1322 1323 return value; 1324 } 1325 1326 DECLARE_RTL_COND(rtl_ocpar_cond) 1327 { 1328 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1329 } 1330 1331 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1332 1333 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1334 { 1335 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1336 } 1337 1338 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1339 { 1340 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1341 } 1342 1343 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1344 { 1345 r8168dp_2_mdio_start(tp); 1346 1347 r8169_mdio_write(tp, reg, value); 1348 1349 r8168dp_2_mdio_stop(tp); 1350 } 1351 1352 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1353 { 1354 int value; 1355 1356 /* Work around issue with chip reporting wrong PHY ID */ 1357 if (reg == MII_PHYSID2) 1358 return 0xc912; 1359 1360 r8168dp_2_mdio_start(tp); 1361 1362 value = r8169_mdio_read(tp, reg); 1363 1364 r8168dp_2_mdio_stop(tp); 1365 1366 return value; 1367 } 1368 1369 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1370 { 1371 switch (tp->mac_version) { 1372 case RTL_GIGA_MAC_VER_28: 1373 case RTL_GIGA_MAC_VER_31: 1374 r8168dp_2_mdio_write(tp, location, val); 1375 break; 1376 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1377 r8168g_mdio_write(tp, location, val); 1378 break; 1379 default: 1380 r8169_mdio_write(tp, location, val); 1381 break; 1382 } 1383 } 1384 1385 static int rtl_readphy(struct rtl8169_private *tp, int location) 1386 { 1387 switch (tp->mac_version) { 1388 case RTL_GIGA_MAC_VER_28: 1389 case RTL_GIGA_MAC_VER_31: 1390 return r8168dp_2_mdio_read(tp, location); 1391 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1392 return r8168g_mdio_read(tp, location); 1393 default: 1394 return r8169_mdio_read(tp, location); 1395 } 1396 } 1397 1398 DECLARE_RTL_COND(rtl_ephyar_cond) 1399 { 1400 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1401 } 1402 1403 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1404 { 1405 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1406 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1407 1408 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1409 1410 udelay(10); 1411 } 1412 1413 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1414 { 1415 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1416 1417 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1418 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1419 } 1420 1421 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1422 { 1423 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1424 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1425 RTL_R32(tp, OCPDR) : ~0; 1426 } 1427 1428 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1429 { 1430 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1431 } 1432 1433 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1434 u32 data) 1435 { 1436 RTL_W32(tp, OCPDR, data); 1437 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1438 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1439 } 1440 1441 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1442 u32 data) 1443 { 1444 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1445 data, ERIAR_OOB); 1446 } 1447 1448 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1449 { 1450 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1451 1452 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1453 } 1454 1455 #define OOB_CMD_RESET 0x00 1456 #define OOB_CMD_DRIVER_START 0x05 1457 #define OOB_CMD_DRIVER_STOP 0x06 1458 1459 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1460 { 1461 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1462 } 1463 1464 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1465 { 1466 u16 reg; 1467 1468 reg = rtl8168_get_ocp_reg(tp); 1469 1470 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1471 } 1472 1473 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1474 { 1475 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1476 } 1477 1478 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1479 { 1480 return RTL_R8(tp, IBISR0) & 0x20; 1481 } 1482 1483 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1484 { 1485 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1486 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1487 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1488 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1489 } 1490 1491 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1492 { 1493 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1494 if (tp->dash_enabled) 1495 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1496 } 1497 1498 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1499 { 1500 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1501 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1502 if (tp->dash_enabled) 1503 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1504 } 1505 1506 static void rtl8125bp_driver_start(struct rtl8169_private *tp) 1507 { 1508 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); 1509 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1510 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1511 } 1512 1513 static void rtl8168_driver_start(struct rtl8169_private *tp) 1514 { 1515 if (tp->dash_type == RTL_DASH_DP) 1516 rtl8168dp_driver_start(tp); 1517 else if (tp->dash_type == RTL_DASH_25_BP) 1518 rtl8125bp_driver_start(tp); 1519 else 1520 rtl8168ep_driver_start(tp); 1521 } 1522 1523 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1524 { 1525 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1526 if (tp->dash_enabled) 1527 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1528 } 1529 1530 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1531 { 1532 rtl8168ep_stop_cmac(tp); 1533 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1534 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1535 if (tp->dash_enabled) 1536 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1537 } 1538 1539 static void rtl8125bp_driver_stop(struct rtl8169_private *tp) 1540 { 1541 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); 1542 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1543 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1544 } 1545 1546 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1547 { 1548 if (tp->dash_type == RTL_DASH_DP) 1549 rtl8168dp_driver_stop(tp); 1550 else if (tp->dash_type == RTL_DASH_25_BP) 1551 rtl8125bp_driver_stop(tp); 1552 else 1553 rtl8168ep_driver_stop(tp); 1554 } 1555 1556 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1557 { 1558 u16 reg = rtl8168_get_ocp_reg(tp); 1559 1560 return r8168dp_ocp_read(tp, reg) & BIT(15); 1561 } 1562 1563 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1564 { 1565 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1566 } 1567 1568 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1569 { 1570 switch (tp->dash_type) { 1571 case RTL_DASH_DP: 1572 return r8168dp_check_dash(tp); 1573 case RTL_DASH_EP: 1574 case RTL_DASH_25_BP: 1575 return r8168ep_check_dash(tp); 1576 default: 1577 return false; 1578 } 1579 } 1580 1581 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1582 { 1583 switch (tp->mac_version) { 1584 case RTL_GIGA_MAC_VER_28: 1585 case RTL_GIGA_MAC_VER_31: 1586 return RTL_DASH_DP; 1587 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 1588 return RTL_DASH_EP; 1589 case RTL_GIGA_MAC_VER_66: 1590 return RTL_DASH_25_BP; 1591 case RTL_GIGA_MAC_VER_80: 1592 return (tp->pci_dev->revision == 0x04) 1593 ? RTL_DASH_25_BP 1594 : RTL_DASH_NONE; 1595 default: 1596 return RTL_DASH_NONE; 1597 } 1598 } 1599 1600 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1601 { 1602 switch (tp->mac_version) { 1603 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_24: 1604 case RTL_GIGA_MAC_VER_28: 1605 case RTL_GIGA_MAC_VER_31: 1606 case RTL_GIGA_MAC_VER_38: 1607 break; 1608 case RTL_GIGA_MAC_VER_80: 1609 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, true); 1610 break; 1611 default: 1612 r8169_mod_reg8_cond(tp, PMCH, D3HOT_NO_PLL_DOWN, true); 1613 r8169_mod_reg8_cond(tp, PMCH, D3COLD_NO_PLL_DOWN, !enable); 1614 break; 1615 } 1616 } 1617 1618 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1619 { 1620 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1621 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1622 } 1623 1624 DECLARE_RTL_COND(rtl_efusear_cond) 1625 { 1626 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1627 } 1628 1629 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1630 { 1631 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1632 1633 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1634 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1635 } 1636 1637 static u32 rtl_get_events(struct rtl8169_private *tp) 1638 { 1639 if (rtl_is_8125(tp)) 1640 return RTL_R32(tp, IntrStatus_8125); 1641 else 1642 return RTL_R16(tp, IntrStatus); 1643 } 1644 1645 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1646 { 1647 if (rtl_is_8125(tp)) 1648 RTL_W32(tp, IntrStatus_8125, bits); 1649 else 1650 RTL_W16(tp, IntrStatus, bits); 1651 } 1652 1653 static void rtl_irq_disable(struct rtl8169_private *tp) 1654 { 1655 if (rtl_is_8125(tp)) 1656 RTL_W32(tp, IntrMask_8125, 0); 1657 else 1658 RTL_W16(tp, IntrMask, 0); 1659 } 1660 1661 static void rtl_irq_enable(struct rtl8169_private *tp) 1662 { 1663 if (rtl_is_8125(tp)) 1664 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1665 else 1666 RTL_W16(tp, IntrMask, tp->irq_mask); 1667 } 1668 1669 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1670 { 1671 rtl_irq_disable(tp); 1672 rtl_ack_events(tp, 0xffffffff); 1673 rtl_pci_commit(tp); 1674 } 1675 1676 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1677 { 1678 struct phy_device *phydev = tp->phydev; 1679 1680 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1681 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1682 if (phydev->speed == SPEED_1000) { 1683 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1684 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1685 } else if (phydev->speed == SPEED_100) { 1686 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1687 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1688 } else { 1689 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1690 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1691 } 1692 rtl_reset_packet_filter(tp); 1693 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1694 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1695 if (phydev->speed == SPEED_1000) { 1696 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1697 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1698 } else { 1699 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1700 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1701 } 1702 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1703 if (phydev->speed == SPEED_10) { 1704 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1705 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1706 } else { 1707 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1708 } 1709 } 1710 } 1711 1712 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1713 1714 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1715 { 1716 struct rtl8169_private *tp = netdev_priv(dev); 1717 1718 wol->supported = WAKE_ANY; 1719 wol->wolopts = tp->saved_wolopts; 1720 } 1721 1722 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1723 { 1724 rtl_unlock_config_regs(tp); 1725 1726 if (rtl_is_8168evl_up(tp)) { 1727 if (wolopts & WAKE_MAGIC) 1728 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1729 else 1730 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1731 } else if (rtl_is_8125(tp)) { 1732 if (wolopts & WAKE_MAGIC) 1733 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1734 else 1735 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1736 } else { 1737 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1738 wolopts & WAKE_MAGIC); 1739 } 1740 1741 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1742 if (rtl_is_8125(tp)) 1743 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1744 wolopts & WAKE_PHY ? 0x13 : 0); 1745 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1746 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1747 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1748 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1749 1750 switch (tp->mac_version) { 1751 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1752 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1753 break; 1754 case RTL_GIGA_MAC_VER_34: 1755 case RTL_GIGA_MAC_VER_37: 1756 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: 1757 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1758 break; 1759 default: 1760 break; 1761 } 1762 1763 rtl_lock_config_regs(tp); 1764 1765 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1766 1767 if (!tp->dash_enabled) { 1768 rtl_set_d3_pll_down(tp, !wolopts); 1769 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1770 } 1771 } 1772 1773 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1774 { 1775 struct rtl8169_private *tp = netdev_priv(dev); 1776 1777 if (wol->wolopts & ~WAKE_ANY) 1778 return -EINVAL; 1779 1780 tp->saved_wolopts = wol->wolopts; 1781 __rtl8169_set_wol(tp, tp->saved_wolopts); 1782 1783 return 0; 1784 } 1785 1786 static void rtl8169_get_drvinfo(struct net_device *dev, 1787 struct ethtool_drvinfo *info) 1788 { 1789 struct rtl8169_private *tp = netdev_priv(dev); 1790 struct rtl_fw *rtl_fw = tp->rtl_fw; 1791 1792 strscpy(info->driver, KBUILD_MODNAME); 1793 strscpy(info->bus_info, pci_name(tp->pci_dev)); 1794 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1795 if (rtl_fw) 1796 strscpy(info->fw_version, rtl_fw->version); 1797 } 1798 1799 static int rtl8169_get_regs_len(struct net_device *dev) 1800 { 1801 return R8169_REGS_SIZE; 1802 } 1803 1804 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1805 netdev_features_t features) 1806 { 1807 struct rtl8169_private *tp = netdev_priv(dev); 1808 1809 if (dev->mtu > TD_MSS_MAX) 1810 features &= ~NETIF_F_ALL_TSO; 1811 1812 if (dev->mtu > ETH_DATA_LEN && 1813 tp->mac_version > RTL_GIGA_MAC_VER_06) 1814 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1815 1816 return features; 1817 } 1818 1819 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1820 netdev_features_t features) 1821 { 1822 u32 rx_config = RTL_R32(tp, RxConfig); 1823 1824 if (features & NETIF_F_RXALL) 1825 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1826 else 1827 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1828 1829 if (rtl_is_8125(tp)) { 1830 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1831 rx_config |= RX_VLAN_8125; 1832 else 1833 rx_config &= ~RX_VLAN_8125; 1834 } 1835 1836 RTL_W32(tp, RxConfig, rx_config); 1837 } 1838 1839 static int rtl8169_set_features(struct net_device *dev, 1840 netdev_features_t features) 1841 { 1842 struct rtl8169_private *tp = netdev_priv(dev); 1843 1844 rtl_set_rx_config_features(tp, features); 1845 1846 if (features & NETIF_F_RXCSUM) 1847 tp->cp_cmd |= RxChkSum; 1848 else 1849 tp->cp_cmd &= ~RxChkSum; 1850 1851 if (!rtl_is_8125(tp)) { 1852 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1853 tp->cp_cmd |= RxVlan; 1854 else 1855 tp->cp_cmd &= ~RxVlan; 1856 } 1857 1858 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1859 rtl_pci_commit(tp); 1860 1861 return 0; 1862 } 1863 1864 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1865 { 1866 return (skb_vlan_tag_present(skb)) ? 1867 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1868 } 1869 1870 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1871 { 1872 u32 opts2 = le32_to_cpu(desc->opts2); 1873 1874 if (opts2 & RxVlanTag) 1875 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1876 } 1877 1878 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1879 void *p) 1880 { 1881 struct rtl8169_private *tp = netdev_priv(dev); 1882 u32 __iomem *data = tp->mmio_addr; 1883 u32 *dw = p; 1884 int i; 1885 1886 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1887 memcpy_fromio(dw++, data++, 4); 1888 } 1889 1890 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1891 "tx_packets", 1892 "rx_packets", 1893 "tx_errors", 1894 "rx_errors", 1895 "rx_missed", 1896 "align_errors", 1897 "tx_single_collisions", 1898 "tx_multi_collisions", 1899 "unicast", 1900 "broadcast", 1901 "multicast", 1902 "tx_aborted", 1903 "tx_underrun", 1904 }; 1905 1906 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1907 { 1908 switch (sset) { 1909 case ETH_SS_STATS: 1910 return ARRAY_SIZE(rtl8169_gstrings); 1911 default: 1912 return -EOPNOTSUPP; 1913 } 1914 } 1915 1916 DECLARE_RTL_COND(rtl_counters_cond) 1917 { 1918 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1919 } 1920 1921 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1922 { 1923 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1924 1925 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1926 rtl_pci_commit(tp); 1927 RTL_W32(tp, CounterAddrLow, cmd); 1928 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1929 1930 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1931 } 1932 1933 static void rtl8169_update_counters(struct rtl8169_private *tp) 1934 { 1935 u8 val = RTL_R8(tp, ChipCmd); 1936 1937 /* 1938 * Some chips are unable to dump tally counters when the receiver 1939 * is disabled. If 0xff chip may be in a PCI power-save state. 1940 */ 1941 if (val & CmdRxEnb && val != 0xff) 1942 rtl8169_do_counters(tp, CounterDump); 1943 } 1944 1945 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1946 { 1947 struct rtl8169_counters *counters = tp->counters; 1948 1949 /* 1950 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1951 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1952 * reset by a power cycle, while the counter values collected by the 1953 * driver are reset at every driver unload/load cycle. 1954 * 1955 * To make sure the HW values returned by @get_stats64 match the SW 1956 * values, we collect the initial values at first open(*) and use them 1957 * as offsets to normalize the values returned by @get_stats64. 1958 * 1959 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1960 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1961 * set at open time by rtl_hw_start. 1962 */ 1963 1964 if (tp->tc_offset.inited) 1965 return; 1966 1967 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1968 rtl8169_do_counters(tp, CounterReset); 1969 } else { 1970 rtl8169_update_counters(tp); 1971 tp->tc_offset.tx_errors = counters->tx_errors; 1972 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1973 tp->tc_offset.tx_aborted = counters->tx_aborted; 1974 tp->tc_offset.rx_missed = counters->rx_missed; 1975 } 1976 1977 tp->tc_offset.inited = true; 1978 } 1979 1980 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1981 struct ethtool_stats *stats, u64 *data) 1982 { 1983 struct rtl8169_private *tp = netdev_priv(dev); 1984 struct rtl8169_counters *counters; 1985 1986 counters = tp->counters; 1987 rtl8169_update_counters(tp); 1988 1989 data[0] = le64_to_cpu(counters->tx_packets); 1990 data[1] = le64_to_cpu(counters->rx_packets); 1991 data[2] = le64_to_cpu(counters->tx_errors); 1992 data[3] = le32_to_cpu(counters->rx_errors); 1993 data[4] = le16_to_cpu(counters->rx_missed); 1994 data[5] = le16_to_cpu(counters->align_errors); 1995 data[6] = le32_to_cpu(counters->tx_one_collision); 1996 data[7] = le32_to_cpu(counters->tx_multi_collision); 1997 data[8] = le64_to_cpu(counters->rx_unicast); 1998 data[9] = le64_to_cpu(counters->rx_broadcast); 1999 data[10] = le32_to_cpu(counters->rx_multicast); 2000 data[11] = le16_to_cpu(counters->tx_aborted); 2001 data[12] = le16_to_cpu(counters->tx_underrun); 2002 } 2003 2004 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2005 { 2006 switch(stringset) { 2007 case ETH_SS_STATS: 2008 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 2009 break; 2010 } 2011 } 2012 2013 /* 2014 * Interrupt coalescing 2015 * 2016 * > 1 - the availability of the IntrMitigate (0xe2) register through the 2017 * > 8169, 8168 and 810x line of chipsets 2018 * 2019 * 8169, 8168, and 8136(810x) serial chipsets support it. 2020 * 2021 * > 2 - the Tx timer unit at gigabit speed 2022 * 2023 * The unit of the timer depends on both the speed and the setting of CPlusCmd 2024 * (0xe0) bit 1 and bit 0. 2025 * 2026 * For 8169 2027 * bit[1:0] \ speed 1000M 100M 10M 2028 * 0 0 320ns 2.56us 40.96us 2029 * 0 1 2.56us 20.48us 327.7us 2030 * 1 0 5.12us 40.96us 655.4us 2031 * 1 1 10.24us 81.92us 1.31ms 2032 * 2033 * For the other 2034 * bit[1:0] \ speed 1000M 100M 10M 2035 * 0 0 5us 2.56us 40.96us 2036 * 0 1 40us 20.48us 327.7us 2037 * 1 0 80us 40.96us 655.4us 2038 * 1 1 160us 81.92us 1.31ms 2039 */ 2040 2041 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 2042 struct rtl_coalesce_info { 2043 u32 speed; 2044 u32 scale_nsecs[4]; 2045 }; 2046 2047 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 2048 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 2049 2050 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 2051 { SPEED_1000, COALESCE_DELAY(320) }, 2052 { SPEED_100, COALESCE_DELAY(2560) }, 2053 { SPEED_10, COALESCE_DELAY(40960) }, 2054 { 0 }, 2055 }; 2056 2057 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 2058 { SPEED_1000, COALESCE_DELAY(5000) }, 2059 { SPEED_100, COALESCE_DELAY(2560) }, 2060 { SPEED_10, COALESCE_DELAY(40960) }, 2061 { 0 }, 2062 }; 2063 #undef COALESCE_DELAY 2064 2065 /* get rx/tx scale vector corresponding to current speed */ 2066 static const struct rtl_coalesce_info * 2067 rtl_coalesce_info(struct rtl8169_private *tp) 2068 { 2069 const struct rtl_coalesce_info *ci; 2070 2071 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 2072 ci = rtl_coalesce_info_8169; 2073 else 2074 ci = rtl_coalesce_info_8168_8136; 2075 2076 /* if speed is unknown assume highest one */ 2077 if (tp->phydev->speed == SPEED_UNKNOWN) 2078 return ci; 2079 2080 for (; ci->speed; ci++) { 2081 if (tp->phydev->speed == ci->speed) 2082 return ci; 2083 } 2084 2085 return ERR_PTR(-ELNRNG); 2086 } 2087 2088 static int rtl_get_coalesce(struct net_device *dev, 2089 struct ethtool_coalesce *ec, 2090 struct kernel_ethtool_coalesce *kernel_coal, 2091 struct netlink_ext_ack *extack) 2092 { 2093 struct rtl8169_private *tp = netdev_priv(dev); 2094 const struct rtl_coalesce_info *ci; 2095 u32 scale, c_us, c_fr; 2096 u16 intrmit; 2097 2098 if (rtl_is_8125(tp)) 2099 return -EOPNOTSUPP; 2100 2101 memset(ec, 0, sizeof(*ec)); 2102 2103 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 2104 ci = rtl_coalesce_info(tp); 2105 if (IS_ERR(ci)) 2106 return PTR_ERR(ci); 2107 2108 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 2109 2110 intrmit = RTL_R16(tp, IntrMitigate); 2111 2112 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 2113 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2114 2115 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 2116 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 2117 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2118 2119 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 2120 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2121 2122 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 2123 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2124 2125 return 0; 2126 } 2127 2128 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 2129 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 2130 u16 *cp01) 2131 { 2132 const struct rtl_coalesce_info *ci; 2133 u16 i; 2134 2135 ci = rtl_coalesce_info(tp); 2136 if (IS_ERR(ci)) 2137 return PTR_ERR(ci); 2138 2139 for (i = 0; i < 4; i++) { 2140 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 2141 *cp01 = i; 2142 return ci->scale_nsecs[i]; 2143 } 2144 } 2145 2146 return -ERANGE; 2147 } 2148 2149 static int rtl_set_coalesce(struct net_device *dev, 2150 struct ethtool_coalesce *ec, 2151 struct kernel_ethtool_coalesce *kernel_coal, 2152 struct netlink_ext_ack *extack) 2153 { 2154 struct rtl8169_private *tp = netdev_priv(dev); 2155 u32 tx_fr = ec->tx_max_coalesced_frames; 2156 u32 rx_fr = ec->rx_max_coalesced_frames; 2157 u32 coal_usec_max, units; 2158 u16 w = 0, cp01 = 0; 2159 int scale; 2160 2161 if (rtl_is_8125(tp)) 2162 return -EOPNOTSUPP; 2163 2164 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2165 return -ERANGE; 2166 2167 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2168 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2169 if (scale < 0) 2170 return scale; 2171 2172 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2173 * not only when usecs=0 because of e.g. the following scenario: 2174 * 2175 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2176 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2177 * - then user does `ethtool -C eth0 rx-usecs 100` 2178 * 2179 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2180 * if we want to ignore rx_frames then it has to be set to 0. 2181 */ 2182 if (rx_fr == 1) 2183 rx_fr = 0; 2184 if (tx_fr == 1) 2185 tx_fr = 0; 2186 2187 /* HW requires time limit to be set if frame limit is set */ 2188 if ((tx_fr && !ec->tx_coalesce_usecs) || 2189 (rx_fr && !ec->rx_coalesce_usecs)) 2190 return -EINVAL; 2191 2192 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2193 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2194 2195 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2196 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2197 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2198 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2199 2200 RTL_W16(tp, IntrMitigate, w); 2201 2202 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2203 if (rtl_is_8168evl_up(tp)) { 2204 if (!rx_fr && !tx_fr) 2205 /* disable packet counter */ 2206 tp->cp_cmd |= PktCntrDisable; 2207 else 2208 tp->cp_cmd &= ~PktCntrDisable; 2209 } 2210 2211 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2212 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2213 rtl_pci_commit(tp); 2214 2215 return 0; 2216 } 2217 2218 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2219 { 2220 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2221 2222 switch (tp->mac_version) { 2223 case RTL_GIGA_MAC_VER_46: 2224 case RTL_GIGA_MAC_VER_48: 2225 tp->tx_lpi_timer = timer_val; 2226 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2227 break; 2228 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2229 tp->tx_lpi_timer = timer_val; 2230 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2231 break; 2232 default: 2233 break; 2234 } 2235 } 2236 2237 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2238 { 2239 unsigned int speed = tp->phydev->speed; 2240 unsigned int timer = tp->tx_lpi_timer; 2241 2242 if (!timer || speed == SPEED_UNKNOWN) 2243 return 0; 2244 2245 /* tx_lpi_timer value is in bytes */ 2246 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2247 } 2248 2249 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2250 { 2251 struct rtl8169_private *tp = netdev_priv(dev); 2252 int ret; 2253 2254 if (!rtl_supports_eee(tp)) 2255 return -EOPNOTSUPP; 2256 2257 ret = phy_ethtool_get_eee(tp->phydev, data); 2258 if (ret) 2259 return ret; 2260 2261 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2262 2263 return 0; 2264 } 2265 2266 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2267 { 2268 struct rtl8169_private *tp = netdev_priv(dev); 2269 2270 if (!rtl_supports_eee(tp)) 2271 return -EOPNOTSUPP; 2272 2273 return phy_ethtool_set_eee(tp->phydev, data); 2274 } 2275 2276 static void rtl8169_get_ringparam(struct net_device *dev, 2277 struct ethtool_ringparam *data, 2278 struct kernel_ethtool_ringparam *kernel_data, 2279 struct netlink_ext_ack *extack) 2280 { 2281 data->rx_max_pending = NUM_RX_DESC; 2282 data->rx_pending = NUM_RX_DESC; 2283 data->tx_max_pending = NUM_TX_DESC; 2284 data->tx_pending = NUM_TX_DESC; 2285 } 2286 2287 static void rtl8169_get_pause_stats(struct net_device *dev, 2288 struct ethtool_pause_stats *pause_stats) 2289 { 2290 struct rtl8169_private *tp = netdev_priv(dev); 2291 2292 if (!rtl_is_8125(tp)) 2293 return; 2294 2295 rtl8169_update_counters(tp); 2296 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2297 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2298 } 2299 2300 static void rtl8169_get_pauseparam(struct net_device *dev, 2301 struct ethtool_pauseparam *data) 2302 { 2303 struct rtl8169_private *tp = netdev_priv(dev); 2304 bool tx_pause, rx_pause; 2305 2306 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2307 2308 data->autoneg = tp->phydev->autoneg; 2309 data->tx_pause = tx_pause ? 1 : 0; 2310 data->rx_pause = rx_pause ? 1 : 0; 2311 } 2312 2313 static int rtl8169_set_pauseparam(struct net_device *dev, 2314 struct ethtool_pauseparam *data) 2315 { 2316 struct rtl8169_private *tp = netdev_priv(dev); 2317 2318 if (dev->mtu > ETH_DATA_LEN) 2319 return -EOPNOTSUPP; 2320 2321 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2322 2323 return 0; 2324 } 2325 2326 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2327 struct ethtool_eth_mac_stats *mac_stats) 2328 { 2329 struct rtl8169_private *tp = netdev_priv(dev); 2330 2331 rtl8169_update_counters(tp); 2332 2333 mac_stats->FramesTransmittedOK = 2334 le64_to_cpu(tp->counters->tx_packets); 2335 mac_stats->SingleCollisionFrames = 2336 le32_to_cpu(tp->counters->tx_one_collision); 2337 mac_stats->MultipleCollisionFrames = 2338 le32_to_cpu(tp->counters->tx_multi_collision); 2339 mac_stats->FramesReceivedOK = 2340 le64_to_cpu(tp->counters->rx_packets); 2341 mac_stats->AlignmentErrors = 2342 le16_to_cpu(tp->counters->align_errors); 2343 mac_stats->FramesLostDueToIntMACXmitError = 2344 le64_to_cpu(tp->counters->tx_errors); 2345 mac_stats->BroadcastFramesReceivedOK = 2346 le64_to_cpu(tp->counters->rx_broadcast); 2347 mac_stats->MulticastFramesReceivedOK = 2348 le32_to_cpu(tp->counters->rx_multicast); 2349 2350 if (!rtl_is_8125(tp)) 2351 return; 2352 2353 mac_stats->AlignmentErrors = 2354 le32_to_cpu(tp->counters->align_errors32); 2355 mac_stats->OctetsTransmittedOK = 2356 le64_to_cpu(tp->counters->tx_octets); 2357 mac_stats->LateCollisions = 2358 le32_to_cpu(tp->counters->tx_late_collision); 2359 mac_stats->FramesAbortedDueToXSColls = 2360 le32_to_cpu(tp->counters->tx_aborted32); 2361 mac_stats->OctetsReceivedOK = 2362 le64_to_cpu(tp->counters->rx_octets); 2363 mac_stats->FramesLostDueToIntMACRcvError = 2364 le32_to_cpu(tp->counters->rx_mac_error); 2365 mac_stats->MulticastFramesXmittedOK = 2366 le64_to_cpu(tp->counters->tx_multicast64); 2367 mac_stats->BroadcastFramesXmittedOK = 2368 le64_to_cpu(tp->counters->tx_broadcast64); 2369 mac_stats->MulticastFramesReceivedOK = 2370 le64_to_cpu(tp->counters->rx_multicast64); 2371 mac_stats->FrameTooLongErrors = 2372 le32_to_cpu(tp->counters->rx_frame_too_long); 2373 } 2374 2375 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2376 struct ethtool_eth_ctrl_stats *ctrl_stats) 2377 { 2378 struct rtl8169_private *tp = netdev_priv(dev); 2379 2380 if (!rtl_is_8125(tp)) 2381 return; 2382 2383 rtl8169_update_counters(tp); 2384 2385 ctrl_stats->UnsupportedOpcodesReceived = 2386 le32_to_cpu(tp->counters->rx_unknown_opcode); 2387 } 2388 2389 static int rtl8169_set_link_ksettings(struct net_device *ndev, 2390 const struct ethtool_link_ksettings *cmd) 2391 { 2392 struct rtl8169_private *tp = netdev_priv(ndev); 2393 struct phy_device *phydev = tp->phydev; 2394 int duplex = cmd->base.duplex; 2395 int speed = cmd->base.speed; 2396 2397 if (!tp->sfp_mode) 2398 return phy_ethtool_ksettings_set(phydev, cmd); 2399 2400 if (cmd->base.autoneg != AUTONEG_DISABLE) 2401 return -EINVAL; 2402 2403 if (!phy_check_valid(speed, duplex, phydev->supported)) 2404 return -EINVAL; 2405 2406 mutex_lock(&phydev->lock); 2407 2408 phydev->autoneg = AUTONEG_DISABLE; 2409 phydev->speed = speed; 2410 phydev->duplex = duplex; 2411 2412 rtl_sfp_init(tp); 2413 2414 mutex_unlock(&phydev->lock); 2415 2416 return 0; 2417 } 2418 2419 static const struct ethtool_ops rtl8169_ethtool_ops = { 2420 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2421 ETHTOOL_COALESCE_MAX_FRAMES, 2422 .get_drvinfo = rtl8169_get_drvinfo, 2423 .get_regs_len = rtl8169_get_regs_len, 2424 .get_link = ethtool_op_get_link, 2425 .get_coalesce = rtl_get_coalesce, 2426 .set_coalesce = rtl_set_coalesce, 2427 .get_regs = rtl8169_get_regs, 2428 .get_wol = rtl8169_get_wol, 2429 .set_wol = rtl8169_set_wol, 2430 .get_strings = rtl8169_get_strings, 2431 .get_sset_count = rtl8169_get_sset_count, 2432 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2433 .get_ts_info = ethtool_op_get_ts_info, 2434 .nway_reset = phy_ethtool_nway_reset, 2435 .get_eee = rtl8169_get_eee, 2436 .set_eee = rtl8169_set_eee, 2437 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2438 .set_link_ksettings = rtl8169_set_link_ksettings, 2439 .get_ringparam = rtl8169_get_ringparam, 2440 .get_pause_stats = rtl8169_get_pause_stats, 2441 .get_pauseparam = rtl8169_get_pauseparam, 2442 .set_pauseparam = rtl8169_set_pauseparam, 2443 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2444 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2445 }; 2446 2447 static const struct rtl_chip_info *rtl8169_get_chip_version(u32 xid, bool gmii) 2448 { 2449 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ 2450 static const struct rtl_chip_info rtl8106eus_info = { 2451 .mac_version = RTL_GIGA_MAC_VER_43, 2452 .name = "RTL8106eus", 2453 .fw_name = FIRMWARE_8106E_2, 2454 }; 2455 static const struct rtl_chip_info rtl8107e_info = { 2456 .mac_version = RTL_GIGA_MAC_VER_48, 2457 .name = "RTL8107e", 2458 .fw_name = FIRMWARE_8107E_2, 2459 }; 2460 const struct rtl_chip_info *p = rtl_chip_infos; 2461 2462 while ((xid & p->mask) != p->val) 2463 p++; 2464 2465 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii) 2466 return &rtl8106eus_info; 2467 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii) 2468 return &rtl8107e_info; 2469 2470 return p; 2471 } 2472 2473 static const struct rtl_chip_info *rtl8169_get_extended_chip_version(u32 xid2) 2474 { 2475 const struct rtl_chip_info *p = rtl_chip_infos_extended; 2476 2477 while ((xid2 & p->mask) != p->val) 2478 p++; 2479 return p; 2480 } 2481 2482 static void rtl_release_firmware(struct rtl8169_private *tp) 2483 { 2484 if (tp->rtl_fw) { 2485 rtl_fw_release_firmware(tp->rtl_fw); 2486 kfree(tp->rtl_fw); 2487 tp->rtl_fw = NULL; 2488 } 2489 } 2490 2491 void r8169_apply_firmware(struct rtl8169_private *tp) 2492 { 2493 int val; 2494 2495 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2496 if (tp->rtl_fw) { 2497 rtl_fw_write_firmware(tp, tp->rtl_fw); 2498 /* At least one firmware doesn't reset tp->ocp_base. */ 2499 tp->ocp_base = OCP_STD_PHY_BASE; 2500 2501 /* PHY soft reset may still be in progress */ 2502 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2503 !(val & BMCR_RESET), 2504 50000, 600000, true); 2505 } 2506 } 2507 2508 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2509 { 2510 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2511 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2512 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2513 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2514 } 2515 2516 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2517 { 2518 u16 data1, data2, ioffset; 2519 2520 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2521 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2522 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2523 2524 ioffset = (data2 >> 1) & 0x7ff8; 2525 ioffset |= data2 & 0x0007; 2526 if (data1 & BIT(7)) 2527 ioffset |= BIT(15); 2528 2529 return ioffset; 2530 } 2531 2532 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2533 { 2534 set_bit(flag, tp->wk.flags); 2535 if (!schedule_work(&tp->wk.work)) 2536 clear_bit(flag, tp->wk.flags); 2537 } 2538 2539 static void rtl8169_init_phy(struct rtl8169_private *tp) 2540 { 2541 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2542 2543 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2544 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2545 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2546 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2547 RTL_W8(tp, 0x82, 0x01); 2548 } 2549 2550 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2551 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2552 tp->pci_dev->subsystem_device == 0xe000) 2553 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2554 2555 if (tp->sfp_mode) 2556 rtl_sfp_init(tp); 2557 2558 /* We may have called phy_speed_down before */ 2559 phy_speed_up(tp->phydev); 2560 2561 genphy_soft_reset(tp->phydev); 2562 } 2563 2564 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2565 { 2566 rtl_unlock_config_regs(tp); 2567 2568 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2569 rtl_pci_commit(tp); 2570 2571 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2572 rtl_pci_commit(tp); 2573 2574 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2575 rtl_rar_exgmac_set(tp, addr); 2576 2577 rtl_lock_config_regs(tp); 2578 } 2579 2580 static int rtl_set_mac_address(struct net_device *dev, void *p) 2581 { 2582 struct rtl8169_private *tp = netdev_priv(dev); 2583 int ret; 2584 2585 ret = eth_mac_addr(dev, p); 2586 if (ret) 2587 return ret; 2588 2589 rtl_rar_set(tp, dev->dev_addr); 2590 2591 return 0; 2592 } 2593 2594 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2595 { 2596 switch (tp->mac_version) { 2597 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2598 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2599 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2600 break; 2601 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2602 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2603 case RTL_GIGA_MAC_VER_38: 2604 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2605 break; 2606 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2607 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2608 break; 2609 case RTL_GIGA_MAC_VER_61: 2610 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2611 break; 2612 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2613 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2614 RX_PAUSE_SLOT_ON); 2615 break; 2616 default: 2617 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2618 break; 2619 } 2620 } 2621 2622 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2623 { 2624 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2625 } 2626 2627 static void rtl_jumbo_config(struct rtl8169_private *tp) 2628 { 2629 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2630 int readrq = 4096; 2631 2632 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2633 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2634 readrq = 512; 2635 2636 rtl_unlock_config_regs(tp); 2637 switch (tp->mac_version) { 2638 case RTL_GIGA_MAC_VER_17: 2639 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2640 break; 2641 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2642 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2643 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2644 break; 2645 case RTL_GIGA_MAC_VER_28: 2646 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2647 break; 2648 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2649 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2650 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2651 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2652 break; 2653 default: 2654 break; 2655 } 2656 rtl_lock_config_regs(tp); 2657 2658 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2659 pcie_set_readrq(tp->pci_dev, readrq); 2660 2661 /* Chip doesn't support pause in jumbo mode */ 2662 if (jumbo) { 2663 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2664 tp->phydev->advertising); 2665 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2666 tp->phydev->advertising); 2667 phy_start_aneg(tp->phydev); 2668 } 2669 } 2670 2671 DECLARE_RTL_COND(rtl_chipcmd_cond) 2672 { 2673 return RTL_R8(tp, ChipCmd) & CmdReset; 2674 } 2675 2676 static void rtl_hw_reset(struct rtl8169_private *tp) 2677 { 2678 RTL_W8(tp, ChipCmd, CmdReset); 2679 2680 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2681 } 2682 2683 static void rtl_request_firmware(struct rtl8169_private *tp) 2684 { 2685 struct rtl_fw *rtl_fw; 2686 2687 /* firmware loaded already or no firmware available */ 2688 if (tp->rtl_fw || !tp->fw_name) 2689 return; 2690 2691 rtl_fw = kzalloc_obj(*rtl_fw); 2692 if (!rtl_fw) 2693 return; 2694 2695 rtl_fw->phy_write = rtl_writephy; 2696 rtl_fw->phy_read = rtl_readphy; 2697 rtl_fw->mac_mcu_write = mac_mcu_write; 2698 rtl_fw->mac_mcu_read = mac_mcu_read; 2699 rtl_fw->fw_name = tp->fw_name; 2700 rtl_fw->dev = tp_to_dev(tp); 2701 2702 if (rtl_fw_request_firmware(rtl_fw)) 2703 kfree(rtl_fw); 2704 else 2705 tp->rtl_fw = rtl_fw; 2706 } 2707 2708 static void rtl_rx_close(struct rtl8169_private *tp) 2709 { 2710 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2711 } 2712 2713 DECLARE_RTL_COND(rtl_npq_cond) 2714 { 2715 return RTL_R8(tp, TxPoll) & NPQ; 2716 } 2717 2718 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2719 { 2720 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2721 } 2722 2723 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2724 { 2725 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2726 } 2727 2728 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2729 { 2730 /* IntrMitigate has new functionality on RTL8125 */ 2731 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2732 } 2733 2734 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2735 { 2736 switch (tp->mac_version) { 2737 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2738 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2739 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2740 break; 2741 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2742 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2743 break; 2744 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2745 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2746 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2747 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2748 break; 2749 default: 2750 break; 2751 } 2752 } 2753 2754 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2755 { 2756 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2757 } 2758 2759 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2760 { 2761 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2762 fsleep(2000); 2763 rtl_wait_txrx_fifo_empty(tp); 2764 } 2765 2766 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2767 { 2768 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2769 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2770 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2771 2772 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2773 rtl_disable_rxdvgate(tp); 2774 } 2775 2776 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2777 { 2778 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2779 tp->mac_version == RTL_GIGA_MAC_VER_33) 2780 rtl_ephy_write(tp, 0x19, 0xff64); 2781 2782 if (device_may_wakeup(tp_to_dev(tp))) { 2783 phy_speed_down(tp->phydev, false); 2784 rtl_wol_enable_rx(tp); 2785 } 2786 } 2787 2788 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2789 { 2790 u32 val = TX_DMA_BURST << TxDMAShift | 2791 InterFrameGap << TxInterFrameGapShift; 2792 2793 if (rtl_is_8168evl_up(tp)) 2794 val |= TXCFG_AUTO_FIFO; 2795 2796 RTL_W32(tp, TxConfig, val); 2797 } 2798 2799 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2800 { 2801 /* Low hurts. Let's disable the filtering. */ 2802 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2803 } 2804 2805 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2806 { 2807 /* 2808 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2809 * register to be written before TxDescAddrLow to work. 2810 * Switching from MMIO to I/O access fixes the issue as well. 2811 */ 2812 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2813 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2814 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2815 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2816 } 2817 2818 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2819 { 2820 u32 val; 2821 2822 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2823 val = 0x000fff00; 2824 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2825 val = 0x00ffff00; 2826 else 2827 return; 2828 2829 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2830 val |= 0xff; 2831 2832 RTL_W32(tp, 0x7c, val); 2833 } 2834 2835 static void rtl_set_rx_mode(struct net_device *dev) 2836 { 2837 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2838 /* Multicast hash filter */ 2839 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2840 struct rtl8169_private *tp = netdev_priv(dev); 2841 u32 tmp; 2842 2843 if (dev->flags & IFF_PROMISC) { 2844 rx_mode |= AcceptAllPhys; 2845 } else if (!(dev->flags & IFF_MULTICAST)) { 2846 rx_mode &= ~AcceptMulticast; 2847 } else if (dev->flags & IFF_ALLMULTI || 2848 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2849 /* accept all multicasts */ 2850 } else if (netdev_mc_empty(dev)) { 2851 rx_mode &= ~AcceptMulticast; 2852 } else { 2853 struct netdev_hw_addr *ha; 2854 2855 mc_filter[1] = mc_filter[0] = 0; 2856 netdev_for_each_mc_addr(ha, dev) { 2857 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2858 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2859 } 2860 2861 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2862 tmp = mc_filter[0]; 2863 mc_filter[0] = swab32(mc_filter[1]); 2864 mc_filter[1] = swab32(tmp); 2865 } 2866 } 2867 2868 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2869 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2870 2871 tmp = RTL_R32(tp, RxConfig); 2872 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2873 } 2874 2875 DECLARE_RTL_COND(rtl_csiar_cond) 2876 { 2877 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2878 } 2879 2880 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2881 { 2882 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2883 2884 RTL_W32(tp, CSIDR, value); 2885 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2886 CSIAR_BYTE_ENABLE | func << 16); 2887 2888 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2889 } 2890 2891 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2892 { 2893 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2894 2895 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2896 CSIAR_BYTE_ENABLE); 2897 2898 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2899 RTL_R32(tp, CSIDR) : ~0; 2900 } 2901 2902 static void rtl_csi_mod(struct rtl8169_private *tp, int addr, 2903 u32 mask, u32 set) 2904 { 2905 u32 val; 2906 2907 WARN(addr % 4, "Invalid CSI address %#x\n", addr); 2908 2909 netdev_notice_once(tp->dev, 2910 "No native access to PCI extended config space, falling back to CSI\n"); 2911 2912 val = rtl_csi_read(tp, addr); 2913 rtl_csi_write(tp, addr, (val & ~mask) | set); 2914 } 2915 2916 static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) 2917 { 2918 struct pci_dev *pdev = tp->pci_dev; 2919 int rc; 2920 u8 val; 2921 2922 #define RTL_GEN3_RELATED_OFF 0x0890 2923 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1 2924 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) { 2925 rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val); 2926 if (rc == PCIBIOS_SUCCESSFUL) { 2927 val &= ~RTL_GEN3_ZRXDC_NONCOMPL; 2928 rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF, 2929 val); 2930 if (rc == PCIBIOS_SUCCESSFUL) 2931 return; 2932 } 2933 } 2934 2935 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); 2936 } 2937 2938 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2939 { 2940 struct pci_dev *pdev = tp->pci_dev; 2941 2942 /* According to Realtek the value at config space address 0x070f 2943 * controls the L0s/L1 entrance latency. We try standard ECAM access 2944 * first and if it fails fall back to CSI. 2945 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2946 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2947 */ 2948 if (pdev->cfg_size > 0x070f && 2949 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2950 return; 2951 2952 rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); 2953 } 2954 2955 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2956 { 2957 /* L0 7us, L1 16us */ 2958 rtl_set_aspm_entry_latency(tp, 0x27); 2959 } 2960 2961 struct ephy_info { 2962 unsigned int offset; 2963 u16 mask; 2964 u16 bits; 2965 }; 2966 2967 static void __rtl_ephy_init(struct rtl8169_private *tp, 2968 const struct ephy_info *e, int len) 2969 { 2970 u16 w; 2971 2972 while (len-- > 0) { 2973 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2974 rtl_ephy_write(tp, e->offset, w); 2975 e++; 2976 } 2977 } 2978 2979 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2980 2981 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2982 { 2983 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2984 PCI_EXP_LNKCTL_CLKREQ_EN); 2985 } 2986 2987 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2988 { 2989 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2990 PCI_EXP_LNKCTL_CLKREQ_EN); 2991 } 2992 2993 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2994 { 2995 /* work around an issue when PCI reset occurs during L2/L3 state */ 2996 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2997 } 2998 2999 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 3000 { 3001 /* Bits control which events trigger ASPM L1 exit: 3002 * Bit 12: rxdv 3003 * Bit 11: ltr_msg 3004 * Bit 10: txdma_poll 3005 * Bit 9: xadm 3006 * Bit 8: pktavi 3007 * Bit 7: txpla 3008 */ 3009 switch (tp->mac_version) { 3010 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 3011 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3012 break; 3013 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 3014 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 3015 break; 3016 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 3017 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 3018 break; 3019 default: 3020 break; 3021 } 3022 } 3023 3024 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 3025 { 3026 switch (tp->mac_version) { 3027 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3028 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 3029 break; 3030 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 3031 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 3032 break; 3033 default: 3034 break; 3035 } 3036 } 3037 3038 static void rtl_enable_ltr(struct rtl8169_private *tp) 3039 { 3040 switch (tp->mac_version) { 3041 case RTL_GIGA_MAC_VER_80: 3042 r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); 3043 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3044 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3045 r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); 3046 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3047 r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); 3048 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3049 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3050 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3051 r8168_mac_ocp_write(tp, 0xcde8, 0x887a); 3052 r8168_mac_ocp_write(tp, 0xcdea, 0x9003); 3053 r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); 3054 r8168_mac_ocp_write(tp, 0xcdee, 0x9003); 3055 r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); 3056 r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); 3057 r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); 3058 r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); 3059 r8168_mac_ocp_write(tp, 0xcdf8, 0x8849); 3060 r8168_mac_ocp_write(tp, 0xcdfa, 0x9003); 3061 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); 3062 break; 3063 case RTL_GIGA_MAC_VER_70: 3064 r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); 3065 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3066 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3067 r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); 3068 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3069 r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); 3070 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3071 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3072 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3073 r8168_mac_ocp_write(tp, 0xcde8, 0x887a); 3074 r8168_mac_ocp_write(tp, 0xcdea, 0x9003); 3075 r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); 3076 r8168_mac_ocp_write(tp, 0xcdee, 0x9003); 3077 r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); 3078 r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); 3079 r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); 3080 r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); 3081 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); 3082 break; 3083 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 3084 r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); 3085 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3086 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3087 r8168_mac_ocp_write(tp, 0xcdd2, 0x889c); 3088 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3089 r8168_mac_ocp_write(tp, 0xcdd4, 0x8c30); 3090 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3091 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3092 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3093 r8168_mac_ocp_write(tp, 0xcde8, 0x883e); 3094 r8168_mac_ocp_write(tp, 0xcdea, 0x9003); 3095 r8168_mac_ocp_write(tp, 0xcdec, 0x889c); 3096 r8168_mac_ocp_write(tp, 0xcdee, 0x9003); 3097 r8168_mac_ocp_write(tp, 0xcdf0, 0x8C09); 3098 r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); 3099 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); 3100 break; 3101 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3102 case RTL_GIGA_MAC_VER_52: 3103 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3104 RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EXTEND_EN); 3105 fallthrough; 3106 case RTL_GIGA_MAC_VER_51: 3107 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3108 r8168_mac_ocp_write(tp, 0xe02c, 0x1880); 3109 r8168_mac_ocp_write(tp, 0xe02e, 0x4880); 3110 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3111 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3112 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3113 r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); 3114 r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); 3115 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3116 break; 3117 default: 3118 return; 3119 } 3120 /* chip can trigger LTR */ 3121 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN); 3122 } 3123 3124 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 3125 { 3126 u8 val8; 3127 3128 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 3129 return; 3130 3131 /* Don't enable ASPM in the chip if OS can't control ASPM */ 3132 if (enable && tp->aspm_manageable) { 3133 /* On these chip versions ASPM can even harm 3134 * bus communication of other PCI devices. 3135 */ 3136 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 3137 tp->mac_version == RTL_GIGA_MAC_VER_43) 3138 return; 3139 3140 rtl_mod_config5(tp, 0, ASPM_en); 3141 switch (tp->mac_version) { 3142 case RTL_GIGA_MAC_VER_70: 3143 case RTL_GIGA_MAC_VER_80: 3144 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 3145 RTL_W8(tp, INT_CFG0_8125, val8); 3146 break; 3147 default: 3148 rtl_mod_config2(tp, 0, ClkReqEn); 3149 break; 3150 } 3151 3152 rtl_enable_ltr(tp); 3153 switch (tp->mac_version) { 3154 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3155 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 3156 /* reset ephy tx/rx disable timer */ 3157 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 3158 /* chip can trigger L1.2 */ 3159 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 3160 break; 3161 default: 3162 break; 3163 } 3164 } else { 3165 switch (tp->mac_version) { 3166 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3167 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 3168 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 3169 break; 3170 default: 3171 break; 3172 } 3173 3174 switch (tp->mac_version) { 3175 case RTL_GIGA_MAC_VER_70: 3176 case RTL_GIGA_MAC_VER_80: 3177 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 3178 RTL_W8(tp, INT_CFG0_8125, val8); 3179 break; 3180 default: 3181 rtl_mod_config2(tp, ClkReqEn, 0); 3182 break; 3183 } 3184 rtl_mod_config5(tp, ASPM_en, 0); 3185 } 3186 } 3187 3188 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 3189 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 3190 { 3191 /* Usage of dynamic vs. static FIFO is controlled by bit 3192 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 3193 */ 3194 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3195 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3196 } 3197 3198 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3199 u8 low, u8 high) 3200 { 3201 /* FIFO thresholds for pause flow control */ 3202 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3203 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3204 } 3205 3206 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3207 { 3208 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3209 } 3210 3211 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3212 { 3213 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3214 3215 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3216 3217 rtl_disable_clock_request(tp); 3218 } 3219 3220 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3221 { 3222 static const struct ephy_info e_info_8168cp[] = { 3223 { 0x01, 0, 0x0001 }, 3224 { 0x02, 0x0800, 0x1000 }, 3225 { 0x03, 0, 0x0042 }, 3226 { 0x06, 0x0080, 0x0000 }, 3227 { 0x07, 0, 0x2000 } 3228 }; 3229 3230 rtl_set_def_aspm_entry_latency(tp); 3231 3232 rtl_ephy_init(tp, e_info_8168cp); 3233 3234 __rtl_hw_start_8168cp(tp); 3235 } 3236 3237 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3238 { 3239 rtl_set_def_aspm_entry_latency(tp); 3240 3241 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3242 } 3243 3244 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3245 { 3246 rtl_set_def_aspm_entry_latency(tp); 3247 3248 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3249 3250 /* Magic. */ 3251 RTL_W8(tp, DBG_REG, 0x20); 3252 } 3253 3254 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3255 { 3256 static const struct ephy_info e_info_8168c_1[] = { 3257 { 0x02, 0x0800, 0x1000 }, 3258 { 0x03, 0, 0x0002 }, 3259 { 0x06, 0x0080, 0x0000 } 3260 }; 3261 3262 rtl_set_def_aspm_entry_latency(tp); 3263 3264 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3265 3266 rtl_ephy_init(tp, e_info_8168c_1); 3267 3268 __rtl_hw_start_8168cp(tp); 3269 } 3270 3271 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3272 { 3273 static const struct ephy_info e_info_8168c_2[] = { 3274 { 0x01, 0, 0x0001 }, 3275 { 0x03, 0x0400, 0x0020 } 3276 }; 3277 3278 rtl_set_def_aspm_entry_latency(tp); 3279 3280 rtl_ephy_init(tp, e_info_8168c_2); 3281 3282 __rtl_hw_start_8168cp(tp); 3283 } 3284 3285 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3286 { 3287 rtl_set_def_aspm_entry_latency(tp); 3288 3289 __rtl_hw_start_8168cp(tp); 3290 } 3291 3292 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3293 { 3294 rtl_set_def_aspm_entry_latency(tp); 3295 3296 rtl_disable_clock_request(tp); 3297 } 3298 3299 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3300 { 3301 static const struct ephy_info e_info_8168d_4[] = { 3302 { 0x0b, 0x0000, 0x0048 }, 3303 { 0x19, 0x0020, 0x0050 }, 3304 { 0x0c, 0x0100, 0x0020 }, 3305 { 0x10, 0x0004, 0x0000 }, 3306 }; 3307 3308 rtl_set_def_aspm_entry_latency(tp); 3309 3310 rtl_ephy_init(tp, e_info_8168d_4); 3311 3312 rtl_enable_clock_request(tp); 3313 } 3314 3315 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3316 { 3317 static const struct ephy_info e_info_8168e_1[] = { 3318 { 0x00, 0x0200, 0x0100 }, 3319 { 0x00, 0x0000, 0x0004 }, 3320 { 0x06, 0x0002, 0x0001 }, 3321 { 0x06, 0x0000, 0x0030 }, 3322 { 0x07, 0x0000, 0x2000 }, 3323 { 0x00, 0x0000, 0x0020 }, 3324 { 0x03, 0x5800, 0x2000 }, 3325 { 0x03, 0x0000, 0x0001 }, 3326 { 0x01, 0x0800, 0x1000 }, 3327 { 0x07, 0x0000, 0x4000 }, 3328 { 0x1e, 0x0000, 0x2000 }, 3329 { 0x19, 0xffff, 0xfe6c }, 3330 { 0x0a, 0x0000, 0x0040 } 3331 }; 3332 3333 rtl_set_def_aspm_entry_latency(tp); 3334 3335 rtl_ephy_init(tp, e_info_8168e_1); 3336 3337 rtl_disable_clock_request(tp); 3338 3339 /* Reset tx FIFO pointer */ 3340 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3341 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3342 3343 rtl_mod_config5(tp, Spi_en, 0); 3344 } 3345 3346 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3347 { 3348 static const struct ephy_info e_info_8168e_2[] = { 3349 { 0x09, 0x0000, 0x0080 }, 3350 { 0x19, 0x0000, 0x0224 }, 3351 { 0x00, 0x0000, 0x0004 }, 3352 { 0x0c, 0x3df0, 0x0200 }, 3353 }; 3354 3355 rtl_set_def_aspm_entry_latency(tp); 3356 3357 rtl_ephy_init(tp, e_info_8168e_2); 3358 3359 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3360 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3361 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3362 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3363 rtl_reset_packet_filter(tp); 3364 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3365 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3366 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3367 3368 rtl_disable_clock_request(tp); 3369 3370 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3371 3372 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3373 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3374 rtl_mod_config5(tp, Spi_en, 0); 3375 } 3376 3377 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3378 { 3379 rtl_set_def_aspm_entry_latency(tp); 3380 3381 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3382 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3383 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3384 rtl_reset_packet_filter(tp); 3385 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3386 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3387 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3388 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3389 3390 rtl_disable_clock_request(tp); 3391 3392 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3393 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3394 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3395 rtl_mod_config5(tp, Spi_en, 0); 3396 } 3397 3398 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3399 { 3400 static const struct ephy_info e_info_8168f_1[] = { 3401 { 0x06, 0x00c0, 0x0020 }, 3402 { 0x08, 0x0001, 0x0002 }, 3403 { 0x09, 0x0000, 0x0080 }, 3404 { 0x19, 0x0000, 0x0224 }, 3405 { 0x00, 0x0000, 0x0008 }, 3406 { 0x0c, 0x3df0, 0x0200 }, 3407 }; 3408 3409 rtl_hw_start_8168f(tp); 3410 3411 rtl_ephy_init(tp, e_info_8168f_1); 3412 } 3413 3414 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3415 { 3416 static const struct ephy_info e_info_8168f_1[] = { 3417 { 0x06, 0x00c0, 0x0020 }, 3418 { 0x0f, 0xffff, 0x5200 }, 3419 { 0x19, 0x0000, 0x0224 }, 3420 { 0x00, 0x0000, 0x0008 }, 3421 { 0x0c, 0x3df0, 0x0200 }, 3422 }; 3423 3424 rtl_hw_start_8168f(tp); 3425 rtl_pcie_state_l2l3_disable(tp); 3426 3427 rtl_ephy_init(tp, e_info_8168f_1); 3428 } 3429 3430 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3431 { 3432 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3433 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3434 3435 rtl_set_def_aspm_entry_latency(tp); 3436 3437 rtl_reset_packet_filter(tp); 3438 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3439 3440 rtl_disable_rxdvgate(tp); 3441 3442 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3443 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3444 3445 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3446 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3447 3448 rtl_pcie_state_l2l3_disable(tp); 3449 } 3450 3451 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3452 { 3453 static const struct ephy_info e_info_8168g_1[] = { 3454 { 0x00, 0x0008, 0x0000 }, 3455 { 0x0c, 0x3ff0, 0x0820 }, 3456 { 0x1e, 0x0000, 0x0001 }, 3457 { 0x19, 0x8000, 0x0000 } 3458 }; 3459 3460 rtl_hw_start_8168g(tp); 3461 rtl_ephy_init(tp, e_info_8168g_1); 3462 } 3463 3464 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3465 { 3466 static const struct ephy_info e_info_8168g_2[] = { 3467 { 0x00, 0x0008, 0x0000 }, 3468 { 0x0c, 0x3ff0, 0x0820 }, 3469 { 0x19, 0xffff, 0x7c00 }, 3470 { 0x1e, 0xffff, 0x20eb }, 3471 { 0x0d, 0xffff, 0x1666 }, 3472 { 0x00, 0xffff, 0x10a3 }, 3473 { 0x06, 0xffff, 0xf050 }, 3474 { 0x04, 0x0000, 0x0010 }, 3475 { 0x1d, 0x4000, 0x0000 }, 3476 }; 3477 3478 rtl_hw_start_8168g(tp); 3479 rtl_ephy_init(tp, e_info_8168g_2); 3480 } 3481 3482 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3483 { 3484 static const u16 fix_data[] = { 3485 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3486 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3487 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3488 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3489 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3490 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3491 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3492 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3493 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3494 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3495 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3496 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3497 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3498 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3499 }; 3500 unsigned long flags; 3501 int i; 3502 3503 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3504 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3505 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3506 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3507 } 3508 3509 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3510 { 3511 static const struct ephy_info e_info_8411_2[] = { 3512 { 0x00, 0x0008, 0x0000 }, 3513 { 0x0c, 0x37d0, 0x0820 }, 3514 { 0x1e, 0x0000, 0x0001 }, 3515 { 0x19, 0x8021, 0x0000 }, 3516 { 0x1e, 0x0000, 0x2000 }, 3517 { 0x0d, 0x0100, 0x0200 }, 3518 { 0x00, 0x0000, 0x0080 }, 3519 { 0x06, 0x0000, 0x0010 }, 3520 { 0x04, 0x0000, 0x0010 }, 3521 { 0x1d, 0x0000, 0x4000 }, 3522 }; 3523 3524 rtl_hw_start_8168g(tp); 3525 3526 rtl_ephy_init(tp, e_info_8411_2); 3527 3528 /* The following Realtek-provided magic fixes an issue with the RX unit 3529 * getting confused after the PHY having been powered-down. 3530 */ 3531 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3532 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3533 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3534 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3535 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3536 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3537 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3538 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3539 mdelay(3); 3540 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3541 3542 rtl8411b_fix_phy_down(tp); 3543 3544 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3545 3546 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3547 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3548 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3549 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3550 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3551 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3552 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3553 } 3554 3555 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3556 { 3557 static const struct ephy_info e_info_8168h_1[] = { 3558 { 0x1e, 0x0800, 0x0001 }, 3559 { 0x1d, 0x0000, 0x0800 }, 3560 { 0x05, 0xffff, 0x2089 }, 3561 { 0x06, 0xffff, 0x5881 }, 3562 { 0x04, 0xffff, 0x854a }, 3563 { 0x01, 0xffff, 0x068b } 3564 }; 3565 int rg_saw_cnt; 3566 3567 rtl_ephy_init(tp, e_info_8168h_1); 3568 3569 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3570 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3571 3572 rtl_set_def_aspm_entry_latency(tp); 3573 3574 rtl_reset_packet_filter(tp); 3575 3576 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3577 3578 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3579 3580 rtl_disable_rxdvgate(tp); 3581 3582 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3583 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3584 3585 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3586 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3587 3588 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3589 3590 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3591 3592 rtl_pcie_state_l2l3_disable(tp); 3593 3594 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3595 if (rg_saw_cnt > 0) { 3596 u16 sw_cnt_1ms_ini; 3597 3598 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3599 sw_cnt_1ms_ini &= 0x0fff; 3600 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3601 } 3602 3603 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); 3604 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3605 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3606 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3607 3608 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3609 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3610 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3611 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3612 } 3613 3614 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3615 { 3616 rtl8168ep_stop_cmac(tp); 3617 3618 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3619 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3620 3621 rtl_set_def_aspm_entry_latency(tp); 3622 3623 rtl_reset_packet_filter(tp); 3624 3625 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3626 3627 rtl_disable_rxdvgate(tp); 3628 3629 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3630 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3631 3632 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3633 3634 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3635 3636 rtl_pcie_state_l2l3_disable(tp); 3637 } 3638 3639 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3640 { 3641 static const struct ephy_info e_info_8168ep_3[] = { 3642 { 0x00, 0x0000, 0x0080 }, 3643 { 0x0d, 0x0100, 0x0200 }, 3644 { 0x19, 0x8021, 0x0000 }, 3645 { 0x1e, 0x0000, 0x2000 }, 3646 }; 3647 3648 rtl_ephy_init(tp, e_info_8168ep_3); 3649 3650 rtl_hw_start_8168ep(tp); 3651 3652 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3653 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3654 3655 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3656 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3657 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3658 } 3659 3660 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3661 { 3662 static const struct ephy_info e_info_8117[] = { 3663 { 0x19, 0x0040, 0x1100 }, 3664 { 0x59, 0x0040, 0x1100 }, 3665 }; 3666 int rg_saw_cnt; 3667 3668 rtl8168ep_stop_cmac(tp); 3669 rtl_ephy_init(tp, e_info_8117); 3670 3671 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3672 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3673 3674 rtl_set_def_aspm_entry_latency(tp); 3675 3676 rtl_reset_packet_filter(tp); 3677 3678 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3679 3680 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3681 3682 rtl_disable_rxdvgate(tp); 3683 3684 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3685 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3686 3687 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3688 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3689 3690 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3691 3692 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3693 3694 rtl_pcie_state_l2l3_disable(tp); 3695 3696 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3697 if (rg_saw_cnt > 0) { 3698 u16 sw_cnt_1ms_ini; 3699 3700 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3701 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3702 } 3703 3704 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); 3705 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3706 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3707 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3708 3709 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3710 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3711 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3712 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3713 3714 /* firmware is for MAC only */ 3715 r8169_apply_firmware(tp); 3716 } 3717 3718 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3719 { 3720 static const struct ephy_info e_info_8102e_1[] = { 3721 { 0x01, 0, 0x6e65 }, 3722 { 0x02, 0, 0x091f }, 3723 { 0x03, 0, 0xc2f9 }, 3724 { 0x06, 0, 0xafb5 }, 3725 { 0x07, 0, 0x0e00 }, 3726 { 0x19, 0, 0xec80 }, 3727 { 0x01, 0, 0x2e65 }, 3728 { 0x01, 0, 0x6e65 } 3729 }; 3730 u8 cfg1; 3731 3732 rtl_set_def_aspm_entry_latency(tp); 3733 3734 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3735 3736 RTL_W8(tp, Config1, 3737 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3738 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3739 3740 cfg1 = RTL_R8(tp, Config1); 3741 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3742 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3743 3744 rtl_ephy_init(tp, e_info_8102e_1); 3745 } 3746 3747 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3748 { 3749 rtl_set_def_aspm_entry_latency(tp); 3750 3751 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3752 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3753 } 3754 3755 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3756 { 3757 rtl_hw_start_8102e_2(tp); 3758 3759 rtl_ephy_write(tp, 0x03, 0xc2f9); 3760 } 3761 3762 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3763 { 3764 static const struct ephy_info e_info_8401[] = { 3765 { 0x01, 0xffff, 0x6fe5 }, 3766 { 0x03, 0xffff, 0x0599 }, 3767 { 0x06, 0xffff, 0xaf25 }, 3768 { 0x07, 0xffff, 0x8e68 }, 3769 }; 3770 3771 rtl_ephy_init(tp, e_info_8401); 3772 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3773 } 3774 3775 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3776 { 3777 static const struct ephy_info e_info_8105e_1[] = { 3778 { 0x07, 0, 0x4000 }, 3779 { 0x19, 0, 0x0200 }, 3780 { 0x19, 0, 0x0020 }, 3781 { 0x1e, 0, 0x2000 }, 3782 { 0x03, 0, 0x0001 }, 3783 { 0x19, 0, 0x0100 }, 3784 { 0x19, 0, 0x0004 }, 3785 { 0x0a, 0, 0x0020 } 3786 }; 3787 3788 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3789 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3790 3791 /* Disable Early Tally Counter */ 3792 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3793 3794 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3795 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3796 3797 rtl_ephy_init(tp, e_info_8105e_1); 3798 3799 rtl_pcie_state_l2l3_disable(tp); 3800 } 3801 3802 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3803 { 3804 rtl_hw_start_8105e_1(tp); 3805 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3806 } 3807 3808 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3809 { 3810 static const struct ephy_info e_info_8402[] = { 3811 { 0x19, 0xffff, 0xff64 }, 3812 { 0x1e, 0, 0x4000 } 3813 }; 3814 3815 rtl_set_def_aspm_entry_latency(tp); 3816 3817 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3818 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3819 3820 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3821 3822 rtl_ephy_init(tp, e_info_8402); 3823 3824 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3825 rtl_reset_packet_filter(tp); 3826 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3827 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3828 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3829 3830 /* disable EEE */ 3831 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3832 3833 rtl_pcie_state_l2l3_disable(tp); 3834 } 3835 3836 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3837 { 3838 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3839 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3840 3841 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3842 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3843 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3844 3845 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3846 rtl_set_aspm_entry_latency(tp, 0x2f); 3847 3848 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3849 3850 /* disable EEE */ 3851 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3852 3853 rtl_pcie_state_l2l3_disable(tp); 3854 } 3855 3856 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3857 { 3858 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3859 } 3860 3861 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3862 { 3863 rtl_pcie_state_l2l3_disable(tp); 3864 3865 RTL_W16(tp, 0x382, 0x221b); 3866 RTL_W32(tp, RSS_CTRL_8125, 0); 3867 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3868 3869 /* disable UPS */ 3870 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3871 3872 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3873 3874 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3875 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3876 3877 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3878 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3879 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3880 3881 /* disable new tx descriptor format */ 3882 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3883 3884 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3885 tp->mac_version == RTL_GIGA_MAC_VER_80) 3886 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3887 3888 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 3889 r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); 3890 else if (tp->mac_version == RTL_GIGA_MAC_VER_70) 3891 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3892 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3893 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3894 else 3895 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3896 3897 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3898 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3899 else 3900 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3901 3902 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3903 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3904 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3905 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); 3906 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3907 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3908 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3909 tp->mac_version == RTL_GIGA_MAC_VER_80) 3910 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3911 else 3912 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3913 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3914 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3915 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3916 3917 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3918 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3919 udelay(1); 3920 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3921 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3922 3923 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3924 3925 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3926 3927 rtl_disable_rxdvgate(tp); 3928 } 3929 3930 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3931 { 3932 static const struct ephy_info e_info_8125a_2[] = { 3933 { 0x04, 0xffff, 0xd000 }, 3934 { 0x0a, 0xffff, 0x8653 }, 3935 { 0x23, 0xffff, 0xab66 }, 3936 { 0x20, 0xffff, 0x9455 }, 3937 { 0x21, 0xffff, 0x99ff }, 3938 { 0x29, 0xffff, 0xfe04 }, 3939 3940 { 0x44, 0xffff, 0xd000 }, 3941 { 0x4a, 0xffff, 0x8653 }, 3942 { 0x63, 0xffff, 0xab66 }, 3943 { 0x60, 0xffff, 0x9455 }, 3944 { 0x61, 0xffff, 0x99ff }, 3945 { 0x69, 0xffff, 0xfe04 }, 3946 }; 3947 3948 rtl_set_def_aspm_entry_latency(tp); 3949 rtl_ephy_init(tp, e_info_8125a_2); 3950 rtl_hw_start_8125_common(tp); 3951 } 3952 3953 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3954 { 3955 static const struct ephy_info e_info_8125b[] = { 3956 { 0x0b, 0xffff, 0xa908 }, 3957 { 0x1e, 0xffff, 0x20eb }, 3958 { 0x4b, 0xffff, 0xa908 }, 3959 { 0x5e, 0xffff, 0x20eb }, 3960 { 0x22, 0x0030, 0x0020 }, 3961 { 0x62, 0x0030, 0x0020 }, 3962 }; 3963 3964 rtl_set_def_aspm_entry_latency(tp); 3965 rtl_ephy_init(tp, e_info_8125b); 3966 rtl_hw_start_8125_common(tp); 3967 } 3968 3969 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3970 { 3971 rtl_set_def_aspm_entry_latency(tp); 3972 rtl_hw_start_8125_common(tp); 3973 } 3974 3975 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3976 { 3977 rtl_disable_zrxdc_timeout(tp); 3978 rtl_set_def_aspm_entry_latency(tp); 3979 rtl_hw_start_8125_common(tp); 3980 } 3981 3982 static void rtl_hw_start_8127a(struct rtl8169_private *tp) 3983 { 3984 rtl_set_def_aspm_entry_latency(tp); 3985 rtl_hw_start_8125_common(tp); 3986 } 3987 3988 static void rtl_hw_config(struct rtl8169_private *tp) 3989 { 3990 static const rtl_generic_fct hw_configs[] = { 3991 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3992 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3993 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3994 [RTL_GIGA_MAC_VER_10] = NULL, 3995 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3996 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3997 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3998 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3999 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 4000 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 4001 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 4002 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 4003 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 4004 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 4005 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 4006 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 4007 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 4008 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 4009 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 4010 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 4011 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 4012 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 4013 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 4014 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 4015 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 4016 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 4017 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 4018 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 4019 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 4020 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 4021 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 4022 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 4023 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 4024 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 4025 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 4026 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 4027 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 4028 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 4029 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, 4030 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, 4031 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, 4032 [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a, 4033 }; 4034 4035 if (hw_configs[tp->mac_version]) 4036 hw_configs[tp->mac_version](tp); 4037 } 4038 4039 static void rtl_hw_start_8125(struct rtl8169_private *tp) 4040 { 4041 int i; 4042 4043 RTL_W8(tp, INT_CFG0_8125, 0x00); 4044 4045 /* disable interrupt coalescing */ 4046 switch (tp->mac_version) { 4047 case RTL_GIGA_MAC_VER_61: 4048 case RTL_GIGA_MAC_VER_64: 4049 case RTL_GIGA_MAC_VER_65: 4050 case RTL_GIGA_MAC_VER_66: 4051 case RTL_GIGA_MAC_VER_80: 4052 for (i = 0xa00; i < 0xb00; i += 4) 4053 RTL_W32(tp, i, 0); 4054 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 4055 RTL_W16(tp, INT_CFG1_8125, 0x0000); 4056 break; 4057 case RTL_GIGA_MAC_VER_63: 4058 case RTL_GIGA_MAC_VER_70: 4059 for (i = 0xa00; i < 0xa80; i += 4) 4060 RTL_W32(tp, i, 0); 4061 RTL_W16(tp, INT_CFG1_8125, 0x0000); 4062 break; 4063 default: 4064 break; 4065 } 4066 4067 /* enable extended tally counter */ 4068 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 4069 4070 rtl_hw_config(tp); 4071 } 4072 4073 static void rtl_hw_start_8168(struct rtl8169_private *tp) 4074 { 4075 if (rtl_is_8168evl_up(tp)) 4076 RTL_W8(tp, MaxTxPacketSize, EarlySize); 4077 else 4078 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 4079 4080 rtl_hw_config(tp); 4081 4082 /* disable interrupt coalescing */ 4083 RTL_W16(tp, IntrMitigate, 0x0000); 4084 } 4085 4086 static void rtl_hw_start_8169(struct rtl8169_private *tp) 4087 { 4088 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 4089 4090 tp->cp_cmd |= PCIMulRW; 4091 4092 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 4093 tp->mac_version == RTL_GIGA_MAC_VER_03) 4094 tp->cp_cmd |= EnAnaPLL; 4095 4096 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 4097 4098 rtl8169_set_magic_reg(tp); 4099 4100 /* disable interrupt coalescing */ 4101 RTL_W16(tp, IntrMitigate, 0x0000); 4102 } 4103 4104 static void rtl_hw_start(struct rtl8169_private *tp) 4105 { 4106 rtl_unlock_config_regs(tp); 4107 /* disable aspm and clock request before ephy access */ 4108 rtl_hw_aspm_clkreq_enable(tp, false); 4109 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 4110 4111 rtl_set_eee_txidle_timer(tp); 4112 4113 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4114 rtl_hw_start_8169(tp); 4115 else if (rtl_is_8125(tp)) 4116 rtl_hw_start_8125(tp); 4117 else 4118 rtl_hw_start_8168(tp); 4119 4120 rtl_enable_exit_l1(tp); 4121 rtl_hw_aspm_clkreq_enable(tp, true); 4122 rtl_set_rx_max_size(tp); 4123 rtl_set_rx_tx_desc_registers(tp); 4124 rtl_lock_config_regs(tp); 4125 4126 rtl_jumbo_config(tp); 4127 4128 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 4129 rtl_pci_commit(tp); 4130 4131 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 4132 rtl_init_rxcfg(tp); 4133 rtl_set_tx_config_registers(tp); 4134 rtl_set_rx_config_features(tp, tp->dev->features); 4135 rtl_set_rx_mode(tp->dev); 4136 rtl_irq_enable(tp); 4137 } 4138 4139 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 4140 { 4141 struct rtl8169_private *tp = netdev_priv(dev); 4142 4143 WRITE_ONCE(dev->mtu, new_mtu); 4144 netdev_update_features(dev); 4145 rtl_jumbo_config(tp); 4146 rtl_set_eee_txidle_timer(tp); 4147 4148 return 0; 4149 } 4150 4151 static void rtl8169_mark_to_asic(struct RxDesc *desc) 4152 { 4153 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 4154 4155 desc->opts2 = 0; 4156 /* Force memory writes to complete before releasing descriptor */ 4157 dma_wmb(); 4158 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 4159 } 4160 4161 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 4162 struct RxDesc *desc) 4163 { 4164 struct device *d = tp_to_dev(tp); 4165 int node = dev_to_node(d); 4166 dma_addr_t mapping; 4167 struct page *data; 4168 4169 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 4170 if (!data) 4171 return NULL; 4172 4173 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4174 if (unlikely(dma_mapping_error(d, mapping))) { 4175 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 4176 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 4177 return NULL; 4178 } 4179 4180 desc->addr = cpu_to_le64(mapping); 4181 rtl8169_mark_to_asic(desc); 4182 4183 return data; 4184 } 4185 4186 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4187 { 4188 int i; 4189 4190 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4191 dma_unmap_page(tp_to_dev(tp), 4192 le64_to_cpu(tp->RxDescArray[i].addr), 4193 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4194 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4195 tp->Rx_databuff[i] = NULL; 4196 tp->RxDescArray[i].addr = 0; 4197 tp->RxDescArray[i].opts1 = 0; 4198 } 4199 } 4200 4201 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4202 { 4203 int i; 4204 4205 for (i = 0; i < NUM_RX_DESC; i++) { 4206 struct page *data; 4207 4208 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4209 if (!data) { 4210 rtl8169_rx_clear(tp); 4211 return -ENOMEM; 4212 } 4213 tp->Rx_databuff[i] = data; 4214 } 4215 4216 /* mark as last descriptor in the ring */ 4217 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4218 4219 return 0; 4220 } 4221 4222 static int rtl8169_init_ring(struct rtl8169_private *tp) 4223 { 4224 rtl8169_init_ring_indexes(tp); 4225 4226 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4227 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4228 4229 return rtl8169_rx_fill(tp); 4230 } 4231 4232 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4233 { 4234 struct ring_info *tx_skb = tp->tx_skb + entry; 4235 struct TxDesc *desc = tp->TxDescArray + entry; 4236 4237 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4238 DMA_TO_DEVICE); 4239 memset(desc, 0, sizeof(*desc)); 4240 memset(tx_skb, 0, sizeof(*tx_skb)); 4241 } 4242 4243 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4244 unsigned int n) 4245 { 4246 unsigned int i; 4247 4248 for (i = 0; i < n; i++) { 4249 unsigned int entry = (start + i) % NUM_TX_DESC; 4250 struct ring_info *tx_skb = tp->tx_skb + entry; 4251 unsigned int len = tx_skb->len; 4252 4253 if (len) { 4254 struct sk_buff *skb = tx_skb->skb; 4255 4256 rtl8169_unmap_tx_skb(tp, entry); 4257 if (skb) 4258 dev_consume_skb_any(skb); 4259 } 4260 } 4261 } 4262 4263 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4264 { 4265 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4266 netdev_reset_queue(tp->dev); 4267 } 4268 4269 static void rtl8169_cleanup(struct rtl8169_private *tp) 4270 { 4271 napi_disable(&tp->napi); 4272 4273 /* Give a racing hard_start_xmit a few cycles to complete. */ 4274 synchronize_net(); 4275 4276 /* Disable interrupts */ 4277 rtl8169_irq_mask_and_ack(tp); 4278 4279 rtl_rx_close(tp); 4280 4281 switch (tp->mac_version) { 4282 case RTL_GIGA_MAC_VER_28: 4283 case RTL_GIGA_MAC_VER_31: 4284 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4285 break; 4286 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4287 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4288 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4289 break; 4290 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 4291 rtl_enable_rxdvgate(tp); 4292 fsleep(2000); 4293 break; 4294 default: 4295 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4296 fsleep(100); 4297 break; 4298 } 4299 4300 rtl_hw_reset(tp); 4301 4302 rtl8169_tx_clear(tp); 4303 rtl8169_init_ring_indexes(tp); 4304 } 4305 4306 static void rtl_reset_work(struct rtl8169_private *tp) 4307 { 4308 int i; 4309 4310 netif_stop_queue(tp->dev); 4311 4312 rtl8169_cleanup(tp); 4313 4314 for (i = 0; i < NUM_RX_DESC; i++) 4315 rtl8169_mark_to_asic(tp->RxDescArray + i); 4316 4317 napi_enable(&tp->napi); 4318 rtl_hw_start(tp); 4319 } 4320 4321 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4322 { 4323 struct rtl8169_private *tp = netdev_priv(dev); 4324 4325 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4326 } 4327 4328 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4329 void *addr, unsigned int entry, bool desc_own) 4330 { 4331 struct TxDesc *txd = tp->TxDescArray + entry; 4332 struct device *d = tp_to_dev(tp); 4333 dma_addr_t mapping; 4334 u32 opts1; 4335 int ret; 4336 4337 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4338 ret = dma_mapping_error(d, mapping); 4339 if (unlikely(ret)) { 4340 if (net_ratelimit()) 4341 netdev_err(tp->dev, "Failed to map TX data!\n"); 4342 return ret; 4343 } 4344 4345 txd->addr = cpu_to_le64(mapping); 4346 txd->opts2 = cpu_to_le32(opts[1]); 4347 4348 opts1 = opts[0] | len; 4349 if (entry == NUM_TX_DESC - 1) 4350 opts1 |= RingEnd; 4351 if (desc_own) 4352 opts1 |= DescOwn; 4353 txd->opts1 = cpu_to_le32(opts1); 4354 4355 tp->tx_skb[entry].len = len; 4356 4357 return 0; 4358 } 4359 4360 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4361 const u32 *opts, unsigned int entry) 4362 { 4363 struct skb_shared_info *info = skb_shinfo(skb); 4364 unsigned int cur_frag; 4365 4366 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4367 const skb_frag_t *frag = info->frags + cur_frag; 4368 void *addr = skb_frag_address(frag); 4369 u32 len = skb_frag_size(frag); 4370 4371 entry = (entry + 1) % NUM_TX_DESC; 4372 4373 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4374 goto err_out; 4375 } 4376 4377 return 0; 4378 4379 err_out: 4380 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4381 return -EIO; 4382 } 4383 4384 static bool rtl_skb_is_udp(struct sk_buff *skb) 4385 { 4386 int no = skb_network_offset(skb); 4387 struct ipv6hdr *i6h, _i6h; 4388 struct iphdr *ih, _ih; 4389 4390 switch (vlan_get_protocol(skb)) { 4391 case htons(ETH_P_IP): 4392 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4393 return ih && ih->protocol == IPPROTO_UDP; 4394 case htons(ETH_P_IPV6): 4395 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4396 return i6h && i6h->nexthdr == IPPROTO_UDP; 4397 default: 4398 return false; 4399 } 4400 } 4401 4402 #define RTL_MIN_PATCH_LEN 47 4403 4404 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4405 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4406 struct sk_buff *skb) 4407 { 4408 unsigned int padto = 0, len = skb->len; 4409 4410 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4411 skb_transport_header_was_set(skb)) { 4412 unsigned int trans_data_len = skb_tail_pointer(skb) - 4413 skb_transport_header(skb); 4414 4415 if (trans_data_len >= offsetof(struct udphdr, len) && 4416 trans_data_len < RTL_MIN_PATCH_LEN) { 4417 u16 dest = ntohs(udp_hdr(skb)->dest); 4418 4419 /* dest is a standard PTP port */ 4420 if (dest == 319 || dest == 320) 4421 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4422 } 4423 4424 if (trans_data_len < sizeof(struct udphdr)) 4425 padto = max_t(unsigned int, padto, 4426 len + sizeof(struct udphdr) - trans_data_len); 4427 } 4428 4429 return padto; 4430 } 4431 4432 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4433 struct sk_buff *skb) 4434 { 4435 unsigned int padto = 0; 4436 4437 switch (tp->mac_version) { 4438 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4439 padto = rtl8125_quirk_udp_padto(tp, skb); 4440 break; 4441 default: 4442 break; 4443 } 4444 4445 switch (tp->mac_version) { 4446 case RTL_GIGA_MAC_VER_34: 4447 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 4448 padto = max_t(unsigned int, padto, ETH_ZLEN); 4449 break; 4450 default: 4451 break; 4452 } 4453 4454 return padto; 4455 } 4456 4457 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4458 { 4459 u32 mss = skb_shinfo(skb)->gso_size; 4460 4461 if (mss) { 4462 opts[0] |= TD_LSO; 4463 opts[0] |= mss << TD0_MSS_SHIFT; 4464 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4465 const struct iphdr *ip = ip_hdr(skb); 4466 4467 if (ip->protocol == IPPROTO_TCP) 4468 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4469 else if (ip->protocol == IPPROTO_UDP) 4470 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4471 else 4472 WARN_ON_ONCE(1); 4473 } 4474 } 4475 4476 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4477 struct sk_buff *skb, u32 *opts) 4478 { 4479 struct skb_shared_info *shinfo = skb_shinfo(skb); 4480 u32 mss = shinfo->gso_size; 4481 4482 if (mss) { 4483 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4484 opts[0] |= TD1_GTSENV4; 4485 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4486 if (skb_cow_head(skb, 0)) 4487 return false; 4488 4489 tcp_v6_gso_csum_prep(skb); 4490 opts[0] |= TD1_GTSENV6; 4491 } else { 4492 WARN_ON_ONCE(1); 4493 } 4494 4495 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4496 opts[1] |= mss << TD1_MSS_SHIFT; 4497 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4498 u8 ip_protocol; 4499 4500 switch (vlan_get_protocol(skb)) { 4501 case htons(ETH_P_IP): 4502 opts[1] |= TD1_IPv4_CS; 4503 ip_protocol = ip_hdr(skb)->protocol; 4504 break; 4505 4506 case htons(ETH_P_IPV6): 4507 opts[1] |= TD1_IPv6_CS; 4508 ip_protocol = ipv6_hdr(skb)->nexthdr; 4509 break; 4510 4511 default: 4512 ip_protocol = IPPROTO_RAW; 4513 break; 4514 } 4515 4516 if (ip_protocol == IPPROTO_TCP) 4517 opts[1] |= TD1_TCP_CS; 4518 else if (ip_protocol == IPPROTO_UDP) 4519 opts[1] |= TD1_UDP_CS; 4520 else 4521 WARN_ON_ONCE(1); 4522 4523 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4524 } else { 4525 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4526 4527 /* skb_padto would free the skb on error */ 4528 return !__skb_put_padto(skb, padto, false); 4529 } 4530 4531 return true; 4532 } 4533 4534 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4535 { 4536 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4537 } 4538 4539 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4540 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4541 { 4542 switch (tp->mac_version) { 4543 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4544 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4545 return false; 4546 default: 4547 return true; 4548 } 4549 } 4550 4551 static void rtl8169_doorbell(struct rtl8169_private *tp) 4552 { 4553 if (rtl_is_8125(tp)) 4554 RTL_W16(tp, TxPoll_8125, BIT(0)); 4555 else 4556 RTL_W8(tp, TxPoll, NPQ); 4557 } 4558 4559 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4560 struct net_device *dev) 4561 { 4562 struct rtl8169_private *tp = netdev_priv(dev); 4563 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4564 struct TxDesc *txd_first, *txd_last; 4565 bool stop_queue, door_bell; 4566 unsigned int frags; 4567 u32 opts[2]; 4568 4569 if (unlikely(!rtl_tx_slots_avail(tp))) { 4570 if (net_ratelimit()) 4571 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4572 netif_stop_queue(dev); 4573 return NETDEV_TX_BUSY; 4574 } 4575 4576 opts[1] = rtl8169_tx_vlan_tag(skb); 4577 opts[0] = 0; 4578 4579 if (!rtl_chip_supports_csum_v2(tp)) 4580 rtl8169_tso_csum_v1(skb, opts); 4581 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4582 goto err_dma_0; 4583 4584 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4585 entry, false))) 4586 goto err_dma_0; 4587 4588 txd_first = tp->TxDescArray + entry; 4589 4590 frags = skb_shinfo(skb)->nr_frags; 4591 if (frags) { 4592 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4593 goto err_dma_1; 4594 entry = (entry + frags) % NUM_TX_DESC; 4595 } 4596 4597 txd_last = tp->TxDescArray + entry; 4598 txd_last->opts1 |= cpu_to_le32(LastFrag); 4599 tp->tx_skb[entry].skb = skb; 4600 4601 skb_tx_timestamp(skb); 4602 4603 /* Force memory writes to complete before releasing descriptor */ 4604 dma_wmb(); 4605 4606 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4607 4608 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4609 4610 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4611 smp_wmb(); 4612 4613 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4614 4615 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4616 R8169_TX_STOP_THRS, 4617 R8169_TX_START_THRS); 4618 if (door_bell || stop_queue) 4619 rtl8169_doorbell(tp); 4620 4621 return NETDEV_TX_OK; 4622 4623 err_dma_1: 4624 rtl8169_unmap_tx_skb(tp, entry); 4625 err_dma_0: 4626 dev_kfree_skb_any(skb); 4627 dev->stats.tx_dropped++; 4628 return NETDEV_TX_OK; 4629 } 4630 4631 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4632 { 4633 struct skb_shared_info *info = skb_shinfo(skb); 4634 unsigned int nr_frags = info->nr_frags; 4635 4636 if (!nr_frags) 4637 return UINT_MAX; 4638 4639 return skb_frag_size(info->frags + nr_frags - 1); 4640 } 4641 4642 /* Workaround for hw issues with TSO on RTL8168evl */ 4643 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4644 netdev_features_t features) 4645 { 4646 /* IPv4 header has options field */ 4647 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4648 ip_hdrlen(skb) > sizeof(struct iphdr)) 4649 features &= ~NETIF_F_ALL_TSO; 4650 4651 /* IPv4 TCP header has options field */ 4652 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4653 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4654 features &= ~NETIF_F_ALL_TSO; 4655 4656 else if (rtl_last_frag_len(skb) <= 6) 4657 features &= ~NETIF_F_ALL_TSO; 4658 4659 return features; 4660 } 4661 4662 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4663 struct net_device *dev, 4664 netdev_features_t features) 4665 { 4666 struct rtl8169_private *tp = netdev_priv(dev); 4667 4668 if (skb_is_gso(skb)) { 4669 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4670 features = rtl8168evl_fix_tso(skb, features); 4671 4672 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4673 rtl_chip_supports_csum_v2(tp)) 4674 features &= ~NETIF_F_ALL_TSO; 4675 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4676 /* work around hw bug on some chip versions */ 4677 if (skb->len < ETH_ZLEN) 4678 features &= ~NETIF_F_CSUM_MASK; 4679 4680 if (rtl_quirk_packet_padto(tp, skb)) 4681 features &= ~NETIF_F_CSUM_MASK; 4682 4683 if (skb_transport_offset(skb) > TCPHO_MAX && 4684 rtl_chip_supports_csum_v2(tp)) 4685 features &= ~NETIF_F_CSUM_MASK; 4686 } 4687 4688 return vlan_features_check(skb, features); 4689 } 4690 4691 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4692 { 4693 struct rtl8169_private *tp = netdev_priv(dev); 4694 struct pci_dev *pdev = tp->pci_dev; 4695 int pci_status_errs; 4696 u16 pci_cmd; 4697 4698 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4699 4700 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4701 4702 if (net_ratelimit()) 4703 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4704 pci_cmd, pci_status_errs); 4705 4706 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4707 } 4708 4709 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4710 int budget) 4711 { 4712 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4713 struct sk_buff *skb; 4714 4715 dirty_tx = tp->dirty_tx; 4716 4717 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4718 unsigned int entry = dirty_tx % NUM_TX_DESC; 4719 u32 status; 4720 4721 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4722 if (status & DescOwn) 4723 break; 4724 4725 skb = tp->tx_skb[entry].skb; 4726 rtl8169_unmap_tx_skb(tp, entry); 4727 4728 if (skb) { 4729 pkts_compl++; 4730 bytes_compl += skb->len; 4731 napi_consume_skb(skb, budget); 4732 } 4733 dirty_tx++; 4734 } 4735 4736 if (tp->dirty_tx != dirty_tx) { 4737 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4738 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4739 4740 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4741 rtl_tx_slots_avail(tp), 4742 R8169_TX_START_THRS); 4743 /* 4744 * 8168 hack: TxPoll requests are lost when the Tx packets are 4745 * too close. Let's kick an extra TxPoll request when a burst 4746 * of start_xmit activity is detected (if it is not detected, 4747 * it is slow enough). -- FR 4748 * If skb is NULL then we come here again once a tx irq is 4749 * triggered after the last fragment is marked transmitted. 4750 */ 4751 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4752 rtl8169_doorbell(tp); 4753 } 4754 } 4755 4756 static inline int rtl8169_fragmented_frame(u32 status) 4757 { 4758 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4759 } 4760 4761 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4762 { 4763 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4764 4765 if (status == RxProtoTCP || status == RxProtoUDP) 4766 skb->ip_summed = CHECKSUM_UNNECESSARY; 4767 else 4768 skb_checksum_none_assert(skb); 4769 } 4770 4771 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4772 { 4773 struct device *d = tp_to_dev(tp); 4774 int count; 4775 4776 for (count = 0; count < budget; count++, tp->cur_rx++) { 4777 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4778 struct RxDesc *desc = tp->RxDescArray + entry; 4779 struct sk_buff *skb; 4780 const void *rx_buf; 4781 dma_addr_t addr; 4782 u32 status; 4783 4784 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4785 if (status & DescOwn) 4786 break; 4787 4788 /* This barrier is needed to keep us from reading 4789 * any other fields out of the Rx descriptor until 4790 * we know the status of DescOwn 4791 */ 4792 dma_rmb(); 4793 4794 if (unlikely(status & RxRES)) { 4795 if (net_ratelimit()) 4796 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4797 status); 4798 dev->stats.rx_errors++; 4799 if (status & (RxRWT | RxRUNT)) 4800 dev->stats.rx_length_errors++; 4801 if (status & RxCRC) 4802 dev->stats.rx_crc_errors++; 4803 4804 if (!(dev->features & NETIF_F_RXALL)) 4805 goto release_descriptor; 4806 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4807 goto release_descriptor; 4808 } 4809 4810 pkt_size = status & GENMASK(13, 0); 4811 if (likely(!(dev->features & NETIF_F_RXFCS))) 4812 pkt_size -= ETH_FCS_LEN; 4813 4814 /* The driver does not support incoming fragmented frames. 4815 * They are seen as a symptom of over-mtu sized frames. 4816 */ 4817 if (unlikely(rtl8169_fragmented_frame(status))) { 4818 dev->stats.rx_dropped++; 4819 dev->stats.rx_length_errors++; 4820 goto release_descriptor; 4821 } 4822 4823 skb = napi_alloc_skb(&tp->napi, pkt_size); 4824 if (unlikely(!skb)) { 4825 dev->stats.rx_dropped++; 4826 goto release_descriptor; 4827 } 4828 4829 addr = le64_to_cpu(desc->addr); 4830 rx_buf = page_address(tp->Rx_databuff[entry]); 4831 4832 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4833 prefetch(rx_buf); 4834 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4835 skb->tail += pkt_size; 4836 skb->len = pkt_size; 4837 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4838 4839 rtl8169_rx_csum(skb, status); 4840 skb->protocol = eth_type_trans(skb, dev); 4841 4842 rtl8169_rx_vlan_tag(desc, skb); 4843 4844 if (skb->pkt_type == PACKET_MULTICAST) 4845 dev->stats.multicast++; 4846 4847 napi_gro_receive(&tp->napi, skb); 4848 4849 dev_sw_netstats_rx_add(dev, pkt_size); 4850 release_descriptor: 4851 rtl8169_mark_to_asic(desc); 4852 } 4853 4854 return count; 4855 } 4856 4857 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4858 { 4859 struct rtl8169_private *tp = dev_instance; 4860 u32 status = rtl_get_events(tp); 4861 4862 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4863 return IRQ_NONE; 4864 4865 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4866 if (unlikely(status & SYSErr && 4867 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4868 rtl8169_pcierr_interrupt(tp->dev); 4869 goto out; 4870 } 4871 4872 if (status & LinkChg) 4873 phy_mac_interrupt(tp->phydev); 4874 4875 rtl_irq_disable(tp); 4876 napi_schedule(&tp->napi); 4877 out: 4878 rtl_ack_events(tp, status); 4879 4880 return IRQ_HANDLED; 4881 } 4882 4883 static void rtl_task(struct work_struct *work) 4884 { 4885 struct rtl8169_private *tp = 4886 container_of(work, struct rtl8169_private, wk.work); 4887 int ret; 4888 4889 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4890 /* if chip isn't accessible, reset bus to revive it */ 4891 if (RTL_R32(tp, TxConfig) == ~0) { 4892 ret = pci_reset_bus(tp->pci_dev); 4893 if (ret < 0) { 4894 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4895 netif_device_detach(tp->dev); 4896 return; 4897 } 4898 } 4899 4900 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4901 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4902 PCIE_LINK_STATE_L0S); 4903 if (!ret) 4904 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4905 goto reset; 4906 } 4907 4908 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4909 reset: 4910 rtl_reset_work(tp); 4911 netif_wake_queue(tp->dev); 4912 } 4913 } 4914 4915 static int rtl8169_poll(struct napi_struct *napi, int budget) 4916 { 4917 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4918 struct net_device *dev = tp->dev; 4919 int work_done; 4920 4921 rtl_tx(dev, tp, budget); 4922 4923 work_done = rtl_rx(dev, tp, budget); 4924 4925 if (work_done < budget && napi_complete_done(napi, work_done)) 4926 rtl_irq_enable(tp); 4927 4928 return work_done; 4929 } 4930 4931 static void rtl_enable_tx_lpi(struct rtl8169_private *tp, bool enable) 4932 { 4933 if (!rtl_supports_eee(tp)) 4934 return; 4935 4936 switch (tp->mac_version) { 4937 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_52: 4938 /* Adjust EEE LED frequency */ 4939 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 4940 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 4941 if (enable) 4942 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 4943 else 4944 rtl_eri_clear_bits(tp, 0x1b0, 0x0003); 4945 break; 4946 case RTL_GIGA_MAC_VER_61: 4947 if (enable) { 4948 r8168_mac_ocp_modify(tp, 0xe040, 0, 0x0003); 4949 r8168_mac_ocp_modify(tp, 0xeb62, 0, 0x0006); 4950 } else { 4951 r8168_mac_ocp_modify(tp, 0xe040, 0x0003, 0); 4952 r8168_mac_ocp_modify(tp, 0xeb62, 0x0006, 0); 4953 } 4954 break; 4955 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 4956 if (enable) 4957 r8168_mac_ocp_modify(tp, 0xe040, 0, 0x0003); 4958 else 4959 r8168_mac_ocp_modify(tp, 0xe040, 0x0003, 0); 4960 break; 4961 default: 4962 break; 4963 } 4964 } 4965 4966 static void r8169_phylink_handler(struct net_device *ndev) 4967 { 4968 struct rtl8169_private *tp = netdev_priv(ndev); 4969 struct device *d = tp_to_dev(tp); 4970 4971 if (netif_carrier_ok(ndev)) { 4972 rtl_link_chg_patch(tp); 4973 rtl_enable_tx_lpi(tp, tp->phydev->enable_tx_lpi); 4974 pm_request_resume(d); 4975 } else { 4976 pm_runtime_idle(d); 4977 } 4978 4979 phy_print_status(tp->phydev); 4980 } 4981 4982 static int r8169_phy_connect(struct rtl8169_private *tp) 4983 { 4984 struct phy_device *phydev = tp->phydev; 4985 phy_interface_t phy_mode; 4986 int ret; 4987 4988 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4989 PHY_INTERFACE_MODE_MII; 4990 4991 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4992 phy_mode); 4993 if (ret) 4994 return ret; 4995 4996 if (!tp->supports_gmii) 4997 phy_set_max_speed(phydev, SPEED_100); 4998 4999 phy_attached_info(phydev); 5000 5001 return 0; 5002 } 5003 5004 static void rtl8169_down(struct rtl8169_private *tp) 5005 { 5006 disable_work_sync(&tp->wk.work); 5007 /* Clear all task flags */ 5008 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 5009 5010 phy_stop(tp->phydev); 5011 5012 /* Reset SerDes PHY to bring down fiber link */ 5013 if (tp->sfp_mode) 5014 rtl_sfp_reset(tp); 5015 5016 rtl8169_update_counters(tp); 5017 5018 pci_clear_master(tp->pci_dev); 5019 rtl_pci_commit(tp); 5020 5021 rtl8169_cleanup(tp); 5022 rtl_disable_exit_l1(tp); 5023 rtl_prepare_power_down(tp); 5024 5025 if (tp->dash_type != RTL_DASH_NONE && !tp->saved_wolopts) 5026 rtl8168_driver_stop(tp); 5027 } 5028 5029 static void rtl8169_up(struct rtl8169_private *tp) 5030 { 5031 if (tp->dash_type != RTL_DASH_NONE) 5032 rtl8168_driver_start(tp); 5033 5034 pci_set_master(tp->pci_dev); 5035 phy_init_hw(tp->phydev); 5036 phy_resume(tp->phydev); 5037 rtl8169_init_phy(tp); 5038 napi_enable(&tp->napi); 5039 enable_work(&tp->wk.work); 5040 rtl_reset_work(tp); 5041 5042 phy_start(tp->phydev); 5043 } 5044 5045 static int rtl8169_close(struct net_device *dev) 5046 { 5047 struct rtl8169_private *tp = netdev_priv(dev); 5048 struct pci_dev *pdev = tp->pci_dev; 5049 5050 pm_runtime_get_sync(&pdev->dev); 5051 5052 netif_stop_queue(dev); 5053 rtl8169_down(tp); 5054 rtl8169_rx_clear(tp); 5055 5056 free_irq(tp->irq, tp); 5057 5058 phy_disconnect(tp->phydev); 5059 5060 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 5061 tp->RxPhyAddr); 5062 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 5063 tp->TxPhyAddr); 5064 tp->TxDescArray = NULL; 5065 tp->RxDescArray = NULL; 5066 5067 pm_runtime_put_sync(&pdev->dev); 5068 5069 return 0; 5070 } 5071 5072 #ifdef CONFIG_NET_POLL_CONTROLLER 5073 static void rtl8169_netpoll(struct net_device *dev) 5074 { 5075 struct rtl8169_private *tp = netdev_priv(dev); 5076 5077 rtl8169_interrupt(tp->irq, tp); 5078 } 5079 #endif 5080 5081 static int rtl_open(struct net_device *dev) 5082 { 5083 struct rtl8169_private *tp = netdev_priv(dev); 5084 struct pci_dev *pdev = tp->pci_dev; 5085 unsigned long irqflags; 5086 int retval = -ENOMEM; 5087 5088 pm_runtime_get_sync(&pdev->dev); 5089 5090 /* 5091 * Rx and Tx descriptors needs 256 bytes alignment. 5092 * dma_alloc_coherent provides more. 5093 */ 5094 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 5095 &tp->TxPhyAddr, GFP_KERNEL); 5096 if (!tp->TxDescArray) 5097 goto out; 5098 5099 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 5100 &tp->RxPhyAddr, GFP_KERNEL); 5101 if (!tp->RxDescArray) 5102 goto err_free_tx_0; 5103 5104 retval = rtl8169_init_ring(tp); 5105 if (retval < 0) 5106 goto err_free_rx_1; 5107 5108 rtl_request_firmware(tp); 5109 5110 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 5111 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 5112 if (retval < 0) 5113 goto err_release_fw_2; 5114 5115 retval = r8169_phy_connect(tp); 5116 if (retval) 5117 goto err_free_irq; 5118 5119 rtl8169_up(tp); 5120 rtl8169_init_counter_offsets(tp); 5121 netif_start_queue(dev); 5122 out: 5123 pm_runtime_put_sync(&pdev->dev); 5124 5125 return retval; 5126 5127 err_free_irq: 5128 free_irq(tp->irq, tp); 5129 err_release_fw_2: 5130 rtl_release_firmware(tp); 5131 rtl8169_rx_clear(tp); 5132 err_free_rx_1: 5133 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 5134 tp->RxPhyAddr); 5135 tp->RxDescArray = NULL; 5136 err_free_tx_0: 5137 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 5138 tp->TxPhyAddr); 5139 tp->TxDescArray = NULL; 5140 goto out; 5141 } 5142 5143 static void 5144 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5145 { 5146 struct rtl8169_private *tp = netdev_priv(dev); 5147 struct pci_dev *pdev = tp->pci_dev; 5148 struct rtl8169_counters *counters = tp->counters; 5149 5150 pm_runtime_get_noresume(&pdev->dev); 5151 5152 netdev_stats_to_stats64(stats, &dev->stats); 5153 dev_fetch_sw_netstats(stats, dev->tstats); 5154 5155 /* 5156 * Fetch additional counter values missing in stats collected by driver 5157 * from tally counters. 5158 */ 5159 if (pm_runtime_active(&pdev->dev)) 5160 rtl8169_update_counters(tp); 5161 5162 /* 5163 * Subtract values fetched during initalization. 5164 * See rtl8169_init_counter_offsets for a description why we do that. 5165 */ 5166 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 5167 le64_to_cpu(tp->tc_offset.tx_errors); 5168 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 5169 le32_to_cpu(tp->tc_offset.tx_multi_collision); 5170 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 5171 le16_to_cpu(tp->tc_offset.tx_aborted); 5172 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 5173 le16_to_cpu(tp->tc_offset.rx_missed); 5174 5175 pm_runtime_put_noidle(&pdev->dev); 5176 } 5177 5178 static void rtl8169_net_suspend(struct rtl8169_private *tp) 5179 { 5180 netif_device_detach(tp->dev); 5181 5182 if (netif_running(tp->dev)) 5183 rtl8169_down(tp); 5184 } 5185 5186 static int rtl8169_runtime_resume(struct device *dev) 5187 { 5188 struct rtl8169_private *tp = dev_get_drvdata(dev); 5189 5190 rtl_rar_set(tp, tp->dev->dev_addr); 5191 __rtl8169_set_wol(tp, tp->saved_wolopts); 5192 5193 if (tp->TxDescArray) 5194 rtl8169_up(tp); 5195 5196 netif_device_attach(tp->dev); 5197 5198 return 0; 5199 } 5200 5201 static int rtl8169_suspend(struct device *device) 5202 { 5203 struct rtl8169_private *tp = dev_get_drvdata(device); 5204 5205 rtnl_lock(); 5206 rtl8169_net_suspend(tp); 5207 if (!device_may_wakeup(tp_to_dev(tp))) 5208 clk_disable_unprepare(tp->clk); 5209 rtnl_unlock(); 5210 5211 return 0; 5212 } 5213 5214 static int rtl8169_resume(struct device *device) 5215 { 5216 struct rtl8169_private *tp = dev_get_drvdata(device); 5217 5218 if (!device_may_wakeup(tp_to_dev(tp))) 5219 clk_prepare_enable(tp->clk); 5220 5221 /* Some chip versions may truncate packets without this initialization */ 5222 rtl_init_rxcfg(tp); 5223 5224 return rtl8169_runtime_resume(device); 5225 } 5226 5227 static int rtl8169_runtime_suspend(struct device *device) 5228 { 5229 struct rtl8169_private *tp = dev_get_drvdata(device); 5230 5231 if (!tp->TxDescArray) { 5232 netif_device_detach(tp->dev); 5233 return 0; 5234 } 5235 5236 rtnl_lock(); 5237 __rtl8169_set_wol(tp, WAKE_PHY); 5238 rtl8169_net_suspend(tp); 5239 rtnl_unlock(); 5240 5241 return 0; 5242 } 5243 5244 static int rtl8169_runtime_idle(struct device *device) 5245 { 5246 struct rtl8169_private *tp = dev_get_drvdata(device); 5247 5248 if (tp->dash_enabled) 5249 return -EBUSY; 5250 5251 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5252 pm_schedule_suspend(device, 10000); 5253 5254 return -EBUSY; 5255 } 5256 5257 static const struct dev_pm_ops rtl8169_pm_ops = { 5258 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5259 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5260 rtl8169_runtime_idle) 5261 }; 5262 5263 static void rtl_shutdown(struct pci_dev *pdev) 5264 { 5265 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5266 5267 rtnl_lock(); 5268 rtl8169_net_suspend(tp); 5269 rtnl_unlock(); 5270 5271 /* Restore original MAC address */ 5272 rtl_rar_set(tp, tp->dev->perm_addr); 5273 5274 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) 5275 pci_prepare_to_sleep(pdev); 5276 } 5277 5278 static void rtl_remove_one(struct pci_dev *pdev) 5279 { 5280 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5281 5282 if (pci_dev_run_wake(pdev)) 5283 pm_runtime_get_noresume(&pdev->dev); 5284 5285 disable_work_sync(&tp->wk.work); 5286 5287 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5288 r8169_remove_leds(tp->leds); 5289 5290 unregister_netdev(tp->dev); 5291 5292 if (tp->dash_type != RTL_DASH_NONE) 5293 rtl8168_driver_stop(tp); 5294 5295 rtl_release_firmware(tp); 5296 5297 /* restore original MAC address */ 5298 rtl_rar_set(tp, tp->dev->perm_addr); 5299 } 5300 5301 static const struct net_device_ops rtl_netdev_ops = { 5302 .ndo_open = rtl_open, 5303 .ndo_stop = rtl8169_close, 5304 .ndo_get_stats64 = rtl8169_get_stats64, 5305 .ndo_start_xmit = rtl8169_start_xmit, 5306 .ndo_features_check = rtl8169_features_check, 5307 .ndo_tx_timeout = rtl8169_tx_timeout, 5308 .ndo_validate_addr = eth_validate_addr, 5309 .ndo_change_mtu = rtl8169_change_mtu, 5310 .ndo_fix_features = rtl8169_fix_features, 5311 .ndo_set_features = rtl8169_set_features, 5312 .ndo_set_mac_address = rtl_set_mac_address, 5313 .ndo_eth_ioctl = phy_do_ioctl_running, 5314 .ndo_set_rx_mode = rtl_set_rx_mode, 5315 #ifdef CONFIG_NET_POLL_CONTROLLER 5316 .ndo_poll_controller = rtl8169_netpoll, 5317 #endif 5318 5319 }; 5320 5321 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5322 { 5323 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5324 5325 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5326 tp->irq_mask |= SYSErr | RxFIFOOver; 5327 } 5328 5329 static int rtl_alloc_irq(struct rtl8169_private *tp) 5330 { 5331 unsigned int flags; 5332 5333 switch (tp->mac_version) { 5334 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5335 rtl_unlock_config_regs(tp); 5336 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5337 rtl_lock_config_regs(tp); 5338 fallthrough; 5339 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5340 flags = PCI_IRQ_INTX; 5341 break; 5342 default: 5343 flags = PCI_IRQ_ALL_TYPES; 5344 break; 5345 } 5346 5347 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5348 } 5349 5350 static void rtl_read_mac_address(struct rtl8169_private *tp, 5351 u8 mac_addr[ETH_ALEN]) 5352 { 5353 /* Get MAC address */ 5354 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5355 u32 value; 5356 5357 value = rtl_eri_read(tp, 0xe0); 5358 put_unaligned_le32(value, mac_addr); 5359 value = rtl_eri_read(tp, 0xe4); 5360 put_unaligned_le16(value, mac_addr + 4); 5361 } else if (rtl_is_8125(tp)) { 5362 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5363 } 5364 } 5365 5366 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5367 { 5368 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5369 } 5370 5371 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5372 { 5373 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5374 } 5375 5376 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5377 { 5378 struct rtl8169_private *tp = mii_bus->priv; 5379 5380 if (phyaddr > 0) 5381 return -ENODEV; 5382 5383 return rtl_readphy(tp, phyreg); 5384 } 5385 5386 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5387 int phyreg, u16 val) 5388 { 5389 struct rtl8169_private *tp = mii_bus->priv; 5390 5391 if (phyaddr > 0) 5392 return -ENODEV; 5393 5394 rtl_writephy(tp, phyreg, val); 5395 5396 return 0; 5397 } 5398 5399 static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr, 5400 int devnum, int regnum) 5401 { 5402 struct rtl8169_private *tp = mii_bus->priv; 5403 5404 if (addr > 0) 5405 return -ENODEV; 5406 5407 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2) 5408 return r8168_phy_ocp_read(tp, regnum); 5409 5410 return 0; 5411 } 5412 5413 static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr, 5414 int devnum, int regnum, u16 val) 5415 { 5416 struct rtl8169_private *tp = mii_bus->priv; 5417 5418 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) 5419 return -ENODEV; 5420 5421 r8168_phy_ocp_write(tp, regnum, val); 5422 5423 return 0; 5424 } 5425 5426 static int r8169_mdio_register(struct rtl8169_private *tp) 5427 { 5428 struct pci_dev *pdev = tp->pci_dev; 5429 struct mii_bus *new_bus; 5430 int ret; 5431 5432 /* On some boards with this chip version the BIOS is buggy and misses 5433 * to reset the PHY page selector. This results in the PHY ID read 5434 * accessing registers on a different page, returning a more or 5435 * less random value. Fix this by resetting the page selector first. 5436 */ 5437 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5438 tp->mac_version == RTL_GIGA_MAC_VER_26) 5439 r8169_mdio_write(tp, 0x1f, 0); 5440 5441 new_bus = devm_mdiobus_alloc(&pdev->dev); 5442 if (!new_bus) 5443 return -ENOMEM; 5444 5445 new_bus->name = "r8169"; 5446 new_bus->priv = tp; 5447 new_bus->parent = &pdev->dev; 5448 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5449 new_bus->phy_mask = GENMASK(31, 1); 5450 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5451 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5452 5453 new_bus->read = r8169_mdio_read_reg; 5454 new_bus->write = r8169_mdio_write_reg; 5455 5456 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) { 5457 new_bus->read_c45 = r8169_mdio_read_reg_c45; 5458 new_bus->write_c45 = r8169_mdio_write_reg_c45; 5459 } 5460 5461 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5462 if (ret) 5463 return ret; 5464 5465 tp->phydev = mdiobus_get_phy(new_bus, 0); 5466 if (!tp->phydev) { 5467 return -ENODEV; 5468 } else if (!tp->phydev->drv) { 5469 /* Most chip versions fail with the genphy driver. 5470 * Therefore ensure that the dedicated PHY driver is loaded. 5471 */ 5472 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5473 tp->phydev->phy_id); 5474 return -EUNATCH; 5475 } 5476 5477 tp->phydev->mac_managed_pm = true; 5478 if (rtl_supports_eee(tp)) 5479 phy_support_eee(tp->phydev); 5480 phy_support_asym_pause(tp->phydev); 5481 5482 /* mimic behavior of r8125/r8126 vendor drivers */ 5483 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5484 phy_disable_eee_mode(tp->phydev, 5485 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5486 5487 /* PHY will be woken up in rtl_open() */ 5488 phy_suspend(tp->phydev); 5489 5490 return 0; 5491 } 5492 5493 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5494 { 5495 rtl_enable_rxdvgate(tp); 5496 5497 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5498 msleep(1); 5499 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5500 5501 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5502 r8168g_wait_ll_share_fifo_ready(tp); 5503 5504 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5505 r8168g_wait_ll_share_fifo_ready(tp); 5506 } 5507 5508 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5509 { 5510 rtl_enable_rxdvgate(tp); 5511 5512 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5513 msleep(1); 5514 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5515 5516 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5517 r8168g_wait_ll_share_fifo_ready(tp); 5518 5519 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5520 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5521 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5522 r8168g_wait_ll_share_fifo_ready(tp); 5523 } 5524 5525 static void rtl_hw_initialize(struct rtl8169_private *tp) 5526 { 5527 switch (tp->mac_version) { 5528 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 5529 rtl8168ep_stop_cmac(tp); 5530 fallthrough; 5531 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5532 rtl_hw_init_8168g(tp); 5533 break; 5534 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5535 rtl_hw_init_8125(tp); 5536 break; 5537 default: 5538 break; 5539 } 5540 } 5541 5542 static int rtl_jumbo_max(struct rtl8169_private *tp) 5543 { 5544 /* Non-GBit versions don't support jumbo frames */ 5545 if (!tp->supports_gmii) 5546 return 0; 5547 5548 switch (tp->mac_version) { 5549 /* RTL8169 */ 5550 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5551 return JUMBO_7K; 5552 /* RTL8168b */ 5553 case RTL_GIGA_MAC_VER_17: 5554 return JUMBO_4K; 5555 /* RTL8168c */ 5556 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5557 return JUMBO_6K; 5558 /* RTL8125/8126 */ 5559 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5560 return JUMBO_16K; 5561 default: 5562 return JUMBO_9K; 5563 } 5564 } 5565 5566 static void rtl_init_mac_address(struct rtl8169_private *tp) 5567 { 5568 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5569 struct net_device *dev = tp->dev; 5570 int rc; 5571 5572 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5573 if (!rc) 5574 goto done; 5575 5576 rtl_read_mac_address(tp, mac_addr); 5577 if (is_valid_ether_addr(mac_addr)) 5578 goto done; 5579 5580 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5581 if (is_valid_ether_addr(mac_addr)) 5582 goto done; 5583 5584 eth_random_addr(mac_addr); 5585 dev->addr_assign_type = NET_ADDR_RANDOM; 5586 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5587 done: 5588 eth_hw_addr_set(dev, mac_addr); 5589 rtl_rar_set(tp, mac_addr); 5590 } 5591 5592 /* register is set if system vendor successfully tested ASPM 1.2 */ 5593 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5594 { 5595 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5596 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5597 return true; 5598 5599 return false; 5600 } 5601 5602 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5603 { 5604 const struct rtl_chip_info *chip; 5605 const char *ext_xid_str = ""; 5606 struct rtl8169_private *tp; 5607 int jumbo_max, region, rc; 5608 struct net_device *dev; 5609 u32 txconfig; 5610 u32 xid; 5611 5612 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5613 if (!dev) 5614 return -ENOMEM; 5615 5616 SET_NETDEV_DEV(dev, &pdev->dev); 5617 dev->netdev_ops = &rtl_netdev_ops; 5618 tp = netdev_priv(dev); 5619 tp->dev = dev; 5620 tp->pci_dev = pdev; 5621 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5622 tp->ocp_base = OCP_STD_PHY_BASE; 5623 5624 raw_spin_lock_init(&tp->mac_ocp_lock); 5625 mutex_init(&tp->led_lock); 5626 5627 /* Get the *optional* external "ether_clk" used on some boards */ 5628 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5629 if (IS_ERR(tp->clk)) 5630 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5631 5632 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5633 rc = pcim_enable_device(pdev); 5634 if (rc < 0) 5635 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5636 5637 if (pcim_set_mwi(pdev) < 0) 5638 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5639 5640 /* use first MMIO region */ 5641 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5642 if (region < 0) 5643 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5644 5645 tp->mmio_addr = pcim_iomap_region(pdev, region, KBUILD_MODNAME); 5646 if (IS_ERR(tp->mmio_addr)) 5647 return dev_err_probe(&pdev->dev, PTR_ERR(tp->mmio_addr), 5648 "cannot remap MMIO, aborting\n"); 5649 5650 txconfig = RTL_R32(tp, TxConfig); 5651 if (txconfig == ~0U) 5652 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5653 5654 xid = (txconfig >> 20) & 0xfcf; 5655 5656 /* Identify chip attached to board */ 5657 chip = rtl8169_get_chip_version(xid, tp->supports_gmii); 5658 5659 if (chip->mac_version == RTL_GIGA_MAC_VER_EXTENDED) { 5660 ext_xid_str = "ext"; 5661 xid = RTL_R32(tp, TX_CONFIG_V2); 5662 chip = rtl8169_get_extended_chip_version(xid); 5663 } 5664 if (chip->mac_version == RTL_GIGA_MAC_NONE) 5665 return dev_err_probe(&pdev->dev, -ENODEV, 5666 "unknown chip %sXID %x, contact r8169 maintainers (see MAINTAINERS file)\n", 5667 ext_xid_str, xid); 5668 tp->mac_version = chip->mac_version; 5669 tp->fw_name = chip->fw_name; 5670 5671 /* Disable ASPM L1 as that cause random device stop working 5672 * problems as well as full system hangs for some PCIe devices users. 5673 */ 5674 if (rtl_aspm_is_safe(tp)) { 5675 dev_info(&pdev->dev, "System vendor flags ASPM as safe\n"); 5676 rc = 0; 5677 } else { 5678 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5679 } 5680 tp->aspm_manageable = !rc; 5681 5682 if (rtl_is_8125(tp)) { 5683 u16 data = r8168_mac_ocp_read(tp, 0xd006); 5684 5685 if ((data & 0xff) == 0x07) 5686 tp->sfp_mode = true; 5687 } 5688 5689 tp->dash_type = rtl_get_dash_type(tp); 5690 tp->dash_enabled = rtl_dash_is_enabled(tp); 5691 5692 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5693 5694 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5695 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5696 dev->features |= NETIF_F_HIGHDMA; 5697 5698 rtl_init_rxcfg(tp); 5699 5700 rtl8169_irq_mask_and_ack(tp); 5701 5702 rtl_hw_initialize(tp); 5703 5704 rtl_hw_reset(tp); 5705 5706 rc = rtl_alloc_irq(tp); 5707 if (rc < 0) 5708 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5709 5710 tp->irq = pci_irq_vector(pdev, 0); 5711 5712 INIT_WORK(&tp->wk.work, rtl_task); 5713 disable_work(&tp->wk.work); 5714 5715 rtl_init_mac_address(tp); 5716 5717 dev->ethtool_ops = &rtl8169_ethtool_ops; 5718 5719 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5720 5721 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5722 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5723 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5724 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5725 5726 /* 5727 * Pretend we are using VLANs; This bypasses a nasty bug where 5728 * Interrupts stop flowing on high load on 8110SCd controllers. 5729 */ 5730 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5731 /* Disallow toggling */ 5732 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5733 5734 if (rtl_chip_supports_csum_v2(tp)) 5735 dev->hw_features |= NETIF_F_IPV6_CSUM; 5736 5737 dev->features |= dev->hw_features; 5738 5739 if (rtl_chip_supports_csum_v2(tp)) { 5740 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5741 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5742 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5743 } else { 5744 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5745 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5746 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5747 } 5748 5749 /* There has been a number of reports that using SG/TSO results in 5750 * tx timeouts. However for a lot of people SG/TSO works fine. 5751 * It's not fully clear which chip versions are affected. Vendor 5752 * drivers enable SG/TSO for certain chip versions per default, 5753 * let's mimic this here. On other chip versions users can 5754 * use ethtool to enable SG/TSO, use at own risk! 5755 */ 5756 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5757 tp->mac_version != RTL_GIGA_MAC_VER_61) 5758 dev->features |= dev->hw_features; 5759 5760 dev->hw_features |= NETIF_F_RXALL; 5761 dev->hw_features |= NETIF_F_RXFCS; 5762 5763 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5764 5765 netdev_sw_irq_coalesce_default_on(dev); 5766 5767 /* configure chip for default features */ 5768 rtl8169_set_features(dev, dev->features); 5769 5770 if (!tp->dash_enabled) { 5771 rtl_set_d3_pll_down(tp, true); 5772 } else { 5773 rtl_set_d3_pll_down(tp, false); 5774 dev->ethtool->wol_enabled = 1; 5775 } 5776 5777 jumbo_max = rtl_jumbo_max(tp); 5778 if (jumbo_max) 5779 dev->max_mtu = jumbo_max; 5780 5781 rtl_set_irq_mask(tp); 5782 5783 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5784 &tp->counters_phys_addr, 5785 GFP_KERNEL); 5786 if (!tp->counters) 5787 return -ENOMEM; 5788 5789 pci_set_drvdata(pdev, tp); 5790 5791 rc = r8169_mdio_register(tp); 5792 if (rc) 5793 return rc; 5794 5795 rc = register_netdev(dev); 5796 if (rc) 5797 return rc; 5798 5799 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5800 if (rtl_is_8125(tp)) 5801 tp->leds = rtl8125_init_leds(dev); 5802 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5803 tp->leds = rtl8168_init_leds(dev); 5804 } 5805 5806 netdev_info(dev, "%s, %pM, %sXID %x, IRQ %d\n", 5807 chip->name, dev->dev_addr, ext_xid_str, xid, tp->irq); 5808 5809 if (jumbo_max) 5810 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5811 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5812 "ok" : "ko"); 5813 5814 if (tp->dash_type != RTL_DASH_NONE) { 5815 netdev_info(dev, "DASH %s\n", 5816 tp->dash_enabled ? "enabled" : "disabled"); 5817 rtl8168_driver_start(tp); 5818 } 5819 5820 if (pci_dev_run_wake(pdev)) 5821 pm_runtime_put_sync(&pdev->dev); 5822 5823 return 0; 5824 } 5825 5826 static struct pci_driver rtl8169_pci_driver = { 5827 .name = KBUILD_MODNAME, 5828 .id_table = rtl8169_pci_tbl, 5829 .probe = rtl_init_one, 5830 .remove = rtl_remove_one, 5831 .shutdown = rtl_shutdown, 5832 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5833 }; 5834 5835 module_pci_driver(rtl8169_pci_driver); 5836