1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 Semihalf.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36
37 #include <machine/bus.h>
38 #include <machine/machdep.h>
39
40 #include <dev/uart/uart.h>
41 #include <dev/uart/uart_cpu.h>
42 #ifdef FDT
43 #include <dev/uart/uart_cpu_fdt.h>
44 #include <dev/ofw/ofw_bus.h>
45 #endif
46 #include <dev/uart/uart_bus.h>
47 #include "uart_if.h"
48
49 #ifdef DEV_ACPI
50 #include <dev/uart/uart_cpu_acpi.h>
51 #include <contrib/dev/acpica/include/acpi.h>
52 #include <contrib/dev/acpica/include/accommon.h>
53 #include <contrib/dev/acpica/include/actables.h>
54 #endif
55
56 #include <sys/kdb.h>
57
58 #ifdef __aarch64__
59 #define IS_FDT (arm64_bus_method == ARM64_BUS_FDT)
60 #elif defined(FDT)
61 #define IS_FDT 1
62 #else
63 #error Unsupported configuration
64 #endif
65
66 /* PL011 UART registers and masks*/
67 #define UART_DR 0x00 /* Data register */
68 #define DR_FE (1 << 8) /* Framing error */
69 #define DR_PE (1 << 9) /* Parity error */
70 #define DR_BE (1 << 10) /* Break error */
71 #define DR_OE (1 << 11) /* Overrun error */
72
73 #define UART_FR 0x06 /* Flag register */
74 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */
75 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */
76 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
77 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
78
79 #define UART_IBRD 0x09 /* Integer baud rate register */
80 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */
81
82 #define UART_FBRD 0x0a /* Fractional baud rate register */
83 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */
84
85 #define UART_LCR_H 0x0b /* Line control register */
86 #define LCR_H_WLEN8 (0x3 << 5)
87 #define LCR_H_WLEN7 (0x2 << 5)
88 #define LCR_H_WLEN6 (0x1 << 5)
89 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */
90 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */
91 #define LCR_H_EPS (1 << 2) /* Even parity select */
92 #define LCR_H_PEN (1 << 1) /* Parity enable */
93
94 #define UART_CR 0x0c /* Control register */
95 #define CR_RXE (1 << 9) /* Receive enable */
96 #define CR_TXE (1 << 8) /* Transmit enable */
97 #define CR_UARTEN (1 << 0) /* UART enable */
98
99 #define UART_IFLS 0x0d /* FIFO level select register */
100 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */
101 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */
102 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */
103 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */
104 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */
105 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */
106 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */
107 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */
108
109 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */
110 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */
111
112 #define UART_RIS 0x0f /* Raw interrupt status register */
113 #define UART_RXREADY (1 << 4) /* RX buffer full */
114 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */
115 #define RIS_RTIM (1 << 6) /* Receive timeout */
116 #define RIS_FE (1 << 7) /* Framing error interrupt status */
117 #define RIS_PE (1 << 8) /* Parity error interrupt status */
118 #define RIS_BE (1 << 9) /* Break error interrupt status */
119 #define RIS_OE (1 << 10) /* Overrun interrupt status */
120
121 #define UART_MIS 0x10 /* Masked interrupt status register */
122 #define UART_ICR 0x11 /* Interrupt clear register */
123
124 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */
125 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */
126 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */
127 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */
128
129 /*
130 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes
131 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For
132 * RX we set the size to the full hardware capacity so that the uart core
133 * allocates enough buffer space to hold a complete fifo full of incoming data.
134 * For TX, we need to limit the size to the capacity we know will be available
135 * when the interrupt occurs; uart_core will feed exactly that many bytes to
136 * uart_pl011_bus_transmit() which must consume them all.
137 */
138 #define FIFO_RX_SIZE_R2 16
139 #define FIFO_TX_SIZE_R2 12
140 #define FIFO_RX_SIZE_R3 32
141 #define FIFO_TX_SIZE_R3 24
142 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th))
143
144 /*
145 * FIXME: actual register size is SoC-dependent, we need to handle it
146 */
147 #define __uart_getreg(bas, reg) \
148 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
149 #define __uart_setreg(bas, reg, value) \
150 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
151
152 /*
153 * Low-level UART interface.
154 */
155 static int uart_pl011_probe(struct uart_bas *bas);
156 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
157 static void uart_pl011_term(struct uart_bas *bas);
158 static void uart_pl011_putc(struct uart_bas *bas, int);
159 static int uart_pl011_rxready(struct uart_bas *bas);
160 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
161
162 static struct uart_ops uart_pl011_ops = {
163 .probe = uart_pl011_probe,
164 .init = uart_pl011_init,
165 .term = uart_pl011_term,
166 .putc = uart_pl011_putc,
167 .rxready = uart_pl011_rxready,
168 .getc = uart_pl011_getc,
169 };
170
171 static int
uart_pl011_probe(struct uart_bas * bas)172 uart_pl011_probe(struct uart_bas *bas)
173 {
174
175 /*
176 * Versions of QEMU before 41f7b58b634e (8.3) reported bogus values for
177 * this tabel. The PL011 IP is always 32-bits wide and should be shifted
178 * 2 to match the 4-byte size of the data. QEMU reported these values
179 * incorrectly before that.
180 * https://github.com/qemu/qemu/commit/41f7b58b634ec3b60ae874375d2bbb61d790971e
181 *
182 * In additon, other hardware vendors also reported this value
183 * incorrectly. It's not tied to what the ACPI device node is, but was a
184 * misunderstanding coupled with a Linux driver that didn't need the
185 * right values. Quirks used to be used to ignore the bad values, now we
186 * detect the historic mistake and override (to allow for a future where
187 * we may need to override these values).
188 *
189 * PL011 Docs: https://developer.arm.com/documentation/ddi0183/latest/
190 */
191 if (bas->regshft == 0 || bas->regiowidth == 1) {
192 bas->regshft = 2;
193 bas->regiowidth = 4;
194 }
195
196 return (0);
197 }
198
199 static void
uart_pl011_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)200 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
201 int parity)
202 {
203 uint32_t ctrl, line;
204 uint32_t baud;
205
206 /*
207 * Zero all settings to make sure
208 * UART is disabled and not configured
209 */
210 ctrl = line = 0x0;
211 __uart_setreg(bas, UART_CR, ctrl);
212
213 /* As we know UART is disabled we may setup the line */
214 switch (databits) {
215 case 7:
216 line |= LCR_H_WLEN7;
217 break;
218 case 6:
219 line |= LCR_H_WLEN6;
220 break;
221 case 8:
222 default:
223 line |= LCR_H_WLEN8;
224 break;
225 }
226
227 if (stopbits == 2)
228 line |= LCR_H_STP2;
229 else
230 line &= ~LCR_H_STP2;
231
232 if (parity)
233 line |= LCR_H_PEN;
234 else
235 line &= ~LCR_H_PEN;
236 line |= LCR_H_FEN;
237
238 /* Configure the rest */
239 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
240
241 if (bas->rclk != 0 && baudrate != 0) {
242 baud = bas->rclk * 4 / baudrate;
243 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT);
244 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC);
245 }
246
247 /* Add config. to line before reenabling UART */
248 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
249 ~0xff) | line);
250
251 /* Set rx and tx fifo levels. */
252 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS);
253
254 __uart_setreg(bas, UART_CR, ctrl);
255
256 /*
257 * Loader tells us to infer the rclk when it sets xo to 0 in
258 * hw.uart.console. The APCI SPCR code does likewise. We know the
259 * baudrate was set by the firmware, so calculate rclk from baudrate and
260 * the divisor register. If 'div' is actually 0, the resulting 0 value
261 * will have us fall back to other rclk methods. This method should be
262 * good to 5% or better because the error in baud rates needs to be
263 * below this for devices to communicate.
264 */
265 if (bas->rclk == 0 && baudrate > 0 && bas->rclk_guess) {
266 uint32_t div;
267
268 div = ((__uart_getreg(bas, UART_IBRD) & IBRD_BDIVINT) << 6) |
269 (__uart_getreg(bas, UART_FBRD) & FBRD_BDIVFRAC);
270 bas->rclk = (div * baudrate) / 4;
271 }
272
273 }
274
275 static void
uart_pl011_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)276 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
277 int parity)
278 {
279 /* Mask all interrupts */
280 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
281 ~IMSC_MASK_ALL);
282
283 uart_pl011_param(bas, baudrate, databits, stopbits, parity);
284 }
285
286 static void
uart_pl011_term(struct uart_bas * bas)287 uart_pl011_term(struct uart_bas *bas)
288 {
289 }
290
291 #if CHECK_EARLY_PRINTF(pl011)
292 static void
uart_pl011_early_putc(int c)293 uart_pl011_early_putc(int c)
294 {
295 volatile uint32_t *fr = (uint32_t *)(socdev_va + UART_FR * 4);
296 volatile uint32_t *dr = (uint32_t *)(socdev_va + UART_DR * 4);
297
298 while ((*fr & FR_TXFF) != 0)
299 ;
300 *dr = c & 0xff;
301 }
302 early_putc_t *early_putc = uart_pl011_early_putc;
303 #endif /* CHECK_EARLY_PRINTF */
304
305 static void
uart_pl011_putc(struct uart_bas * bas,int c)306 uart_pl011_putc(struct uart_bas *bas, int c)
307 {
308
309 /* Wait when TX FIFO full. Push character otherwise. */
310 while (__uart_getreg(bas, UART_FR) & FR_TXFF)
311 ;
312 __uart_setreg(bas, UART_DR, c & 0xff);
313 }
314
315 static int
uart_pl011_rxready(struct uart_bas * bas)316 uart_pl011_rxready(struct uart_bas *bas)
317 {
318
319 return !(__uart_getreg(bas, UART_FR) & FR_RXFE);
320 }
321
322 static int
uart_pl011_getc(struct uart_bas * bas,struct mtx * hwmtx)323 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
324 {
325 int c;
326
327 while (!uart_pl011_rxready(bas))
328 ;
329 c = __uart_getreg(bas, UART_DR) & 0xff;
330
331 return (c);
332 }
333
334 /*
335 * High-level UART interface.
336 */
337 struct uart_pl011_softc {
338 struct uart_softc base;
339 uint16_t imsc; /* Interrupt mask */
340 };
341
342 static int uart_pl011_bus_attach(struct uart_softc *);
343 static int uart_pl011_bus_detach(struct uart_softc *);
344 static int uart_pl011_bus_flush(struct uart_softc *, int);
345 static int uart_pl011_bus_getsig(struct uart_softc *);
346 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
347 static int uart_pl011_bus_ipend(struct uart_softc *);
348 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
349 static int uart_pl011_bus_probe(struct uart_softc *);
350 static int uart_pl011_bus_receive(struct uart_softc *);
351 static int uart_pl011_bus_setsig(struct uart_softc *, int);
352 static int uart_pl011_bus_transmit(struct uart_softc *);
353 static void uart_pl011_bus_grab(struct uart_softc *);
354 static void uart_pl011_bus_ungrab(struct uart_softc *);
355
356 static kobj_method_t uart_pl011_methods[] = {
357 KOBJMETHOD(uart_attach, uart_pl011_bus_attach),
358 KOBJMETHOD(uart_detach, uart_pl011_bus_detach),
359 KOBJMETHOD(uart_flush, uart_pl011_bus_flush),
360 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig),
361 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl),
362 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend),
363 KOBJMETHOD(uart_param, uart_pl011_bus_param),
364 KOBJMETHOD(uart_probe, uart_pl011_bus_probe),
365 KOBJMETHOD(uart_receive, uart_pl011_bus_receive),
366 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig),
367 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit),
368 KOBJMETHOD(uart_grab, uart_pl011_bus_grab),
369 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab),
370 { 0, 0 }
371 };
372
373 static struct uart_class uart_pl011_class = {
374 "pl011",
375 uart_pl011_methods,
376 sizeof(struct uart_pl011_softc),
377 .uc_ops = &uart_pl011_ops,
378 .uc_range = 0x48,
379 .uc_rclk = 0,
380 .uc_rshift = 2,
381 .uc_riowidth = 4,
382 };
383 UART_CLASS(uart_pl011_class);
384
385 #ifdef FDT
386 static struct ofw_compat_data fdt_compat_data[] = {
387 {"arm,pl011", (uintptr_t)&uart_pl011_class},
388 {NULL, (uintptr_t)NULL},
389 };
390 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data);
391 #endif
392
393 #ifdef DEV_ACPI
394 static struct acpi_uart_compat_data acpi_compat_data[] = {
395 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011, 2, 0, 0, 0, "uart pl011"},
396 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC, 2, 0, 0, 0, "uart pl011"},
397 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT, 2, 0, 0, 0, "uart pl011"},
398 {NULL, NULL, 0, 0, 0, 0, 0, NULL},
399 };
400 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
401 #endif
402
403 static int
uart_pl011_bus_attach(struct uart_softc * sc)404 uart_pl011_bus_attach(struct uart_softc *sc)
405 {
406 struct uart_pl011_softc *psc;
407 struct uart_bas *bas;
408
409 psc = (struct uart_pl011_softc *)sc;
410 bas = &sc->sc_bas;
411
412 /* Enable interrupts */
413 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
414 __uart_setreg(bas, UART_IMSC, psc->imsc);
415
416 /* Clear interrupts */
417 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
418
419 return (0);
420 }
421
422 static int
uart_pl011_bus_detach(struct uart_softc * sc)423 uart_pl011_bus_detach(struct uart_softc *sc)
424 {
425
426 return (0);
427 }
428
429 static int
uart_pl011_bus_flush(struct uart_softc * sc,int what)430 uart_pl011_bus_flush(struct uart_softc *sc, int what)
431 {
432
433 return (0);
434 }
435
436 static int
uart_pl011_bus_getsig(struct uart_softc * sc)437 uart_pl011_bus_getsig(struct uart_softc *sc)
438 {
439
440 return (0);
441 }
442
443 static int
uart_pl011_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)444 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
445 {
446 int error;
447
448 error = 0;
449 uart_lock(sc->sc_hwmtx);
450 switch (request) {
451 case UART_IOCTL_BREAK:
452 break;
453 case UART_IOCTL_BAUD:
454 *(int*)data = 115200;
455 break;
456 default:
457 error = EINVAL;
458 break;
459 }
460 uart_unlock(sc->sc_hwmtx);
461
462 return (error);
463 }
464
465 static int
uart_pl011_bus_ipend(struct uart_softc * sc)466 uart_pl011_bus_ipend(struct uart_softc *sc)
467 {
468 struct uart_pl011_softc *psc;
469 struct uart_bas *bas;
470 uint32_t ints;
471 int ipend;
472
473 psc = (struct uart_pl011_softc *)sc;
474 bas = &sc->sc_bas;
475
476 uart_lock(sc->sc_hwmtx);
477 ints = __uart_getreg(bas, UART_MIS);
478 ipend = 0;
479
480 if (ints & (UART_RXREADY | RIS_RTIM))
481 ipend |= SER_INT_RXREADY;
482 if (ints & RIS_BE)
483 ipend |= SER_INT_BREAK;
484 if (ints & RIS_OE)
485 ipend |= SER_INT_OVERRUN;
486 if (ints & UART_TXEMPTY) {
487 if (sc->sc_txbusy)
488 ipend |= SER_INT_TXIDLE;
489
490 /* Disable TX interrupt */
491 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);
492 }
493
494 uart_unlock(sc->sc_hwmtx);
495
496 return (ipend);
497 }
498
499 static int
uart_pl011_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)500 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
501 int stopbits, int parity)
502 {
503
504 uart_lock(sc->sc_hwmtx);
505 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
506 uart_unlock(sc->sc_hwmtx);
507
508 return (0);
509 }
510
511 #ifdef FDT
512 static int
uart_pl011_bus_hwrev_fdt(struct uart_softc * sc)513 uart_pl011_bus_hwrev_fdt(struct uart_softc *sc)
514 {
515 pcell_t node;
516 uint32_t periphid;
517
518 /*
519 * The FIFO sizes vary depending on hardware; rev 2 and below have 16
520 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the
521 * primecell periphid register, but we get a bit of drama, as always,
522 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte
523 * FIFOs. We check for both the old freebsd-historic and the proper
524 * bindings-defined compatible strings for bcm2835, and also check the
525 * workaround the linux drivers use for rpi3, which is to override the
526 * primecell periphid register value with a property.
527 */
528 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") ||
529 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) {
530 return (2);
531 } else {
532 node = ofw_bus_get_node(sc->sc_dev);
533 if (OF_getencprop(node, "arm,primecell-periphid", &periphid,
534 sizeof(periphid)) > 0) {
535 return ((periphid >> 20) & 0x0f);
536 }
537 }
538
539 return (-1);
540 }
541 #endif
542
543 static int
uart_pl011_bus_probe(struct uart_softc * sc)544 uart_pl011_bus_probe(struct uart_softc *sc)
545 {
546 int hwrev;
547
548 hwrev = -1;
549 #ifdef FDT
550 if (IS_FDT)
551 hwrev = uart_pl011_bus_hwrev_fdt(sc);
552 #endif
553 if (hwrev < 0)
554 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4;
555
556 if (hwrev <= 2) {
557 sc->sc_rxfifosz = FIFO_RX_SIZE_R2;
558 sc->sc_txfifosz = FIFO_TX_SIZE_R2;
559 } else {
560 sc->sc_rxfifosz = FIFO_RX_SIZE_R3;
561 sc->sc_txfifosz = FIFO_TX_SIZE_R3;
562 }
563
564 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
565
566 return (0);
567 }
568
569 static int
uart_pl011_bus_receive(struct uart_softc * sc)570 uart_pl011_bus_receive(struct uart_softc *sc)
571 {
572 struct uart_bas *bas;
573 uint32_t ints, xc;
574 int rx;
575
576 bas = &sc->sc_bas;
577 uart_lock(sc->sc_hwmtx);
578
579 for (;;) {
580 ints = __uart_getreg(bas, UART_FR);
581 if (ints & FR_RXFE)
582 break;
583 if (uart_rx_full(sc)) {
584 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
585 break;
586 }
587
588 xc = __uart_getreg(bas, UART_DR);
589 rx = xc & 0xff;
590
591 if (xc & DR_FE)
592 rx |= UART_STAT_FRAMERR;
593 if (xc & DR_PE)
594 rx |= UART_STAT_PARERR;
595
596 uart_rx_put(sc, rx);
597 }
598
599 uart_unlock(sc->sc_hwmtx);
600
601 return (0);
602 }
603
604 static int
uart_pl011_bus_setsig(struct uart_softc * sc,int sig)605 uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
606 {
607
608 return (0);
609 }
610
611 static int
uart_pl011_bus_transmit(struct uart_softc * sc)612 uart_pl011_bus_transmit(struct uart_softc *sc)
613 {
614 struct uart_pl011_softc *psc;
615 struct uart_bas *bas;
616 int i;
617
618 psc = (struct uart_pl011_softc *)sc;
619 bas = &sc->sc_bas;
620 uart_lock(sc->sc_hwmtx);
621
622 for (i = 0; i < sc->sc_txdatasz; i++) {
623 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
624 uart_barrier(bas);
625 }
626
627 /* Mark busy and enable TX interrupt */
628 sc->sc_txbusy = 1;
629 __uart_setreg(bas, UART_IMSC, psc->imsc);
630
631 uart_unlock(sc->sc_hwmtx);
632
633 return (0);
634 }
635
636 static void
uart_pl011_bus_grab(struct uart_softc * sc)637 uart_pl011_bus_grab(struct uart_softc *sc)
638 {
639 struct uart_pl011_softc *psc;
640 struct uart_bas *bas;
641
642 psc = (struct uart_pl011_softc *)sc;
643 bas = &sc->sc_bas;
644
645 /* Disable interrupts on switch to polling */
646 uart_lock(sc->sc_hwmtx);
647 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);
648 uart_unlock(sc->sc_hwmtx);
649 }
650
651 static void
uart_pl011_bus_ungrab(struct uart_softc * sc)652 uart_pl011_bus_ungrab(struct uart_softc *sc)
653 {
654 struct uart_pl011_softc *psc;
655 struct uart_bas *bas;
656
657 psc = (struct uart_pl011_softc *)sc;
658 bas = &sc->sc_bas;
659
660 /* Switch to using interrupts while not grabbed */
661 uart_lock(sc->sc_hwmtx);
662 __uart_setreg(bas, UART_IMSC, psc->imsc);
663 uart_unlock(sc->sc_hwmtx);
664 }
665