1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 #include <asm/msr.h> 21 22 /* To enable MSR tracing please use the generic trace points. */ 23 24 /* 25 * | NHM/WSM | SNB | 26 * register ------------------------------- 27 * | HT | no HT | HT | no HT | 28 *----------------------------------------- 29 * offcore | core | core | cpu | core | 30 * lbr_sel | core | core | cpu | core | 31 * ld_lat | cpu | core | cpu | core | 32 *----------------------------------------- 33 * 34 * Given that there is a small number of shared regs, 35 * we can pre-allocate their slot in the per-cpu 36 * per-core reg tables. 37 */ 38 enum extra_reg_type { 39 EXTRA_REG_NONE = -1, /* not used */ 40 41 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 42 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 43 EXTRA_REG_LBR = 2, /* lbr_select */ 44 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 45 EXTRA_REG_FE = 4, /* fe_* */ 46 EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */ 47 EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */ 48 EXTRA_REG_OMR_0 = 7, /* OMR 0 */ 49 EXTRA_REG_OMR_1 = 8, /* OMR 1 */ 50 EXTRA_REG_OMR_2 = 9, /* OMR 2 */ 51 EXTRA_REG_OMR_3 = 10, /* OMR 3 */ 52 53 EXTRA_REG_MAX /* number of entries needed */ 54 }; 55 56 struct event_constraint { 57 union { 58 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 59 u64 idxmsk64; 60 }; 61 u64 code; 62 u64 cmask; 63 int weight; 64 int overlap; 65 int flags; 66 unsigned int size; 67 }; 68 69 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 70 { 71 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 72 } 73 74 #define PERF_ARCH(name, val) \ 75 PERF_X86_EVENT_##name = val, 76 77 /* 78 * struct hw_perf_event.flags flags 79 */ 80 enum { 81 #include "perf_event_flags.h" 82 }; 83 84 #undef PERF_ARCH 85 86 #define PERF_ARCH(name, val) \ 87 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \ 88 PERF_X86_EVENT_##name); 89 90 #include "perf_event_flags.h" 91 92 #undef PERF_ARCH 93 94 static inline bool is_topdown_count(struct perf_event *event) 95 { 96 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 97 } 98 99 static inline bool is_metric_event(struct perf_event *event) 100 { 101 u64 config = event->attr.config; 102 103 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 104 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 105 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 106 } 107 108 static inline bool is_slots_event(struct perf_event *event) 109 { 110 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 111 } 112 113 static inline bool is_topdown_event(struct perf_event *event) 114 { 115 return is_metric_event(event) || is_slots_event(event); 116 } 117 118 int is_x86_event(struct perf_event *event); 119 120 static inline bool check_leader_group(struct perf_event *leader, int flags) 121 { 122 return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false; 123 } 124 125 static inline bool is_branch_counters_group(struct perf_event *event) 126 { 127 return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS); 128 } 129 130 static inline bool is_pebs_counter_event_group(struct perf_event *event) 131 { 132 return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR); 133 } 134 135 static inline bool is_acr_event_group(struct perf_event *event) 136 { 137 return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); 138 } 139 140 static inline bool is_acr_self_reload_event(struct perf_event *event) 141 { 142 struct hw_perf_event *hwc = &event->hw; 143 144 if (hwc->idx < 0) 145 return false; 146 147 return test_bit(hwc->idx, (unsigned long *)&hwc->config1); 148 } 149 150 struct amd_nb { 151 int nb_id; /* NorthBridge id */ 152 int refcnt; /* reference count */ 153 struct perf_event *owners[X86_PMC_IDX_MAX]; 154 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 155 }; 156 157 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 158 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 159 #define PEBS_OUTPUT_OFFSET 61 160 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 161 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 162 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 163 164 /* 165 * Flags PEBS can handle without an PMI. 166 * 167 * TID can only be handled by flushing at context switch. 168 * REGS_USER can be handled for events limited to ring 3. 169 * 170 */ 171 #define LARGE_PEBS_FLAGS \ 172 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 173 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 174 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 175 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 176 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 177 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \ 178 PERF_SAMPLE_WEIGHT_TYPE) 179 180 #define PEBS_GP_REGS \ 181 ((1ULL << PERF_REG_X86_AX) | \ 182 (1ULL << PERF_REG_X86_BX) | \ 183 (1ULL << PERF_REG_X86_CX) | \ 184 (1ULL << PERF_REG_X86_DX) | \ 185 (1ULL << PERF_REG_X86_DI) | \ 186 (1ULL << PERF_REG_X86_SI) | \ 187 (1ULL << PERF_REG_X86_SP) | \ 188 (1ULL << PERF_REG_X86_BP) | \ 189 (1ULL << PERF_REG_X86_IP) | \ 190 (1ULL << PERF_REG_X86_FLAGS) | \ 191 (1ULL << PERF_REG_X86_R8) | \ 192 (1ULL << PERF_REG_X86_R9) | \ 193 (1ULL << PERF_REG_X86_R10) | \ 194 (1ULL << PERF_REG_X86_R11) | \ 195 (1ULL << PERF_REG_X86_R12) | \ 196 (1ULL << PERF_REG_X86_R13) | \ 197 (1ULL << PERF_REG_X86_R14) | \ 198 (1ULL << PERF_REG_X86_R15)) 199 200 /* user space rdpmc control values */ 201 enum { 202 X86_USER_RDPMC_NEVER_ENABLE = 0, 203 X86_USER_RDPMC_CONDITIONAL_ENABLE = 1, 204 X86_USER_RDPMC_ALWAYS_ENABLE = 2, 205 }; 206 207 /* 208 * Per register state. 209 */ 210 struct er_account { 211 raw_spinlock_t lock; /* per-core: protect structure */ 212 u64 config; /* extra MSR config */ 213 u64 reg; /* extra MSR number */ 214 atomic_t ref; /* reference count */ 215 }; 216 217 /* 218 * Per core/cpu state 219 * 220 * Used to coordinate shared registers between HT threads or 221 * among events on a single PMU. 222 */ 223 struct intel_shared_regs { 224 struct er_account regs[EXTRA_REG_MAX]; 225 int refcnt; /* per-core: #HT threads */ 226 unsigned core_id; /* per-core: core id */ 227 }; 228 229 enum intel_excl_state_type { 230 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 231 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 232 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 233 }; 234 235 struct intel_excl_states { 236 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 237 bool sched_started; /* true if scheduling has started */ 238 }; 239 240 struct intel_excl_cntrs { 241 raw_spinlock_t lock; 242 243 struct intel_excl_states states[2]; 244 245 union { 246 u16 has_exclusive[2]; 247 u32 exclusive_present; 248 }; 249 250 int refcnt; /* per-core: #HT threads */ 251 unsigned core_id; /* per-core: core id */ 252 }; 253 254 struct x86_perf_task_context; 255 #define MAX_LBR_ENTRIES 32 256 257 enum { 258 LBR_FORMAT_32 = 0x00, 259 LBR_FORMAT_LIP = 0x01, 260 LBR_FORMAT_EIP = 0x02, 261 LBR_FORMAT_EIP_FLAGS = 0x03, 262 LBR_FORMAT_EIP_FLAGS2 = 0x04, 263 LBR_FORMAT_INFO = 0x05, 264 LBR_FORMAT_TIME = 0x06, 265 LBR_FORMAT_INFO2 = 0x07, 266 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 267 }; 268 269 enum { 270 X86_PERF_KFREE_SHARED = 0, 271 X86_PERF_KFREE_EXCL = 1, 272 X86_PERF_KFREE_MAX 273 }; 274 275 struct cpu_hw_events { 276 /* 277 * Generic x86 PMC bits 278 */ 279 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 280 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 281 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 282 int enabled; 283 284 int n_events; /* the # of events in the below arrays */ 285 int n_added; /* the # last events in the below arrays; 286 they've never been enabled yet */ 287 int n_txn; /* the # last events in the below arrays; 288 added in the current transaction */ 289 int n_txn_pair; 290 int n_txn_metric; 291 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 292 u64 tags[X86_PMC_IDX_MAX]; 293 294 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 295 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 296 297 int n_excl; /* the number of exclusive events */ 298 int n_late_setup; /* the num of events needs late setup */ 299 300 unsigned int txn_flags; 301 int is_fake; 302 303 /* 304 * Intel DebugStore bits 305 */ 306 struct debug_store *ds; 307 void *ds_bts_vaddr; 308 /* DS based PEBS or arch-PEBS buffer address */ 309 void *pebs_vaddr; 310 u64 pebs_enabled; 311 int n_pebs; 312 int n_large_pebs; 313 int n_pebs_via_pt; 314 int pebs_output; 315 316 /* Current super set of events hardware configuration */ 317 u64 pebs_data_cfg; 318 u64 active_pebs_data_cfg; 319 int pebs_record_size; 320 321 /* Intel Fixed counter configuration */ 322 u64 fixed_ctrl_val; 323 u64 active_fixed_ctrl_val; 324 325 /* Intel ACR/arch-PEBS configuration */ 326 u64 acr_cfg_b[X86_PMC_IDX_MAX]; 327 u64 cfg_c_val[X86_PMC_IDX_MAX]; 328 329 /* 330 * Intel LBR bits 331 */ 332 int lbr_users; 333 int lbr_pebs_users; 334 struct perf_branch_stack lbr_stack; 335 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 336 u64 lbr_counters[MAX_LBR_ENTRIES]; /* branch stack extra */ 337 union { 338 struct er_account *lbr_sel; 339 struct er_account *lbr_ctl; 340 }; 341 u64 br_sel; 342 void *last_task_ctx; 343 int last_log_id; 344 int lbr_select; 345 void *lbr_xsave; 346 347 /* 348 * Intel host/guest exclude bits 349 */ 350 u64 intel_ctrl_guest_mask; 351 u64 intel_ctrl_host_mask; 352 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 353 354 /* 355 * Intel checkpoint mask 356 */ 357 u64 intel_cp_status; 358 359 /* 360 * manage shared (per-core, per-cpu) registers 361 * used on Intel NHM/WSM/SNB 362 */ 363 struct intel_shared_regs *shared_regs; 364 /* 365 * manage exclusive counter access between hyperthread 366 */ 367 struct event_constraint *constraint_list; /* in enable order */ 368 struct intel_excl_cntrs *excl_cntrs; 369 int excl_thread_id; /* 0 or 1 */ 370 371 /* 372 * SKL TSX_FORCE_ABORT shadow 373 */ 374 u64 tfa_shadow; 375 376 /* 377 * Perf Metrics 378 */ 379 /* number of accepted metrics events */ 380 int n_metric; 381 382 /* 383 * AMD specific bits 384 */ 385 struct amd_nb *amd_nb; 386 int brs_active; /* BRS is enabled */ 387 388 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 389 u64 perf_ctr_virt_mask; 390 int n_pair; /* Large increment events */ 391 392 void *kfree_on_online[X86_PERF_KFREE_MAX]; 393 394 struct pmu *pmu; 395 }; 396 397 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 398 { .idxmsk64 = (n) }, \ 399 .code = (c), \ 400 .size = (e) - (c), \ 401 .cmask = (m), \ 402 .weight = (w), \ 403 .overlap = (o), \ 404 .flags = f, \ 405 } 406 407 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 408 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 409 410 #define EVENT_CONSTRAINT(c, n, m) \ 411 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 412 413 /* 414 * The constraint_match() function only works for 'simple' event codes 415 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 416 */ 417 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 418 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 419 420 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 421 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 422 0, PERF_X86_EVENT_EXCL) 423 424 /* 425 * The overlap flag marks event constraints with overlapping counter 426 * masks. This is the case if the counter mask of such an event is not 427 * a subset of any other counter mask of a constraint with an equal or 428 * higher weight, e.g.: 429 * 430 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 431 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 432 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 433 * 434 * The event scheduler may not select the correct counter in the first 435 * cycle because it needs to know which subsequent events will be 436 * scheduled. It may fail to schedule the events then. So we set the 437 * overlap flag for such constraints to give the scheduler a hint which 438 * events to select for counter rescheduling. 439 * 440 * Care must be taken as the rescheduling algorithm is O(n!) which 441 * will increase scheduling cycles for an over-committed system 442 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 443 * and its counter masks must be kept at a minimum. 444 */ 445 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 446 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 447 448 /* 449 * Constraint on the Event code. 450 */ 451 #define INTEL_EVENT_CONSTRAINT(c, n) \ 452 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 453 454 /* 455 * Constraint on a range of Event codes 456 */ 457 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 458 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 459 460 /* 461 * Constraint on the Event code + UMask + fixed-mask 462 * 463 * filter mask to validate fixed counter events. 464 * the following filters disqualify for fixed counters: 465 * - inv 466 * - edge 467 * - cnt-mask 468 * - in_tx 469 * - in_tx_checkpointed 470 * The other filters are supported by fixed counters. 471 * The any-thread option is supported starting with v3. 472 */ 473 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 474 #define FIXED_EVENT_CONSTRAINT(c, n) \ 475 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 476 477 /* 478 * The special metric counters do not actually exist. They are calculated from 479 * the combination of the FxCtr3 + MSR_PERF_METRICS. 480 * 481 * The special metric counters are mapped to a dummy offset for the scheduler. 482 * The sharing between multiple users of the same metric without multiplexing 483 * is not allowed, even though the hardware supports that in principle. 484 */ 485 486 #define METRIC_EVENT_CONSTRAINT(c, n) \ 487 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 488 INTEL_ARCH_EVENT_MASK) 489 490 /* 491 * Constraint on the Event code + UMask 492 */ 493 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 494 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 495 496 /* Constraint on specific umask bit only + event */ 497 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 498 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 499 500 /* Like UEVENT_CONSTRAINT, but match flags too */ 501 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 502 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 503 504 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 505 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 506 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 507 508 #define INTEL_PLD_CONSTRAINT(c, n) \ 509 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 510 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 511 512 #define INTEL_PSD_CONSTRAINT(c, n) \ 513 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 514 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 515 516 #define INTEL_PST_CONSTRAINT(c, n) \ 517 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 518 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 519 520 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \ 521 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 522 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID) 523 524 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \ 525 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 526 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW) 527 528 #define INTEL_HYBRID_STLAT_CONSTRAINT(c, n) \ 529 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 530 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW) 531 532 /* Event constraint, but match on all event flags too. */ 533 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 534 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 535 536 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 537 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 538 539 /* Check only flags, but allow all event/umask */ 540 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 541 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 542 543 /* Check flags and event code, and set the HSW store flag */ 544 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 545 __EVENT_CONSTRAINT(code, n, \ 546 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 547 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 548 549 /* Check flags and event code, and set the HSW load flag */ 550 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 551 __EVENT_CONSTRAINT(code, n, \ 552 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 553 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 554 555 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 556 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 557 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 558 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 559 560 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 561 __EVENT_CONSTRAINT(code, n, \ 562 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 563 HWEIGHT(n), 0, \ 564 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 565 566 /* Check flags and event code/umask, and set the HSW store flag */ 567 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 568 __EVENT_CONSTRAINT(code, n, \ 569 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 570 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 571 572 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 573 __EVENT_CONSTRAINT(code, n, \ 574 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 575 HWEIGHT(n), 0, \ 576 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 577 578 /* Check flags and event code/umask, and set the HSW load flag */ 579 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 580 __EVENT_CONSTRAINT(code, n, \ 581 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 582 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 583 584 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 585 __EVENT_CONSTRAINT(code, n, \ 586 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 587 HWEIGHT(n), 0, \ 588 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 589 590 /* Check flags and event code/umask, and set the HSW N/A flag */ 591 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 592 __EVENT_CONSTRAINT(code, n, \ 593 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 594 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 595 596 597 /* 598 * We define the end marker as having a weight of -1 599 * to enable blacklisting of events using a counter bitmask 600 * of zero and thus a weight of zero. 601 * The end marker has a weight that cannot possibly be 602 * obtained from counting the bits in the bitmask. 603 */ 604 #define EVENT_CONSTRAINT_END { .weight = -1 } 605 606 /* 607 * Check for end marker with weight == -1 608 */ 609 #define for_each_event_constraint(e, c) \ 610 for ((e) = (c); (e)->weight != -1; (e)++) 611 612 /* 613 * Extra registers for specific events. 614 * 615 * Some events need large masks and require external MSRs. 616 * Those extra MSRs end up being shared for all events on 617 * a PMU and sometimes between PMU of sibling HT threads. 618 * In either case, the kernel needs to handle conflicting 619 * accesses to those extra, shared, regs. The data structure 620 * to manage those registers is stored in cpu_hw_event. 621 */ 622 struct extra_reg { 623 unsigned int event; 624 unsigned int msr; 625 u64 config_mask; 626 u64 valid_mask; 627 int idx; /* per_xxx->regs[] reg index */ 628 bool extra_msr_access; 629 }; 630 631 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 632 .event = (e), \ 633 .msr = (ms), \ 634 .config_mask = (m), \ 635 .valid_mask = (vm), \ 636 .idx = EXTRA_REG_##i, \ 637 .extra_msr_access = true, \ 638 } 639 640 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 641 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 642 643 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 644 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 645 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 646 647 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 648 INTEL_UEVENT_EXTRA_REG(c, \ 649 MSR_PEBS_LD_LAT_THRESHOLD, \ 650 0xffff, \ 651 LDLAT) 652 653 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 654 655 union perf_capabilities { 656 struct { 657 u64 lbr_format:6; 658 u64 pebs_trap:1; 659 u64 pebs_arch_reg:1; 660 u64 pebs_format:4; 661 u64 smm_freeze:1; 662 /* 663 * PMU supports separate counter range for writing 664 * values > 32bit. 665 */ 666 u64 full_width_write:1; 667 u64 pebs_baseline:1; 668 u64 perf_metrics:1; 669 u64 pebs_output_pt_available:1; 670 u64 pebs_timing_info:1; 671 u64 anythread_deprecated:1; 672 u64 rdpmc_metrics_clear:1; 673 }; 674 u64 capabilities; 675 }; 676 677 struct x86_pmu_quirk { 678 struct x86_pmu_quirk *next; 679 void (*func)(void); 680 }; 681 682 union x86_pmu_config { 683 struct { 684 u64 event:8, 685 umask:8, 686 usr:1, 687 os:1, 688 edge:1, 689 pc:1, 690 interrupt:1, 691 __reserved1:1, 692 en:1, 693 inv:1, 694 cmask:8, 695 event2:4, 696 __reserved2:4, 697 go:1, 698 ho:1; 699 } bits; 700 u64 value; 701 }; 702 703 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 704 705 enum { 706 x86_lbr_exclusive_lbr, 707 x86_lbr_exclusive_bts, 708 x86_lbr_exclusive_pt, 709 x86_lbr_exclusive_max, 710 }; 711 712 #define PERF_PEBS_DATA_SOURCE_MAX 0x100 713 #define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1) 714 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 715 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) 716 717 #define X86_HYBRID_PMU_ATOM_IDX 0 718 #define X86_HYBRID_PMU_CORE_IDX 1 719 #define X86_HYBRID_PMU_TINY_IDX 2 720 721 enum hybrid_pmu_type { 722 not_hybrid, 723 hybrid_small = BIT(X86_HYBRID_PMU_ATOM_IDX), 724 hybrid_big = BIT(X86_HYBRID_PMU_CORE_IDX), 725 hybrid_tiny = BIT(X86_HYBRID_PMU_TINY_IDX), 726 727 /* The belows are only used for matching */ 728 hybrid_big_small = hybrid_big | hybrid_small, 729 hybrid_small_tiny = hybrid_small | hybrid_tiny, 730 hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny, 731 }; 732 733 struct arch_pebs_cap { 734 u64 caps; 735 u64 counters; 736 u64 pdists; 737 }; 738 739 struct x86_hybrid_pmu { 740 struct pmu pmu; 741 const char *name; 742 enum hybrid_pmu_type pmu_type; 743 cpumask_t supported_cpus; 744 union perf_capabilities intel_cap; 745 u64 intel_ctrl; 746 u64 pebs_events_mask; 747 u64 config_mask; 748 union { 749 u64 cntr_mask64; 750 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 751 }; 752 union { 753 u64 fixed_cntr_mask64; 754 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 755 }; 756 757 union { 758 u64 acr_cntr_mask64; 759 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 760 }; 761 union { 762 u64 acr_cause_mask64; 763 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 764 }; 765 struct event_constraint unconstrained; 766 767 u64 hw_cache_event_ids 768 [PERF_COUNT_HW_CACHE_MAX] 769 [PERF_COUNT_HW_CACHE_OP_MAX] 770 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 771 u64 hw_cache_extra_regs 772 [PERF_COUNT_HW_CACHE_MAX] 773 [PERF_COUNT_HW_CACHE_OP_MAX] 774 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 775 struct event_constraint *event_constraints; 776 struct event_constraint *pebs_constraints; 777 struct extra_reg *extra_regs; 778 779 unsigned int late_ack :1, 780 mid_ack :1, 781 enabled_ack :1; 782 783 struct arch_pebs_cap arch_pebs_cap; 784 785 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX]; 786 }; 787 788 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 789 { 790 return container_of(pmu, struct x86_hybrid_pmu, pmu); 791 } 792 793 extern struct static_key_false perf_is_hybrid; 794 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 795 796 #define hybrid(_pmu, _field) \ 797 (*({ \ 798 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 799 \ 800 if (is_hybrid() && (_pmu)) \ 801 __Fp = &hybrid_pmu(_pmu)->_field; \ 802 \ 803 __Fp; \ 804 })) 805 806 #define hybrid_var(_pmu, _var) \ 807 (*({ \ 808 typeof(&_var) __Fp = &_var; \ 809 \ 810 if (is_hybrid() && (_pmu)) \ 811 __Fp = &hybrid_pmu(_pmu)->_var; \ 812 \ 813 __Fp; \ 814 })) 815 816 #define hybrid_bit(_pmu, _field) \ 817 ({ \ 818 bool __Fp = x86_pmu._field; \ 819 \ 820 if (is_hybrid() && (_pmu)) \ 821 __Fp = hybrid_pmu(_pmu)->_field; \ 822 \ 823 __Fp; \ 824 }) 825 826 /* 827 * struct x86_pmu - generic x86 pmu 828 */ 829 struct x86_pmu { 830 /* 831 * Generic x86 PMC bits 832 */ 833 const char *name; 834 int version; 835 int (*handle_irq)(struct pt_regs *); 836 void (*disable_all)(void); 837 void (*enable_all)(int added); 838 void (*enable)(struct perf_event *); 839 void (*disable)(struct perf_event *); 840 void (*assign)(struct perf_event *event, int idx); 841 void (*add)(struct perf_event *); 842 void (*del)(struct perf_event *); 843 void (*read)(struct perf_event *event); 844 int (*set_period)(struct perf_event *event); 845 u64 (*update)(struct perf_event *event); 846 int (*hw_config)(struct perf_event *event); 847 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 848 void (*late_setup)(void); 849 void (*pebs_enable)(struct perf_event *event); 850 void (*pebs_disable)(struct perf_event *event); 851 void (*pebs_enable_all)(void); 852 void (*pebs_disable_all)(void); 853 unsigned eventsel; 854 unsigned perfctr; 855 unsigned fixedctr; 856 int (*addr_offset)(int index, bool eventsel); 857 int (*rdpmc_index)(int index); 858 u64 (*event_map)(int); 859 int max_events; 860 u64 config_mask; 861 union { 862 u64 cntr_mask64; 863 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 864 }; 865 union { 866 u64 fixed_cntr_mask64; 867 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 868 }; 869 union { 870 u64 acr_cntr_mask64; 871 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 872 }; 873 union { 874 u64 acr_cause_mask64; 875 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 876 }; 877 int cntval_bits; 878 u64 cntval_mask; 879 union { 880 unsigned long events_maskl; 881 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 882 }; 883 int events_mask_len; 884 int apic; 885 u64 max_period; 886 struct event_constraint * 887 (*get_event_constraints)(struct cpu_hw_events *cpuc, 888 int idx, 889 struct perf_event *event); 890 891 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 892 struct perf_event *event); 893 894 void (*start_scheduling)(struct cpu_hw_events *cpuc); 895 896 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 897 898 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 899 900 struct event_constraint *event_constraints; 901 struct x86_pmu_quirk *quirks; 902 void (*limit_period)(struct perf_event *event, s64 *l); 903 904 /* PMI handler bits */ 905 unsigned int late_ack :1, 906 mid_ack :1, 907 enabled_ack :1; 908 /* 909 * sysfs attrs 910 */ 911 int attr_rdpmc_broken; 912 int attr_rdpmc; 913 struct attribute **format_attrs; 914 915 ssize_t (*events_sysfs_show)(char *page, u64 config); 916 const struct attribute_group **attr_update; 917 918 unsigned long attr_freeze_on_smi; 919 920 /* 921 * CPU Hotplug hooks 922 */ 923 int (*cpu_prepare)(int cpu); 924 void (*cpu_starting)(int cpu); 925 void (*cpu_dying)(int cpu); 926 void (*cpu_dead)(int cpu); 927 928 void (*check_microcode)(void); 929 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx, 930 struct task_struct *task, bool sched_in); 931 932 /* 933 * Intel Arch Perfmon v2+ 934 */ 935 u64 intel_ctrl; 936 union perf_capabilities intel_cap; 937 938 /* 939 * Intel DebugStore and PEBS bits 940 */ 941 unsigned int bts :1, 942 bts_active :1, 943 ds_pebs :1, 944 pebs_active :1, 945 pebs_broken :1, 946 pebs_prec_dist :1, 947 pebs_no_tlb :1, 948 pebs_no_isolation :1, 949 pebs_block :1, 950 pebs_ept :1, 951 arch_pebs :1; 952 int pebs_record_size; 953 int pebs_buffer_size; 954 u64 pebs_events_mask; 955 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 956 struct event_constraint *pebs_constraints; 957 void (*pebs_aliases)(struct perf_event *event); 958 u64 (*pebs_latency_data)(struct perf_event *event, u64 status); 959 unsigned long large_pebs_flags; 960 u64 rtm_abort_event; 961 u64 pebs_capable; 962 963 /* 964 * Intel Architectural PEBS 965 */ 966 struct arch_pebs_cap arch_pebs_cap; 967 968 /* 969 * Intel LBR 970 */ 971 unsigned int lbr_tos, lbr_from, lbr_to, 972 lbr_info, lbr_nr; /* LBR base regs and size */ 973 union { 974 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 975 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 976 }; 977 union { 978 const int *lbr_sel_map; /* lbr_select mappings */ 979 int *lbr_ctl_map; /* LBR_CTL mappings */ 980 }; 981 u64 lbr_callstack_users; /* lbr callstack system wide users */ 982 bool lbr_double_abort; /* duplicated lbr aborts */ 983 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 984 985 unsigned int lbr_has_info:1; 986 unsigned int lbr_has_tsx:1; 987 unsigned int lbr_from_flags:1; 988 unsigned int lbr_to_cycles:1; 989 990 /* 991 * Intel Architectural LBR CPUID Enumeration 992 */ 993 unsigned int lbr_depth_mask:8; 994 unsigned int lbr_deep_c_reset:1; 995 unsigned int lbr_lip:1; 996 unsigned int lbr_cpl:1; 997 unsigned int lbr_filter:1; 998 unsigned int lbr_call_stack:1; 999 unsigned int lbr_mispred:1; 1000 unsigned int lbr_timed_lbr:1; 1001 unsigned int lbr_br_type:1; 1002 unsigned int lbr_counters:4; 1003 1004 void (*lbr_reset)(void); 1005 void (*lbr_read)(struct cpu_hw_events *cpuc); 1006 void (*lbr_save)(void *ctx); 1007 void (*lbr_restore)(void *ctx); 1008 1009 /* 1010 * Intel PT/LBR/BTS are exclusive 1011 */ 1012 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 1013 1014 /* 1015 * Intel perf metrics 1016 */ 1017 int num_topdown_events; 1018 1019 /* 1020 * AMD bits 1021 */ 1022 unsigned int amd_nb_constraints : 1; 1023 u64 perf_ctr_pair_en; 1024 1025 /* 1026 * Extra registers for events 1027 */ 1028 struct extra_reg *extra_regs; 1029 unsigned int flags; 1030 1031 /* 1032 * Intel host/guest support (KVM) 1033 */ 1034 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data); 1035 1036 /* 1037 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 1038 */ 1039 int (*check_period) (struct perf_event *event, u64 period); 1040 1041 int (*aux_output_match) (struct perf_event *event); 1042 1043 void (*filter)(struct pmu *pmu, int cpu, bool *ret); 1044 /* 1045 * Hybrid support 1046 * 1047 * Most PMU capabilities are the same among different hybrid PMUs. 1048 * The global x86_pmu saves the architecture capabilities, which 1049 * are available for all PMUs. The hybrid_pmu only includes the 1050 * unique capabilities. 1051 */ 1052 int num_hybrid_pmus; 1053 struct x86_hybrid_pmu *hybrid_pmu; 1054 enum intel_cpu_type (*get_hybrid_cpu_type) (void); 1055 }; 1056 1057 struct x86_perf_task_context_opt { 1058 int lbr_callstack_users; 1059 int lbr_stack_state; 1060 int log_id; 1061 }; 1062 1063 struct x86_perf_task_context { 1064 u64 lbr_sel; 1065 int tos; 1066 int valid_lbrs; 1067 struct x86_perf_task_context_opt opt; 1068 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 1069 }; 1070 1071 struct x86_perf_task_context_arch_lbr { 1072 struct x86_perf_task_context_opt opt; 1073 struct lbr_entry entries[]; 1074 }; 1075 1076 /* 1077 * Add padding to guarantee the 64-byte alignment of the state buffer. 1078 * 1079 * The structure is dynamically allocated. The size of the LBR state may vary 1080 * based on the number of LBR registers. 1081 * 1082 * Do not put anything after the LBR state. 1083 */ 1084 struct x86_perf_task_context_arch_lbr_xsave { 1085 struct x86_perf_task_context_opt opt; 1086 1087 union { 1088 struct xregs_state xsave; 1089 struct { 1090 struct fxregs_state i387; 1091 struct xstate_header header; 1092 struct arch_lbr_state lbr; 1093 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 1094 }; 1095 }; 1096 1097 #define x86_add_quirk(func_) \ 1098 do { \ 1099 static struct x86_pmu_quirk __quirk __initdata = { \ 1100 .func = func_, \ 1101 }; \ 1102 __quirk.next = x86_pmu.quirks; \ 1103 x86_pmu.quirks = &__quirk; \ 1104 } while (0) 1105 1106 /* 1107 * x86_pmu flags 1108 */ 1109 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 1110 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 1111 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 1112 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 1113 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 1114 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 1115 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 1116 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 1117 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 1118 #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ 1119 #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */ 1120 #define PMU_FL_DYN_CONSTRAINT 0x800 /* Needs dynamic constraint */ 1121 #define PMU_FL_HAS_OMR 0x1000 /* has 4 equivalent OMR regs */ 1122 1123 #define EVENT_VAR(_id) event_attr_##_id 1124 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 1125 1126 #define EVENT_ATTR(_name, _id) \ 1127 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 1128 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1129 .id = PERF_COUNT_HW_##_id, \ 1130 .event_str = NULL, \ 1131 }; 1132 1133 #define EVENT_ATTR_STR(_name, v, str) \ 1134 static struct perf_pmu_events_attr event_attr_##v = { \ 1135 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1136 .id = 0, \ 1137 .event_str = str, \ 1138 }; 1139 1140 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1141 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1142 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1143 .id = 0, \ 1144 .event_str_noht = noht, \ 1145 .event_str_ht = ht, \ 1146 } 1147 1148 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1149 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1150 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1151 .id = 0, \ 1152 .event_str = str, \ 1153 .pmu_type = _pmu, \ 1154 } 1155 1156 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1157 1158 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1159 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1160 .attr = __ATTR_RO(_name), \ 1161 .pmu_type = _pmu, \ 1162 } 1163 1164 struct pmu *x86_get_pmu(unsigned int cpu); 1165 extern struct x86_pmu x86_pmu __read_mostly; 1166 1167 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period); 1168 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update); 1169 DECLARE_STATIC_CALL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs); 1170 DECLARE_STATIC_CALL(x86_pmu_late_setup, *x86_pmu.late_setup); 1171 DECLARE_STATIC_CALL(x86_pmu_pebs_enable, *x86_pmu.pebs_enable); 1172 DECLARE_STATIC_CALL(x86_pmu_pebs_disable, *x86_pmu.pebs_disable); 1173 DECLARE_STATIC_CALL(x86_pmu_pebs_enable_all, *x86_pmu.pebs_enable_all); 1174 DECLARE_STATIC_CALL(x86_pmu_pebs_disable_all, *x86_pmu.pebs_disable_all); 1175 1176 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1177 { 1178 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1179 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1180 1181 return &((struct x86_perf_task_context *)ctx)->opt; 1182 } 1183 1184 static inline bool x86_pmu_has_lbr_callstack(void) 1185 { 1186 return x86_pmu.lbr_sel_map && 1187 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1188 } 1189 1190 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1191 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1192 1193 int x86_perf_event_set_period(struct perf_event *event); 1194 1195 /* 1196 * Generalized hw caching related hw_event table, filled 1197 * in on a per model basis. A value of 0 means 1198 * 'not supported', -1 means 'hw_event makes no sense on 1199 * this CPU', any other value means the raw hw_event 1200 * ID. 1201 */ 1202 1203 #define C(x) PERF_COUNT_HW_CACHE_##x 1204 1205 extern u64 __read_mostly hw_cache_event_ids 1206 [PERF_COUNT_HW_CACHE_MAX] 1207 [PERF_COUNT_HW_CACHE_OP_MAX] 1208 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1209 extern u64 __read_mostly hw_cache_extra_regs 1210 [PERF_COUNT_HW_CACHE_MAX] 1211 [PERF_COUNT_HW_CACHE_OP_MAX] 1212 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1213 1214 u64 x86_perf_event_update(struct perf_event *event); 1215 1216 static inline u64 intel_pmu_topdown_event_update(struct perf_event *event, u64 *val) 1217 { 1218 return x86_perf_event_update(event); 1219 } 1220 DECLARE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 1221 1222 static inline unsigned int x86_pmu_config_addr(int index) 1223 { 1224 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1225 x86_pmu.addr_offset(index, true) : index); 1226 } 1227 1228 static inline unsigned int x86_pmu_event_addr(int index) 1229 { 1230 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1231 x86_pmu.addr_offset(index, false) : index); 1232 } 1233 1234 static inline unsigned int x86_pmu_fixed_ctr_addr(int index) 1235 { 1236 return x86_pmu.fixedctr + (x86_pmu.addr_offset ? 1237 x86_pmu.addr_offset(index, false) : index); 1238 } 1239 1240 static inline int x86_pmu_rdpmc_index(int index) 1241 { 1242 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1243 } 1244 1245 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask, 1246 unsigned long *fixed_cntr_mask); 1247 1248 int x86_add_exclusive(unsigned int what); 1249 1250 void x86_del_exclusive(unsigned int what); 1251 1252 int x86_reserve_hardware(void); 1253 1254 void x86_release_hardware(void); 1255 1256 int x86_pmu_max_precise(struct pmu *pmu); 1257 1258 void hw_perf_lbr_event_destroy(struct perf_event *event); 1259 1260 int x86_setup_perfctr(struct perf_event *event); 1261 1262 int x86_pmu_hw_config(struct perf_event *event); 1263 1264 void x86_pmu_disable_all(void); 1265 1266 static inline bool has_amd_brs(struct hw_perf_event *hwc) 1267 { 1268 return hwc->flags & PERF_X86_EVENT_AMD_BRS; 1269 } 1270 1271 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1272 { 1273 return hwc->flags & PERF_X86_EVENT_PAIR; 1274 } 1275 1276 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1277 u64 enable_mask) 1278 { 1279 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1280 1281 if (hwc->extra_reg.reg) 1282 wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); 1283 1284 /* 1285 * Add enabled Merge event on next counter 1286 * if large increment event being enabled on this counter 1287 */ 1288 if (is_counter_pair(hwc)) 1289 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1290 1291 wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1292 } 1293 1294 void x86_pmu_enable_all(int added); 1295 1296 int perf_assign_events(struct event_constraint **constraints, int n, 1297 int wmin, int wmax, int gpmax, int *assign); 1298 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1299 1300 void x86_pmu_stop(struct perf_event *event, int flags); 1301 1302 static inline void x86_pmu_disable_event(struct perf_event *event) 1303 { 1304 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1305 struct hw_perf_event *hwc = &event->hw; 1306 1307 wrmsrq(hwc->config_base, hwc->config & ~disable_mask); 1308 1309 if (is_counter_pair(hwc)) 1310 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0); 1311 } 1312 1313 void x86_pmu_enable_event(struct perf_event *event); 1314 1315 int x86_pmu_handle_irq(struct pt_regs *regs); 1316 1317 void x86_pmu_show_pmu_cap(struct pmu *pmu); 1318 1319 static inline int x86_pmu_num_counters(struct pmu *pmu) 1320 { 1321 return hweight64(hybrid(pmu, cntr_mask64)); 1322 } 1323 1324 static inline int x86_pmu_max_num_counters(struct pmu *pmu) 1325 { 1326 return fls64(hybrid(pmu, cntr_mask64)); 1327 } 1328 1329 static inline int x86_pmu_num_counters_fixed(struct pmu *pmu) 1330 { 1331 return hweight64(hybrid(pmu, fixed_cntr_mask64)); 1332 } 1333 1334 static inline int x86_pmu_max_num_counters_fixed(struct pmu *pmu) 1335 { 1336 return fls64(hybrid(pmu, fixed_cntr_mask64)); 1337 } 1338 1339 static inline u64 x86_pmu_get_event_config(struct perf_event *event) 1340 { 1341 return event->attr.config & hybrid(event->pmu, config_mask); 1342 } 1343 1344 static inline bool x86_pmu_has_rdpmc_user_disable(struct pmu *pmu) 1345 { 1346 return !!(hybrid(pmu, config_mask) & 1347 ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE); 1348 } 1349 1350 extern struct event_constraint emptyconstraint; 1351 1352 extern struct event_constraint unconstrained; 1353 1354 static inline bool kernel_ip(unsigned long ip) 1355 { 1356 #ifdef CONFIG_X86_32 1357 return ip > PAGE_OFFSET; 1358 #else 1359 return (long)ip < 0; 1360 #endif 1361 } 1362 1363 /* 1364 * Not all PMUs provide the right context information to place the reported IP 1365 * into full context. Specifically segment registers are typically not 1366 * supplied. 1367 * 1368 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1369 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1370 * to reflect this. 1371 * 1372 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1373 * much we can do about that but pray and treat it like a linear address. 1374 */ 1375 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1376 { 1377 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1378 if (regs->flags & X86_VM_MASK) 1379 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1380 regs->ip = ip; 1381 } 1382 1383 /* 1384 * x86control flow change classification 1385 * x86control flow changes include branches, interrupts, traps, faults 1386 */ 1387 enum { 1388 X86_BR_NONE = 0, /* unknown */ 1389 1390 X86_BR_USER = 1 << 0, /* branch target is user */ 1391 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ 1392 1393 X86_BR_CALL = 1 << 2, /* call */ 1394 X86_BR_RET = 1 << 3, /* return */ 1395 X86_BR_SYSCALL = 1 << 4, /* syscall */ 1396 X86_BR_SYSRET = 1 << 5, /* syscall return */ 1397 X86_BR_INT = 1 << 6, /* sw interrupt */ 1398 X86_BR_IRET = 1 << 7, /* return from interrupt */ 1399 X86_BR_JCC = 1 << 8, /* conditional */ 1400 X86_BR_JMP = 1 << 9, /* jump */ 1401 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ 1402 X86_BR_IND_CALL = 1 << 11,/* indirect calls */ 1403 X86_BR_ABORT = 1 << 12,/* transaction abort */ 1404 X86_BR_IN_TX = 1 << 13,/* in transaction */ 1405 X86_BR_NO_TX = 1 << 14,/* not in transaction */ 1406 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ 1407 X86_BR_CALL_STACK = 1 << 16,/* call stack */ 1408 X86_BR_IND_JMP = 1 << 17,/* indirect jump */ 1409 1410 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */ 1411 1412 }; 1413 1414 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) 1415 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) 1416 1417 #define X86_BR_ANY \ 1418 (X86_BR_CALL |\ 1419 X86_BR_RET |\ 1420 X86_BR_SYSCALL |\ 1421 X86_BR_SYSRET |\ 1422 X86_BR_INT |\ 1423 X86_BR_IRET |\ 1424 X86_BR_JCC |\ 1425 X86_BR_JMP |\ 1426 X86_BR_IRQ |\ 1427 X86_BR_ABORT |\ 1428 X86_BR_IND_CALL |\ 1429 X86_BR_IND_JMP |\ 1430 X86_BR_ZERO_CALL) 1431 1432 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) 1433 1434 #define X86_BR_ANY_CALL \ 1435 (X86_BR_CALL |\ 1436 X86_BR_IND_CALL |\ 1437 X86_BR_ZERO_CALL |\ 1438 X86_BR_SYSCALL |\ 1439 X86_BR_IRQ |\ 1440 X86_BR_INT) 1441 1442 int common_branch_type(int type); 1443 int branch_type(unsigned long from, unsigned long to, int abort); 1444 int branch_type_fused(unsigned long from, unsigned long to, int abort, 1445 int *offset); 1446 1447 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1448 ssize_t intel_event_sysfs_show(char *page, u64 config); 1449 1450 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1451 char *page); 1452 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1453 char *page); 1454 ssize_t events_hybrid_sysfs_show(struct device *dev, 1455 struct device_attribute *attr, 1456 char *page); 1457 1458 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1459 { 1460 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1461 1462 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1463 } 1464 1465 #ifdef CONFIG_CPU_SUP_AMD 1466 1467 int amd_pmu_init(void); 1468 1469 int amd_pmu_lbr_init(void); 1470 void amd_pmu_lbr_reset(void); 1471 void amd_pmu_lbr_read(void); 1472 void amd_pmu_lbr_add(struct perf_event *event); 1473 void amd_pmu_lbr_del(struct perf_event *event); 1474 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, 1475 struct task_struct *task, bool sched_in); 1476 void amd_pmu_lbr_enable_all(void); 1477 void amd_pmu_lbr_disable_all(void); 1478 int amd_pmu_lbr_hw_config(struct perf_event *event); 1479 1480 static __always_inline void __amd_pmu_lbr_disable(void) 1481 { 1482 u64 dbg_ctl, dbg_extn_cfg; 1483 1484 rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 1485 wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); 1486 1487 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { 1488 rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 1489 wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1490 } 1491 } 1492 1493 #ifdef CONFIG_PERF_EVENTS_AMD_BRS 1494 1495 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */ 1496 1497 int amd_brs_init(void); 1498 void amd_brs_disable(void); 1499 void amd_brs_enable(void); 1500 void amd_brs_enable_all(void); 1501 void amd_brs_disable_all(void); 1502 void amd_brs_drain(void); 1503 void amd_brs_lopwr_init(void); 1504 int amd_brs_hw_config(struct perf_event *event); 1505 void amd_brs_reset(void); 1506 1507 static inline void amd_pmu_brs_add(struct perf_event *event) 1508 { 1509 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1510 1511 perf_sched_cb_inc(event->pmu); 1512 cpuc->lbr_users++; 1513 /* 1514 * No need to reset BRS because it is reset 1515 * on brs_enable() and it is saturating 1516 */ 1517 } 1518 1519 static inline void amd_pmu_brs_del(struct perf_event *event) 1520 { 1521 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1522 1523 cpuc->lbr_users--; 1524 WARN_ON_ONCE(cpuc->lbr_users < 0); 1525 1526 perf_sched_cb_dec(event->pmu); 1527 } 1528 1529 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, 1530 struct task_struct *task, bool sched_in); 1531 #else 1532 static inline int amd_brs_init(void) 1533 { 1534 return 0; 1535 } 1536 static inline void amd_brs_disable(void) {} 1537 static inline void amd_brs_enable(void) {} 1538 static inline void amd_brs_drain(void) {} 1539 static inline void amd_brs_lopwr_init(void) {} 1540 static inline void amd_brs_disable_all(void) {} 1541 static inline int amd_brs_hw_config(struct perf_event *event) 1542 { 1543 return 0; 1544 } 1545 static inline void amd_brs_reset(void) {} 1546 1547 static inline void amd_pmu_brs_add(struct perf_event *event) 1548 { 1549 } 1550 1551 static inline void amd_pmu_brs_del(struct perf_event *event) 1552 { 1553 } 1554 1555 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, 1556 struct task_struct *task, bool sched_in) 1557 { 1558 } 1559 1560 static inline void amd_brs_enable_all(void) 1561 { 1562 } 1563 1564 #endif 1565 1566 #else /* CONFIG_CPU_SUP_AMD */ 1567 1568 static inline int amd_pmu_init(void) 1569 { 1570 return 0; 1571 } 1572 1573 static inline int amd_brs_init(void) 1574 { 1575 return -EOPNOTSUPP; 1576 } 1577 1578 static inline void amd_brs_drain(void) 1579 { 1580 } 1581 1582 static inline void amd_brs_enable_all(void) 1583 { 1584 } 1585 1586 static inline void amd_brs_disable_all(void) 1587 { 1588 } 1589 #endif /* CONFIG_CPU_SUP_AMD */ 1590 1591 static inline int is_pebs_pt(struct perf_event *event) 1592 { 1593 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1594 } 1595 1596 #ifdef CONFIG_CPU_SUP_INTEL 1597 1598 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1599 { 1600 struct hw_perf_event *hwc = &event->hw; 1601 unsigned int hw_event, bts_event; 1602 1603 /* 1604 * Only use BTS for fixed rate period==1 events. 1605 */ 1606 if (event->attr.freq || period != 1) 1607 return false; 1608 1609 /* 1610 * BTS doesn't virtualize. 1611 */ 1612 if (event->attr.exclude_host) 1613 return false; 1614 1615 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1616 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1617 1618 return hw_event == bts_event; 1619 } 1620 1621 static inline bool intel_pmu_has_bts(struct perf_event *event) 1622 { 1623 struct hw_perf_event *hwc = &event->hw; 1624 1625 return intel_pmu_has_bts_period(event, hwc->sample_period); 1626 } 1627 1628 static __always_inline void __intel_pmu_pebs_disable_all(void) 1629 { 1630 wrmsrq(MSR_IA32_PEBS_ENABLE, 0); 1631 } 1632 1633 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1634 { 1635 wrmsrq(MSR_ARCH_LBR_CTL, 0); 1636 } 1637 1638 static __always_inline void __intel_pmu_lbr_disable(void) 1639 { 1640 u64 debugctl; 1641 1642 rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1643 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1644 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1645 } 1646 1647 int intel_pmu_save_and_restart(struct perf_event *event); 1648 1649 struct event_constraint * 1650 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1651 struct perf_event *event); 1652 1653 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1654 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1655 1656 int intel_pmu_init(void); 1657 1658 int alloc_arch_pebs_buf_on_cpu(int cpu); 1659 1660 void release_arch_pebs_buf_on_cpu(int cpu); 1661 1662 void init_arch_pebs_on_cpu(int cpu); 1663 1664 void fini_arch_pebs_on_cpu(int cpu); 1665 1666 void init_debug_store_on_cpu(int cpu); 1667 1668 void fini_debug_store_on_cpu(int cpu); 1669 1670 void release_ds_buffers(void); 1671 1672 void reserve_ds_buffers(void); 1673 1674 void release_lbr_buffers(void); 1675 1676 void reserve_lbr_buffers(void); 1677 1678 extern struct event_constraint bts_constraint; 1679 extern struct event_constraint vlbr_constraint; 1680 1681 void intel_pmu_enable_bts(u64 config); 1682 1683 void intel_pmu_disable_bts(void); 1684 1685 int intel_pmu_drain_bts_buffer(void); 1686 1687 void intel_pmu_late_setup(void); 1688 1689 u64 grt_latency_data(struct perf_event *event, u64 status); 1690 1691 u64 cmt_latency_data(struct perf_event *event, u64 status); 1692 1693 u64 lnl_latency_data(struct perf_event *event, u64 status); 1694 1695 u64 arl_h_latency_data(struct perf_event *event, u64 status); 1696 1697 u64 pnc_latency_data(struct perf_event *event, u64 status); 1698 1699 u64 nvl_latency_data(struct perf_event *event, u64 status); 1700 1701 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1702 1703 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1704 1705 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1706 1707 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1708 1709 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1710 1711 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1712 1713 extern struct event_constraint intel_cmt_pebs_event_constraints[]; 1714 1715 extern struct event_constraint intel_dkt_pebs_event_constraints[]; 1716 1717 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1718 1719 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1720 1721 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1722 1723 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1724 1725 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1726 1727 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1728 1729 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1730 1731 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1732 1733 extern struct event_constraint intel_glc_pebs_event_constraints[]; 1734 1735 extern struct event_constraint intel_lnc_pebs_event_constraints[]; 1736 1737 extern struct event_constraint intel_pnc_pebs_event_constraints[]; 1738 1739 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1740 1741 void intel_pmu_pebs_add(struct perf_event *event); 1742 1743 void intel_pmu_pebs_del(struct perf_event *event); 1744 1745 void intel_pmu_pebs_enable(struct perf_event *event); 1746 1747 void intel_pmu_pebs_disable(struct perf_event *event); 1748 1749 void intel_pmu_pebs_enable_all(void); 1750 1751 void intel_pmu_pebs_disable_all(void); 1752 1753 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1754 1755 void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc); 1756 1757 void intel_pmu_drain_pebs_buffer(void); 1758 1759 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1760 1761 void intel_pebs_init(void); 1762 1763 void intel_pmu_lbr_save_brstack(struct perf_sample_data *data, 1764 struct cpu_hw_events *cpuc, 1765 struct perf_event *event); 1766 1767 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, 1768 struct task_struct *task, bool sched_in); 1769 1770 u64 lbr_from_signext_quirk_wr(u64 val); 1771 1772 void intel_pmu_lbr_reset(void); 1773 1774 void intel_pmu_lbr_reset_32(void); 1775 1776 void intel_pmu_lbr_reset_64(void); 1777 1778 void intel_pmu_lbr_add(struct perf_event *event); 1779 1780 void intel_pmu_lbr_del(struct perf_event *event); 1781 1782 void intel_pmu_lbr_enable_all(bool pmi); 1783 1784 void intel_pmu_lbr_disable_all(void); 1785 1786 void intel_pmu_lbr_read(void); 1787 1788 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1789 1790 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1791 1792 void intel_pmu_lbr_save(void *ctx); 1793 1794 void intel_pmu_lbr_restore(void *ctx); 1795 1796 void intel_pmu_lbr_init_core(void); 1797 1798 void intel_pmu_lbr_init_nhm(void); 1799 1800 void intel_pmu_lbr_init_atom(void); 1801 1802 void intel_pmu_lbr_init_slm(void); 1803 1804 void intel_pmu_lbr_init_snb(void); 1805 1806 void intel_pmu_lbr_init_hsw(void); 1807 1808 void intel_pmu_lbr_init_skl(void); 1809 1810 void intel_pmu_lbr_init_knl(void); 1811 1812 void intel_pmu_lbr_init(void); 1813 1814 void intel_pmu_arch_lbr_init(void); 1815 1816 void intel_pmu_pebs_data_source_nhm(void); 1817 1818 void intel_pmu_pebs_data_source_skl(bool pmem); 1819 1820 void intel_pmu_pebs_data_source_adl(void); 1821 1822 void intel_pmu_pebs_data_source_grt(void); 1823 1824 void intel_pmu_pebs_data_source_mtl(void); 1825 1826 void intel_pmu_pebs_data_source_arl_h(void); 1827 1828 void intel_pmu_pebs_data_source_cmt(void); 1829 1830 void intel_pmu_pebs_data_source_lnl(void); 1831 1832 u64 intel_get_arch_pebs_data_config(struct perf_event *event); 1833 1834 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1835 1836 void intel_pt_interrupt(void); 1837 1838 int intel_bts_interrupt(void); 1839 1840 void intel_bts_enable_local(void); 1841 1842 void intel_bts_disable_local(void); 1843 1844 int p4_pmu_init(void); 1845 1846 int p6_pmu_init(void); 1847 1848 int knc_pmu_init(void); 1849 1850 static inline int is_ht_workaround_enabled(void) 1851 { 1852 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1853 } 1854 1855 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) 1856 { 1857 return MAX_PEBS_EVENTS_MASK & cntr_mask; 1858 } 1859 1860 static inline int intel_pmu_max_num_pebs(struct pmu *pmu) 1861 { 1862 static_assert(MAX_PEBS_EVENTS == 32); 1863 return fls((u32)hybrid(pmu, pebs_events_mask)); 1864 } 1865 1866 static inline bool intel_pmu_has_pebs(void) 1867 { 1868 return x86_pmu.ds_pebs || x86_pmu.arch_pebs; 1869 } 1870 1871 #else /* CONFIG_CPU_SUP_INTEL */ 1872 1873 static inline void reserve_ds_buffers(void) 1874 { 1875 } 1876 1877 static inline void release_ds_buffers(void) 1878 { 1879 } 1880 1881 static inline void release_lbr_buffers(void) 1882 { 1883 } 1884 1885 static inline void reserve_lbr_buffers(void) 1886 { 1887 } 1888 1889 static inline int intel_pmu_init(void) 1890 { 1891 return 0; 1892 } 1893 1894 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1895 { 1896 return 0; 1897 } 1898 1899 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1900 { 1901 } 1902 1903 static inline int is_ht_workaround_enabled(void) 1904 { 1905 return 0; 1906 } 1907 #endif /* CONFIG_CPU_SUP_INTEL */ 1908 1909 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1910 int zhaoxin_pmu_init(void); 1911 #else 1912 static inline int zhaoxin_pmu_init(void) 1913 { 1914 return 0; 1915 } 1916 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1917