1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2015, 2016 ARM Ltd.
4 */
5 #ifndef __KVM_ARM_VGIC_H
6 #define __KVM_ARM_VGIC_H
7
8 #include <linux/bits.h>
9 #include <linux/kvm.h>
10 #include <linux/irqreturn.h>
11 #include <linux/kref.h>
12 #include <linux/mutex.h>
13 #include <linux/spinlock.h>
14 #include <linux/static_key.h>
15 #include <linux/types.h>
16 #include <linux/xarray.h>
17 #include <kvm/iodev.h>
18 #include <linux/list.h>
19 #include <linux/jump_label.h>
20
21 #include <linux/irqchip/arm-gic-v4.h>
22
23 #define VGIC_V3_MAX_CPUS 512
24 #define VGIC_V2_MAX_CPUS 8
25 #define VGIC_NR_IRQS_LEGACY 256
26 #define VGIC_NR_SGIS 16
27 #define VGIC_NR_PPIS 16
28 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
29 #define VGIC_MAX_SPI 1019
30 #define VGIC_MAX_RESERVED 1023
31 #define VGIC_MIN_LPI 8192
32 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
33
34 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
35 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
36 (irq) <= VGIC_MAX_SPI)
37
38 enum vgic_type {
39 VGIC_V2, /* Good ol' GICv2 */
40 VGIC_V3, /* New fancy GICv3 */
41 VGIC_V5, /* Newer, fancier GICv5 */
42 };
43
44 /* same for all guests, as depending only on the _host's_ GIC model */
45 struct vgic_global {
46 /* type of the host GIC */
47 enum vgic_type type;
48
49 /* Physical address of vgic virtual cpu interface */
50 phys_addr_t vcpu_base;
51
52 /* GICV mapping, kernel VA */
53 void __iomem *vcpu_base_va;
54 /* GICV mapping, HYP VA */
55 void __iomem *vcpu_hyp_va;
56
57 /* virtual control interface mapping, kernel VA */
58 void __iomem *vctrl_base;
59 /* virtual control interface mapping, HYP VA */
60 void __iomem *vctrl_hyp;
61
62 /* Number of implemented list registers */
63 int nr_lr;
64
65 /* Maintenance IRQ number */
66 unsigned int maint_irq;
67
68 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
69 int max_gic_vcpus;
70
71 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
72 bool can_emulate_gicv2;
73
74 /* Hardware has GICv4? */
75 bool has_gicv4;
76 bool has_gicv4_1;
77
78 /* Pseudo GICv3 from outer space */
79 bool no_hw_deactivation;
80
81 /* GICv3 system register CPU interface */
82 struct static_key_false gicv3_cpuif;
83
84 /* GICv3 compat mode on a GICv5 host */
85 bool has_gcie_v3_compat;
86
87 u32 ich_vtr_el2;
88 };
89
90 extern struct vgic_global kvm_vgic_global_state;
91
92 #define VGIC_V2_MAX_LRS (1 << 6)
93 #define VGIC_V3_MAX_LRS 16
94 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
95
96 enum vgic_irq_config {
97 VGIC_CONFIG_EDGE = 0,
98 VGIC_CONFIG_LEVEL
99 };
100
101 /*
102 * Per-irq ops overriding some common behavious.
103 *
104 * Always called in non-preemptible section and the functions can use
105 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private IRQs.
106 */
107 struct irq_ops {
108 /* Per interrupt flags for special-cased interrupts */
109 unsigned long flags;
110
111 #define VGIC_IRQ_SW_RESAMPLE BIT(0) /* Clear the active state for resampling */
112
113 /*
114 * Callback function pointer to in-kernel devices that can tell us the
115 * state of the input level of mapped level-triggered IRQ faster than
116 * peaking into the physical GIC.
117 */
118 bool (*get_input_level)(int vintid);
119 };
120
121 struct vgic_irq {
122 raw_spinlock_t irq_lock; /* Protects the content of the struct */
123 struct rcu_head rcu;
124 struct list_head ap_list;
125
126 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
127 * SPIs and LPIs: The VCPU whose ap_list
128 * this is queued on.
129 */
130
131 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
132 * be sent to, as a result of the
133 * targets reg (v2) or the
134 * affinity reg (v3).
135 */
136
137 u32 intid; /* Guest visible INTID */
138 bool line_level; /* Level only */
139 bool pending_latch; /* The pending latch state used to calculate
140 * the pending state for both level
141 * and edge triggered IRQs. */
142 bool active; /* not used for LPIs */
143 bool enabled;
144 bool hw; /* Tied to HW IRQ */
145 struct kref refcount; /* Used for LPIs */
146 u32 hwintid; /* HW INTID number */
147 unsigned int host_irq; /* linux irq corresponding to hwintid */
148 union {
149 u8 targets; /* GICv2 target VCPUs mask */
150 u32 mpidr; /* GICv3 target VCPU */
151 };
152 u8 source; /* GICv2 SGIs only */
153 u8 active_source; /* GICv2 SGIs only */
154 u8 priority;
155 u8 group; /* 0 == group 0, 1 == group 1 */
156 enum vgic_irq_config config; /* Level or edge */
157
158 struct irq_ops *ops;
159
160 void *owner; /* Opaque pointer to reserve an interrupt
161 for in-kernel devices. */
162 };
163
vgic_irq_needs_resampling(struct vgic_irq * irq)164 static inline bool vgic_irq_needs_resampling(struct vgic_irq *irq)
165 {
166 return irq->ops && (irq->ops->flags & VGIC_IRQ_SW_RESAMPLE);
167 }
168
169 struct vgic_register_region;
170 struct vgic_its;
171
172 enum iodev_type {
173 IODEV_CPUIF,
174 IODEV_DIST,
175 IODEV_REDIST,
176 IODEV_ITS
177 };
178
179 struct vgic_io_device {
180 gpa_t base_addr;
181 union {
182 struct kvm_vcpu *redist_vcpu;
183 struct vgic_its *its;
184 };
185 const struct vgic_register_region *regions;
186 enum iodev_type iodev_type;
187 int nr_regions;
188 struct kvm_io_device dev;
189 };
190
191 struct vgic_its {
192 /* The base address of the ITS control register frame */
193 gpa_t vgic_its_base;
194
195 bool enabled;
196 struct vgic_io_device iodev;
197 struct kvm_device *dev;
198
199 /* These registers correspond to GITS_BASER{0,1} */
200 u64 baser_device_table;
201 u64 baser_coll_table;
202
203 /* Protects the command queue */
204 struct mutex cmd_lock;
205 u64 cbaser;
206 u32 creadr;
207 u32 cwriter;
208
209 /* migration ABI revision in use */
210 u32 abi_rev;
211
212 /* Protects the device and collection lists */
213 struct mutex its_lock;
214 struct list_head device_list;
215 struct list_head collection_list;
216
217 /*
218 * Caches the (device_id, event_id) -> vgic_irq translation for
219 * LPIs that are mapped and enabled.
220 */
221 struct xarray translation_cache;
222 };
223
224 struct vgic_state_iter;
225
226 struct vgic_redist_region {
227 u32 index;
228 gpa_t base;
229 u32 count; /* number of redistributors or 0 if single region */
230 u32 free_index; /* index of the next free redistributor */
231 struct list_head list;
232 };
233
234 struct vgic_dist {
235 bool in_kernel;
236 bool ready;
237 bool initialized;
238
239 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
240 u32 vgic_model;
241
242 /* Implementation revision as reported in the GICD_IIDR */
243 u32 implementation_rev;
244 #define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */
245 #define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */
246 #define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3
247
248 /* Userspace can write to GICv2 IGROUPR */
249 bool v2_groups_user_writable;
250
251 /* Do injected MSIs require an additional device ID? */
252 bool msis_require_devid;
253
254 int nr_spis;
255
256 /* The GIC maintenance IRQ for nested hypervisors. */
257 u32 mi_intid;
258
259 /* base addresses in guest physical address space: */
260 gpa_t vgic_dist_base; /* distributor */
261 union {
262 /* either a GICv2 CPU interface */
263 gpa_t vgic_cpu_base;
264 /* or a number of GICv3 redistributor regions */
265 struct list_head rd_regions;
266 };
267
268 /* distributor enabled */
269 bool enabled;
270
271 /* Supports SGIs without active state */
272 bool nassgicap;
273
274 /* Wants SGIs without active state */
275 bool nassgireq;
276
277 struct vgic_irq *spis;
278
279 struct vgic_io_device dist_iodev;
280
281 bool has_its;
282 bool table_write_in_progress;
283
284 /*
285 * Contains the attributes and gpa of the LPI configuration table.
286 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
287 * one address across all redistributors.
288 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
289 */
290 u64 propbaser;
291
292 #define LPI_XA_MARK_DEBUG_ITER XA_MARK_0
293 struct xarray lpi_xa;
294
295 /* used by vgic-debug */
296 struct vgic_state_iter *iter;
297
298 /*
299 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
300 * array, the property table pointer as well as allocation
301 * data. This essentially ties the Linux IRQ core and ITS
302 * together, and avoids leaking KVM's data structures anywhere
303 * else.
304 */
305 struct its_vm its_vm;
306 };
307
308 struct vgic_v2_cpu_if {
309 u32 vgic_hcr;
310 u32 vgic_vmcr;
311 u32 vgic_apr;
312 u32 vgic_lr[VGIC_V2_MAX_LRS];
313
314 unsigned int used_lrs;
315 };
316
317 struct vgic_v3_cpu_if {
318 u32 vgic_hcr;
319 u32 vgic_vmcr;
320 u32 vgic_sre; /* Restored only, change ignored */
321 u32 vgic_ap0r[4];
322 u32 vgic_ap1r[4];
323 u64 vgic_lr[VGIC_V3_MAX_LRS];
324
325 /*
326 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
327 * pending table pointer, the its_vm pointer and a few other
328 * HW specific things. As for the its_vm structure, this is
329 * linking the Linux IRQ subsystem and the ITS together.
330 */
331 struct its_vpe its_vpe;
332
333 unsigned int used_lrs;
334 };
335
336 struct vgic_cpu {
337 /* CPU vif control registers for world switch */
338 union {
339 struct vgic_v2_cpu_if vgic_v2;
340 struct vgic_v3_cpu_if vgic_v3;
341 };
342
343 struct vgic_irq *private_irqs;
344
345 raw_spinlock_t ap_list_lock; /* Protects the ap_list */
346
347 /*
348 * List of IRQs that this VCPU should consider because they are either
349 * Active or Pending (hence the name; AP list), or because they recently
350 * were one of the two and need to be migrated off this list to another
351 * VCPU.
352 */
353 struct list_head ap_list_head;
354
355 /*
356 * Members below are used with GICv3 emulation only and represent
357 * parts of the redistributor.
358 */
359 struct vgic_io_device rd_iodev;
360 struct vgic_redist_region *rdreg;
361 u32 rdreg_index;
362 atomic_t syncr_busy;
363
364 /* Contains the attributes and gpa of the LPI pending tables. */
365 u64 pendbaser;
366 /* GICR_CTLR.{ENABLE_LPIS,RWP} */
367 atomic_t ctlr;
368
369 /* Cache guest priority bits */
370 u32 num_pri_bits;
371
372 /* Cache guest interrupt ID bits */
373 u32 num_id_bits;
374 };
375
376 extern struct static_key_false vgic_v2_cpuif_trap;
377 extern struct static_key_false vgic_v3_cpuif_trap;
378
379 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr);
380 void kvm_vgic_early_init(struct kvm *kvm);
381 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
382 int kvm_vgic_vcpu_nv_init(struct kvm_vcpu *vcpu);
383 int kvm_vgic_create(struct kvm *kvm, u32 type);
384 void kvm_vgic_destroy(struct kvm *kvm);
385 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
386 int kvm_vgic_map_resources(struct kvm *kvm);
387 int kvm_vgic_hyp_init(void);
388 void kvm_vgic_init_cpu_hardware(void);
389
390 int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
391 unsigned int intid, bool level, void *owner);
392 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
393 u32 vintid, struct irq_ops *ops);
394 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
395 int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid);
396 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
397
398 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
399
400 void kvm_vgic_load(struct kvm_vcpu *vcpu);
401 void kvm_vgic_put(struct kvm_vcpu *vcpu);
402
403 u16 vgic_v3_get_eisr(struct kvm_vcpu *vcpu);
404 u16 vgic_v3_get_elrsr(struct kvm_vcpu *vcpu);
405 u64 vgic_v3_get_misr(struct kvm_vcpu *vcpu);
406
407 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
408 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
409 #define vgic_ready(k) ((k)->arch.vgic.ready)
410 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
411 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
412
413 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
414 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
415 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
416 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
417
418 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1);
419
420 /**
421 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
422 *
423 * The host's GIC naturally limits the maximum amount of VCPUs a guest
424 * can use.
425 */
kvm_vgic_get_max_vcpus(void)426 static inline int kvm_vgic_get_max_vcpus(void)
427 {
428 return kvm_vgic_global_state.max_gic_vcpus;
429 }
430
431 /**
432 * kvm_vgic_setup_default_irq_routing:
433 * Setup a default flat gsi routing table mapping all SPIs
434 */
435 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
436
437 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
438
439 struct kvm_kernel_irq_routing_entry;
440
441 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
442 struct kvm_kernel_irq_routing_entry *irq_entry);
443
444 void kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int host_irq);
445
446 int vgic_v4_load(struct kvm_vcpu *vcpu);
447 void vgic_v4_commit(struct kvm_vcpu *vcpu);
448 int vgic_v4_put(struct kvm_vcpu *vcpu);
449
450 bool vgic_state_is_nested(struct kvm_vcpu *vcpu);
451
452 /* CPU HP callbacks */
453 void kvm_vgic_cpu_up(void);
454 void kvm_vgic_cpu_down(void);
455
456 #endif /* __KVM_ARM_VGIC_H */
457