1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Check for KVM_GET_REG_LIST regressions. 4 * 5 * Copyright (c) 2023 Intel Corporation 6 * 7 */ 8 #include <stdio.h> 9 #include "kvm_util.h" 10 #include "test_util.h" 11 #include "processor.h" 12 13 #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK) 14 15 enum { 16 VCPU_FEATURE_ISA_EXT = 0, 17 VCPU_FEATURE_SBI_EXT, 18 }; 19 20 enum { 21 KVM_RISC_V_REG_OFFSET_VSTART = 0, 22 KVM_RISC_V_REG_OFFSET_VL, 23 KVM_RISC_V_REG_OFFSET_VTYPE, 24 KVM_RISC_V_REG_OFFSET_VCSR, 25 KVM_RISC_V_REG_OFFSET_VLENB, 26 KVM_RISC_V_REG_OFFSET_MAX, 27 }; 28 29 static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; 30 static bool sbi_ext_enabled[KVM_RISCV_SBI_EXT_MAX]; 31 32 bool filter_reg(__u64 reg) 33 { 34 switch (reg & ~REG_MASK) { 35 /* 36 * Same set of ISA_EXT registers are not present on all host because 37 * ISA_EXT registers are visible to the KVM user space based on the 38 * ISA extensions available on the host. Also, disabling an ISA 39 * extension using corresponding ISA_EXT register does not affect 40 * the visibility of the ISA_EXT register itself. 41 * 42 * Based on above, we should filter-out all ISA_EXT registers. 43 * 44 * Note: The below list is alphabetically sorted. 45 */ 46 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_A: 47 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_C: 48 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D: 49 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F: 50 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_H: 51 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I: 52 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M: 53 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V: 54 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMNPM: 55 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: 56 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: 57 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF: 58 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM: 59 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: 60 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE: 61 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: 62 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: 63 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: 64 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: 65 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC: 66 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO: 67 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA: 68 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS: 69 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALASR: 70 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC: 71 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS: 72 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA: 73 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB: 74 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC: 75 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB: 76 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: 77 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: 78 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS: 79 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA: 80 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: 81 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: 82 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: 83 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCLSD: 84 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: 85 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: 86 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN: 87 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: 88 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: 89 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM: 90 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP: 91 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ: 92 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE: 93 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR: 94 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND: 95 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR: 96 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI: 97 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL: 98 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: 99 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM: 100 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZILSD: 101 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP: 102 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND: 103 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE: 104 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH: 105 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR: 106 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED: 107 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH: 108 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT: 109 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO: 110 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB: 111 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC: 112 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN: 113 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA: 114 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH: 115 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN: 116 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB: 117 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG: 118 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED: 119 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA: 120 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB: 121 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED: 122 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH: 123 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT: 124 /* 125 * Like ISA_EXT registers, SBI_EXT registers are only visible when the 126 * host supports them and disabling them does not affect the visibility 127 * of the SBI_EXT register itself. 128 */ 129 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01: 130 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME: 131 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI: 132 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE: 133 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST: 134 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM: 135 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU: 136 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN: 137 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SUSP: 138 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA: 139 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT: 140 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_MPXY: 141 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL: 142 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR: 143 return true; 144 /* AIA registers are always available when Ssaia can't be disabled */ 145 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): 146 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): 147 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): 148 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): 149 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): 150 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): 151 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): 152 return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA]; 153 /* 154 * FWFT misaligned delegation registers are always visible when the SBI FWFT 155 * extension is enable and the host supports the misaligned delegation. 156 */ 157 case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable): 158 case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags): 159 case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value): 160 return sbi_ext_enabled[KVM_RISCV_SBI_EXT_FWFT]; 161 default: 162 break; 163 } 164 165 return false; 166 } 167 168 bool check_reject_set(int err) 169 { 170 return err == EINVAL; 171 } 172 173 static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s, 174 u64 feature) 175 { 176 unsigned long vlenb_reg = 0; 177 int rc; 178 u64 reg, size; 179 180 /* Enable V extension so that we can get the vlenb register */ 181 rc = __vcpu_set_reg(vcpu, feature, 1); 182 if (rc) 183 return rc; 184 185 vlenb_reg = vcpu_get_reg(vcpu, s->regs[KVM_RISC_V_REG_OFFSET_VLENB]); 186 if (!vlenb_reg) { 187 TEST_FAIL("Can't compute vector register size from zero vlenb\n"); 188 return -EPERM; 189 } 190 191 size = __builtin_ctzl(vlenb_reg); 192 size <<= KVM_REG_SIZE_SHIFT; 193 194 for (int i = 0; i < 32; i++) { 195 reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size | KVM_REG_RISCV_VECTOR_REG(i); 196 s->regs[KVM_RISC_V_REG_OFFSET_MAX + i] = reg; 197 } 198 199 /* We should assert if disabling failed here while enabling succeeded before */ 200 vcpu_set_reg(vcpu, feature, 0); 201 202 return 0; 203 } 204 205 void check_fwft_feature(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s, u64 feature) 206 { 207 unsigned long value; 208 int rc; 209 210 /* Enable SBI FWFT extension so that we can check the supported register */ 211 rc = __vcpu_set_reg(vcpu, feature, 1); 212 if (rc) 213 return; 214 215 for (int i = 0; i < s->regs_n; i++) { 216 if ((s->regs[i] & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE) { 217 rc = __vcpu_get_reg(vcpu, s->regs[i], &value); 218 __TEST_REQUIRE(!rc, "%s not available, skipping tests", s->name); 219 } 220 } 221 222 /* We should assert if disabling failed here while enabling succeeded before */ 223 vcpu_set_reg(vcpu, feature, 0); 224 } 225 226 void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) 227 { 228 unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; 229 struct vcpu_reg_sublist *s; 230 u64 feature; 231 int rc; 232 233 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) 234 __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]); 235 236 /* 237 * Disable all extensions which were enabled by default 238 * if they were available in the risc-v host. 239 */ 240 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { 241 rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); 242 if (rc && isa_ext_state[i]) 243 isa_ext_cant_disable[i] = true; 244 } 245 246 for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { 247 rc = __vcpu_set_reg(vcpu, RISCV_SBI_EXT_REG(i), 0); 248 TEST_ASSERT(!rc || (rc == -1 && errno == ENOENT), "Unexpected error"); 249 } 250 251 for_each_sublist(c, s) { 252 if (!s->feature) 253 continue; 254 255 if (s->feature == KVM_RISCV_ISA_EXT_V) { 256 feature = RISCV_ISA_EXT_REG(s->feature); 257 rc = override_vector_reg_size(vcpu, s, feature); 258 if (rc) 259 goto skip; 260 } 261 262 switch (s->feature_type) { 263 case VCPU_FEATURE_ISA_EXT: 264 feature = RISCV_ISA_EXT_REG(s->feature); 265 break; 266 case VCPU_FEATURE_SBI_EXT: 267 feature = RISCV_SBI_EXT_REG(s->feature); 268 if (s->feature == KVM_RISCV_SBI_EXT_FWFT) 269 check_fwft_feature(vcpu, s, feature); 270 sbi_ext_enabled[s->feature] = true; 271 break; 272 default: 273 TEST_FAIL("Unknown feature type"); 274 } 275 276 /* Try to enable the desired extension */ 277 __vcpu_set_reg(vcpu, feature, 1); 278 279 skip: 280 /* Double check whether the desired extension was enabled */ 281 __TEST_REQUIRE(__vcpu_has_ext(vcpu, feature), 282 "%s not available, skipping tests", s->name); 283 } 284 } 285 286 static const char *config_id_to_str(const char *prefix, __u64 id) 287 { 288 /* reg_off is the offset into struct kvm_riscv_config */ 289 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); 290 291 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG); 292 293 switch (reg_off) { 294 case KVM_REG_RISCV_CONFIG_REG(isa): 295 return "KVM_REG_RISCV_CONFIG_REG(isa)"; 296 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): 297 return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)"; 298 case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): 299 return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)"; 300 case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size): 301 return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)"; 302 case KVM_REG_RISCV_CONFIG_REG(mvendorid): 303 return "KVM_REG_RISCV_CONFIG_REG(mvendorid)"; 304 case KVM_REG_RISCV_CONFIG_REG(marchid): 305 return "KVM_REG_RISCV_CONFIG_REG(marchid)"; 306 case KVM_REG_RISCV_CONFIG_REG(mimpid): 307 return "KVM_REG_RISCV_CONFIG_REG(mimpid)"; 308 case KVM_REG_RISCV_CONFIG_REG(satp_mode): 309 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)"; 310 } 311 312 return strdup_printf("%lld /* UNKNOWN */", reg_off); 313 } 314 315 static const char *core_id_to_str(const char *prefix, __u64 id) 316 { 317 /* reg_off is the offset into struct kvm_riscv_core */ 318 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); 319 320 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE); 321 322 switch (reg_off) { 323 case KVM_REG_RISCV_CORE_REG(regs.pc): 324 return "KVM_REG_RISCV_CORE_REG(regs.pc)"; 325 case KVM_REG_RISCV_CORE_REG(regs.ra): 326 return "KVM_REG_RISCV_CORE_REG(regs.ra)"; 327 case KVM_REG_RISCV_CORE_REG(regs.sp): 328 return "KVM_REG_RISCV_CORE_REG(regs.sp)"; 329 case KVM_REG_RISCV_CORE_REG(regs.gp): 330 return "KVM_REG_RISCV_CORE_REG(regs.gp)"; 331 case KVM_REG_RISCV_CORE_REG(regs.tp): 332 return "KVM_REG_RISCV_CORE_REG(regs.tp)"; 333 case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2): 334 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)", 335 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); 336 case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1): 337 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)", 338 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); 339 case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7): 340 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)", 341 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0)); 342 case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11): 343 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)", 344 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2); 345 case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6): 346 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)", 347 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3); 348 case KVM_REG_RISCV_CORE_REG(mode): 349 return "KVM_REG_RISCV_CORE_REG(mode)"; 350 } 351 352 return strdup_printf("%lld /* UNKNOWN */", reg_off); 353 } 354 355 #define RISCV_CSR_GENERAL(csr) \ 356 "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" 357 #define RISCV_CSR_AIA(csr) \ 358 "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" 359 #define RISCV_CSR_SMSTATEEN(csr) \ 360 "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" 361 362 static const char *general_csr_id_to_str(__u64 reg_off) 363 { 364 /* reg_off is the offset into struct kvm_riscv_csr */ 365 switch (reg_off) { 366 case KVM_REG_RISCV_CSR_REG(sstatus): 367 return RISCV_CSR_GENERAL(sstatus); 368 case KVM_REG_RISCV_CSR_REG(sie): 369 return RISCV_CSR_GENERAL(sie); 370 case KVM_REG_RISCV_CSR_REG(stvec): 371 return RISCV_CSR_GENERAL(stvec); 372 case KVM_REG_RISCV_CSR_REG(sscratch): 373 return RISCV_CSR_GENERAL(sscratch); 374 case KVM_REG_RISCV_CSR_REG(sepc): 375 return RISCV_CSR_GENERAL(sepc); 376 case KVM_REG_RISCV_CSR_REG(scause): 377 return RISCV_CSR_GENERAL(scause); 378 case KVM_REG_RISCV_CSR_REG(stval): 379 return RISCV_CSR_GENERAL(stval); 380 case KVM_REG_RISCV_CSR_REG(sip): 381 return RISCV_CSR_GENERAL(sip); 382 case KVM_REG_RISCV_CSR_REG(satp): 383 return RISCV_CSR_GENERAL(satp); 384 case KVM_REG_RISCV_CSR_REG(scounteren): 385 return RISCV_CSR_GENERAL(scounteren); 386 case KVM_REG_RISCV_CSR_REG(senvcfg): 387 return RISCV_CSR_GENERAL(senvcfg); 388 } 389 390 return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off); 391 } 392 393 static const char *aia_csr_id_to_str(__u64 reg_off) 394 { 395 /* reg_off is the offset into struct kvm_riscv_aia_csr */ 396 switch (reg_off) { 397 case KVM_REG_RISCV_CSR_AIA_REG(siselect): 398 return RISCV_CSR_AIA(siselect); 399 case KVM_REG_RISCV_CSR_AIA_REG(iprio1): 400 return RISCV_CSR_AIA(iprio1); 401 case KVM_REG_RISCV_CSR_AIA_REG(iprio2): 402 return RISCV_CSR_AIA(iprio2); 403 case KVM_REG_RISCV_CSR_AIA_REG(sieh): 404 return RISCV_CSR_AIA(sieh); 405 case KVM_REG_RISCV_CSR_AIA_REG(siph): 406 return RISCV_CSR_AIA(siph); 407 case KVM_REG_RISCV_CSR_AIA_REG(iprio1h): 408 return RISCV_CSR_AIA(iprio1h); 409 case KVM_REG_RISCV_CSR_AIA_REG(iprio2h): 410 return RISCV_CSR_AIA(iprio2h); 411 } 412 413 return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off); 414 } 415 416 static const char *smstateen_csr_id_to_str(__u64 reg_off) 417 { 418 /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ 419 switch (reg_off) { 420 case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): 421 return RISCV_CSR_SMSTATEEN(sstateen0); 422 } 423 424 TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); 425 return NULL; 426 } 427 428 static const char *csr_id_to_str(const char *prefix, __u64 id) 429 { 430 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); 431 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 432 433 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); 434 435 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 436 437 switch (reg_subtype) { 438 case KVM_REG_RISCV_CSR_GENERAL: 439 return general_csr_id_to_str(reg_off); 440 case KVM_REG_RISCV_CSR_AIA: 441 return aia_csr_id_to_str(reg_off); 442 case KVM_REG_RISCV_CSR_SMSTATEEN: 443 return smstateen_csr_id_to_str(reg_off); 444 } 445 446 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 447 } 448 449 static const char *timer_id_to_str(const char *prefix, __u64 id) 450 { 451 /* reg_off is the offset into struct kvm_riscv_timer */ 452 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); 453 454 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER); 455 456 switch (reg_off) { 457 case KVM_REG_RISCV_TIMER_REG(frequency): 458 return "KVM_REG_RISCV_TIMER_REG(frequency)"; 459 case KVM_REG_RISCV_TIMER_REG(time): 460 return "KVM_REG_RISCV_TIMER_REG(time)"; 461 case KVM_REG_RISCV_TIMER_REG(compare): 462 return "KVM_REG_RISCV_TIMER_REG(compare)"; 463 case KVM_REG_RISCV_TIMER_REG(state): 464 return "KVM_REG_RISCV_TIMER_REG(state)"; 465 } 466 467 return strdup_printf("%lld /* UNKNOWN */", reg_off); 468 } 469 470 static const char *fp_f_id_to_str(const char *prefix, __u64 id) 471 { 472 /* reg_off is the offset into struct __riscv_f_ext_state */ 473 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); 474 475 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F); 476 477 switch (reg_off) { 478 case KVM_REG_RISCV_FP_F_REG(f[0]) ... 479 KVM_REG_RISCV_FP_F_REG(f[31]): 480 return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off); 481 case KVM_REG_RISCV_FP_F_REG(fcsr): 482 return "KVM_REG_RISCV_FP_F_REG(fcsr)"; 483 } 484 485 return strdup_printf("%lld /* UNKNOWN */", reg_off); 486 } 487 488 static const char *fp_d_id_to_str(const char *prefix, __u64 id) 489 { 490 /* reg_off is the offset into struct __riscv_d_ext_state */ 491 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); 492 493 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D); 494 495 switch (reg_off) { 496 case KVM_REG_RISCV_FP_D_REG(f[0]) ... 497 KVM_REG_RISCV_FP_D_REG(f[31]): 498 return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off); 499 case KVM_REG_RISCV_FP_D_REG(fcsr): 500 return "KVM_REG_RISCV_FP_D_REG(fcsr)"; 501 } 502 503 return strdup_printf("%lld /* UNKNOWN */", reg_off); 504 } 505 506 static const char *vector_id_to_str(const char *prefix, __u64 id) 507 { 508 /* reg_off is the offset into struct __riscv_v_ext_state */ 509 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR); 510 int reg_index = 0; 511 512 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_VECTOR); 513 514 if (reg_off >= KVM_REG_RISCV_VECTOR_REG(0)) 515 reg_index = reg_off - KVM_REG_RISCV_VECTOR_REG(0); 516 switch (reg_off) { 517 case KVM_REG_RISCV_VECTOR_REG(0) ... 518 KVM_REG_RISCV_VECTOR_REG(31): 519 return strdup_printf("KVM_REG_RISCV_VECTOR_REG(%d)", reg_index); 520 case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): 521 return "KVM_REG_RISCV_VECTOR_CSR_REG(vstart)"; 522 case KVM_REG_RISCV_VECTOR_CSR_REG(vl): 523 return "KVM_REG_RISCV_VECTOR_CSR_REG(vl)"; 524 case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): 525 return "KVM_REG_RISCV_VECTOR_CSR_REG(vtype)"; 526 case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): 527 return "KVM_REG_RISCV_VECTOR_CSR_REG(vcsr)"; 528 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): 529 return "KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)"; 530 } 531 532 return strdup_printf("%lld /* UNKNOWN */", reg_off); 533 } 534 535 #define KVM_ISA_EXT_ARR(ext) \ 536 [KVM_RISCV_ISA_EXT_##ext] = "KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_" #ext 537 538 static const char *isa_ext_single_id_to_str(__u64 reg_off) 539 { 540 static const char * const kvm_isa_ext_reg_name[] = { 541 KVM_ISA_EXT_ARR(A), 542 KVM_ISA_EXT_ARR(C), 543 KVM_ISA_EXT_ARR(D), 544 KVM_ISA_EXT_ARR(F), 545 KVM_ISA_EXT_ARR(H), 546 KVM_ISA_EXT_ARR(I), 547 KVM_ISA_EXT_ARR(M), 548 KVM_ISA_EXT_ARR(V), 549 KVM_ISA_EXT_ARR(SMNPM), 550 KVM_ISA_EXT_ARR(SMSTATEEN), 551 KVM_ISA_EXT_ARR(SSAIA), 552 KVM_ISA_EXT_ARR(SSCOFPMF), 553 KVM_ISA_EXT_ARR(SSNPM), 554 KVM_ISA_EXT_ARR(SSTC), 555 KVM_ISA_EXT_ARR(SVADE), 556 KVM_ISA_EXT_ARR(SVADU), 557 KVM_ISA_EXT_ARR(SVINVAL), 558 KVM_ISA_EXT_ARR(SVNAPOT), 559 KVM_ISA_EXT_ARR(SVPBMT), 560 KVM_ISA_EXT_ARR(SVVPTC), 561 KVM_ISA_EXT_ARR(ZAAMO), 562 KVM_ISA_EXT_ARR(ZABHA), 563 KVM_ISA_EXT_ARR(ZACAS), 564 KVM_ISA_EXT_ARR(ZALASR), 565 KVM_ISA_EXT_ARR(ZALRSC), 566 KVM_ISA_EXT_ARR(ZAWRS), 567 KVM_ISA_EXT_ARR(ZBA), 568 KVM_ISA_EXT_ARR(ZBB), 569 KVM_ISA_EXT_ARR(ZBC), 570 KVM_ISA_EXT_ARR(ZBKB), 571 KVM_ISA_EXT_ARR(ZBKC), 572 KVM_ISA_EXT_ARR(ZBKX), 573 KVM_ISA_EXT_ARR(ZBS), 574 KVM_ISA_EXT_ARR(ZCA), 575 KVM_ISA_EXT_ARR(ZCB), 576 KVM_ISA_EXT_ARR(ZCD), 577 KVM_ISA_EXT_ARR(ZCF), 578 KVM_ISA_EXT_ARR(ZCLSD), 579 KVM_ISA_EXT_ARR(ZCMOP), 580 KVM_ISA_EXT_ARR(ZFA), 581 KVM_ISA_EXT_ARR(ZFBFMIN), 582 KVM_ISA_EXT_ARR(ZFH), 583 KVM_ISA_EXT_ARR(ZFHMIN), 584 KVM_ISA_EXT_ARR(ZICBOM), 585 KVM_ISA_EXT_ARR(ZICBOP), 586 KVM_ISA_EXT_ARR(ZICBOZ), 587 KVM_ISA_EXT_ARR(ZICCRSE), 588 KVM_ISA_EXT_ARR(ZICNTR), 589 KVM_ISA_EXT_ARR(ZICOND), 590 KVM_ISA_EXT_ARR(ZICSR), 591 KVM_ISA_EXT_ARR(ZIFENCEI), 592 KVM_ISA_EXT_ARR(ZIHINTNTL), 593 KVM_ISA_EXT_ARR(ZIHINTPAUSE), 594 KVM_ISA_EXT_ARR(ZIHPM), 595 KVM_ISA_EXT_ARR(ZILSD), 596 KVM_ISA_EXT_ARR(ZIMOP), 597 KVM_ISA_EXT_ARR(ZKND), 598 KVM_ISA_EXT_ARR(ZKNE), 599 KVM_ISA_EXT_ARR(ZKNH), 600 KVM_ISA_EXT_ARR(ZKR), 601 KVM_ISA_EXT_ARR(ZKSED), 602 KVM_ISA_EXT_ARR(ZKSH), 603 KVM_ISA_EXT_ARR(ZKT), 604 KVM_ISA_EXT_ARR(ZTSO), 605 KVM_ISA_EXT_ARR(ZVBB), 606 KVM_ISA_EXT_ARR(ZVBC), 607 KVM_ISA_EXT_ARR(ZVFBFMIN), 608 KVM_ISA_EXT_ARR(ZVFBFWMA), 609 KVM_ISA_EXT_ARR(ZVFH), 610 KVM_ISA_EXT_ARR(ZVFHMIN), 611 KVM_ISA_EXT_ARR(ZVKB), 612 KVM_ISA_EXT_ARR(ZVKG), 613 KVM_ISA_EXT_ARR(ZVKNED), 614 KVM_ISA_EXT_ARR(ZVKNHA), 615 KVM_ISA_EXT_ARR(ZVKNHB), 616 KVM_ISA_EXT_ARR(ZVKSED), 617 KVM_ISA_EXT_ARR(ZVKSH), 618 KVM_ISA_EXT_ARR(ZVKT), 619 }; 620 621 if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) 622 return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off); 623 624 return kvm_isa_ext_reg_name[reg_off]; 625 } 626 627 static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) 628 { 629 const char *unknown = ""; 630 631 if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST) 632 unknown = " /* UNKNOWN */"; 633 634 switch (reg_subtype) { 635 case KVM_REG_RISCV_ISA_MULTI_EN: 636 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown); 637 case KVM_REG_RISCV_ISA_MULTI_DIS: 638 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown); 639 } 640 641 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 642 } 643 644 static const char *isa_ext_id_to_str(const char *prefix, __u64 id) 645 { 646 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); 647 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 648 649 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT); 650 651 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 652 653 switch (reg_subtype) { 654 case KVM_REG_RISCV_ISA_SINGLE: 655 return isa_ext_single_id_to_str(reg_off); 656 case KVM_REG_RISCV_ISA_MULTI_EN: 657 case KVM_REG_RISCV_ISA_MULTI_DIS: 658 return isa_ext_multi_id_to_str(reg_subtype, reg_off); 659 } 660 661 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 662 } 663 664 #define KVM_SBI_EXT_ARR(ext) \ 665 [ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext 666 667 static const char *sbi_ext_single_id_to_str(__u64 reg_off) 668 { 669 /* reg_off is KVM_RISCV_SBI_EXT_ID */ 670 static const char * const kvm_sbi_ext_reg_name[] = { 671 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01), 672 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME), 673 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI), 674 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE), 675 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST), 676 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM), 677 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), 678 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN), 679 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SUSP), 680 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA), 681 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_FWFT), 682 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_MPXY), 683 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), 684 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), 685 }; 686 687 if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) 688 return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off); 689 690 return kvm_sbi_ext_reg_name[reg_off]; 691 } 692 693 static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) 694 { 695 const char *unknown = ""; 696 697 if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST) 698 unknown = " /* UNKNOWN */"; 699 700 switch (reg_subtype) { 701 case KVM_REG_RISCV_SBI_MULTI_EN: 702 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown); 703 case KVM_REG_RISCV_SBI_MULTI_DIS: 704 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown); 705 } 706 707 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 708 } 709 710 static const char *sbi_ext_id_to_str(const char *prefix, __u64 id) 711 { 712 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); 713 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 714 715 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT); 716 717 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 718 719 switch (reg_subtype) { 720 case KVM_REG_RISCV_SBI_SINGLE: 721 return sbi_ext_single_id_to_str(reg_off); 722 case KVM_REG_RISCV_SBI_MULTI_EN: 723 case KVM_REG_RISCV_SBI_MULTI_DIS: 724 return sbi_ext_multi_id_to_str(reg_subtype, reg_off); 725 } 726 727 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 728 } 729 730 static const char *sbi_sta_id_to_str(__u64 reg_off) 731 { 732 switch (reg_off) { 733 case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)"; 734 case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)"; 735 } 736 return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off); 737 } 738 739 static const char *sbi_fwft_id_to_str(__u64 reg_off) 740 { 741 switch (reg_off) { 742 case 0: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable)"; 743 case 1: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags)"; 744 case 2: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value)"; 745 case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)"; 746 case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)"; 747 case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)"; 748 } 749 return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off); 750 } 751 752 static const char *sbi_id_to_str(const char *prefix, __u64 id) 753 { 754 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); 755 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 756 757 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE); 758 759 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 760 761 switch (reg_subtype) { 762 case KVM_REG_RISCV_SBI_STA: 763 return sbi_sta_id_to_str(reg_off); 764 case KVM_REG_RISCV_SBI_FWFT: 765 return sbi_fwft_id_to_str(reg_off); 766 } 767 768 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 769 } 770 771 void print_reg(const char *prefix, __u64 id) 772 { 773 const char *reg_size = NULL; 774 775 TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV, 776 "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id); 777 778 switch (id & KVM_REG_SIZE_MASK) { 779 case KVM_REG_SIZE_U32: 780 reg_size = "KVM_REG_SIZE_U32"; 781 break; 782 case KVM_REG_SIZE_U64: 783 reg_size = "KVM_REG_SIZE_U64"; 784 break; 785 case KVM_REG_SIZE_U128: 786 reg_size = "KVM_REG_SIZE_U128"; 787 break; 788 case KVM_REG_SIZE_U256: 789 reg_size = "KVM_REG_SIZE_U256"; 790 break; 791 default: 792 printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,\n", 793 (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & ~REG_MASK); 794 return; 795 } 796 797 switch (id & KVM_REG_RISCV_TYPE_MASK) { 798 case KVM_REG_RISCV_CONFIG: 799 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n", 800 reg_size, config_id_to_str(prefix, id)); 801 break; 802 case KVM_REG_RISCV_CORE: 803 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n", 804 reg_size, core_id_to_str(prefix, id)); 805 break; 806 case KVM_REG_RISCV_CSR: 807 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n", 808 reg_size, csr_id_to_str(prefix, id)); 809 break; 810 case KVM_REG_RISCV_TIMER: 811 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n", 812 reg_size, timer_id_to_str(prefix, id)); 813 break; 814 case KVM_REG_RISCV_FP_F: 815 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n", 816 reg_size, fp_f_id_to_str(prefix, id)); 817 break; 818 case KVM_REG_RISCV_FP_D: 819 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n", 820 reg_size, fp_d_id_to_str(prefix, id)); 821 break; 822 case KVM_REG_RISCV_VECTOR: 823 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_VECTOR | %s,\n", 824 reg_size, vector_id_to_str(prefix, id)); 825 break; 826 case KVM_REG_RISCV_ISA_EXT: 827 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n", 828 reg_size, isa_ext_id_to_str(prefix, id)); 829 break; 830 case KVM_REG_RISCV_SBI_EXT: 831 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n", 832 reg_size, sbi_ext_id_to_str(prefix, id)); 833 break; 834 case KVM_REG_RISCV_SBI_STATE: 835 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_STATE | %s,\n", 836 reg_size, sbi_id_to_str(prefix, id)); 837 break; 838 default: 839 printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n", 840 reg_size, id & ~REG_MASK); 841 return; 842 } 843 } 844 845 /* 846 * The current blessed list was primed with the output of kernel version 847 * v6.5-rc3 and then later updated with new registers. 848 */ 849 static __u64 base_regs[] = { 850 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa), 851 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), 852 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid), 853 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid), 854 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid), 855 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size), 856 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode), 857 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size), 858 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc), 859 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra), 860 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp), 861 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp), 862 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp), 863 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0), 864 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1), 865 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2), 866 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0), 867 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1), 868 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0), 869 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1), 870 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2), 871 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3), 872 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4), 873 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5), 874 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6), 875 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7), 876 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2), 877 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3), 878 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4), 879 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5), 880 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6), 881 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7), 882 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8), 883 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9), 884 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10), 885 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11), 886 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3), 887 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4), 888 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5), 889 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6), 890 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode), 891 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus), 892 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie), 893 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec), 894 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch), 895 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc), 896 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause), 897 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval), 898 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip), 899 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp), 900 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), 901 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), 902 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency), 903 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), 904 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), 905 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), 906 }; 907 908 /* 909 * The skips_set list registers that should skip set test. 910 * - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly. 911 */ 912 static __u64 base_skips_set[] = { 913 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), 914 }; 915 916 static __u64 sbi_base_regs[] = { 917 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01, 918 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME, 919 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI, 920 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE, 921 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST, 922 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM, 923 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL, 924 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR, 925 }; 926 927 static __u64 sbi_sta_regs[] = { 928 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA, 929 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo), 930 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi), 931 }; 932 933 static __u64 sbi_fwft_misaligned_deleg_regs[] = { 934 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 935 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable), 936 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags), 937 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value), 938 }; 939 940 static __u64 sbi_fwft_pointer_masking_regs[] = { 941 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 942 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable), 943 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), 944 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), 945 }; 946 947 static __u64 zicbom_regs[] = { 948 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), 949 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, 950 }; 951 952 static __u64 zicbop_regs[] = { 953 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size), 954 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP, 955 }; 956 957 static __u64 zicboz_regs[] = { 958 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size), 959 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ, 960 }; 961 962 static __u64 aia_regs[] = { 963 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect), 964 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1), 965 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2), 966 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh), 967 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph), 968 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h), 969 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h), 970 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA, 971 }; 972 973 static __u64 smstateen_regs[] = { 974 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), 975 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN, 976 }; 977 978 static __u64 fp_f_regs[] = { 979 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]), 980 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]), 981 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]), 982 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]), 983 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]), 984 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]), 985 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]), 986 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]), 987 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]), 988 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]), 989 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]), 990 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]), 991 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]), 992 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]), 993 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]), 994 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]), 995 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]), 996 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]), 997 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]), 998 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]), 999 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]), 1000 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]), 1001 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]), 1002 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]), 1003 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]), 1004 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]), 1005 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]), 1006 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]), 1007 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]), 1008 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]), 1009 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]), 1010 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]), 1011 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr), 1012 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F, 1013 }; 1014 1015 static __u64 fp_d_regs[] = { 1016 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]), 1017 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]), 1018 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]), 1019 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]), 1020 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]), 1021 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]), 1022 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]), 1023 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]), 1024 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]), 1025 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]), 1026 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]), 1027 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]), 1028 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]), 1029 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]), 1030 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]), 1031 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]), 1032 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]), 1033 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]), 1034 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]), 1035 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]), 1036 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]), 1037 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]), 1038 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]), 1039 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]), 1040 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]), 1041 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]), 1042 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]), 1043 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]), 1044 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]), 1045 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]), 1046 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]), 1047 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]), 1048 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr), 1049 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D, 1050 }; 1051 1052 /* Define a default vector registers with length. This will be overwritten at runtime */ 1053 static __u64 v_regs[] = { 1054 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vstart), 1055 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vl), 1056 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vtype), 1057 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vcsr), 1058 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb), 1059 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(0), 1060 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(1), 1061 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(2), 1062 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(3), 1063 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(4), 1064 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(5), 1065 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(6), 1066 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(7), 1067 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(8), 1068 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(9), 1069 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(10), 1070 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(11), 1071 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(12), 1072 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(13), 1073 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(14), 1074 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(15), 1075 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(16), 1076 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(17), 1077 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(18), 1078 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(19), 1079 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(20), 1080 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(21), 1081 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(22), 1082 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(23), 1083 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(24), 1084 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(25), 1085 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(26), 1086 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(27), 1087 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(28), 1088 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(29), 1089 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(30), 1090 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(31), 1091 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V, 1092 }; 1093 1094 #define SUBLIST_BASE \ 1095 {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \ 1096 .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),} 1097 1098 #define SUBLIST_ISA(ext, extu) \ 1099 { \ 1100 .name = #ext, \ 1101 .feature = KVM_RISCV_ISA_EXT_##extu, \ 1102 .regs = ext##_regs, \ 1103 .regs_n = ARRAY_SIZE(ext##_regs), \ 1104 } 1105 1106 #define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \ 1107 static __u64 ext##_regs[] = { \ 1108 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ 1109 KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \ 1110 KVM_RISCV_ISA_EXT_##extu, \ 1111 }; \ 1112 static struct vcpu_reg_list config_##ext = { \ 1113 .sublists = { \ 1114 SUBLIST_BASE, \ 1115 SUBLIST_ISA(ext, extu), \ 1116 {0}, \ 1117 }, \ 1118 } \ 1119 1120 #define SUBLIST_SBI(ext, extu) \ 1121 { \ 1122 .name = "sbi-"#ext, \ 1123 .feature_type = VCPU_FEATURE_SBI_EXT, \ 1124 .feature = KVM_RISCV_SBI_EXT_##extu, \ 1125 .regs = sbi_##ext##_regs, \ 1126 .regs_n = ARRAY_SIZE(sbi_##ext##_regs), \ 1127 } 1128 1129 #define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \ 1130 static __u64 sbi_##ext##_regs[] = { \ 1131 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ 1132 KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \ 1133 KVM_RISCV_SBI_EXT_##extu, \ 1134 }; \ 1135 static struct vcpu_reg_list config_sbi_##ext = { \ 1136 .sublists = { \ 1137 SUBLIST_BASE, \ 1138 SUBLIST_SBI(ext, extu), \ 1139 {0}, \ 1140 }, \ 1141 } \ 1142 1143 #define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \ 1144 static struct vcpu_reg_list config_##ext = { \ 1145 .sublists = { \ 1146 SUBLIST_BASE, \ 1147 SUBLIST_ISA(ext, extu), \ 1148 {0}, \ 1149 }, \ 1150 } \ 1151 1152 #define KVM_SBI_EXT_SUBLIST_CONFIG(ext, extu) \ 1153 static struct vcpu_reg_list config_sbi_##ext = { \ 1154 .sublists = { \ 1155 SUBLIST_BASE, \ 1156 SUBLIST_SBI(ext, extu), \ 1157 {0}, \ 1158 }, \ 1159 } \ 1160 1161 /* Note: The below list is alphabetically sorted. */ 1162 1163 KVM_SBI_EXT_SUBLIST_CONFIG(base, V01); 1164 KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA); 1165 KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); 1166 KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); 1167 KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); 1168 KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY); 1169 1170 KVM_ISA_EXT_SUBLIST_CONFIG(aia, SSAIA); 1171 KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, F); 1172 KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, D); 1173 KVM_ISA_EXT_SUBLIST_CONFIG(v, V); 1174 KVM_ISA_EXT_SIMPLE_CONFIG(h, H); 1175 KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM); 1176 KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); 1177 KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); 1178 KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM); 1179 KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); 1180 KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); 1181 KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); 1182 KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); 1183 KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); 1184 KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); 1185 KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC); 1186 KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO); 1187 KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA); 1188 KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS); 1189 KVM_ISA_EXT_SIMPLE_CONFIG(zalasr, ZALASR); 1190 KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC); 1191 KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS); 1192 KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA); 1193 KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB); 1194 KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC); 1195 KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); 1196 KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); 1197 KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); 1198 KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); 1199 KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA); 1200 KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB); 1201 KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD); 1202 KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF); 1203 KVM_ISA_EXT_SIMPLE_CONFIG(zclsd, ZCLSD); 1204 KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); 1205 KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); 1206 KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN); 1207 KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); 1208 KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); 1209 KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM); 1210 KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP); 1211 KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ); 1212 KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE); 1213 KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR); 1214 KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND); 1215 KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR); 1216 KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI); 1217 KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL); 1218 KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE); 1219 KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM); 1220 KVM_ISA_EXT_SIMPLE_CONFIG(zilsd, ZILSD); 1221 KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP); 1222 KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND); 1223 KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE); 1224 KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH); 1225 KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR); 1226 KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED); 1227 KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH); 1228 KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT); 1229 KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO); 1230 KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB); 1231 KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC); 1232 KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN); 1233 KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA); 1234 KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH); 1235 KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN); 1236 KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB); 1237 KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG); 1238 KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED); 1239 KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA); 1240 KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB); 1241 KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED); 1242 KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH); 1243 KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT); 1244 1245 static struct vcpu_reg_list config_sbi_fwft_misaligned_deleg = { 1246 .sublists = { 1247 SUBLIST_BASE, 1248 SUBLIST_SBI(fwft_misaligned_deleg, FWFT), 1249 {0}, 1250 }, 1251 }; 1252 1253 static struct vcpu_reg_list config_sbi_fwft_pointer_masking = { 1254 .sublists = { 1255 SUBLIST_BASE, 1256 SUBLIST_ISA(smnpm, SMNPM), 1257 SUBLIST_SBI(fwft_pointer_masking, FWFT), 1258 {0}, 1259 }, 1260 }; 1261 1262 struct vcpu_reg_list *vcpu_configs[] = { 1263 &config_sbi_base, 1264 &config_sbi_sta, 1265 &config_sbi_pmu, 1266 &config_sbi_dbcn, 1267 &config_sbi_susp, 1268 &config_sbi_mpxy, 1269 &config_sbi_fwft_misaligned_deleg, 1270 &config_sbi_fwft_pointer_masking, 1271 &config_aia, 1272 &config_fp_f, 1273 &config_fp_d, 1274 &config_h, 1275 &config_v, 1276 &config_smnpm, 1277 &config_smstateen, 1278 &config_sscofpmf, 1279 &config_ssnpm, 1280 &config_sstc, 1281 &config_svade, 1282 &config_svadu, 1283 &config_svinval, 1284 &config_svnapot, 1285 &config_svpbmt, 1286 &config_svvptc, 1287 &config_zaamo, 1288 &config_zabha, 1289 &config_zacas, 1290 &config_zalrsc, 1291 &config_zalasr, 1292 &config_zawrs, 1293 &config_zba, 1294 &config_zbb, 1295 &config_zbc, 1296 &config_zbkb, 1297 &config_zbkc, 1298 &config_zbkx, 1299 &config_zbs, 1300 &config_zca, 1301 &config_zcb, 1302 &config_zcd, 1303 &config_zcf, 1304 &config_zclsd, 1305 &config_zcmop, 1306 &config_zfa, 1307 &config_zfbfmin, 1308 &config_zfh, 1309 &config_zfhmin, 1310 &config_zicbom, 1311 &config_zicbop, 1312 &config_zicboz, 1313 &config_ziccrse, 1314 &config_zicntr, 1315 &config_zicond, 1316 &config_zicsr, 1317 &config_zifencei, 1318 &config_zihintntl, 1319 &config_zihintpause, 1320 &config_zihpm, 1321 &config_zilsd, 1322 &config_zimop, 1323 &config_zknd, 1324 &config_zkne, 1325 &config_zknh, 1326 &config_zkr, 1327 &config_zksed, 1328 &config_zksh, 1329 &config_zkt, 1330 &config_ztso, 1331 &config_zvbb, 1332 &config_zvbc, 1333 &config_zvfbfmin, 1334 &config_zvfbfwma, 1335 &config_zvfh, 1336 &config_zvfhmin, 1337 &config_zvkb, 1338 &config_zvkg, 1339 &config_zvkned, 1340 &config_zvknha, 1341 &config_zvknhb, 1342 &config_zvksed, 1343 &config_zvksh, 1344 &config_zvkt, 1345 }; 1346 int vcpu_configs_n = ARRAY_SIZE(vcpu_configs); 1347