1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 /* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved.
3 * Parts of this driver are based on the following:
4 * - Kvaser linux pciefd driver (version 5.42)
5 * - PEAK linux canfd driver
6 */
7
8 #include "kvaser_pciefd.h"
9
10 #include <linux/bitfield.h>
11 #include <linux/can/dev.h>
12 #include <linux/device.h>
13 #include <linux/ethtool.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/minmax.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/pci.h>
20 #include <linux/timer.h>
21 #include <net/netdev_queues.h>
22
23 MODULE_LICENSE("Dual BSD/GPL");
24 MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");
25 MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
26
27 #define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd"
28
29 #define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
30 #define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
31 #define KVASER_PCIEFD_MAX_ERR_REP 256U
32
33 #define KVASER_PCIEFD_VENDOR 0x1a07
34
35 /* Altera based devices */
36 #define KVASER_PCIEFD_4HS_DEVICE_ID 0x000d
37 #define KVASER_PCIEFD_2HS_V2_DEVICE_ID 0x000e
38 #define KVASER_PCIEFD_HS_V2_DEVICE_ID 0x000f
39 #define KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID 0x0010
40 #define KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID 0x0011
41
42 /* SmartFusion2 based devices */
43 #define KVASER_PCIEFD_2CAN_V3_DEVICE_ID 0x0012
44 #define KVASER_PCIEFD_1CAN_V3_DEVICE_ID 0x0013
45 #define KVASER_PCIEFD_4CAN_V2_DEVICE_ID 0x0014
46 #define KVASER_PCIEFD_MINIPCIE_2CAN_V3_DEVICE_ID 0x0015
47 #define KVASER_PCIEFD_MINIPCIE_1CAN_V3_DEVICE_ID 0x0016
48
49 /* Xilinx based devices */
50 #define KVASER_PCIEFD_M2_4CAN_DEVICE_ID 0x0017
51 #define KVASER_PCIEFD_8CAN_DEVICE_ID 0x0019
52
53 /* Altera SerDes Enable 64-bit DMA address translation */
54 #define KVASER_PCIEFD_ALTERA_DMA_64BIT BIT(0)
55
56 /* SmartFusion2 SerDes LSB address translation mask */
57 #define KVASER_PCIEFD_SF2_DMA_LSB_MASK GENMASK(31, 12)
58
59 /* Xilinx SerDes LSB address translation mask */
60 #define KVASER_PCIEFD_XILINX_DMA_LSB_MASK GENMASK(31, 12)
61
62 /* Kvaser KCAN CAN controller registers */
63 #define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
64 #define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
65 #define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
66 #define KVASER_PCIEFD_KCAN_CMD_REG 0x400
67 #define KVASER_PCIEFD_KCAN_IOC_REG 0x404
68 #define KVASER_PCIEFD_KCAN_IEN_REG 0x408
69 #define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
70 #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG 0x414
71 #define KVASER_PCIEFD_KCAN_STAT_REG 0x418
72 #define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
73 #define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
74 #define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
75 #define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
76 #define KVASER_PCIEFD_KCAN_PWM_REG 0x430
77 /* System identification and information registers */
78 #define KVASER_PCIEFD_SYSID_VERSION_REG 0x8
79 #define KVASER_PCIEFD_SYSID_CANFREQ_REG 0xc
80 #define KVASER_PCIEFD_SYSID_BUSFREQ_REG 0x10
81 #define KVASER_PCIEFD_SYSID_BUILD_REG 0x14
82 /* Shared receive buffer FIFO registers */
83 #define KVASER_PCIEFD_SRB_FIFO_LAST_REG 0x1f4
84 /* Shared receive buffer registers */
85 #define KVASER_PCIEFD_SRB_CMD_REG 0x0
86 #define KVASER_PCIEFD_SRB_IEN_REG 0x04
87 #define KVASER_PCIEFD_SRB_IRQ_REG 0x0c
88 #define KVASER_PCIEFD_SRB_STAT_REG 0x10
89 #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG 0x14
90 #define KVASER_PCIEFD_SRB_CTRL_REG 0x18
91
92 /* System build information fields */
93 #define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK GENMASK(31, 24)
94 #define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK GENMASK(23, 16)
95 #define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)
96 #define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK GENMASK(15, 1)
97
98 /* Reset DMA buffer 0, 1 and FIFO offset */
99 #define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
100 #define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
101 #define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
102
103 /* DMA underflow, buffer 0 and 1 */
104 #define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
105 #define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
106 /* DMA overflow, buffer 0 and 1 */
107 #define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
108 #define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
109 /* DMA packet done, buffer 0 and 1 */
110 #define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
111 #define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
112
113 /* Got DMA support */
114 #define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
115 /* DMA idle */
116 #define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
117
118 /* SRB current packet level */
119 #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)
120
121 /* DMA Enable */
122 #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
123
124 /* KCAN CTRL packet types */
125 #define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK GENMASK(31, 29)
126 #define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH 0x4
127 #define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME 0x5
128
129 /* Command sequence number */
130 #define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK GENMASK(23, 16)
131 /* Command bits */
132 #define KVASER_PCIEFD_KCAN_CMD_MASK GENMASK(5, 0)
133 /* Abort, flush and reset */
134 #define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
135 /* Request status packet */
136 #define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
137
138 /* Control CAN LED, active low */
139 #define KVASER_PCIEFD_KCAN_IOC_LED BIT(0)
140
141 /* Transmitter unaligned */
142 #define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
143 /* Tx FIFO empty */
144 #define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
145 /* Tx FIFO overflow */
146 #define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
147 /* Tx buffer flush done */
148 #define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
149 /* Abort done */
150 #define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
151 /* Rx FIFO overflow */
152 #define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
153 /* FDF bit when controller is in classic CAN mode */
154 #define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
155 /* Bus parameter protection error */
156 #define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
157 /* Tx FIFO unaligned end */
158 #define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
159 /* Tx FIFO unaligned read */
160 #define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
161
162 /* Tx FIFO size */
163 #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK GENMASK(23, 16)
164 /* Tx FIFO current packet level */
165 #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)
166
167 /* Current status packet sequence number */
168 #define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK GENMASK(31, 24)
169 /* Controller got CAN FD capability */
170 #define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
171 /* Controller got one-shot capability */
172 #define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
173 /* Controller in reset mode */
174 #define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
175 /* Reset mode request */
176 #define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
177 /* Bus off */
178 #define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
179 /* Idle state. Controller in reset mode and no abort or flush pending */
180 #define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
181 /* Abort request */
182 #define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
183 /* Controller is bus off */
184 #define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK \
185 (KVASER_PCIEFD_KCAN_STAT_AR | KVASER_PCIEFD_KCAN_STAT_BOFF | \
186 KVASER_PCIEFD_KCAN_STAT_RMR | KVASER_PCIEFD_KCAN_STAT_IRM)
187
188 /* Classic CAN mode */
189 #define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
190 /* Active error flag enable. Clear to force error passive */
191 #define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
192 /* Acknowledgment packet type */
193 #define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
194 /* CAN FD non-ISO */
195 #define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
196 /* Error packet enable */
197 #define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
198 /* Listen only mode */
199 #define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
200 /* Reset mode */
201 #define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
202
203 /* BTRN and BTRD fields */
204 #define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK GENMASK(30, 26)
205 #define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK GENMASK(25, 17)
206 #define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK GENMASK(16, 13)
207 #define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)
208
209 /* PWM Control fields */
210 #define KVASER_PCIEFD_KCAN_PWM_TOP_MASK GENMASK(23, 16)
211 #define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)
212
213 /* KCAN packet type IDs */
214 #define KVASER_PCIEFD_PACK_TYPE_DATA 0x0
215 #define KVASER_PCIEFD_PACK_TYPE_ACK 0x1
216 #define KVASER_PCIEFD_PACK_TYPE_TXRQ 0x2
217 #define KVASER_PCIEFD_PACK_TYPE_ERROR 0x3
218 #define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 0x4
219 #define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 0x5
220 #define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 0x6
221 #define KVASER_PCIEFD_PACK_TYPE_STATUS 0x8
222 #define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 0x9
223
224 /* Common KCAN packet definitions, second word */
225 #define KVASER_PCIEFD_PACKET_TYPE_MASK GENMASK(31, 28)
226 #define KVASER_PCIEFD_PACKET_CHID_MASK GENMASK(27, 25)
227 #define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)
228
229 /* KCAN Transmit/Receive data packet, first word */
230 #define KVASER_PCIEFD_RPACKET_IDE BIT(30)
231 #define KVASER_PCIEFD_RPACKET_RTR BIT(29)
232 #define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)
233 /* KCAN Transmit data packet, second word */
234 #define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
235 #define KVASER_PCIEFD_TPACKET_SMS BIT(16)
236 /* KCAN Transmit/Receive data packet, second word */
237 #define KVASER_PCIEFD_RPACKET_FDF BIT(15)
238 #define KVASER_PCIEFD_RPACKET_BRS BIT(14)
239 #define KVASER_PCIEFD_RPACKET_ESI BIT(13)
240 #define KVASER_PCIEFD_RPACKET_DLC_MASK GENMASK(11, 8)
241
242 /* KCAN Transmit acknowledge packet, first word */
243 #define KVASER_PCIEFD_APACKET_NACK BIT(11)
244 #define KVASER_PCIEFD_APACKET_ABL BIT(10)
245 #define KVASER_PCIEFD_APACKET_CT BIT(9)
246 #define KVASER_PCIEFD_APACKET_FLU BIT(8)
247
248 /* KCAN Status packet, first word */
249 #define KVASER_PCIEFD_SPACK_RMCD BIT(22)
250 #define KVASER_PCIEFD_SPACK_IRM BIT(21)
251 #define KVASER_PCIEFD_SPACK_IDET BIT(20)
252 #define KVASER_PCIEFD_SPACK_BOFF BIT(16)
253 #define KVASER_PCIEFD_SPACK_RXERR_MASK GENMASK(15, 8)
254 #define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)
255 /* KCAN Status packet, second word */
256 #define KVASER_PCIEFD_SPACK_EPLR BIT(24)
257 #define KVASER_PCIEFD_SPACK_EWLR BIT(23)
258 #define KVASER_PCIEFD_SPACK_AUTO BIT(21)
259
260 /* KCAN Error detected packet, second word */
261 #define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
262
263 /* Macros for calculating addresses of registers */
264 #define KVASER_PCIEFD_GET_BLOCK_ADDR(pcie, block) \
265 ((pcie)->reg_base + (pcie)->driver_data->address_offset->block)
266 #define KVASER_PCIEFD_PCI_IEN_ADDR(pcie) \
267 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), pci_ien))
268 #define KVASER_PCIEFD_PCI_IRQ_ADDR(pcie) \
269 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), pci_irq))
270 #define KVASER_PCIEFD_SERDES_ADDR(pcie) \
271 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), serdes))
272 #define KVASER_PCIEFD_SYSID_ADDR(pcie) \
273 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), sysid))
274 #define KVASER_PCIEFD_LOOPBACK_ADDR(pcie) \
275 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), loopback))
276 #define KVASER_PCIEFD_SRB_FIFO_ADDR(pcie) \
277 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_srb_fifo))
278 #define KVASER_PCIEFD_SRB_ADDR(pcie) \
279 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_srb))
280 #define KVASER_PCIEFD_KCAN_CH0_ADDR(pcie) \
281 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_ch0))
282 #define KVASER_PCIEFD_KCAN_CH1_ADDR(pcie) \
283 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_ch1))
284 #define KVASER_PCIEFD_KCAN_CHANNEL_SPAN(pcie) \
285 (KVASER_PCIEFD_KCAN_CH1_ADDR((pcie)) - KVASER_PCIEFD_KCAN_CH0_ADDR((pcie)))
286 #define KVASER_PCIEFD_KCAN_CHX_ADDR(pcie, i) \
287 (KVASER_PCIEFD_KCAN_CH0_ADDR((pcie)) + (i) * KVASER_PCIEFD_KCAN_CHANNEL_SPAN((pcie)))
288
289 struct kvaser_pciefd;
290 static void kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd *pcie,
291 dma_addr_t addr, int index);
292 static void kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd *pcie,
293 dma_addr_t addr, int index);
294 static void kvaser_pciefd_write_dma_map_xilinx(struct kvaser_pciefd *pcie,
295 dma_addr_t addr, int index);
296
297 static const struct kvaser_pciefd_address_offset kvaser_pciefd_altera_address_offset = {
298 .serdes = 0x1000,
299 .pci_ien = 0x50,
300 .pci_irq = 0x40,
301 .sysid = 0x1f020,
302 .loopback = 0x1f000,
303 .kcan_srb_fifo = 0x1f200,
304 .kcan_srb = 0x1f400,
305 .kcan_ch0 = 0x10000,
306 .kcan_ch1 = 0x11000,
307 };
308
309 static const struct kvaser_pciefd_address_offset kvaser_pciefd_sf2_address_offset = {
310 .serdes = 0x280c8,
311 .pci_ien = 0x102004,
312 .pci_irq = 0x102008,
313 .sysid = 0x100000,
314 .loopback = 0x103000,
315 .kcan_srb_fifo = 0x120000,
316 .kcan_srb = 0x121000,
317 .kcan_ch0 = 0x140000,
318 .kcan_ch1 = 0x142000,
319 };
320
321 static const struct kvaser_pciefd_address_offset kvaser_pciefd_xilinx_address_offset = {
322 .serdes = 0x00208,
323 .pci_ien = 0x102004,
324 .pci_irq = 0x102008,
325 .sysid = 0x100000,
326 .loopback = 0x103000,
327 .kcan_srb_fifo = 0x120000,
328 .kcan_srb = 0x121000,
329 .kcan_ch0 = 0x140000,
330 .kcan_ch1 = 0x142000,
331 };
332
333 static const struct kvaser_pciefd_irq_mask kvaser_pciefd_altera_irq_mask = {
334 .kcan_rx0 = BIT(4),
335 .kcan_tx = { BIT(0), BIT(1), BIT(2), BIT(3) },
336 .all = GENMASK(4, 0),
337 };
338
339 static const struct kvaser_pciefd_irq_mask kvaser_pciefd_sf2_irq_mask = {
340 .kcan_rx0 = BIT(4),
341 .kcan_tx = { BIT(16), BIT(17), BIT(18), BIT(19) },
342 .all = GENMASK(19, 16) | BIT(4),
343 };
344
345 static const struct kvaser_pciefd_irq_mask kvaser_pciefd_xilinx_irq_mask = {
346 .kcan_rx0 = BIT(4),
347 .kcan_tx = { BIT(16), BIT(17), BIT(18), BIT(19), BIT(20), BIT(21), BIT(22), BIT(23) },
348 .all = GENMASK(23, 16) | BIT(4),
349 };
350
351 static const struct kvaser_pciefd_dev_ops kvaser_pciefd_altera_dev_ops = {
352 .kvaser_pciefd_write_dma_map = kvaser_pciefd_write_dma_map_altera,
353 };
354
355 static const struct kvaser_pciefd_dev_ops kvaser_pciefd_sf2_dev_ops = {
356 .kvaser_pciefd_write_dma_map = kvaser_pciefd_write_dma_map_sf2,
357 };
358
359 static const struct kvaser_pciefd_dev_ops kvaser_pciefd_xilinx_dev_ops = {
360 .kvaser_pciefd_write_dma_map = kvaser_pciefd_write_dma_map_xilinx,
361 };
362
363 static const struct kvaser_pciefd_driver_data kvaser_pciefd_altera_driver_data = {
364 .address_offset = &kvaser_pciefd_altera_address_offset,
365 .irq_mask = &kvaser_pciefd_altera_irq_mask,
366 .ops = &kvaser_pciefd_altera_dev_ops,
367 };
368
369 static const struct kvaser_pciefd_driver_data kvaser_pciefd_sf2_driver_data = {
370 .address_offset = &kvaser_pciefd_sf2_address_offset,
371 .irq_mask = &kvaser_pciefd_sf2_irq_mask,
372 .ops = &kvaser_pciefd_sf2_dev_ops,
373 };
374
375 static const struct kvaser_pciefd_driver_data kvaser_pciefd_xilinx_driver_data = {
376 .address_offset = &kvaser_pciefd_xilinx_address_offset,
377 .irq_mask = &kvaser_pciefd_xilinx_irq_mask,
378 .ops = &kvaser_pciefd_xilinx_dev_ops,
379 };
380
381 struct kvaser_pciefd_rx_packet {
382 u32 header[2];
383 u64 timestamp;
384 };
385
386 struct kvaser_pciefd_tx_packet {
387 u32 header[2];
388 u8 data[64];
389 };
390
391 static const struct can_bittiming_const kvaser_pciefd_bittiming_const = {
392 .name = KVASER_PCIEFD_DRV_NAME,
393 .tseg1_min = 1,
394 .tseg1_max = 512,
395 .tseg2_min = 1,
396 .tseg2_max = 32,
397 .sjw_max = 16,
398 .brp_min = 1,
399 .brp_max = 8192,
400 .brp_inc = 1,
401 };
402
403 static struct pci_device_id kvaser_pciefd_id_table[] = {
404 {
405 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_DEVICE_ID),
406 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
407 },
408 {
409 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_V2_DEVICE_ID),
410 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
411 },
412 {
413 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_V2_DEVICE_ID),
414 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
415 },
416 {
417 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID),
418 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
419 },
420 {
421 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID),
422 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
423 },
424 {
425 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2CAN_V3_DEVICE_ID),
426 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
427 },
428 {
429 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_1CAN_V3_DEVICE_ID),
430 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
431 },
432 {
433 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4CAN_V2_DEVICE_ID),
434 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
435 },
436 {
437 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2CAN_V3_DEVICE_ID),
438 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
439 },
440 {
441 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_1CAN_V3_DEVICE_ID),
442 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
443 },
444 {
445 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_M2_4CAN_DEVICE_ID),
446 .driver_data = (kernel_ulong_t)&kvaser_pciefd_xilinx_driver_data,
447 },
448 {
449 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_8CAN_DEVICE_ID),
450 .driver_data = (kernel_ulong_t)&kvaser_pciefd_xilinx_driver_data,
451 },
452 {
453 0,
454 },
455 };
456 MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
457
kvaser_pciefd_send_kcan_cmd(struct kvaser_pciefd_can * can,u32 cmd)458 static inline void kvaser_pciefd_send_kcan_cmd(struct kvaser_pciefd_can *can, u32 cmd)
459 {
460 iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_MASK, cmd) |
461 FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq),
462 can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
463 }
464
kvaser_pciefd_request_status(struct kvaser_pciefd_can * can)465 static inline void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
466 {
467 kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_SRQ);
468 }
469
kvaser_pciefd_abort_flush_reset(struct kvaser_pciefd_can * can)470 static inline void kvaser_pciefd_abort_flush_reset(struct kvaser_pciefd_can *can)
471 {
472 kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_AT);
473 }
474
kvaser_pciefd_set_led(struct kvaser_pciefd_can * can,bool on)475 static inline void kvaser_pciefd_set_led(struct kvaser_pciefd_can *can, bool on)
476 {
477 if (on)
478 can->ioc &= ~KVASER_PCIEFD_KCAN_IOC_LED;
479 else
480 can->ioc |= KVASER_PCIEFD_KCAN_IOC_LED;
481
482 iowrite32(can->ioc, can->reg_base + KVASER_PCIEFD_KCAN_IOC_REG);
483 }
484
kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can * can)485 static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
486 {
487 u32 mode;
488 unsigned long irq;
489
490 spin_lock_irqsave(&can->lock, irq);
491 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
492 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) {
493 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
494 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
495 }
496 spin_unlock_irqrestore(&can->lock, irq);
497 }
498
kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can * can)499 static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can)
500 {
501 u32 mode;
502 unsigned long irq;
503
504 spin_lock_irqsave(&can->lock, irq);
505 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
506 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN;
507 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
508 spin_unlock_irqrestore(&can->lock, irq);
509 }
510
kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can * can)511 static inline void kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
512 {
513 u32 msk;
514
515 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF |
516 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |
517 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |
518 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |
519 KVASER_PCIEFD_KCAN_IRQ_TAR;
520
521 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
522 }
523
kvaser_pciefd_set_skb_timestamp(const struct kvaser_pciefd * pcie,struct sk_buff * skb,u64 timestamp)524 static inline void kvaser_pciefd_set_skb_timestamp(const struct kvaser_pciefd *pcie,
525 struct sk_buff *skb, u64 timestamp)
526 {
527 skb_hwtstamps(skb)->hwtstamp =
528 ns_to_ktime(div_u64(timestamp * 1000, pcie->freq_to_ticks_div));
529 }
530
kvaser_pciefd_setup_controller(struct kvaser_pciefd_can * can)531 static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
532 {
533 u32 mode;
534 unsigned long irq;
535
536 spin_lock_irqsave(&can->lock, irq);
537 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
538 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
539 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
540 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
541 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN;
542 else
543 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
544 } else {
545 mode |= KVASER_PCIEFD_KCAN_MODE_CCM;
546 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
547 }
548
549 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
550 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;
551 else
552 mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;
553 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;
554 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
555 /* Use ACK packet type */
556 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT;
557 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
558 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
559
560 spin_unlock_irqrestore(&can->lock, irq);
561 }
562
kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can * can)563 static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
564 {
565 u32 status;
566 unsigned long irq;
567
568 spin_lock_irqsave(&can->lock, irq);
569 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
570 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
571 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
572 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
573 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
574 /* If controller is already idle, run abort, flush and reset */
575 kvaser_pciefd_abort_flush_reset(can);
576 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
577 u32 mode;
578
579 /* Put controller in reset mode */
580 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
581 mode |= KVASER_PCIEFD_KCAN_MODE_RM;
582 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
583 }
584 spin_unlock_irqrestore(&can->lock, irq);
585 }
586
kvaser_pciefd_bus_on(struct kvaser_pciefd_can * can)587 static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can)
588 {
589 u32 mode;
590 unsigned long irq;
591
592 timer_delete(&can->bec_poll_timer);
593 if (!completion_done(&can->flush_comp))
594 kvaser_pciefd_start_controller_flush(can);
595
596 if (!wait_for_completion_timeout(&can->flush_comp,
597 KVASER_PCIEFD_WAIT_TIMEOUT)) {
598 netdev_err(can->can.dev, "Timeout during bus on flush\n");
599 return -ETIMEDOUT;
600 }
601
602 spin_lock_irqsave(&can->lock, irq);
603 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
604 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
605 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
606 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
607 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
608 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
609 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
610 spin_unlock_irqrestore(&can->lock, irq);
611
612 if (!wait_for_completion_timeout(&can->start_comp,
613 KVASER_PCIEFD_WAIT_TIMEOUT)) {
614 netdev_err(can->can.dev, "Timeout during bus on reset\n");
615 return -ETIMEDOUT;
616 }
617 /* Reset interrupt handling */
618 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
619 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
620
621 kvaser_pciefd_set_tx_irq(can);
622 kvaser_pciefd_setup_controller(can);
623 can->can.state = CAN_STATE_ERROR_ACTIVE;
624 netif_wake_queue(can->can.dev);
625 can->bec.txerr = 0;
626 can->bec.rxerr = 0;
627 can->err_rep_cnt = 0;
628
629 return 0;
630 }
631
kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can * can)632 static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)
633 {
634 u8 top;
635 u32 pwm_ctrl;
636 unsigned long irq;
637
638 spin_lock_irqsave(&can->lock, irq);
639 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
640 top = FIELD_GET(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, pwm_ctrl);
641 /* Set duty cycle to zero */
642 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
643 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
644 spin_unlock_irqrestore(&can->lock, irq);
645 }
646
kvaser_pciefd_pwm_start(struct kvaser_pciefd_can * can)647 static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can)
648 {
649 int top, trigger;
650 u32 pwm_ctrl;
651 unsigned long irq;
652
653 kvaser_pciefd_pwm_stop(can);
654 spin_lock_irqsave(&can->lock, irq);
655 /* Set frequency to 500 KHz */
656 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
657
658 pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
659 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
660 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
661
662 /* Set duty cycle to 95 */
663 trigger = (100 * top - 95 * (top + 1) + 50) / 100;
664 pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, trigger);
665 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
666 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
667 spin_unlock_irqrestore(&can->lock, irq);
668 }
669
kvaser_pciefd_open(struct net_device * netdev)670 static int kvaser_pciefd_open(struct net_device *netdev)
671 {
672 int ret;
673 struct kvaser_pciefd_can *can = netdev_priv(netdev);
674
675 can->tx_idx = 0;
676 can->ack_idx = 0;
677
678 ret = open_candev(netdev);
679 if (ret)
680 return ret;
681
682 ret = kvaser_pciefd_bus_on(can);
683 if (ret) {
684 close_candev(netdev);
685 return ret;
686 }
687
688 return 0;
689 }
690
kvaser_pciefd_stop(struct net_device * netdev)691 static int kvaser_pciefd_stop(struct net_device *netdev)
692 {
693 struct kvaser_pciefd_can *can = netdev_priv(netdev);
694 int ret = 0;
695
696 /* Don't interrupt ongoing flush */
697 if (!completion_done(&can->flush_comp))
698 kvaser_pciefd_start_controller_flush(can);
699
700 if (!wait_for_completion_timeout(&can->flush_comp,
701 KVASER_PCIEFD_WAIT_TIMEOUT)) {
702 netdev_err(can->can.dev, "Timeout during stop\n");
703 ret = -ETIMEDOUT;
704 } else {
705 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
706 timer_delete(&can->bec_poll_timer);
707 }
708 can->can.state = CAN_STATE_STOPPED;
709 netdev_reset_queue(netdev);
710 close_candev(netdev);
711
712 return ret;
713 }
714
kvaser_pciefd_tx_avail(const struct kvaser_pciefd_can * can)715 static unsigned int kvaser_pciefd_tx_avail(const struct kvaser_pciefd_can *can)
716 {
717 return can->tx_max_count - (READ_ONCE(can->tx_idx) - READ_ONCE(can->ack_idx));
718 }
719
kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet * p,struct can_priv * can,u8 seq,struct sk_buff * skb)720 static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
721 struct can_priv *can, u8 seq,
722 struct sk_buff *skb)
723 {
724 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
725 int packet_size;
726
727 memset(p, 0, sizeof(*p));
728 if (can->ctrlmode & CAN_CTRLMODE_ONE_SHOT)
729 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;
730
731 if (cf->can_id & CAN_RTR_FLAG)
732 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR;
733
734 if (cf->can_id & CAN_EFF_FLAG)
735 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
736
737 p->header[0] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_ID_MASK, cf->can_id);
738 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
739
740 if (can_is_canfd_skb(skb)) {
741 p->header[1] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
742 can_fd_len2dlc(cf->len));
743 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;
744 if (cf->flags & CANFD_BRS)
745 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;
746 if (cf->flags & CANFD_ESI)
747 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
748 } else {
749 p->header[1] |=
750 FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
751 can_get_cc_dlc((struct can_frame *)cf, can->ctrlmode));
752 }
753
754 p->header[1] |= FIELD_PREP(KVASER_PCIEFD_PACKET_SEQ_MASK, seq);
755
756 packet_size = cf->len;
757 memcpy(p->data, cf->data, packet_size);
758
759 return DIV_ROUND_UP(packet_size, 4);
760 }
761
kvaser_pciefd_start_xmit(struct sk_buff * skb,struct net_device * netdev)762 static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb,
763 struct net_device *netdev)
764 {
765 struct kvaser_pciefd_can *can = netdev_priv(netdev);
766 struct kvaser_pciefd_tx_packet packet;
767 unsigned int seq = can->tx_idx & (can->can.echo_skb_max - 1);
768 unsigned int frame_len;
769 int nr_words;
770
771 if (can_dev_dropped_skb(netdev, skb))
772 return NETDEV_TX_OK;
773 if (!netif_subqueue_maybe_stop(netdev, 0, kvaser_pciefd_tx_avail(can), 1, 1))
774 return NETDEV_TX_BUSY;
775
776 nr_words = kvaser_pciefd_prepare_tx_packet(&packet, &can->can, seq, skb);
777
778 /* Prepare and save echo skb in internal slot */
779 WRITE_ONCE(can->can.echo_skb[seq], NULL);
780 frame_len = can_skb_get_frame_len(skb);
781 can_put_echo_skb(skb, netdev, seq, frame_len);
782 netdev_sent_queue(netdev, frame_len);
783 WRITE_ONCE(can->tx_idx, can->tx_idx + 1);
784
785 /* Write header to fifo */
786 iowrite32(packet.header[0],
787 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
788 iowrite32(packet.header[1],
789 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
790
791 if (nr_words) {
792 u32 data_last = ((u32 *)packet.data)[nr_words - 1];
793
794 /* Write data to fifo, except last word */
795 iowrite32_rep(can->reg_base +
796 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
797 nr_words - 1);
798 /* Write last word to end of fifo */
799 __raw_writel(data_last, can->reg_base +
800 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
801 } else {
802 /* Complete write to fifo */
803 __raw_writel(0, can->reg_base +
804 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
805 }
806
807 netif_subqueue_maybe_stop(netdev, 0, kvaser_pciefd_tx_avail(can), 1, 1);
808
809 return NETDEV_TX_OK;
810 }
811
kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can * can,bool data)812 static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data)
813 {
814 u32 mode, test, btrn;
815 unsigned long irq_flags;
816 int ret;
817 struct can_bittiming *bt;
818
819 if (data)
820 bt = &can->can.fd.data_bittiming;
821 else
822 bt = &can->can.bittiming;
823
824 btrn = FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK, bt->phase_seg2 - 1) |
825 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK, bt->prop_seg + bt->phase_seg1 - 1) |
826 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_SJW_MASK, bt->sjw - 1) |
827 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_BRP_MASK, bt->brp - 1);
828
829 spin_lock_irqsave(&can->lock, irq_flags);
830 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
831 /* Put the circuit in reset mode */
832 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,
833 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
834
835 /* Can only set bittiming if in reset mode */
836 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
837 test, test & KVASER_PCIEFD_KCAN_MODE_RM, 0, 10);
838 if (ret) {
839 spin_unlock_irqrestore(&can->lock, irq_flags);
840 return -EBUSY;
841 }
842
843 if (data)
844 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
845 else
846 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
847 /* Restore previous reset mode status */
848 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
849 spin_unlock_irqrestore(&can->lock, irq_flags);
850
851 return 0;
852 }
853
kvaser_pciefd_set_nominal_bittiming(struct net_device * ndev)854 static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev)
855 {
856 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false);
857 }
858
kvaser_pciefd_set_data_bittiming(struct net_device * ndev)859 static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev)
860 {
861 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true);
862 }
863
kvaser_pciefd_set_mode(struct net_device * ndev,enum can_mode mode)864 static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode)
865 {
866 struct kvaser_pciefd_can *can = netdev_priv(ndev);
867 int ret = 0;
868
869 switch (mode) {
870 case CAN_MODE_START:
871 if (!can->can.restart_ms)
872 ret = kvaser_pciefd_bus_on(can);
873 break;
874 default:
875 return -EOPNOTSUPP;
876 }
877
878 return ret;
879 }
880
kvaser_pciefd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)881 static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev,
882 struct can_berr_counter *bec)
883 {
884 struct kvaser_pciefd_can *can = netdev_priv(ndev);
885
886 bec->rxerr = can->bec.rxerr;
887 bec->txerr = can->bec.txerr;
888
889 return 0;
890 }
891
kvaser_pciefd_bec_poll_timer(struct timer_list * data)892 static void kvaser_pciefd_bec_poll_timer(struct timer_list *data)
893 {
894 struct kvaser_pciefd_can *can = timer_container_of(can, data,
895 bec_poll_timer);
896
897 kvaser_pciefd_enable_err_gen(can);
898 kvaser_pciefd_request_status(can);
899 can->err_rep_cnt = 0;
900 }
901
902 static const struct net_device_ops kvaser_pciefd_netdev_ops = {
903 .ndo_open = kvaser_pciefd_open,
904 .ndo_stop = kvaser_pciefd_stop,
905 .ndo_eth_ioctl = can_eth_ioctl_hwts,
906 .ndo_start_xmit = kvaser_pciefd_start_xmit,
907 .ndo_change_mtu = can_change_mtu,
908 };
909
kvaser_pciefd_set_phys_id(struct net_device * netdev,enum ethtool_phys_id_state state)910 static int kvaser_pciefd_set_phys_id(struct net_device *netdev,
911 enum ethtool_phys_id_state state)
912 {
913 struct kvaser_pciefd_can *can = netdev_priv(netdev);
914
915 switch (state) {
916 case ETHTOOL_ID_ACTIVE:
917 return 3; /* 3 On/Off cycles per second */
918
919 case ETHTOOL_ID_ON:
920 kvaser_pciefd_set_led(can, true);
921 return 0;
922
923 case ETHTOOL_ID_OFF:
924 case ETHTOOL_ID_INACTIVE:
925 kvaser_pciefd_set_led(can, false);
926 return 0;
927
928 default:
929 return -EINVAL;
930 }
931 }
932
933 static const struct ethtool_ops kvaser_pciefd_ethtool_ops = {
934 .get_ts_info = can_ethtool_op_get_ts_info_hwts,
935 .set_phys_id = kvaser_pciefd_set_phys_id,
936 };
937
kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd * pcie)938 static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
939 {
940 int i;
941
942 for (i = 0; i < pcie->nr_channels; i++) {
943 struct net_device *netdev;
944 struct kvaser_pciefd_can *can;
945 u32 status, tx_nr_packets_max;
946 int ret;
947
948 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
949 roundup_pow_of_two(KVASER_PCIEFD_CAN_TX_MAX_COUNT));
950 if (!netdev)
951 return -ENOMEM;
952
953 can = netdev_priv(netdev);
954 netdev->netdev_ops = &kvaser_pciefd_netdev_ops;
955 netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops;
956 can->reg_base = KVASER_PCIEFD_KCAN_CHX_ADDR(pcie, i);
957 can->kv_pcie = pcie;
958 can->cmd_seq = 0;
959 can->err_rep_cnt = 0;
960 can->completed_tx_pkts = 0;
961 can->completed_tx_bytes = 0;
962 can->bec.txerr = 0;
963 can->bec.rxerr = 0;
964 can->can.dev->dev_port = i;
965
966 init_completion(&can->start_comp);
967 init_completion(&can->flush_comp);
968 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 0);
969
970 /* Disable Bus load reporting */
971 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
972
973 can->ioc = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IOC_REG);
974 kvaser_pciefd_set_led(can, false);
975
976 tx_nr_packets_max =
977 FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK,
978 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
979 can->tx_max_count = min(KVASER_PCIEFD_CAN_TX_MAX_COUNT, tx_nr_packets_max - 1);
980
981 can->can.clock.freq = pcie->freq;
982 spin_lock_init(&can->lock);
983
984 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
985 can->can.fd.data_bittiming_const = &kvaser_pciefd_bittiming_const;
986 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
987 can->can.fd.do_set_data_bittiming = kvaser_pciefd_set_data_bittiming;
988 can->can.do_set_mode = kvaser_pciefd_set_mode;
989 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
990 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
991 CAN_CTRLMODE_FD |
992 CAN_CTRLMODE_FD_NON_ISO |
993 CAN_CTRLMODE_CC_LEN8_DLC |
994 CAN_CTRLMODE_BERR_REPORTING;
995
996 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
997 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
998 dev_err(&pcie->pci->dev,
999 "CAN FD not supported as expected %d\n", i);
1000
1001 free_candev(netdev);
1002 return -ENODEV;
1003 }
1004
1005 if (status & KVASER_PCIEFD_KCAN_STAT_CAP)
1006 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
1007
1008 netdev->flags |= IFF_ECHO;
1009 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
1010
1011 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1012 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1013 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1014
1015 pcie->can[i] = can;
1016 kvaser_pciefd_pwm_start(can);
1017 ret = kvaser_pciefd_devlink_port_register(can);
1018 if (ret) {
1019 dev_err(&pcie->pci->dev, "Failed to register devlink port\n");
1020 return ret;
1021 }
1022 }
1023
1024 return 0;
1025 }
1026
kvaser_pciefd_reg_candev(struct kvaser_pciefd * pcie)1027 static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie)
1028 {
1029 int i;
1030
1031 for (i = 0; i < pcie->nr_channels; i++) {
1032 int ret = register_candev(pcie->can[i]->can.dev);
1033
1034 if (ret) {
1035 int j;
1036
1037 /* Unregister all successfully registered devices. */
1038 for (j = 0; j < i; j++)
1039 unregister_candev(pcie->can[j]->can.dev);
1040 return ret;
1041 }
1042 }
1043
1044 return 0;
1045 }
1046
kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd * pcie,dma_addr_t addr,int index)1047 static void kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd *pcie,
1048 dma_addr_t addr, int index)
1049 {
1050 void __iomem *serdes_base;
1051 u32 word1, word2;
1052
1053 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) {
1054 word1 = lower_32_bits(addr) | KVASER_PCIEFD_ALTERA_DMA_64BIT;
1055 word2 = upper_32_bits(addr);
1056 } else {
1057 word1 = addr;
1058 word2 = 0;
1059 }
1060 serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x8 * index;
1061 iowrite32(word1, serdes_base);
1062 iowrite32(word2, serdes_base + 0x4);
1063 }
1064
kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd * pcie,dma_addr_t addr,int index)1065 static void kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd *pcie,
1066 dma_addr_t addr, int index)
1067 {
1068 void __iomem *serdes_base;
1069 u32 lsb = addr & KVASER_PCIEFD_SF2_DMA_LSB_MASK;
1070 u32 msb = 0x0;
1071
1072 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
1073 msb = upper_32_bits(addr);
1074
1075 serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x10 * index;
1076 iowrite32(lsb, serdes_base);
1077 iowrite32(msb, serdes_base + 0x4);
1078 }
1079
kvaser_pciefd_write_dma_map_xilinx(struct kvaser_pciefd * pcie,dma_addr_t addr,int index)1080 static void kvaser_pciefd_write_dma_map_xilinx(struct kvaser_pciefd *pcie,
1081 dma_addr_t addr, int index)
1082 {
1083 void __iomem *serdes_base;
1084 u32 lsb = addr & KVASER_PCIEFD_XILINX_DMA_LSB_MASK;
1085 u32 msb = 0x0;
1086
1087 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
1088 msb = upper_32_bits(addr);
1089
1090 serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x8 * index;
1091 iowrite32(msb, serdes_base);
1092 iowrite32(lsb, serdes_base + 0x4);
1093 }
1094
kvaser_pciefd_setup_dma(struct kvaser_pciefd * pcie)1095 static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
1096 {
1097 int i;
1098 u32 srb_status;
1099 u32 srb_packet_count;
1100 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT];
1101
1102 /* Disable the DMA */
1103 iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1104
1105 dma_set_mask_and_coherent(&pcie->pci->dev, DMA_BIT_MASK(64));
1106
1107 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1108 pcie->dma_data[i] = dmam_alloc_coherent(&pcie->pci->dev,
1109 KVASER_PCIEFD_DMA_SIZE,
1110 &dma_addr[i],
1111 GFP_KERNEL);
1112
1113 if (!pcie->dma_data[i] || !dma_addr[i]) {
1114 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1115 KVASER_PCIEFD_DMA_SIZE);
1116 return -ENOMEM;
1117 }
1118 pcie->driver_data->ops->kvaser_pciefd_write_dma_map(pcie, dma_addr[i], i);
1119 }
1120
1121 /* Reset Rx FIFO, and both DMA buffers */
1122 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |
1123 KVASER_PCIEFD_SRB_CMD_RDB1,
1124 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1125 /* Empty Rx FIFO */
1126 srb_packet_count =
1127 FIELD_GET(KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK,
1128 ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) +
1129 KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG));
1130 while (srb_packet_count) {
1131 /* Drop current packet in FIFO */
1132 ioread32(KVASER_PCIEFD_SRB_FIFO_ADDR(pcie) + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
1133 srb_packet_count--;
1134 }
1135
1136 srb_status = ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_STAT_REG);
1137 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) {
1138 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
1139 return -EIO;
1140 }
1141
1142 /* Enable the DMA */
1143 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE,
1144 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1145
1146 return 0;
1147 }
1148
kvaser_pciefd_setup_board(struct kvaser_pciefd * pcie)1149 static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1150 {
1151 u32 version, srb_status, build;
1152
1153 version = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_VERSION_REG);
1154 build = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_BUILD_REG);
1155 pcie->nr_channels = min(KVASER_PCIEFD_MAX_CAN_CHANNELS,
1156 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK, version));
1157 pcie->fw_version.major = FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK, version);
1158 pcie->fw_version.minor = FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK, version);
1159 pcie->fw_version.build = FIELD_GET(KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK, build);
1160
1161 srb_status = ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_STAT_REG);
1162 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1163 dev_err(&pcie->pci->dev, "Hardware without DMA is not supported\n");
1164 return -ENODEV;
1165 }
1166
1167 pcie->bus_freq = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_BUSFREQ_REG);
1168 pcie->freq = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1169 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1170 if (pcie->freq_to_ticks_div == 0)
1171 pcie->freq_to_ticks_div = 1;
1172 /* Turn off all loopback functionality */
1173 iowrite32(0, KVASER_PCIEFD_LOOPBACK_ADDR(pcie));
1174
1175 return 0;
1176 }
1177
kvaser_pciefd_handle_data_packet(struct kvaser_pciefd * pcie,struct kvaser_pciefd_rx_packet * p,__le32 * data)1178 static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
1179 struct kvaser_pciefd_rx_packet *p,
1180 __le32 *data)
1181 {
1182 struct sk_buff *skb;
1183 struct canfd_frame *cf;
1184 struct can_priv *priv;
1185 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1186 u8 dlc;
1187
1188 if (ch_id >= pcie->nr_channels)
1189 return -EIO;
1190
1191 priv = &pcie->can[ch_id]->can;
1192 dlc = FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK, p->header[1]);
1193
1194 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1195 skb = alloc_canfd_skb(priv->dev, &cf);
1196 if (!skb) {
1197 priv->dev->stats.rx_dropped++;
1198 return 0;
1199 }
1200
1201 cf->len = can_fd_dlc2len(dlc);
1202 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1203 cf->flags |= CANFD_BRS;
1204 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1205 cf->flags |= CANFD_ESI;
1206 } else {
1207 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1208 if (!skb) {
1209 priv->dev->stats.rx_dropped++;
1210 return 0;
1211 }
1212 can_frame_set_cc_len((struct can_frame *)cf, dlc, priv->ctrlmode);
1213 }
1214
1215 cf->can_id = FIELD_GET(KVASER_PCIEFD_RPACKET_ID_MASK, p->header[0]);
1216 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1217 cf->can_id |= CAN_EFF_FLAG;
1218
1219 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {
1220 cf->can_id |= CAN_RTR_FLAG;
1221 } else {
1222 memcpy(cf->data, data, cf->len);
1223 priv->dev->stats.rx_bytes += cf->len;
1224 }
1225 priv->dev->stats.rx_packets++;
1226 kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1227
1228 netif_rx(skb);
1229
1230 return 0;
1231 }
1232
kvaser_pciefd_change_state(struct kvaser_pciefd_can * can,const struct can_berr_counter * bec,struct can_frame * cf,enum can_state new_state,enum can_state tx_state,enum can_state rx_state)1233 static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can,
1234 const struct can_berr_counter *bec,
1235 struct can_frame *cf,
1236 enum can_state new_state,
1237 enum can_state tx_state,
1238 enum can_state rx_state)
1239 {
1240 enum can_state old_state;
1241
1242 old_state = can->can.state;
1243 can_change_state(can->can.dev, cf, tx_state, rx_state);
1244
1245 if (new_state == CAN_STATE_BUS_OFF) {
1246 struct net_device *ndev = can->can.dev;
1247 unsigned long irq_flags;
1248
1249 spin_lock_irqsave(&can->lock, irq_flags);
1250 netif_stop_queue(can->can.dev);
1251 spin_unlock_irqrestore(&can->lock, irq_flags);
1252 /* Prevent CAN controller from auto recover from bus off */
1253 if (!can->can.restart_ms) {
1254 kvaser_pciefd_start_controller_flush(can);
1255 can_bus_off(ndev);
1256 }
1257 }
1258 if (old_state == CAN_STATE_BUS_OFF &&
1259 new_state == CAN_STATE_ERROR_ACTIVE &&
1260 can->can.restart_ms) {
1261 can->can.can_stats.restarts++;
1262 if (cf)
1263 cf->can_id |= CAN_ERR_RESTARTED;
1264 }
1265 if (cf && new_state != CAN_STATE_BUS_OFF) {
1266 cf->can_id |= CAN_ERR_CNT;
1267 cf->data[6] = bec->txerr;
1268 cf->data[7] = bec->rxerr;
1269 }
1270 }
1271
kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet * p,struct can_berr_counter * bec,enum can_state * new_state,enum can_state * tx_state,enum can_state * rx_state)1272 static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p,
1273 struct can_berr_counter *bec,
1274 enum can_state *new_state,
1275 enum can_state *tx_state,
1276 enum can_state *rx_state)
1277 {
1278 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||
1279 p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1280 *new_state = CAN_STATE_BUS_OFF;
1281 else if (bec->txerr >= 255 || bec->rxerr >= 255)
1282 *new_state = CAN_STATE_BUS_OFF;
1283 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1284 *new_state = CAN_STATE_ERROR_PASSIVE;
1285 else if (bec->txerr >= 128 || bec->rxerr >= 128)
1286 *new_state = CAN_STATE_ERROR_PASSIVE;
1287 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR)
1288 *new_state = CAN_STATE_ERROR_WARNING;
1289 else if (bec->txerr >= 96 || bec->rxerr >= 96)
1290 *new_state = CAN_STATE_ERROR_WARNING;
1291 else
1292 *new_state = CAN_STATE_ERROR_ACTIVE;
1293
1294 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0;
1295 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;
1296 }
1297
kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can * can,struct kvaser_pciefd_rx_packet * p)1298 static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can,
1299 struct kvaser_pciefd_rx_packet *p)
1300 {
1301 struct can_berr_counter bec;
1302 enum can_state old_state, new_state, tx_state, rx_state;
1303 struct net_device *ndev = can->can.dev;
1304 struct sk_buff *skb = NULL;
1305 struct can_frame *cf = NULL;
1306
1307 old_state = can->can.state;
1308
1309 bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
1310 bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1311
1312 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1313 if (can->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1314 skb = alloc_can_err_skb(ndev, &cf);
1315 if (new_state != old_state) {
1316 kvaser_pciefd_change_state(can, &bec, cf, new_state, tx_state, rx_state);
1317 }
1318
1319 can->err_rep_cnt++;
1320 can->can.can_stats.bus_error++;
1321 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)
1322 ndev->stats.tx_errors++;
1323 else
1324 ndev->stats.rx_errors++;
1325
1326 can->bec.txerr = bec.txerr;
1327 can->bec.rxerr = bec.rxerr;
1328
1329 if (can->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) {
1330 if (!skb) {
1331 netdev_warn(ndev, "No memory left for err_skb\n");
1332 ndev->stats.rx_dropped++;
1333 return -ENOMEM;
1334 }
1335 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1336 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_CNT;
1337 cf->data[6] = bec.txerr;
1338 cf->data[7] = bec.rxerr;
1339 netif_rx(skb);
1340 }
1341
1342 return 0;
1343 }
1344
kvaser_pciefd_handle_error_packet(struct kvaser_pciefd * pcie,struct kvaser_pciefd_rx_packet * p)1345 static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
1346 struct kvaser_pciefd_rx_packet *p)
1347 {
1348 struct kvaser_pciefd_can *can;
1349 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1350
1351 if (ch_id >= pcie->nr_channels)
1352 return -EIO;
1353
1354 can = pcie->can[ch_id];
1355 kvaser_pciefd_rx_error_frame(can, p);
1356 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1357 /* Do not report more errors, until bec_poll_timer expires */
1358 kvaser_pciefd_disable_err_gen(can);
1359 /* Start polling the error counters */
1360 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1361
1362 return 0;
1363 }
1364
kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can * can,struct kvaser_pciefd_rx_packet * p)1365 static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can,
1366 struct kvaser_pciefd_rx_packet *p)
1367 {
1368 struct can_berr_counter bec;
1369 enum can_state old_state, new_state, tx_state, rx_state;
1370 int ret = 0;
1371
1372 old_state = can->can.state;
1373
1374 bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
1375 bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1376
1377 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1378 if (new_state != old_state) {
1379 struct net_device *ndev = can->can.dev;
1380 struct sk_buff *skb;
1381 struct can_frame *cf;
1382
1383 skb = alloc_can_err_skb(ndev, &cf);
1384 kvaser_pciefd_change_state(can, &bec, cf, new_state, tx_state, rx_state);
1385 if (skb) {
1386 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1387 netif_rx(skb);
1388 } else {
1389 ndev->stats.rx_dropped++;
1390 netdev_warn(ndev, "No memory left for err_skb\n");
1391 ret = -ENOMEM;
1392 }
1393 }
1394 can->bec.txerr = bec.txerr;
1395 can->bec.rxerr = bec.rxerr;
1396 /* Check if we need to poll the error counters */
1397 if (bec.txerr || bec.rxerr)
1398 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1399
1400 return ret;
1401 }
1402
kvaser_pciefd_handle_status_packet(struct kvaser_pciefd * pcie,struct kvaser_pciefd_rx_packet * p)1403 static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
1404 struct kvaser_pciefd_rx_packet *p)
1405 {
1406 struct kvaser_pciefd_can *can;
1407 u8 cmdseq;
1408 u32 status;
1409 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1410
1411 if (ch_id >= pcie->nr_channels)
1412 return -EIO;
1413
1414 can = pcie->can[ch_id];
1415
1416 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1417 cmdseq = FIELD_GET(KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK, status);
1418
1419 /* Reset done, start abort and flush */
1420 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1421 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1422 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1423 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1424 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1425 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1426 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1427 kvaser_pciefd_abort_flush_reset(can);
1428 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1429 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1430 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1431 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1432 /* Reset detected, send end of flush if no packet are in FIFO */
1433 u8 count;
1434
1435 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
1436 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1437 if (!count)
1438 iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK,
1439 KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH),
1440 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1441 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1442 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1])) {
1443 /* Response to status request received */
1444 kvaser_pciefd_handle_status_resp(can, p);
1445 if (can->can.state != CAN_STATE_BUS_OFF &&
1446 can->can.state != CAN_STATE_ERROR_ACTIVE) {
1447 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1448 }
1449 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1450 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK)) {
1451 /* Reset to bus on detected */
1452 if (!completion_done(&can->start_comp))
1453 complete(&can->start_comp);
1454 }
1455
1456 return 0;
1457 }
1458
kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can * can,struct kvaser_pciefd_rx_packet * p)1459 static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1460 struct kvaser_pciefd_rx_packet *p)
1461 {
1462 struct sk_buff *skb;
1463 struct can_frame *cf;
1464
1465 skb = alloc_can_err_skb(can->can.dev, &cf);
1466 can->can.dev->stats.tx_errors++;
1467 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1468 if (skb)
1469 cf->can_id |= CAN_ERR_LOSTARB;
1470 can->can.can_stats.arbitration_lost++;
1471 } else if (skb) {
1472 cf->can_id |= CAN_ERR_ACK;
1473 }
1474
1475 if (skb) {
1476 cf->can_id |= CAN_ERR_BUSERROR;
1477 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1478 netif_rx(skb);
1479 } else {
1480 can->can.dev->stats.rx_dropped++;
1481 netdev_warn(can->can.dev, "No memory left for err_skb\n");
1482 }
1483 }
1484
kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd * pcie,struct kvaser_pciefd_rx_packet * p)1485 static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
1486 struct kvaser_pciefd_rx_packet *p)
1487 {
1488 struct kvaser_pciefd_can *can;
1489 bool one_shot_fail = false;
1490 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1491
1492 if (ch_id >= pcie->nr_channels)
1493 return -EIO;
1494
1495 can = pcie->can[ch_id];
1496 /* Ignore control packet ACK */
1497 if (p->header[0] & KVASER_PCIEFD_APACKET_CT)
1498 return 0;
1499
1500 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) {
1501 kvaser_pciefd_handle_nack_packet(can, p);
1502 one_shot_fail = true;
1503 }
1504
1505 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1506 netdev_dbg(can->can.dev, "Packet was flushed\n");
1507 } else {
1508 int echo_idx = FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[0]);
1509 unsigned int len, frame_len = 0;
1510 struct sk_buff *skb;
1511
1512 if (echo_idx != (can->ack_idx & (can->can.echo_skb_max - 1)))
1513 return 0;
1514 skb = can->can.echo_skb[echo_idx];
1515 if (!skb)
1516 return 0;
1517 kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1518 len = can_get_echo_skb(can->can.dev, echo_idx, &frame_len);
1519
1520 /* Pairs with barrier in kvaser_pciefd_start_xmit() */
1521 smp_store_release(&can->ack_idx, can->ack_idx + 1);
1522 can->completed_tx_pkts++;
1523 can->completed_tx_bytes += frame_len;
1524
1525 if (!one_shot_fail) {
1526 can->can.dev->stats.tx_bytes += len;
1527 can->can.dev->stats.tx_packets++;
1528 }
1529 }
1530
1531 return 0;
1532 }
1533
kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd * pcie,struct kvaser_pciefd_rx_packet * p)1534 static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
1535 struct kvaser_pciefd_rx_packet *p)
1536 {
1537 struct kvaser_pciefd_can *can;
1538 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1539
1540 if (ch_id >= pcie->nr_channels)
1541 return -EIO;
1542
1543 can = pcie->can[ch_id];
1544
1545 if (!completion_done(&can->flush_comp))
1546 complete(&can->flush_comp);
1547
1548 return 0;
1549 }
1550
kvaser_pciefd_read_packet(struct kvaser_pciefd * pcie,int * start_pos,int dma_buf)1551 static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
1552 int dma_buf)
1553 {
1554 __le32 *buffer = pcie->dma_data[dma_buf];
1555 __le64 timestamp;
1556 struct kvaser_pciefd_rx_packet packet;
1557 struct kvaser_pciefd_rx_packet *p = &packet;
1558 u8 type;
1559 int pos = *start_pos;
1560 int size;
1561 int ret = 0;
1562
1563 size = le32_to_cpu(buffer[pos++]);
1564 if (!size) {
1565 *start_pos = 0;
1566 return 0;
1567 }
1568
1569 p->header[0] = le32_to_cpu(buffer[pos++]);
1570 p->header[1] = le32_to_cpu(buffer[pos++]);
1571
1572 /* Read 64-bit timestamp */
1573 memcpy(×tamp, &buffer[pos], sizeof(__le64));
1574 pos += 2;
1575 p->timestamp = le64_to_cpu(timestamp);
1576
1577 type = FIELD_GET(KVASER_PCIEFD_PACKET_TYPE_MASK, p->header[1]);
1578 switch (type) {
1579 case KVASER_PCIEFD_PACK_TYPE_DATA:
1580 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1581 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1582 u8 data_len;
1583
1584 data_len = can_fd_dlc2len(FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK,
1585 p->header[1]));
1586 pos += DIV_ROUND_UP(data_len, 4);
1587 }
1588 break;
1589
1590 case KVASER_PCIEFD_PACK_TYPE_ACK:
1591 ret = kvaser_pciefd_handle_ack_packet(pcie, p);
1592 break;
1593
1594 case KVASER_PCIEFD_PACK_TYPE_STATUS:
1595 ret = kvaser_pciefd_handle_status_packet(pcie, p);
1596 break;
1597
1598 case KVASER_PCIEFD_PACK_TYPE_ERROR:
1599 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1600 break;
1601
1602 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1603 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1604 break;
1605
1606 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1607 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
1608 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1609 case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1610 dev_info(&pcie->pci->dev,
1611 "Received unexpected packet type 0x%08X\n", type);
1612 break;
1613
1614 default:
1615 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);
1616 ret = -EIO;
1617 break;
1618 }
1619
1620 if (ret)
1621 return ret;
1622
1623 /* Position does not point to the end of the package,
1624 * corrupted packet size?
1625 */
1626 if (unlikely((*start_pos + size) != pos))
1627 return -EIO;
1628
1629 /* Point to the next packet header, if any */
1630 *start_pos = pos;
1631
1632 return ret;
1633 }
1634
kvaser_pciefd_read_buffer(struct kvaser_pciefd * pcie,int dma_buf)1635 static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf)
1636 {
1637 int pos = 0;
1638 int res = 0;
1639 unsigned int i;
1640
1641 do {
1642 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf);
1643 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE);
1644
1645 /* Report ACKs in this buffer to BQL en masse for correct periods */
1646 for (i = 0; i < pcie->nr_channels; ++i) {
1647 struct kvaser_pciefd_can *can = pcie->can[i];
1648
1649 if (!can->completed_tx_pkts)
1650 continue;
1651 netif_subqueue_completed_wake(can->can.dev, 0,
1652 can->completed_tx_pkts,
1653 can->completed_tx_bytes,
1654 kvaser_pciefd_tx_avail(can), 1);
1655 can->completed_tx_pkts = 0;
1656 can->completed_tx_bytes = 0;
1657 }
1658
1659 return res;
1660 }
1661
kvaser_pciefd_receive_irq(struct kvaser_pciefd * pcie)1662 static void kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1663 {
1664 void __iomem *srb_cmd_reg = KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG;
1665 u32 irq = ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IRQ_REG);
1666
1667 iowrite32(irq, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IRQ_REG);
1668
1669 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) {
1670 kvaser_pciefd_read_buffer(pcie, 0);
1671 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0, srb_cmd_reg); /* Rearm buffer */
1672 }
1673
1674 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) {
1675 kvaser_pciefd_read_buffer(pcie, 1);
1676 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1, srb_cmd_reg); /* Rearm buffer */
1677 }
1678
1679 if (unlikely(irq & KVASER_PCIEFD_SRB_IRQ_DOF0 ||
1680 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 ||
1681 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 ||
1682 irq & KVASER_PCIEFD_SRB_IRQ_DUF1))
1683 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1684 }
1685
kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can * can)1686 static void kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1687 {
1688 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1689
1690 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF)
1691 netdev_err(can->can.dev, "Tx FIFO overflow\n");
1692
1693 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP)
1694 netdev_err(can->can.dev,
1695 "Fail to change bittiming, when not in reset mode\n");
1696
1697 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC)
1698 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n");
1699
1700 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF)
1701 netdev_err(can->can.dev, "Rx FIFO overflow\n");
1702
1703 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1704 }
1705
kvaser_pciefd_irq_handler(int irq,void * dev)1706 static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
1707 {
1708 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev;
1709 const struct kvaser_pciefd_irq_mask *irq_mask = pcie->driver_data->irq_mask;
1710 u32 pci_irq = ioread32(KVASER_PCIEFD_PCI_IRQ_ADDR(pcie));
1711 int i;
1712
1713 if (!(pci_irq & irq_mask->all))
1714 return IRQ_NONE;
1715
1716 iowrite32(0, KVASER_PCIEFD_PCI_IEN_ADDR(pcie));
1717
1718 if (pci_irq & irq_mask->kcan_rx0)
1719 kvaser_pciefd_receive_irq(pcie);
1720
1721 for (i = 0; i < pcie->nr_channels; i++) {
1722 if (pci_irq & irq_mask->kcan_tx[i])
1723 kvaser_pciefd_transmit_irq(pcie->can[i]);
1724 }
1725
1726 iowrite32(irq_mask->all, KVASER_PCIEFD_PCI_IEN_ADDR(pcie));
1727
1728 return IRQ_HANDLED;
1729 }
1730
kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd * pcie)1731 static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1732 {
1733 int i;
1734
1735 for (i = 0; i < pcie->nr_channels; i++) {
1736 struct kvaser_pciefd_can *can = pcie->can[i];
1737
1738 if (can) {
1739 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1740 kvaser_pciefd_pwm_stop(can);
1741 kvaser_pciefd_devlink_port_unregister(can);
1742 free_candev(can->can.dev);
1743 }
1744 }
1745 }
1746
kvaser_pciefd_disable_irq_srcs(struct kvaser_pciefd * pcie)1747 static void kvaser_pciefd_disable_irq_srcs(struct kvaser_pciefd *pcie)
1748 {
1749 unsigned int i;
1750
1751 /* Masking PCI_IRQ is insufficient as running ISR will unmask it */
1752 iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IEN_REG);
1753 for (i = 0; i < pcie->nr_channels; ++i)
1754 iowrite32(0, pcie->can[i]->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1755 }
1756
kvaser_pciefd_probe(struct pci_dev * pdev,const struct pci_device_id * id)1757 static int kvaser_pciefd_probe(struct pci_dev *pdev,
1758 const struct pci_device_id *id)
1759 {
1760 int ret;
1761 struct devlink *devlink;
1762 struct device *dev = &pdev->dev;
1763 struct kvaser_pciefd *pcie;
1764 const struct kvaser_pciefd_irq_mask *irq_mask;
1765
1766 devlink = devlink_alloc(&kvaser_pciefd_devlink_ops, sizeof(*pcie), dev);
1767 if (!devlink)
1768 return -ENOMEM;
1769
1770 pcie = devlink_priv(devlink);
1771 pci_set_drvdata(pdev, pcie);
1772 pcie->pci = pdev;
1773 pcie->driver_data = (const struct kvaser_pciefd_driver_data *)id->driver_data;
1774 irq_mask = pcie->driver_data->irq_mask;
1775
1776 ret = pci_enable_device(pdev);
1777 if (ret)
1778 goto err_free_devlink;
1779
1780 ret = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME);
1781 if (ret)
1782 goto err_disable_pci;
1783
1784 pcie->reg_base = pci_iomap(pdev, 0, 0);
1785 if (!pcie->reg_base) {
1786 ret = -ENOMEM;
1787 goto err_release_regions;
1788 }
1789
1790 ret = kvaser_pciefd_setup_board(pcie);
1791 if (ret)
1792 goto err_pci_iounmap;
1793
1794 ret = kvaser_pciefd_setup_dma(pcie);
1795 if (ret)
1796 goto err_pci_iounmap;
1797
1798 pci_set_master(pdev);
1799
1800 ret = kvaser_pciefd_setup_can_ctrls(pcie);
1801 if (ret)
1802 goto err_teardown_can_ctrls;
1803
1804 ret = pci_alloc_irq_vectors(pcie->pci, 1, 1, PCI_IRQ_INTX | PCI_IRQ_MSI);
1805 if (ret < 0) {
1806 dev_err(dev, "Failed to allocate IRQ vectors.\n");
1807 goto err_teardown_can_ctrls;
1808 }
1809
1810 ret = pci_irq_vector(pcie->pci, 0);
1811 if (ret < 0)
1812 goto err_pci_free_irq_vectors;
1813
1814 pcie->pci->irq = ret;
1815
1816 ret = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,
1817 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);
1818 if (ret) {
1819 dev_err(dev, "Failed to request IRQ %d\n", pcie->pci->irq);
1820 goto err_pci_free_irq_vectors;
1821 }
1822 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1,
1823 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IRQ_REG);
1824
1825 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 |
1826 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 |
1827 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,
1828 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IEN_REG);
1829
1830 /* Enable PCI interrupts */
1831 iowrite32(irq_mask->all, KVASER_PCIEFD_PCI_IEN_ADDR(pcie));
1832 /* Ready the DMA buffers */
1833 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1834 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1835 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1836 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1837
1838 ret = kvaser_pciefd_reg_candev(pcie);
1839 if (ret)
1840 goto err_free_irq;
1841
1842 devlink_register(devlink);
1843
1844 return 0;
1845
1846 err_free_irq:
1847 kvaser_pciefd_disable_irq_srcs(pcie);
1848 free_irq(pcie->pci->irq, pcie);
1849
1850 err_pci_free_irq_vectors:
1851 pci_free_irq_vectors(pcie->pci);
1852
1853 err_teardown_can_ctrls:
1854 kvaser_pciefd_teardown_can_ctrls(pcie);
1855 iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1856 pci_clear_master(pdev);
1857
1858 err_pci_iounmap:
1859 pci_iounmap(pdev, pcie->reg_base);
1860
1861 err_release_regions:
1862 pci_release_regions(pdev);
1863
1864 err_disable_pci:
1865 pci_disable_device(pdev);
1866
1867 err_free_devlink:
1868 devlink_free(devlink);
1869
1870 return ret;
1871 }
1872
kvaser_pciefd_remove(struct pci_dev * pdev)1873 static void kvaser_pciefd_remove(struct pci_dev *pdev)
1874 {
1875 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev);
1876 unsigned int i;
1877
1878 for (i = 0; i < pcie->nr_channels; ++i) {
1879 struct kvaser_pciefd_can *can = pcie->can[i];
1880
1881 unregister_candev(can->can.dev);
1882 timer_delete(&can->bec_poll_timer);
1883 kvaser_pciefd_pwm_stop(can);
1884 kvaser_pciefd_devlink_port_unregister(can);
1885 }
1886
1887 kvaser_pciefd_disable_irq_srcs(pcie);
1888 free_irq(pcie->pci->irq, pcie);
1889 pci_free_irq_vectors(pcie->pci);
1890
1891 for (i = 0; i < pcie->nr_channels; ++i)
1892 free_candev(pcie->can[i]->can.dev);
1893
1894 devlink_unregister(priv_to_devlink(pcie));
1895 pci_iounmap(pdev, pcie->reg_base);
1896 pci_release_regions(pdev);
1897 pci_disable_device(pdev);
1898 devlink_free(priv_to_devlink(pcie));
1899 }
1900
1901 static struct pci_driver kvaser_pciefd = {
1902 .name = KVASER_PCIEFD_DRV_NAME,
1903 .id_table = kvaser_pciefd_id_table,
1904 .probe = kvaser_pciefd_probe,
1905 .remove = kvaser_pciefd_remove,
1906 };
1907
1908 module_pci_driver(kvaser_pciefd)
1909