xref: /linux/arch/mips/include/asm/dec/ecc.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *	include/asm-mips/dec/ecc.h
4  *
5  *	ECC handling logic definitions common to DECstation/DECsystem
6  *	5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
7  *	DECsystem 5900 (KN03), 5900/260 (KN05) systems.
8  *
9  *	Copyright (C) 2003  Maciej W. Rozycki
10  */
11 #ifndef __ASM_MIPS_DEC_ECC_H
12 #define __ASM_MIPS_DEC_ECC_H
13 
14 /*
15  * Error Address Register bits.
16  * The register is r/wc -- any write clears it.
17  */
18 #define KN0X_EAR_VALID		(1<<31)		/* error data valid, bus IRQ */
19 #define KN0X_EAR_CPU		(1<<30)		/* CPU/DMA transaction */
20 #define KN0X_EAR_WRITE		(1<<29)		/* write/read transaction */
21 #define KN0X_EAR_ECCERR		(1<<28)		/* ECC/timeout or overrun */
22 #define KN0X_EAR_RES_27		(1<<27)		/* unused */
23 #define KN0X_EAR_ADDRESS	(0x7ffffff<<0)	/* address involved */
24 
25 /*
26  * Error Syndrome Register bits.
27  * The register is frozen when EAR.VALID is set, otherwise it records bits
28  * from the last memory read.  The register is r/wc -- any write clears it.
29  */
30 #define KN0X_ESR_VLDHI		(1<<31)		/* error data valid hi word */
31 #define KN0X_ESR_CHKHI		(0x7f<<24)	/* check bits read from mem */
32 #define KN0X_ESR_SNGHI		(1<<23)		/* single/double bit error */
33 #define KN0X_ESR_SYNHI		(0x7f<<16)	/* syndrome from ECC logic */
34 #define KN0X_ESR_VLDLO		(1<<15)		/* error data valid lo word */
35 #define KN0X_ESR_CHKLO		(0x7f<<8)	/* check bits read from mem */
36 #define KN0X_ESR_SNGLO		(1<<7)		/* single/double bit error */
37 #define KN0X_ESR_SYNLO		(0x7f<<0)	/* syndrome from ECC logic */
38 
39 
40 #ifndef __ASSEMBLY__
41 
42 #include <linux/interrupt.h>
43 
44 struct pt_regs;
45 
46 extern void dec_ecc_be_init(void);
47 extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
48 extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
49 #endif
50 
51 #endif /* __ASM_MIPS_DEC_ECC_H */
52