xref: /linux/arch/powerpc/include/asm/keylargo.h (revision 498495dba268b20e8eadd7fe93c140c68b6cc9d2)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_KEYLARGO_H
3 #define _ASM_POWERPC_KEYLARGO_H
4 #ifdef __KERNEL__
5 /*
6  * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
7  *
8  */
9 
10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11  * has device-id 0x22. The rev. of the pangea one is 0, so we
12  * fake an artificial rev. in keylargo_rev by oring 0x100
13  */
14 #define KL_PANGEA_REV		0x100
15 
16 /* offset from base for feature control registers */
17 #define KEYLARGO_MBCR		0x34	/* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0		0x38
19 #define KEYLARGO_FCR1		0x3c
20 #define KEYLARGO_FCR2		0x40
21 #define KEYLARGO_FCR3		0x44
22 #define KEYLARGO_FCR4		0x48
23 #define KEYLARGO_FCR5		0x4c	/* Pangea only */
24 
25 /* K2 additional FCRs */
26 #define K2_FCR6			0x34
27 #define K2_FCR7			0x30
28 #define K2_FCR8			0x2c
29 #define K2_FCR9			0x28
30 #define K2_FCR10		0x24
31 
32 /* GPIO registers */
33 #define KEYLARGO_GPIO_LEVELS0		0x50
34 #define KEYLARGO_GPIO_LEVELS1		0x54
35 #define KEYLARGO_GPIO_EXTINT_0		0x58
36 #define KEYLARGO_GPIO_EXTINT_CNT	18
37 #define KEYLARGO_GPIO_0			0x6A
38 #define KEYLARGO_GPIO_CNT		17
39 #define KEYLARGO_GPIO_EXTINT_DUAL_EDGE	0x80
40 #define KEYLARGO_GPIO_OUTPUT_ENABLE	0x04
41 #define KEYLARGO_GPIO_OUTOUT_DATA	0x01
42 #define KEYLARGO_GPIO_INPUT_DATA	0x02
43 
44 /* K2 does only extint GPIOs and does 51 of them */
45 #define K2_GPIO_EXTINT_0		0x58
46 #define K2_GPIO_EXTINT_CNT		51
47 
48 /* Specific GPIO regs */
49 
50 #define KL_GPIO_MODEM_RESET		(KEYLARGO_GPIO_0+0x03)
51 #define KL_GPIO_MODEM_POWER		(KEYLARGO_GPIO_0+0x02) /* Pangea */
52 
53 #define KL_GPIO_SOUND_POWER		(KEYLARGO_GPIO_0+0x05)
54 
55 /* Hrm... this one is only to be used on Pismo. It seems to also
56  * control the timebase enable on other machines. Still to be
57  * experimented... --BenH.
58  */
59 #define KL_GPIO_FW_CABLE_POWER		(KEYLARGO_GPIO_0+0x09)
60 #define KL_GPIO_TB_ENABLE		(KEYLARGO_GPIO_0+0x09)
61 
62 #define KL_GPIO_ETH_PHY_RESET		(KEYLARGO_GPIO_0+0x10)
63 
64 #define KL_GPIO_EXTINT_CPU1		(KEYLARGO_GPIO_0+0x0a)
65 #define KL_GPIO_EXTINT_CPU1_ASSERT	0x04
66 #define KL_GPIO_EXTINT_CPU1_RELEASE	0x38
67 
68 #define KL_GPIO_RESET_CPU0		(KEYLARGO_GPIO_EXTINT_0+0x03)
69 #define KL_GPIO_RESET_CPU1		(KEYLARGO_GPIO_EXTINT_0+0x04)
70 #define KL_GPIO_RESET_CPU2		(KEYLARGO_GPIO_EXTINT_0+0x0f)
71 #define KL_GPIO_RESET_CPU3		(KEYLARGO_GPIO_EXTINT_0+0x10)
72 
73 #define KL_GPIO_PMU_MESSAGE_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x09)
74 #define KL_GPIO_PMU_MESSAGE_BIT		KEYLARGO_GPIO_INPUT_DATA
75 
76 #define KL_GPIO_MEDIABAY_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x0e)
77 
78 #define KL_GPIO_AIRPORT_0		(KEYLARGO_GPIO_EXTINT_0+0x0a)
79 #define KL_GPIO_AIRPORT_1		(KEYLARGO_GPIO_EXTINT_0+0x0d)
80 #define KL_GPIO_AIRPORT_2		(KEYLARGO_GPIO_0+0x0d)
81 #define KL_GPIO_AIRPORT_3		(KEYLARGO_GPIO_0+0x0e)
82 #define KL_GPIO_AIRPORT_4		(KEYLARGO_GPIO_0+0x0f)
83 
84 /*
85  * Bits in feature control register. Those bits different for K2 are
86  * listed separately
87  */
88 #define KL_MBCR_MB0_PCI_ENABLE		0x00000800	/* exist ? */
89 #define KL_MBCR_MB0_IDE_ENABLE		0x00001000
90 #define KL_MBCR_MB0_FLOPPY_ENABLE	0x00002000	/* exist ? */
91 #define KL_MBCR_MB0_SOUND_ENABLE	0x00004000	/* hrm... */
92 #define KL_MBCR_MB0_DEV_MASK		0x00007800
93 #define KL_MBCR_MB0_DEV_POWER		0x00000400
94 #define KL_MBCR_MB0_DEV_RESET		0x00000200
95 #define KL_MBCR_MB0_ENABLE		0x00000100
96 #define KL_MBCR_MB1_PCI_ENABLE		0x08000000	/* exist ? */
97 #define KL_MBCR_MB1_IDE_ENABLE		0x10000000
98 #define KL_MBCR_MB1_FLOPPY_ENABLE	0x20000000	/* exist ? */
99 #define KL_MBCR_MB1_SOUND_ENABLE	0x40000000	/* hrm... */
100 #define KL_MBCR_MB1_DEV_MASK		0x78000000
101 #define KL_MBCR_MB1_DEV_POWER		0x04000000
102 #define KL_MBCR_MB1_DEV_RESET		0x02000000
103 #define KL_MBCR_MB1_ENABLE		0x01000000
104 
105 #define KL0_SCC_B_INTF_ENABLE		0x00000001	/* (KL Only) */
106 #define KL0_SCC_A_INTF_ENABLE		0x00000002
107 #define KL0_SCC_SLOWPCLK		0x00000004
108 #define KL0_SCC_RESET			0x00000008
109 #define KL0_SCCA_ENABLE			0x00000010
110 #define KL0_SCCB_ENABLE			0x00000020
111 #define KL0_SCC_CELL_ENABLE		0x00000040
112 #define KL0_IRDA_HIGH_BAND		0x00000100	/* (KL Only) */
113 #define KL0_IRDA_SOURCE2_SEL		0x00000200	/* (KL Only) */
114 #define KL0_IRDA_SOURCE1_SEL		0x00000400	/* (KL Only) */
115 #define KL0_PG_USB0_PMI_ENABLE		0x00000400	/* (Pangea/Intrepid Only) */
116 #define KL0_IRDA_RESET			0x00000800	/* (KL Only) */
117 #define KL0_PG_USB0_REF_SUSPEND_SEL	0x00000800	/* (Pangea/Intrepid Only) */
118 #define KL0_IRDA_DEFAULT1		0x00001000	/* (KL Only) */
119 #define KL0_PG_USB0_REF_SUSPEND		0x00001000	/* (Pangea/Intrepid Only) */
120 #define KL0_IRDA_DEFAULT0		0x00002000	/* (KL Only) */
121 #define KL0_PG_USB0_PAD_SUSPEND		0x00002000	/* (Pangea/Intrepid Only) */
122 #define KL0_IRDA_FAST_CONNECT		0x00004000	/* (KL Only) */
123 #define KL0_PG_USB1_PMI_ENABLE		0x00004000	/* (Pangea/Intrepid Only) */
124 #define KL0_IRDA_ENABLE			0x00008000	/* (KL Only) */
125 #define KL0_PG_USB1_REF_SUSPEND_SEL	0x00008000	/* (Pangea/Intrepid Only) */
126 #define KL0_IRDA_CLK32_ENABLE		0x00010000	/* (KL Only) */
127 #define KL0_PG_USB1_REF_SUSPEND		0x00010000	/* (Pangea/Intrepid Only) */
128 #define KL0_IRDA_CLK19_ENABLE		0x00020000	/* (KL Only) */
129 #define KL0_PG_USB1_PAD_SUSPEND		0x00020000	/* (Pangea/Intrepid Only) */
130 #define KL0_USB0_PAD_SUSPEND0		0x00040000
131 #define KL0_USB0_PAD_SUSPEND1		0x00080000
132 #define KL0_USB0_CELL_ENABLE		0x00100000
133 #define KL0_USB1_PAD_SUSPEND0		0x00400000
134 #define KL0_USB1_PAD_SUSPEND1		0x00800000
135 #define KL0_USB1_CELL_ENABLE		0x01000000
136 #define KL0_USB_REF_SUSPEND		0x10000000	/* (KL Only) */
137 
138 #define KL0_SERIAL_ENABLE		(KL0_SCC_B_INTF_ENABLE | \
139 					KL0_SCC_SLOWPCLK | \
140 					KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
141 
142 #define KL1_USB2_PMI_ENABLE		0x00000001	/* Intrepid only */
143 #define KL1_AUDIO_SEL_22MCLK		0x00000002	/* KL/Pangea only */
144 #define KL1_USB2_REF_SUSPEND_SEL	0x00000002	/* Intrepid only */
145 #define KL1_USB2_REF_SUSPEND		0x00000004	/* Intrepid only */
146 #define KL1_AUDIO_CLK_ENABLE_BIT	0x00000008	/* KL/Pangea only */
147 #define KL1_USB2_PAD_SUSPEND_SEL	0x00000008	/* Intrepid only */
148 #define KL1_USB2_PAD_SUSPEND0		0x00000010	/* Intrepid only */
149 #define KL1_AUDIO_CLK_OUT_ENABLE	0x00000020	/* KL/Pangea only */
150 #define KL1_USB2_PAD_SUSPEND1		0x00000020	/* Intrepid only */
151 #define KL1_AUDIO_CELL_ENABLE		0x00000040	/* KL/Pangea only */
152 #define KL1_USB2_CELL_ENABLE		0x00000040	/* Intrepid only */
153 #define KL1_AUDIO_CHOOSE		0x00000080	/* KL/Pangea only */
154 #define KL1_I2S0_CHOOSE			0x00000200	/* KL Only */
155 #define KL1_I2S0_CELL_ENABLE		0x00000400
156 #define KL1_I2S0_CLK_ENABLE_BIT		0x00001000
157 #define KL1_I2S0_ENABLE			0x00002000
158 #define KL1_I2S1_CELL_ENABLE		0x00020000
159 #define KL1_I2S1_CLK_ENABLE_BIT		0x00080000
160 #define KL1_I2S1_ENABLE			0x00100000
161 #define KL1_EIDE0_ENABLE		0x00800000	/* KL/Intrepid Only */
162 #define KL1_EIDE0_RESET_N		0x01000000	/* KL/Intrepid Only */
163 #define KL1_EIDE1_ENABLE		0x04000000	/* KL Only */
164 #define KL1_EIDE1_RESET_N		0x08000000	/* KL Only */
165 #define KL1_UIDE_ENABLE			0x20000000	/* KL/Pangea Only */
166 #define KL1_UIDE_RESET_N		0x40000000	/* KL/Pangea Only */
167 
168 #define KL2_IOBUS_ENABLE		0x00000002
169 #define KL2_SLEEP_STATE_BIT		0x00000100	/* KL Only */
170 #define KL2_PG_STOP_ALL_CLOCKS		0x00000100	/* Pangea Only */
171 #define KL2_MPIC_ENABLE			0x00020000
172 #define KL2_CARDSLOT_RESET		0x00040000	/* Pangea/Intrepid Only */
173 #define KL2_ALT_DATA_OUT		0x02000000	/* KL Only ??? */
174 #define KL2_MEM_IS_BIG			0x04000000
175 #define KL2_CARDSEL_16			0x08000000
176 
177 #define KL3_SHUTDOWN_PLL_TOTAL		0x00000001	/* KL/Pangea only */
178 #define KL3_SHUTDOWN_PLLKW6		0x00000002	/* KL/Pangea only */
179 #define KL3_IT_SHUTDOWN_PLL3		0x00000002	/* Intrepid only */
180 #define KL3_SHUTDOWN_PLLKW4		0x00000004	/* KL/Pangea only */
181 #define KL3_IT_SHUTDOWN_PLL2		0x00000004	/* Intrepid only */
182 #define KL3_SHUTDOWN_PLLKW35		0x00000008	/* KL/Pangea only */
183 #define KL3_IT_SHUTDOWN_PLL1		0x00000008	/* Intrepid only */
184 #define KL3_SHUTDOWN_PLLKW12		0x00000010	/* KL Only */
185 #define KL3_IT_ENABLE_PLL3_SHUTDOWN	0x00000010	/* Intrepid only */
186 #define KL3_PLL_RESET			0x00000020	/* KL/Pangea only */
187 #define KL3_IT_ENABLE_PLL2_SHUTDOWN	0x00000020	/* Intrepid only */
188 #define KL3_IT_ENABLE_PLL1_SHUTDOWN	0x00000010	/* Intrepid only */
189 #define KL3_SHUTDOWN_PLL2X		0x00000080	/* KL Only */
190 #define KL3_CLK66_ENABLE		0x00000100	/* KL Only */
191 #define KL3_CLK49_ENABLE		0x00000200
192 #define KL3_CLK45_ENABLE		0x00000400
193 #define KL3_CLK31_ENABLE		0x00000800	/* KL/Pangea only */
194 #define KL3_TIMER_CLK18_ENABLE		0x00001000
195 #define KL3_I2S1_CLK18_ENABLE		0x00002000
196 #define KL3_I2S0_CLK18_ENABLE		0x00004000
197 #define KL3_VIA_CLK16_ENABLE		0x00008000	/* KL/Pangea only */
198 #define KL3_IT_VIA_CLK32_ENABLE		0x00008000	/* Intrepid only */
199 #define KL3_STOPPING33_ENABLED		0x00080000	/* KL Only */
200 #define KL3_PG_PLL_ENABLE_TEST		0x00080000	/* Pangea Only */
201 
202 /* Intrepid USB bus 2, port 0,1 */
203 #define KL3_IT_PORT_WAKEUP_ENABLE(p)		(0x00080000 << ((p)<<3))
204 #define KL3_IT_PORT_RESUME_WAKE_EN(p)		(0x00040000 << ((p)<<3))
205 #define KL3_IT_PORT_CONNECT_WAKE_EN(p)		(0x00020000 << ((p)<<3))
206 #define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)	(0x00010000 << ((p)<<3))
207 #define KL3_IT_PORT_RESUME_STAT(p)		(0x00300000 << ((p)<<3))
208 #define KL3_IT_PORT_CONNECT_STAT(p)		(0x00200000 << ((p)<<3))
209 #define KL3_IT_PORT_DISCONNECT_STAT(p)		(0x00100000 << ((p)<<3))
210 
211 /* Port 0,1 : bus 0, port 2,3 : bus 1 */
212 #define KL4_PORT_WAKEUP_ENABLE(p)	(0x00000008 << ((p)<<3))
213 #define KL4_PORT_RESUME_WAKE_EN(p)	(0x00000004 << ((p)<<3))
214 #define KL4_PORT_CONNECT_WAKE_EN(p)	(0x00000002 << ((p)<<3))
215 #define KL4_PORT_DISCONNECT_WAKE_EN(p)	(0x00000001 << ((p)<<3))
216 #define KL4_PORT_RESUME_STAT(p)		(0x00000040 << ((p)<<3))
217 #define KL4_PORT_CONNECT_STAT(p)	(0x00000020 << ((p)<<3))
218 #define KL4_PORT_DISCONNECT_STAT(p)	(0x00000010 << ((p)<<3))
219 
220 /* Pangea and Intrepid only */
221 #define KL5_VIA_USE_CLK31		0000000001	/* Pangea Only */
222 #define KL5_SCC_USE_CLK31		0x00000002	/* Pangea Only */
223 #define KL5_PWM_CLK32_EN		0x00000004
224 #define KL5_CLK3_68_EN			0x00000010
225 #define KL5_CLK32_EN			0x00000020
226 
227 
228 /* K2 definitions */
229 #define K2_FCR0_USB0_SWRESET		0x00200000
230 #define K2_FCR0_USB1_SWRESET		0x02000000
231 #define K2_FCR0_RING_PME_DISABLE	0x08000000
232 
233 #define K2_FCR1_PCI1_BUS_RESET_N	0x00000010
234 #define K2_FCR1_PCI1_SLEEP_RESET_EN	0x00000020
235 #define K2_FCR1_I2S0_CELL_ENABLE	0x00000400
236 #define K2_FCR1_I2S0_RESET		0x00000800
237 #define K2_FCR1_I2S0_CLK_ENABLE_BIT	0x00001000
238 #define K2_FCR1_I2S0_ENABLE    		0x00002000
239 #define K2_FCR1_PCI1_CLK_ENABLE		0x00004000
240 #define K2_FCR1_FW_CLK_ENABLE		0x00008000
241 #define K2_FCR1_FW_RESET_N		0x00010000
242 #define K2_FCR1_I2S1_CELL_ENABLE	0x00020000
243 #define K2_FCR1_I2S1_CLK_ENABLE_BIT	0x00080000
244 #define K2_FCR1_I2S1_ENABLE		0x00100000
245 #define K2_FCR1_GMAC_CLK_ENABLE		0x00400000
246 #define K2_FCR1_GMAC_POWER_DOWN		0x00800000
247 #define K2_FCR1_GMAC_RESET_N		0x01000000
248 #define K2_FCR1_SATA_CLK_ENABLE		0x02000000
249 #define K2_FCR1_SATA_POWER_DOWN		0x04000000
250 #define K2_FCR1_SATA_RESET_N		0x08000000
251 #define K2_FCR1_UATA_CLK_ENABLE		0x10000000
252 #define K2_FCR1_UATA_RESET_N		0x40000000
253 #define K2_FCR1_UATA_CHOOSE_CLK66	0x80000000
254 
255 /* Shasta definitions */
256 #define SH_FCR1_I2S2_CELL_ENABLE	0x00000010
257 #define SH_FCR1_I2S2_CLK_ENABLE_BIT	0x00000040
258 #define SH_FCR1_I2S2_ENABLE		0x00000080
259 #define SH_FCR3_I2S2_CLK18_ENABLE	0x00008000
260 
261 #endif /* __KERNEL__ */
262 #endif /* _ASM_POWERPC_KEYLARGO_H */
263