xref: /linux/drivers/pinctrl/intel/pinctrl-jasperlake.c (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Jasper Lake PCH pinctrl/GPIO driver
4  *
5  * Copyright (C) 2020, Intel Corporation
6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  */
8 
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm.h>
13 
14 #include <linux/pinctrl/pinctrl.h>
15 
16 #include "pinctrl-intel.h"
17 
18 #define JSL_PAD_OWN	0x020
19 #define JSL_PADCFGLOCK	0x080
20 #define JSL_HOSTSW_OWN	0x0c0
21 #define JSL_GPI_IS	0x100
22 #define JSL_GPI_IE	0x120
23 
24 #define JSL_GPP(r, s, e, g)				\
25 	{						\
26 		.reg_num = (r),				\
27 		.base = (s),				\
28 		.size = ((e) - (s) + 1),		\
29 		.gpio_base = (g),			\
30 	}
31 
32 #define JSL_COMMUNITY(b, s, e, g)			\
33 	INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
34 
35 /* Jasper Lake */
36 static const struct pinctrl_pin_desc jsl_pins[] = {
37 	/* GPP_F */
38 	PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"),
39 	PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"),
40 	PINCTRL_PIN(2, "EMMC_HIP_MON"),
41 	PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"),
42 	PINCTRL_PIN(4, "CNV_RF_RESET_B"),
43 	PINCTRL_PIN(5, "MODEM_CLKREQ"),
44 	PINCTRL_PIN(6, "CNV_PA_BLANKING"),
45 	PINCTRL_PIN(7, "EMMC_CMD"),
46 	PINCTRL_PIN(8, "EMMC_DATA0"),
47 	PINCTRL_PIN(9, "EMMC_DATA1"),
48 	PINCTRL_PIN(10, "EMMC_DATA2"),
49 	PINCTRL_PIN(11, "EMMC_DATA3"),
50 	PINCTRL_PIN(12, "EMMC_DATA4"),
51 	PINCTRL_PIN(13, "EMMC_DATA5"),
52 	PINCTRL_PIN(14, "EMMC_DATA6"),
53 	PINCTRL_PIN(15, "EMMC_DATA7"),
54 	PINCTRL_PIN(16, "EMMC_RCLK"),
55 	PINCTRL_PIN(17, "EMMC_CLK"),
56 	PINCTRL_PIN(18, "EMMC_RESETB"),
57 	PINCTRL_PIN(19, "A4WP_PRESENT"),
58 	/* SPI */
59 	PINCTRL_PIN(20, "SPI0_IO_2"),
60 	PINCTRL_PIN(21, "SPI0_IO_3"),
61 	PINCTRL_PIN(22, "SPI0_MOSI_IO_0"),
62 	PINCTRL_PIN(23, "SPI0_MISO_IO_1"),
63 	PINCTRL_PIN(24, "SPI0_TPM_CSB"),
64 	PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"),
65 	PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"),
66 	PINCTRL_PIN(27, "SPI0_CLK"),
67 	PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"),
68 	/* GPP_B */
69 	PINCTRL_PIN(29, "CORE_VID_0"),
70 	PINCTRL_PIN(30, "CORE_VID_1"),
71 	PINCTRL_PIN(31, "VRALERTB"),
72 	PINCTRL_PIN(32, "CPU_GP_2"),
73 	PINCTRL_PIN(33, "CPU_GP_3"),
74 	PINCTRL_PIN(34, "SRCCLKREQB_0"),
75 	PINCTRL_PIN(35, "SRCCLKREQB_1"),
76 	PINCTRL_PIN(36, "SRCCLKREQB_2"),
77 	PINCTRL_PIN(37, "SRCCLKREQB_3"),
78 	PINCTRL_PIN(38, "SRCCLKREQB_4"),
79 	PINCTRL_PIN(39, "SRCCLKREQB_5"),
80 	PINCTRL_PIN(40, "PMCALERTB"),
81 	PINCTRL_PIN(41, "SLP_S0B"),
82 	PINCTRL_PIN(42, "PLTRSTB"),
83 	PINCTRL_PIN(43, "SPKR"),
84 	PINCTRL_PIN(44, "GSPI0_CS0B"),
85 	PINCTRL_PIN(45, "GSPI0_CLK"),
86 	PINCTRL_PIN(46, "GSPI0_MISO"),
87 	PINCTRL_PIN(47, "GSPI0_MOSI"),
88 	PINCTRL_PIN(48, "GSPI1_CS0B"),
89 	PINCTRL_PIN(49, "GSPI1_CLK"),
90 	PINCTRL_PIN(50, "GSPI1_MISO"),
91 	PINCTRL_PIN(51, "GSPI1_MOSI"),
92 	PINCTRL_PIN(52, "DDSP_HPD_A"),
93 	PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"),
94 	PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"),
95 	/* GPP_A */
96 	PINCTRL_PIN(55, "ESPI_IO_0"),
97 	PINCTRL_PIN(56, "ESPI_IO_1"),
98 	PINCTRL_PIN(57, "ESPI_IO_2"),
99 	PINCTRL_PIN(58, "ESPI_IO_3"),
100 	PINCTRL_PIN(59, "ESPI_CSB"),
101 	PINCTRL_PIN(60, "ESPI_CLK"),
102 	PINCTRL_PIN(61, "ESPI_RESETB"),
103 	PINCTRL_PIN(62, "SMBCLK"),
104 	PINCTRL_PIN(63, "SMBDATA"),
105 	PINCTRL_PIN(64, "SMBALERTB"),
106 	PINCTRL_PIN(65, "CPU_GP_0"),
107 	PINCTRL_PIN(66, "CPU_GP_1"),
108 	PINCTRL_PIN(67, "USB2_OCB_1"),
109 	PINCTRL_PIN(68, "USB2_OCB_2"),
110 	PINCTRL_PIN(69, "USB2_OCB_3"),
111 	PINCTRL_PIN(70, "DDSP_HPD_A_TIME_SYNC_0"),
112 	PINCTRL_PIN(71, "DDSP_HPD_B"),
113 	PINCTRL_PIN(72, "DDSP_HPD_C"),
114 	PINCTRL_PIN(73, "USB2_OCB_0"),
115 	PINCTRL_PIN(74, "PCHHOTB"),
116 	PINCTRL_PIN(75, "ESPI_CLK_LOOPBK"),
117 	/* GPP_S */
118 	PINCTRL_PIN(76, "SNDW1_CLK"),
119 	PINCTRL_PIN(77, "SNDW1_DATA"),
120 	PINCTRL_PIN(78, "SNDW2_CLK"),
121 	PINCTRL_PIN(79, "SNDW2_DATA"),
122 	PINCTRL_PIN(80, "SNDW1_CLK"),
123 	PINCTRL_PIN(81, "SNDW1_DATA"),
124 	PINCTRL_PIN(82, "SNDW4_CLK_DMIC_CLK_0"),
125 	PINCTRL_PIN(83, "SNDW4_DATA_DMIC_DATA_0"),
126 	/* GPP_R */
127 	PINCTRL_PIN(84, "HDA_BCLK"),
128 	PINCTRL_PIN(85, "HDA_SYNC"),
129 	PINCTRL_PIN(86, "HDA_SDO"),
130 	PINCTRL_PIN(87, "HDA_SDI_0"),
131 	PINCTRL_PIN(88, "HDA_RSTB"),
132 	PINCTRL_PIN(89, "HDA_SDI_1"),
133 	PINCTRL_PIN(90, "I2S1_SFRM"),
134 	PINCTRL_PIN(91, "I2S1_TXD"),
135 	/* GPP_H */
136 	PINCTRL_PIN(92, "GPPC_H_0"),
137 	PINCTRL_PIN(93, "SD_PWR_EN_B"),
138 	PINCTRL_PIN(94, "MODEM_CLKREQ"),
139 	PINCTRL_PIN(95, "SX_EXIT_HOLDOFFB"),
140 	PINCTRL_PIN(96, "I2C2_SDA"),
141 	PINCTRL_PIN(97, "I2C2_SCL"),
142 	PINCTRL_PIN(98, "I2C3_SDA"),
143 	PINCTRL_PIN(99, "I2C3_SCL"),
144 	PINCTRL_PIN(100, "I2C4_SDA"),
145 	PINCTRL_PIN(101, "I2C4_SCL"),
146 	PINCTRL_PIN(102, "CPU_VCCIO_PWR_GATEB"),
147 	PINCTRL_PIN(103, "I2S2_SCLK"),
148 	PINCTRL_PIN(104, "I2S2_SFRM"),
149 	PINCTRL_PIN(105, "I2S2_TXD"),
150 	PINCTRL_PIN(106, "I2S2_RXD"),
151 	PINCTRL_PIN(107, "I2S1_SCLK"),
152 	PINCTRL_PIN(108, "GPPC_H_16"),
153 	PINCTRL_PIN(109, "GPPC_H_17"),
154 	PINCTRL_PIN(110, "GPPC_H_18"),
155 	PINCTRL_PIN(111, "GPPC_H_19"),
156 	PINCTRL_PIN(112, "GPPC_H_20"),
157 	PINCTRL_PIN(113, "GPPC_H_21"),
158 	PINCTRL_PIN(114, "GPPC_H_22"),
159 	PINCTRL_PIN(115, "GPPC_H_23"),
160 	/* GPP_D */
161 	PINCTRL_PIN(116, "SPI1_CSB"),
162 	PINCTRL_PIN(117, "SPI1_CLK"),
163 	PINCTRL_PIN(118, "SPI1_MISO_IO_1"),
164 	PINCTRL_PIN(119, "SPI1_MOSI_IO_0"),
165 	PINCTRL_PIN(120, "ISH_I2C0_SDA"),
166 	PINCTRL_PIN(121, "ISH_I2C0_SCL"),
167 	PINCTRL_PIN(122, "ISH_I2C1_SDA"),
168 	PINCTRL_PIN(123, "ISH_I2C1_SCL"),
169 	PINCTRL_PIN(124, "ISH_SPI_CSB"),
170 	PINCTRL_PIN(125, "ISH_SPI_CLK"),
171 	PINCTRL_PIN(126, "ISH_SPI_MISO"),
172 	PINCTRL_PIN(127, "ISH_SPI_MOSI"),
173 	PINCTRL_PIN(128, "ISH_UART0_RXD"),
174 	PINCTRL_PIN(129, "ISH_UART0_TXD"),
175 	PINCTRL_PIN(130, "ISH_UART0_RTSB"),
176 	PINCTRL_PIN(131, "ISH_UART0_CTSB"),
177 	PINCTRL_PIN(132, "SPI1_IO_2"),
178 	PINCTRL_PIN(133, "SPI1_IO_3"),
179 	PINCTRL_PIN(134, "I2S_MCLK"),
180 	PINCTRL_PIN(135, "CNV_MFUART2_RXD"),
181 	PINCTRL_PIN(136, "CNV_MFUART2_TXD"),
182 	PINCTRL_PIN(137, "CNV_PA_BLANKING"),
183 	PINCTRL_PIN(138, "I2C5_SDA"),
184 	PINCTRL_PIN(139, "I2C5_SCL"),
185 	PINCTRL_PIN(140, "GSPI2_CLK_LOOPBK"),
186 	PINCTRL_PIN(141, "SPI1_CLK_LOOPBK"),
187 	/* vGPIO */
188 	PINCTRL_PIN(142, "CNV_BTEN"),
189 	PINCTRL_PIN(143, "CNV_WCEN"),
190 	PINCTRL_PIN(144, "CNV_BT_HOST_WAKEB"),
191 	PINCTRL_PIN(145, "CNV_BT_IF_SELECT"),
192 	PINCTRL_PIN(146, "vCNV_BT_UART_TXD"),
193 	PINCTRL_PIN(147, "vCNV_BT_UART_RXD"),
194 	PINCTRL_PIN(148, "vCNV_BT_UART_CTS_B"),
195 	PINCTRL_PIN(149, "vCNV_BT_UART_RTS_B"),
196 	PINCTRL_PIN(150, "vCNV_MFUART1_TXD"),
197 	PINCTRL_PIN(151, "vCNV_MFUART1_RXD"),
198 	PINCTRL_PIN(152, "vCNV_MFUART1_CTS_B"),
199 	PINCTRL_PIN(153, "vCNV_MFUART1_RTS_B"),
200 	PINCTRL_PIN(154, "vUART0_TXD"),
201 	PINCTRL_PIN(155, "vUART0_RXD"),
202 	PINCTRL_PIN(156, "vUART0_CTS_B"),
203 	PINCTRL_PIN(157, "vUART0_RTS_B"),
204 	PINCTRL_PIN(158, "vISH_UART0_TXD"),
205 	PINCTRL_PIN(159, "vISH_UART0_RXD"),
206 	PINCTRL_PIN(160, "vISH_UART0_CTS_B"),
207 	PINCTRL_PIN(161, "vISH_UART0_RTS_B"),
208 	PINCTRL_PIN(162, "vCNV_BT_I2S_BCLK"),
209 	PINCTRL_PIN(163, "vCNV_BT_I2S_WS_SYNC"),
210 	PINCTRL_PIN(164, "vCNV_BT_I2S_SDO"),
211 	PINCTRL_PIN(165, "vCNV_BT_I2S_SDI"),
212 	PINCTRL_PIN(166, "vI2S2_SCLK"),
213 	PINCTRL_PIN(167, "vI2S2_SFRM"),
214 	PINCTRL_PIN(168, "vI2S2_TXD"),
215 	PINCTRL_PIN(169, "vI2S2_RXD"),
216 	PINCTRL_PIN(170, "vSD3_CD_B"),
217 	/* GPP_C */
218 	PINCTRL_PIN(171, "GPPC_C_0"),
219 	PINCTRL_PIN(172, "GPPC_C_1"),
220 	PINCTRL_PIN(173, "GPPC_C_2"),
221 	PINCTRL_PIN(174, "GPPC_C_3"),
222 	PINCTRL_PIN(175, "GPPC_C_4"),
223 	PINCTRL_PIN(176, "GPPC_C_5"),
224 	PINCTRL_PIN(177, "SUSWARNB_SUSPWRDNACK"),
225 	PINCTRL_PIN(178, "SUSACKB"),
226 	PINCTRL_PIN(179, "UART0_RXD"),
227 	PINCTRL_PIN(180, "UART0_TXD"),
228 	PINCTRL_PIN(181, "UART0_RTSB"),
229 	PINCTRL_PIN(182, "UART0_CTSB"),
230 	PINCTRL_PIN(183, "UART1_RXD"),
231 	PINCTRL_PIN(184, "UART1_TXD"),
232 	PINCTRL_PIN(185, "UART1_RTSB"),
233 	PINCTRL_PIN(186, "UART1_CTSB"),
234 	PINCTRL_PIN(187, "I2C0_SDA"),
235 	PINCTRL_PIN(188, "I2C0_SCL"),
236 	PINCTRL_PIN(189, "I2C1_SDA"),
237 	PINCTRL_PIN(190, "I2C1_SCL"),
238 	PINCTRL_PIN(191, "UART2_RXD"),
239 	PINCTRL_PIN(192, "UART2_TXD"),
240 	PINCTRL_PIN(193, "UART2_RTSB"),
241 	PINCTRL_PIN(194, "UART2_CTSB"),
242 	/* HVCMOS */
243 	PINCTRL_PIN(195, "L_BKLTEN"),
244 	PINCTRL_PIN(196, "L_BKLTCTL"),
245 	PINCTRL_PIN(197, "L_VDDEN"),
246 	PINCTRL_PIN(198, "SYS_PWROK"),
247 	PINCTRL_PIN(199, "SYS_RESETB"),
248 	PINCTRL_PIN(200, "MLK_RSTB"),
249 	/* GPP_E */
250 	PINCTRL_PIN(201, "ISH_GP_0"),
251 	PINCTRL_PIN(202, "ISH_GP_1"),
252 	PINCTRL_PIN(203, "IMGCLKOUT_1"),
253 	PINCTRL_PIN(204, "ISH_GP_2"),
254 	PINCTRL_PIN(205, "IMGCLKOUT_2"),
255 	PINCTRL_PIN(206, "SATA_LEDB"),
256 	PINCTRL_PIN(207, "IMGCLKOUT_3"),
257 	PINCTRL_PIN(208, "ISH_GP_3"),
258 	PINCTRL_PIN(209, "ISH_GP_4"),
259 	PINCTRL_PIN(210, "ISH_GP_5"),
260 	PINCTRL_PIN(211, "ISH_GP_6"),
261 	PINCTRL_PIN(212, "ISH_GP_7"),
262 	PINCTRL_PIN(213, "IMGCLKOUT_4"),
263 	PINCTRL_PIN(214, "DDPA_CTRLCLK"),
264 	PINCTRL_PIN(215, "DDPA_CTRLDATA"),
265 	PINCTRL_PIN(216, "DDPB_CTRLCLK"),
266 	PINCTRL_PIN(217, "DDPB_CTRLDATA"),
267 	PINCTRL_PIN(218, "DDPC_CTRLCLK"),
268 	PINCTRL_PIN(219, "DDPC_CTRLDATA"),
269 	PINCTRL_PIN(220, "IMGCLKOUT_5"),
270 	PINCTRL_PIN(221, "CNV_BRI_DT"),
271 	PINCTRL_PIN(222, "CNV_BRI_RSP"),
272 	PINCTRL_PIN(223, "CNV_RGI_DT"),
273 	PINCTRL_PIN(224, "CNV_RGI_RSP"),
274 	/* GPP_G */
275 	PINCTRL_PIN(225, "SD3_CMD"),
276 	PINCTRL_PIN(226, "SD3_D0"),
277 	PINCTRL_PIN(227, "SD3_D1"),
278 	PINCTRL_PIN(228, "SD3_D2"),
279 	PINCTRL_PIN(229, "SD3_D3"),
280 	PINCTRL_PIN(230, "SD3_CDB"),
281 	PINCTRL_PIN(231, "SD3_CLK"),
282 	PINCTRL_PIN(232, "SD3_WP"),
283 };
284 
285 static const struct intel_padgroup jsl_community0_gpps[] = {
286 	JSL_GPP(0, 0, 19, 320),				/* GPP_F */
287 	JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP),	/* SPI */
288 	JSL_GPP(2, 29, 54, 32),				/* GPP_B */
289 	JSL_GPP(3, 55, 75, 64),				/* GPP_A */
290 	JSL_GPP(4, 76, 83, 96),				/* GPP_S */
291 	JSL_GPP(5, 84, 91, 128),			/* GPP_R */
292 };
293 
294 static const struct intel_padgroup jsl_community1_gpps[] = {
295 	JSL_GPP(0, 92, 115, 160),			/* GPP_H */
296 	JSL_GPP(1, 116, 141, 192),			/* GPP_D */
297 	JSL_GPP(2, 142, 170, 224),			/* vGPIO */
298 	JSL_GPP(3, 171, 194, 256),			/* GPP_C */
299 };
300 
301 static const struct intel_padgroup jsl_community4_gpps[] = {
302 	JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
303 	JSL_GPP(1, 201, 224, 288),			/* GPP_E */
304 };
305 
306 static const struct intel_padgroup jsl_community5_gpps[] = {
307 	JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO),	/* GPP_G */
308 };
309 
310 static const struct intel_community jsl_communities[] = {
311 	JSL_COMMUNITY(0, 0, 91, jsl_community0_gpps),
312 	JSL_COMMUNITY(1, 92, 194, jsl_community1_gpps),
313 	JSL_COMMUNITY(2, 195, 224, jsl_community4_gpps),
314 	JSL_COMMUNITY(3, 225, 232, jsl_community5_gpps),
315 };
316 
317 static const struct intel_pinctrl_soc_data jsl_soc_data = {
318 	.pins = jsl_pins,
319 	.npins = ARRAY_SIZE(jsl_pins),
320 	.communities = jsl_communities,
321 	.ncommunities = ARRAY_SIZE(jsl_communities),
322 };
323 
324 static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {
325 	{ "INT34C8", (kernel_ulong_t)&jsl_soc_data },
326 	{ }
327 };
328 MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
329 
330 static struct platform_driver jsl_pinctrl_driver = {
331 	.probe = intel_pinctrl_probe_by_hid,
332 	.driver = {
333 		.name = "jasperlake-pinctrl",
334 		.acpi_match_table = jsl_pinctrl_acpi_match,
335 		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
336 	},
337 };
338 module_platform_driver(jsl_pinctrl_driver);
339 
340 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
341 MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver");
342 MODULE_LICENSE("GPL v2");
343 MODULE_IMPORT_NS(PINCTRL_INTEL);
344