Home
last modified time | relevance | path

Searched defs:IsKill (Results 1 – 25 of 29) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h50 bool IsKill, int Offset) { in addRegIndirectWithDisp()
H A DM68kInstrInfo.cpp841 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp114 bool IsKill = false; in eliminateFI() local
H A DMipsSERegisterInfo.cpp196 bool IsKill = false; in eliminateFI() local
H A DMipsSEFrameLowering.cpp796 bool IsKill = !IsRAAndRetAddrIsTaken; in spillCalleeSavedRegisters() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaRegisterInfo.cpp102 bool IsKill = false; in eliminateFrameIndex() local
H A DXtensaFrameLowering.cpp314 bool IsKill = !IsA0AndRetAddrIsTaken; in spillCalleeSavedRegisters() local
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp127 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DFixupStatepointCallerSaved.cpp117 bool &IsKill, const TargetInstrInfo &TII, in performCopyPropagation()
416 bool IsKill = true; in spillRegisters() local
H A DScheduleDAGInstrs.cpp433 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() local
1135 bool IsKill = LiveRegs.available(Reg); in toggleKills() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp346 bool IsKill = NewAddrDwords == Info->VAddrDwords; in shrinkMIMG() local
586 const bool IsKill = SrcReg->isKill(); in shrinkScalarLogicOp() local
H A DSIOptimizeExecMaskingPreRA.cpp255 bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill(); in optimizeVcndVcmpPair() local
H A DSIRegisterInfo.cpp90 bool IsKill; member
1452 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR()
1571 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore()
H A DSIFrameLowering.cpp150 bool IsKill = !MBB.isLiveIn(SpillReg); in buildPrologSpill() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp273 unsigned Dst, unsigned Src, bool IsKill) { in insertCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp393 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp296 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1405 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); in insertCSRSpillsInBlock() local
1736 bool IsKill = MI->getOperand(2).isKill(); in expandStoreInt() local
1799 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVecPred() local
1888 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec2() local
1975 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec() local
H A DHexagonBlockRanges.cpp324 bool IsKill = Op.isKill(); in computeInitialLiveRanges() local
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFrameLowering.cpp449 bool IsKill = in spillCalleeSavedRegisters() local
H A DLoongArchInstrInfo.cpp115 bool IsKill, int FI, const TargetRegisterClass *RC, in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp751 bool IsKill = I.getOperand(1).isKill(); in select() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp49 Register SourceRegister, bool IsKill, int FrameIndex, in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DBasicBlockUtils.cpp506 bool IsKill = DVR.isKillLocation() && IsDbgValueKind; in DbgVariableRecordsRemoveUndefDbgAssignsFromEntryBlock() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp870 bool IsKill = MO.isKill(); in MergeOpsUpdate() local

12