xref: /linux/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h (revision 8be4d31cb8aaeea27bde4b7ddb26e28a89062ebf)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
3 
4 #ifndef _IXGBE_TYPE_H_
5 #define _IXGBE_TYPE_H_
6 
7 #include <linux/types.h>
8 #include <linux/mdio.h>
9 #include <linux/netdevice.h>
10 #include "ixgbe_type_e610.h"
11 
12 /* Device IDs */
13 #define IXGBE_DEV_ID_82598               0x10B6
14 #define IXGBE_DEV_ID_82598_BX            0x1508
15 #define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
16 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
17 #define IXGBE_DEV_ID_82598EB_SFP_LOM     0x10DB
18 #define IXGBE_DEV_ID_82598AT             0x10C8
19 #define IXGBE_DEV_ID_82598AT2            0x150B
20 #define IXGBE_DEV_ID_82598EB_CX4         0x10DD
21 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
22 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT  0x10F1
23 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
24 #define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
25 #define IXGBE_DEV_ID_82599_KX4           0x10F7
26 #define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
27 #define IXGBE_DEV_ID_82599_KR            0x1517
28 #define IXGBE_DEV_ID_82599_T3_LOM        0x151C
29 #define IXGBE_DEV_ID_82599_CX4           0x10F9
30 #define IXGBE_DEV_ID_82599_SFP           0x10FB
31 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152a
32 #define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
33 #define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
34 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0   0x1071
35 #define IXGBE_SUBDEV_ID_82599_RNDC       0x1F72
36 #define IXGBE_SUBDEV_ID_82599_560FLR     0x17D0
37 #define IXGBE_SUBDEV_ID_82599_SP_560FLR  0x211B
38 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6		0x2159
39 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP		0x000D
40 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP		0x0008
41 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1	0x8976
42 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2	0x06EE
43 #define IXGBE_SUBDEV_ID_82599_ECNA_DP    0x0470
44 #define IXGBE_DEV_ID_82599_SFP_EM        0x1507
45 #define IXGBE_DEV_ID_82599_SFP_SF2       0x154D
46 #define IXGBE_DEV_ID_82599EN_SFP         0x1557
47 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
48 #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
49 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
50 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
51 #define IXGBE_DEV_ID_82599_LS            0x154F
52 #define IXGBE_DEV_ID_X540T               0x1528
53 #define IXGBE_DEV_ID_82599_SFP_SF_QP     0x154A
54 #define IXGBE_DEV_ID_82599_QSFP_SF_QP    0x1558
55 #define IXGBE_DEV_ID_X540T1              0x1560
56 
57 #define IXGBE_DEV_ID_X550T		0x1563
58 #define IXGBE_DEV_ID_X550T1		0x15D1
59 #define IXGBE_DEV_ID_X550EM_X_KX4	0x15AA
60 #define IXGBE_DEV_ID_X550EM_X_KR	0x15AB
61 #define IXGBE_DEV_ID_X550EM_X_SFP	0x15AC
62 #define IXGBE_DEV_ID_X550EM_X_10G_T	0x15AD
63 #define IXGBE_DEV_ID_X550EM_X_1G_T	0x15AE
64 #define IXGBE_DEV_ID_X550EM_X_XFI	0x15B0
65 #define IXGBE_DEV_ID_X550EM_A_KR	0x15C2
66 #define IXGBE_DEV_ID_X550EM_A_KR_L	0x15C3
67 #define IXGBE_DEV_ID_X550EM_A_SFP_N	0x15C4
68 #define IXGBE_DEV_ID_X550EM_A_SGMII	0x15C6
69 #define IXGBE_DEV_ID_X550EM_A_SGMII_L	0x15C7
70 #define IXGBE_DEV_ID_X550EM_A_10G_T	0x15C8
71 #define IXGBE_DEV_ID_X550EM_A_SFP	0x15CE
72 #define IXGBE_DEV_ID_X550EM_A_1G_T	0x15E4
73 #define IXGBE_DEV_ID_X550EM_A_1G_T_L	0x15E5
74 
75 #define IXGBE_DEV_ID_E610_BACKPLANE	0x57AE
76 #define IXGBE_DEV_ID_E610_SFP		0x57AF
77 #define IXGBE_DEV_ID_E610_10G_T		0x57B0
78 #define IXGBE_DEV_ID_E610_2_5G_T	0x57B1
79 #define IXGBE_DEV_ID_E610_SGMII		0x57B2
80 
81 /* VF Device IDs */
82 #define IXGBE_DEV_ID_82599_VF		0x10ED
83 #define IXGBE_DEV_ID_X540_VF		0x1515
84 #define IXGBE_DEV_ID_X550_VF		0x1565
85 #define IXGBE_DEV_ID_X550EM_X_VF	0x15A8
86 #define IXGBE_DEV_ID_X550EM_A_VF	0x15C5
87 #define IXGBE_DEV_ID_E610_VF		0x57AD
88 
89 #define IXGBE_CAT(r, m)	IXGBE_##r##_##m
90 
91 #define IXGBE_BY_MAC(_hw, r)	((_hw)->mvals[IXGBE_CAT(r, IDX)])
92 
93 /* General Registers */
94 #define IXGBE_CTRL      0x00000
95 #define IXGBE_STATUS    0x00008
96 #define IXGBE_CTRL_EXT  0x00018
97 #define IXGBE_ESDP      0x00020
98 #define IXGBE_EODSDP    0x00028
99 
100 #define IXGBE_I2CCTL_8259X	0x00028
101 #define IXGBE_I2CCTL_X540	IXGBE_I2CCTL_8259X
102 #define IXGBE_I2CCTL_X550	0x15F5C
103 #define IXGBE_I2CCTL_X550EM_x	IXGBE_I2CCTL_X550
104 #define IXGBE_I2CCTL_X550EM_a	IXGBE_I2CCTL_X550
105 #define IXGBE_I2CCTL(_hw)	IXGBE_BY_MAC((_hw), I2CCTL)
106 
107 #define IXGBE_LEDCTL    0x00200
108 #define IXGBE_FRTIMER   0x00048
109 #define IXGBE_TCPTIMER  0x0004C
110 #define IXGBE_CORESPARE 0x00600
111 #define IXGBE_EXVET     0x05078
112 
113 /* NVM Registers */
114 #define IXGBE_EEC_8259X		0x10010
115 #define IXGBE_EEC_X540		IXGBE_EEC_8259X
116 #define IXGBE_EEC_X550		IXGBE_EEC_8259X
117 #define IXGBE_EEC_X550EM_x	IXGBE_EEC_8259X
118 #define IXGBE_EEC_X550EM_a	0x15FF8
119 #define IXGBE_EEC(_hw)		IXGBE_BY_MAC((_hw), EEC)
120 #define IXGBE_EERD      0x10014
121 #define IXGBE_EEWR      0x10018
122 #define IXGBE_FLA_8259X		0x1001C
123 #define IXGBE_FLA_X540		IXGBE_FLA_8259X
124 #define IXGBE_FLA_X550		IXGBE_FLA_8259X
125 #define IXGBE_FLA_X550EM_x	IXGBE_FLA_8259X
126 #define IXGBE_FLA_X550EM_a	0x15F68
127 #define IXGBE_FLA(_hw)		IXGBE_BY_MAC((_hw), FLA)
128 #define IXGBE_EEMNGCTL  0x10110
129 #define IXGBE_EEMNGDATA 0x10114
130 #define IXGBE_FLMNGCTL  0x10118
131 #define IXGBE_FLMNGDATA 0x1011C
132 #define IXGBE_FLMNGCNT  0x10120
133 #define IXGBE_FLOP      0x1013C
134 #define IXGBE_GRC_8259X		0x10200
135 #define IXGBE_GRC_X540		IXGBE_GRC_8259X
136 #define IXGBE_GRC_X550		IXGBE_GRC_8259X
137 #define IXGBE_GRC_X550EM_x	IXGBE_GRC_8259X
138 #define IXGBE_GRC_X550EM_a	0x15F64
139 #define IXGBE_GRC(_hw)		IXGBE_BY_MAC((_hw), GRC)
140 
141 /* General Receive Control */
142 #define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
143 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
144 
145 #define IXGBE_VPDDIAG0  0x10204
146 #define IXGBE_VPDDIAG1  0x10208
147 
148 /* I2CCTL Bit Masks */
149 #define IXGBE_I2C_CLK_IN_8259X		0x00000001
150 #define IXGBE_I2C_CLK_IN_X540		IXGBE_I2C_CLK_IN_8259X
151 #define IXGBE_I2C_CLK_IN_X550		0x00004000
152 #define IXGBE_I2C_CLK_IN_X550EM_x	IXGBE_I2C_CLK_IN_X550
153 #define IXGBE_I2C_CLK_IN_X550EM_a	IXGBE_I2C_CLK_IN_X550
154 #define IXGBE_I2C_CLK_IN(_hw)		IXGBE_BY_MAC((_hw), I2C_CLK_IN)
155 
156 #define IXGBE_I2C_CLK_OUT_8259X		0x00000002
157 #define IXGBE_I2C_CLK_OUT_X540		IXGBE_I2C_CLK_OUT_8259X
158 #define IXGBE_I2C_CLK_OUT_X550		0x00000200
159 #define IXGBE_I2C_CLK_OUT_X550EM_x	IXGBE_I2C_CLK_OUT_X550
160 #define IXGBE_I2C_CLK_OUT_X550EM_a	IXGBE_I2C_CLK_OUT_X550
161 #define IXGBE_I2C_CLK_OUT(_hw)		IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
162 
163 #define IXGBE_I2C_DATA_IN_8259X		0x00000004
164 #define IXGBE_I2C_DATA_IN_X540		IXGBE_I2C_DATA_IN_8259X
165 #define IXGBE_I2C_DATA_IN_X550		0x00001000
166 #define IXGBE_I2C_DATA_IN_X550EM_x	IXGBE_I2C_DATA_IN_X550
167 #define IXGBE_I2C_DATA_IN_X550EM_a	IXGBE_I2C_DATA_IN_X550
168 #define IXGBE_I2C_DATA_IN(_hw)		IXGBE_BY_MAC((_hw), I2C_DATA_IN)
169 
170 #define IXGBE_I2C_DATA_OUT_8259X	0x00000008
171 #define IXGBE_I2C_DATA_OUT_X540		IXGBE_I2C_DATA_OUT_8259X
172 #define IXGBE_I2C_DATA_OUT_X550		0x00000400
173 #define IXGBE_I2C_DATA_OUT_X550EM_x	IXGBE_I2C_DATA_OUT_X550
174 #define IXGBE_I2C_DATA_OUT_X550EM_a	IXGBE_I2C_DATA_OUT_X550
175 #define IXGBE_I2C_DATA_OUT(_hw)		IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
176 
177 #define IXGBE_I2C_DATA_OE_N_EN_8259X	0
178 #define IXGBE_I2C_DATA_OE_N_EN_X540	IXGBE_I2C_DATA_OE_N_EN_8259X
179 #define IXGBE_I2C_DATA_OE_N_EN_X550	0x00000800
180 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x	IXGBE_I2C_DATA_OE_N_EN_X550
181 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a	IXGBE_I2C_DATA_OE_N_EN_X550
182 #define IXGBE_I2C_DATA_OE_N_EN(_hw)	IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
183 
184 #define IXGBE_I2C_BB_EN_8259X		0
185 #define IXGBE_I2C_BB_EN_X540		IXGBE_I2C_BB_EN_8259X
186 #define IXGBE_I2C_BB_EN_X550		0x00000100
187 #define IXGBE_I2C_BB_EN_X550EM_x	IXGBE_I2C_BB_EN_X550
188 #define IXGBE_I2C_BB_EN_X550EM_a	IXGBE_I2C_BB_EN_X550
189 #define IXGBE_I2C_BB_EN(_hw)		IXGBE_BY_MAC((_hw), I2C_BB_EN)
190 
191 #define IXGBE_I2C_CLK_OE_N_EN_8259X	0
192 #define IXGBE_I2C_CLK_OE_N_EN_X540	IXGBE_I2C_CLK_OE_N_EN_8259X
193 #define IXGBE_I2C_CLK_OE_N_EN_X550	0x00002000
194 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x	IXGBE_I2C_CLK_OE_N_EN_X550
195 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a	IXGBE_I2C_CLK_OE_N_EN_X550
196 #define IXGBE_I2C_CLK_OE_N_EN(_hw)	 IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
197 
198 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT	500
199 
200 #define IXGBE_I2C_THERMAL_SENSOR_ADDR	0xF8
201 #define IXGBE_EMC_INTERNAL_DATA		0x00
202 #define IXGBE_EMC_INTERNAL_THERM_LIMIT	0x20
203 #define IXGBE_EMC_DIODE1_DATA		0x01
204 #define IXGBE_EMC_DIODE1_THERM_LIMIT	0x19
205 #define IXGBE_EMC_DIODE2_DATA		0x23
206 #define IXGBE_EMC_DIODE2_THERM_LIMIT	0x1A
207 
208 #define IXGBE_MAX_SENSORS		3
209 
210 struct ixgbe_thermal_diode_data {
211 	u8 location;
212 	u8 temp;
213 	u8 caution_thresh;
214 	u8 max_op_thresh;
215 };
216 
217 struct ixgbe_thermal_sensor_data {
218 	struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
219 };
220 
221 #define NVM_OROM_OFFSET		0x17
222 #define NVM_OROM_BLK_LOW	0x83
223 #define NVM_OROM_BLK_HI		0x84
224 #define NVM_OROM_PATCH_MASK	0xFF
225 #define NVM_OROM_SHIFT		8
226 
227 #define NVM_VER_MASK		0x00FF	/* version mask */
228 #define NVM_VER_SHIFT		8	/* version bit shift */
229 #define NVM_OEM_PROD_VER_PTR	0x1B /* OEM Product version block pointer */
230 #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */
231 #define NVM_OEM_PROD_VER_OFF_L	0x2  /* OEM Product version offset low */
232 #define NVM_OEM_PROD_VER_OFF_H	0x3  /* OEM Product version offset high */
233 #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
234 #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */
235 #define NVM_ETK_OFF_LOW		0x2D /* version low order word */
236 #define NVM_ETK_OFF_HI		0x2E /* version high order word */
237 #define NVM_ETK_SHIFT		16   /* high version word shift */
238 #define NVM_VER_INVALID		0xFFFF
239 #define NVM_ETK_VALID		0x8000
240 #define NVM_INVALID_PTR		0xFFFF
241 #define NVM_VER_SIZE		32   /* version string size */
242 
243 struct ixgbe_nvm_version {
244 	u32 etk_id;
245 	u8  nvm_major;
246 	u16 nvm_minor;
247 	u8  nvm_id;
248 
249 	bool oem_valid;
250 	u8   oem_major;
251 	u8   oem_minor;
252 	u16  oem_release;
253 
254 	bool or_valid;
255 	u8  or_major;
256 	u16 or_build;
257 	u8  or_patch;
258 };
259 
260 /* Interrupt Registers */
261 #define IXGBE_EICR      0x00800
262 #define IXGBE_EICS      0x00808
263 #define IXGBE_EIMS      0x00880
264 #define IXGBE_EIMC      0x00888
265 #define IXGBE_EIAC      0x00810
266 #define IXGBE_EIAM      0x00890
267 #define IXGBE_EICS_EX(_i)   (0x00A90 + (_i) * 4)
268 #define IXGBE_EIMS_EX(_i)   (0x00AA0 + (_i) * 4)
269 #define IXGBE_EIMC_EX(_i)   (0x00AB0 + (_i) * 4)
270 #define IXGBE_EIAM_EX(_i)   (0x00AD0 + (_i) * 4)
271 /*
272  * 82598 EITR is 16 bits but set the limits based on the max
273  * supported by all ixgbe hardware.  82599 EITR is only 12 bits,
274  * with the lower 3 always zero.
275  */
276 #define IXGBE_MAX_INT_RATE 488281
277 #define IXGBE_MIN_INT_RATE 956
278 #define IXGBE_MAX_EITR     0x00000FF8
279 #define IXGBE_MIN_EITR     8
280 #define IXGBE_EITR(_i)  (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
281 			 (0x012300 + (((_i) - 24) * 4)))
282 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
283 #define IXGBE_EITR_LLI_MOD      0x00008000
284 #define IXGBE_EITR_CNT_WDIS     0x80000000
285 #define IXGBE_IVAR(_i)  (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
286 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
287 #define IXGBE_EITRSEL   0x00894
288 #define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
289 #define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
290 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
291 #define IXGBE_GPIE      0x00898
292 
293 /* Flow Control Registers */
294 #define IXGBE_FCADBUL   0x03210
295 #define IXGBE_FCADBUH   0x03214
296 #define IXGBE_FCAMACL   0x04328
297 #define IXGBE_FCAMACH   0x0432C
298 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
299 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
300 #define IXGBE_PFCTOP    0x03008
301 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
302 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
303 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
304 #define IXGBE_FCRTV     0x032A0
305 #define IXGBE_FCCFG     0x03D00
306 #define IXGBE_TFCS      0x0CE00
307 
308 /* Receive DMA Registers */
309 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
310 			 (0x0D000 + (((_i) - 64) * 0x40)))
311 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
312 			 (0x0D004 + (((_i) - 64) * 0x40)))
313 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
314 			 (0x0D008 + (((_i) - 64) * 0x40)))
315 #define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
316 			 (0x0D010 + (((_i) - 64) * 0x40)))
317 #define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
318 			 (0x0D018 + (((_i) - 64) * 0x40)))
319 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
320 			 (0x0D028 + (((_i) - 64) * 0x40)))
321 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
322 			 (0x0D02C + (((_i) - 64) * 0x40)))
323 #define IXGBE_RSCDBU     0x03028
324 #define IXGBE_RDDCC      0x02F20
325 #define IXGBE_RXMEMWRAP  0x03190
326 #define IXGBE_STARCTRL   0x03024
327 /*
328  * Split and Replication Receive Control Registers
329  * 00-15 : 0x02100 + n*4
330  * 16-64 : 0x01014 + n*0x40
331  * 64-127: 0x0D014 + (n-64)*0x40
332  */
333 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
334 			  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
335 			  (0x0D014 + (((_i) - 64) * 0x40))))
336 /*
337  * Rx DCA Control Register:
338  * 00-15 : 0x02200 + n*4
339  * 16-64 : 0x0100C + n*0x40
340  * 64-127: 0x0D00C + (n-64)*0x40
341  */
342 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
343 				 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
344 				 (0x0D00C + (((_i) - 64) * 0x40))))
345 #define IXGBE_RDRXCTL           0x02F00
346 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
347 					     /* 8 of these 0x03C00 - 0x03C1C */
348 #define IXGBE_RXCTRL    0x03000
349 #define IXGBE_DROPEN    0x03D04
350 #define IXGBE_RXPBSIZE_SHIFT 10
351 
352 /* Receive Registers */
353 #define IXGBE_RXCSUM    0x05000
354 #define IXGBE_RFCTL     0x05008
355 #define IXGBE_DRECCCTL  0x02F08
356 #define IXGBE_DRECCCTL_DISABLE 0
357 /* Multicast Table Array - 128 entries */
358 #define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
359 #define IXGBE_RAL(_i)   (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
360 			 (0x0A200 + ((_i) * 8)))
361 #define IXGBE_RAH(_i)   (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
362 			 (0x0A204 + ((_i) * 8)))
363 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
364 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
365 /* Packet split receive type */
366 #define IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
367 			      (0x0EA00 + ((_i) * 4)))
368 /* array of 4096 1-bit vlan filters */
369 #define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
370 /*array of 4096 4-bit vlan vmdq indices */
371 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
372 #define IXGBE_FCTRL     0x05080
373 #define IXGBE_VLNCTRL   0x05088
374 #define IXGBE_MCSTCTRL  0x05090
375 #define IXGBE_MRQC      0x05818
376 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
377 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
378 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
379 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
380 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
381 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
382 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
383 #define IXGBE_RQTC      0x0EC70
384 #define IXGBE_MTQC      0x08120
385 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
386 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
387 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
388 #define IXGBE_PFFLPL	0x050B0
389 #define IXGBE_PFFLPH	0x050B4
390 #define IXGBE_VT_CTL         0x051B0
391 #define IXGBE_PFMAILBOX(_i)  (0x04B00 + (4 * (_i))) /* 64 total */
392 #define IXGBE_PFMBMEM(_i)    (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
393 #define IXGBE_PFMBICR(_i)    (0x00710 + (4 * (_i))) /* 4 total */
394 #define IXGBE_PFMBIMR(_i)    (0x00720 + (4 * (_i))) /* 4 total */
395 #define IXGBE_VFRE(_i)       (0x051E0 + ((_i) * 4))
396 #define IXGBE_VFTE(_i)       (0x08110 + ((_i) * 4))
397 #define IXGBE_VMECM(_i)      (0x08790 + ((_i) * 4))
398 #define IXGBE_QDE            0x2F04
399 #define IXGBE_VMTXSW(_i)     (0x05180 + ((_i) * 4)) /* 2 total */
400 #define IXGBE_VMOLR(_i)      (0x0F000 + ((_i) * 4)) /* 64 total */
401 #define IXGBE_UTA(_i)        (0x0F400 + ((_i) * 4))
402 #define IXGBE_MRCTL(_i)      (0x0F600 + ((_i) * 4))
403 #define IXGBE_VMRVLAN(_i)    (0x0F610 + ((_i) * 4))
404 #define IXGBE_VMRVM(_i)      (0x0F630 + ((_i) * 4))
405 #define IXGBE_LVMMC_RX	     0x2FA8
406 #define IXGBE_LVMMC_TX	     0x8108
407 #define IXGBE_WQBR_RX(_i)    (0x2FB0 + ((_i) * 4)) /* 4 total */
408 #define IXGBE_WQBR_TX(_i)    (0x8130 + ((_i) * 4)) /* 4 total */
409 #define IXGBE_L34T_IMIR(_i)  (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
410 #define IXGBE_RXFECCERR0         0x051B8
411 #define IXGBE_LLITHRESH 0x0EC90
412 #define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
413 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
414 #define IXGBE_IMIRVP    0x05AC0
415 #define IXGBE_VMD_CTL   0x0581C
416 #define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
417 #define IXGBE_ERETA(_i)	(0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */
418 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
419 
420 /* Registers for setting up RSS on X550 with SRIOV
421  * _p - pool number (0..63)
422  * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
423  */
424 #define IXGBE_PFVFMRQC(_p)	(0x03400 + ((_p) * 4))
425 #define IXGBE_PFVFRSSRK(_i, _p)	(0x018000 + ((_i) * 4) + ((_p) * 0x40))
426 #define IXGBE_PFVFRETA(_i, _p)	(0x019000 + ((_i) * 4) + ((_p) * 0x40))
427 
428 /* Flow Director registers */
429 #define IXGBE_FDIRCTRL  0x0EE00
430 #define IXGBE_FDIRHKEY  0x0EE68
431 #define IXGBE_FDIRSKEY  0x0EE6C
432 #define IXGBE_FDIRDIP4M 0x0EE3C
433 #define IXGBE_FDIRSIP4M 0x0EE40
434 #define IXGBE_FDIRTCPM  0x0EE44
435 #define IXGBE_FDIRUDPM  0x0EE48
436 #define IXGBE_FDIRSCTPM	0x0EE78
437 #define IXGBE_FDIRIP6M  0x0EE74
438 #define IXGBE_FDIRM     0x0EE70
439 
440 /* Flow Director Stats registers */
441 #define IXGBE_FDIRFREE  0x0EE38
442 #define IXGBE_FDIRLEN   0x0EE4C
443 #define IXGBE_FDIRUSTAT 0x0EE50
444 #define IXGBE_FDIRFSTAT 0x0EE54
445 #define IXGBE_FDIRMATCH 0x0EE58
446 #define IXGBE_FDIRMISS  0x0EE5C
447 
448 /* Flow Director Programming registers */
449 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
450 #define IXGBE_FDIRIPSA      0x0EE18
451 #define IXGBE_FDIRIPDA      0x0EE1C
452 #define IXGBE_FDIRPORT      0x0EE20
453 #define IXGBE_FDIRVLAN      0x0EE24
454 #define IXGBE_FDIRHASH      0x0EE28
455 #define IXGBE_FDIRCMD       0x0EE2C
456 
457 /* Transmit DMA registers */
458 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
459 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
460 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
461 #define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
462 #define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
463 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
464 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
465 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
466 #define IXGBE_DTXCTL    0x07E00
467 
468 #define IXGBE_DMATXCTL      0x04A80
469 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
470 #define IXGBE_PFDTXGSWC     0x08220
471 #define IXGBE_DTXMXSZRQ     0x08100
472 #define IXGBE_DTXTCPFLGL    0x04A88
473 #define IXGBE_DTXTCPFLGH    0x04A8C
474 #define IXGBE_LBDRPEN       0x0CA00
475 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
476 
477 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
478 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
479 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
480 #define IXGBE_DMATXCTL_MDP_EN   0x20 /* Bit 5 */
481 #define IXGBE_DMATXCTL_MBINTEN  0x40 /* Bit 6 */
482 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
483 
484 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
485 
486 /* Anti-spoofing defines */
487 #define IXGBE_SPOOF_MACAS_MASK          0xFF
488 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
489 #define IXGBE_SPOOF_VLANAS_SHIFT        8
490 #define IXGBE_SPOOF_ETHERTYPEAS		0xFF000000
491 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT	16
492 #define IXGBE_PFVFSPOOF_REG_COUNT       8
493 
494 #define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
495 /* Tx DCA Control register : 128 of these (0-127) */
496 #define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
497 #define IXGBE_TIPG      0x0CB00
498 #define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) * 4)) /* 8 of these */
499 #define IXGBE_MNGTXMAP  0x0CD10
500 #define IXGBE_TIPG_FIBER_DEFAULT 3
501 #define IXGBE_TXPBSIZE_SHIFT    10
502 
503 /* Wake up registers */
504 #define IXGBE_WUC       0x05800
505 #define IXGBE_WUFC      0x05808
506 #define IXGBE_WUS       0x05810
507 #define IXGBE_IPAV      0x05838
508 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
509 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
510 
511 #define IXGBE_WUPL      0x05900
512 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
513 #define IXGBE_VXLANCTRL	0x0000507C /* Rx filter VXLAN UDPPORT Register */
514 #define IXGBE_FHFT(_n)	(0x09000 + ((_n) * 0x100)) /* Flex host filter table */
515 #define IXGBE_FHFT_EXT(_n)	(0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
516 							    * Filter Table */
517 
518 /* masks for accessing VXLAN and GENEVE UDP ports */
519 #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK     0x0000ffff /* VXLAN port */
520 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK    0xffff0000 /* GENEVE port */
521 #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK       0xffffffff /* GENEVE/VXLAN */
522 
523 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT   16
524 
525 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
526 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
527 
528 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
529 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX  128
530 #define IXGBE_FHFT_LENGTH_OFFSET        0xFC  /* Length byte in FHFT */
531 #define IXGBE_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
532 
533 /* Definitions for power management and wakeup registers */
534 /* Wake Up Control */
535 #define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
536 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
537 #define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
538 
539 /* Wake Up Filter Control */
540 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
541 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
542 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
543 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
544 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
545 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
546 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
547 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
548 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
549 
550 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
551 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
552 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
553 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
554 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
555 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
556 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
557 #define IXGBE_WUFC_FLX_FILTERS     0x000F0000 /* Mask for 4 flex filters */
558 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
559 #define IXGBE_WUFC_ALL_FILTERS     0x003F00FF /* Mask for all wakeup filters */
560 #define IXGBE_WUFC_FLX_OFFSET      16 /* Offset to the Flexible Filters bits */
561 
562 /* Wake Up Status */
563 #define IXGBE_WUS_LNKC  IXGBE_WUFC_LNKC
564 #define IXGBE_WUS_MAG   IXGBE_WUFC_MAG
565 #define IXGBE_WUS_EX    IXGBE_WUFC_EX
566 #define IXGBE_WUS_MC    IXGBE_WUFC_MC
567 #define IXGBE_WUS_BC    IXGBE_WUFC_BC
568 #define IXGBE_WUS_ARP   IXGBE_WUFC_ARP
569 #define IXGBE_WUS_IPV4  IXGBE_WUFC_IPV4
570 #define IXGBE_WUS_IPV6  IXGBE_WUFC_IPV6
571 #define IXGBE_WUS_MNG   IXGBE_WUFC_MNG
572 #define IXGBE_WUS_FLX0  IXGBE_WUFC_FLX0
573 #define IXGBE_WUS_FLX1  IXGBE_WUFC_FLX1
574 #define IXGBE_WUS_FLX2  IXGBE_WUFC_FLX2
575 #define IXGBE_WUS_FLX3  IXGBE_WUFC_FLX3
576 #define IXGBE_WUS_FLX4  IXGBE_WUFC_FLX4
577 #define IXGBE_WUS_FLX5  IXGBE_WUFC_FLX5
578 #define IXGBE_WUS_FLX_FILTERS  IXGBE_WUFC_FLX_FILTERS
579 
580 /* Wake Up Packet Length */
581 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
582 
583 /* DCB registers */
584 #define MAX_TRAFFIC_CLASS        8
585 #define X540_TRAFFIC_CLASS       4
586 #define DEF_TRAFFIC_CLASS        1
587 #define IXGBE_RMCS      0x03D00
588 #define IXGBE_DPMCS     0x07F40
589 #define IXGBE_PDPMCS    0x0CD00
590 #define IXGBE_RUPPBMR   0x050A0
591 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
592 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
593 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
594 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
595 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
596 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
597 
598 /* Security Control Registers */
599 #define IXGBE_SECTXCTRL         0x08800
600 #define IXGBE_SECTXSTAT         0x08804
601 #define IXGBE_SECTXBUFFAF       0x08808
602 #define IXGBE_SECTXMINIFG       0x08810
603 #define IXGBE_SECRXCTRL         0x08D00
604 #define IXGBE_SECRXSTAT         0x08D04
605 
606 /* Security Bit Fields and Masks */
607 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
608 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
609 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
610 
611 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
612 #define IXGBE_SECTXSTAT_SECTX_OFF_DIS   0x00000002
613 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000004
614 
615 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
616 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
617 
618 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
619 #define IXGBE_SECRXSTAT_SECRX_OFF_DIS   0x00000002
620 #define IXGBE_SECRXSTAT_ECC_RXERR       0x00000004
621 
622 /* LinkSec (MacSec) Registers */
623 #define IXGBE_LSECTXCAP         0x08A00
624 #define IXGBE_LSECRXCAP         0x08F00
625 #define IXGBE_LSECTXCTRL        0x08A04
626 #define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
627 #define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
628 #define IXGBE_LSECTXSA          0x08A10
629 #define IXGBE_LSECTXPN0         0x08A14
630 #define IXGBE_LSECTXPN1         0x08A18
631 #define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
632 #define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
633 #define IXGBE_LSECRXCTRL        0x08F04
634 #define IXGBE_LSECRXSCL         0x08F08
635 #define IXGBE_LSECRXSCH         0x08F0C
636 #define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
637 #define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
638 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
639 #define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
640 #define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
641 #define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
642 #define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
643 #define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
644 #define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
645 #define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
646 #define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
647 #define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
648 #define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
649 #define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
650 #define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
651 #define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
652 #define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
653 #define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
654 #define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
655 #define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
656 #define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
657 #define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
658 
659 /* LinkSec (MacSec) Bit Fields and Masks */
660 #define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
661 #define IXGBE_LSECTXCAP_SUM_SHIFT       16
662 #define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
663 #define IXGBE_LSECRXCAP_SUM_SHIFT       16
664 
665 #define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
666 #define IXGBE_LSECTXCTRL_DISABLE        0x0
667 #define IXGBE_LSECTXCTRL_AUTH           0x1
668 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
669 #define IXGBE_LSECTXCTRL_AISCI          0x00000020
670 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
671 #define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
672 
673 #define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
674 #define IXGBE_LSECRXCTRL_EN_SHIFT       2
675 #define IXGBE_LSECRXCTRL_DISABLE        0x0
676 #define IXGBE_LSECRXCTRL_CHECK          0x1
677 #define IXGBE_LSECRXCTRL_STRICT         0x2
678 #define IXGBE_LSECRXCTRL_DROP           0x3
679 #define IXGBE_LSECRXCTRL_PLSH           0x00000040
680 #define IXGBE_LSECRXCTRL_RP             0x00000080
681 #define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
682 
683 /* IpSec Registers */
684 #define IXGBE_IPSTXIDX          0x08900
685 #define IXGBE_IPSTXSALT         0x08904
686 #define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
687 #define IXGBE_IPSRXIDX          0x08E00
688 #define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
689 #define IXGBE_IPSRXSPI          0x08E14
690 #define IXGBE_IPSRXIPIDX        0x08E18
691 #define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
692 #define IXGBE_IPSRXSALT         0x08E2C
693 #define IXGBE_IPSRXMOD          0x08E30
694 
695 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
696 
697 /* DCB registers */
698 #define IXGBE_RTRPCS      0x02430
699 #define IXGBE_RTTDCS      0x04900
700 #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
701 #define IXGBE_RTTPCS      0x0CD00
702 #define IXGBE_RTRUP2TC    0x03020
703 #define IXGBE_RTTUP2TC    0x0C800
704 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
705 #define IXGBE_TXLLQ(_i)   (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
706 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
707 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
708 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
709 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
710 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
711 #define IXGBE_RTTDQSEL    0x04904
712 #define IXGBE_RTTDT1C     0x04908
713 #define IXGBE_RTTDT1S     0x0490C
714 #define IXGBE_RTTQCNCR    0x08B00
715 #define IXGBE_RTTQCNTG    0x04A90
716 #define IXGBE_RTTBCNRD    0x0498C
717 #define IXGBE_RTTQCNRR    0x0498C
718 #define IXGBE_RTTDTECC    0x04990
719 #define IXGBE_RTTDTECC_NO_BCN   0x00000100
720 #define IXGBE_RTTBCNRC    0x04984
721 #define IXGBE_RTTBCNRC_RS_ENA	0x80000000
722 #define IXGBE_RTTBCNRC_RF_DEC_MASK	0x00003FFF
723 #define IXGBE_RTTBCNRC_RF_INT_SHIFT	14
724 #define IXGBE_RTTBCNRC_RF_INT_MASK	\
725 	(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
726 #define IXGBE_RTTBCNRM    0x04980
727 #define IXGBE_RTTQCNRM    0x04980
728 
729 /* FCoE Direct DMA Context */
730 #define IXGBE_FCDDC(_i, _j)	(0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
731 /* FCoE DMA Context Registers */
732 #define IXGBE_FCPTRL    0x02410 /* FC User Desc. PTR Low */
733 #define IXGBE_FCPTRH    0x02414 /* FC USer Desc. PTR High */
734 #define IXGBE_FCBUFF    0x02418 /* FC Buffer Control */
735 #define IXGBE_FCDMARW   0x02420 /* FC Receive DMA RW */
736 #define IXGBE_FCINVST0  0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
737 #define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
738 #define IXGBE_FCBUFF_VALID      BIT(0)    /* DMA Context Valid */
739 #define IXGBE_FCBUFF_BUFFSIZE   (3u << 3) /* User Buffer Size */
740 #define IXGBE_FCBUFF_WRCONTX    BIT(7)    /* 0: Initiator, 1: Target */
741 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
742 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
743 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT  3
744 #define IXGBE_FCBUFF_BUFFCNT_SHIFT   8
745 #define IXGBE_FCBUFF_OFFSET_SHIFT    16
746 #define IXGBE_FCDMARW_WE        BIT(14)   /* Write enable */
747 #define IXGBE_FCDMARW_RE        BIT(15)   /* Read enable */
748 #define IXGBE_FCDMARW_FCOESEL   0x000001ff  /* FC X_ID: 11 bits */
749 #define IXGBE_FCDMARW_LASTSIZE  0xffff0000  /* Last User Buffer Size */
750 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
751 
752 /* FCoE SOF/EOF */
753 #define IXGBE_TEOFF     0x04A94 /* Tx FC EOF */
754 #define IXGBE_TSOFF     0x04A98 /* Tx FC SOF */
755 #define IXGBE_REOFF     0x05158 /* Rx FC EOF */
756 #define IXGBE_RSOFF     0x051F8 /* Rx FC SOF */
757 /* FCoE Direct Filter Context */
758 #define IXGBE_FCDFC(_i, _j)	(0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
759 #define IXGBE_FCDFCD(_i)	(0x30000 + ((_i) * 0x4))
760 /* FCoE Filter Context Registers */
761 #define IXGBE_FCFLT     0x05108 /* FC FLT Context */
762 #define IXGBE_FCFLTRW   0x05110 /* FC Filter RW Control */
763 #define IXGBE_FCPARAM   0x051d8 /* FC Offset Parameter */
764 #define IXGBE_FCFLT_VALID       BIT(0)   /* Filter Context Valid */
765 #define IXGBE_FCFLT_FIRST       BIT(1)   /* Filter First */
766 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
767 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
768 #define IXGBE_FCFLTRW_RVALDT    BIT(13)  /* Fast Re-Validation */
769 #define IXGBE_FCFLTRW_WE        BIT(14)  /* Write Enable */
770 #define IXGBE_FCFLTRW_RE        BIT(15)  /* Read Enable */
771 /* FCoE Receive Control */
772 #define IXGBE_FCRXCTRL  0x05100 /* FC Receive Control */
773 #define IXGBE_FCRXCTRL_FCOELLI  BIT(0)   /* Low latency interrupt */
774 #define IXGBE_FCRXCTRL_SAVBAD   BIT(1)   /* Save Bad Frames */
775 #define IXGBE_FCRXCTRL_FRSTRDH  BIT(2)   /* EN 1st Read Header */
776 #define IXGBE_FCRXCTRL_LASTSEQH BIT(3)   /* EN Last Header in Seq */
777 #define IXGBE_FCRXCTRL_ALLH     BIT(4)   /* EN All Headers */
778 #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5)   /* EN 1st Seq. Header */
779 #define IXGBE_FCRXCTRL_ICRC     BIT(6)   /* Ignore Bad FC CRC */
780 #define IXGBE_FCRXCTRL_FCCRCBO  BIT(7)   /* FC CRC Byte Ordering */
781 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
782 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
783 /* FCoE Redirection */
784 #define IXGBE_FCRECTL   0x0ED00 /* FC Redirection Control */
785 #define IXGBE_FCRETA0   0x0ED10 /* FC Redirection Table 0 */
786 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
787 #define IXGBE_FCRECTL_ENA       0x1        /* FCoE Redir Table Enable */
788 #define IXGBE_FCRETA_SIZE       8          /* Max entries in FCRETA */
789 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
790 #define IXGBE_FCRETA_SIZE_X550	32 /* Max entries in FCRETA */
791 /* Higher 7 bits for the queue index */
792 #define IXGBE_FCRETA_ENTRY_HIGH_MASK	0x007F0000
793 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT	16
794 
795 /* Stats registers */
796 #define IXGBE_CRCERRS   0x04000
797 #define IXGBE_ILLERRC   0x04004
798 #define IXGBE_ERRBC     0x04008
799 #define IXGBE_MSPDC     0x04010
800 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
801 #define IXGBE_MLFC      0x04034
802 #define IXGBE_MRFC      0x04038
803 #define IXGBE_RLEC      0x04040
804 #define IXGBE_LXONTXC   0x03F60
805 #define IXGBE_LXONRXC   0x0CF60
806 #define IXGBE_LXOFFTXC  0x03F68
807 #define IXGBE_LXOFFRXC  0x0CF68
808 #define IXGBE_LXONRXCNT 0x041A4
809 #define IXGBE_LXOFFRXCNT 0x041A8
810 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
811 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
812 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
813 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
814 #define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
815 #define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
816 #define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
817 #define IXGBE_PRC64     0x0405C
818 #define IXGBE_PRC127    0x04060
819 #define IXGBE_PRC255    0x04064
820 #define IXGBE_PRC511    0x04068
821 #define IXGBE_PRC1023   0x0406C
822 #define IXGBE_PRC1522   0x04070
823 #define IXGBE_GPRC      0x04074
824 #define IXGBE_BPRC      0x04078
825 #define IXGBE_MPRC      0x0407C
826 #define IXGBE_GPTC      0x04080
827 #define IXGBE_GORCL     0x04088
828 #define IXGBE_GORCH     0x0408C
829 #define IXGBE_GOTCL     0x04090
830 #define IXGBE_GOTCH     0x04094
831 #define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
832 #define IXGBE_RUC       0x040A4
833 #define IXGBE_RFC       0x040A8
834 #define IXGBE_ROC       0x040AC
835 #define IXGBE_RJC       0x040B0
836 #define IXGBE_MNGPRC    0x040B4
837 #define IXGBE_MNGPDC    0x040B8
838 #define IXGBE_MNGPTC    0x0CF90
839 #define IXGBE_TORL      0x040C0
840 #define IXGBE_TORH      0x040C4
841 #define IXGBE_TPR       0x040D0
842 #define IXGBE_TPT       0x040D4
843 #define IXGBE_PTC64     0x040D8
844 #define IXGBE_PTC127    0x040DC
845 #define IXGBE_PTC255    0x040E0
846 #define IXGBE_PTC511    0x040E4
847 #define IXGBE_PTC1023   0x040E8
848 #define IXGBE_PTC1522   0x040EC
849 #define IXGBE_MPTC      0x040F0
850 #define IXGBE_BPTC      0x040F4
851 #define IXGBE_XEC       0x04120
852 #define IXGBE_SSVPC     0x08780
853 
854 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
855 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
856 			 (0x08600 + ((_i) * 4)))
857 #define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
858 
859 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
860 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
861 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
862 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
863 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
864 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
865 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
866 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
867 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
868 #define IXGBE_FCCRC     0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
869 #define IXGBE_FCOERPDC  0x0241C /* FCoE Rx Packets Dropped Count */
870 #define IXGBE_FCLAST    0x02424 /* FCoE Last Error Count */
871 #define IXGBE_FCOEPRC   0x02428 /* Number of FCoE Packets Received */
872 #define IXGBE_FCOEDWRC  0x0242C /* Number of FCoE DWords Received */
873 #define IXGBE_FCOEPTC   0x08784 /* Number of FCoE Packets Transmitted */
874 #define IXGBE_FCOEDWTC  0x08788 /* Number of FCoE DWords Transmitted */
875 #define IXGBE_O2BGPTC   0x041C4
876 #define IXGBE_O2BSPC    0x087B0
877 #define IXGBE_B2OSPC    0x041C0
878 #define IXGBE_B2OGPRC   0x02F90
879 #define IXGBE_PCRC8ECL  0x0E810
880 #define IXGBE_PCRC8ECH  0x0E811
881 #define IXGBE_PCRC8ECH_MASK     0x1F
882 #define IXGBE_LDPCECL   0x0E820
883 #define IXGBE_LDPCECH   0x0E821
884 
885 /* MII clause 22/28 definitions */
886 #define IXGBE_MDIO_PHY_LOW_POWER_MODE	0x0800
887 
888 #define IXGBE_MDIO_XENPAK_LASI_STATUS	0x9005 /* XENPAK LASI Status register */
889 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */
890 
891 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS	0x4 /* Indicates if link is up */
892 
893 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK	0x7 /* Speed/Duplex Mask */
894 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK	0x6 /* Speed Mask */
895 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
896 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
897 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */
898 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */
899 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */
900 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
901 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
902 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
903 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB	0x4 /* 1Gb/s */
904 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB	0x6 /* 10Gb/s */
905 
906 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400	/* 1G Provisioning 1 */
907 #define IXGBE_MII_AUTONEG_XNP_TX_REG		0x17	/* 1G XNP Transmit */
908 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX	0x4000	/* full duplex, bit:14*/
909 #define IXGBE_MII_1GBASE_T_ADVERTISE		0x8000	/* full duplex, bit:15*/
910 #define IXGBE_MII_2_5GBASE_T_ADVERTISE		0x0400
911 #define IXGBE_MII_5GBASE_T_ADVERTISE		0x0800
912 #define IXGBE_MII_RESTART			0x200
913 #define IXGBE_MII_AUTONEG_LINK_UP		0x04
914 #define IXGBE_MII_AUTONEG_REG			0x0
915 
916 /* Management */
917 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
918 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
919 #define IXGBE_MANC      0x05820
920 #define IXGBE_MFVAL     0x05824
921 #define IXGBE_MANC2H    0x05860
922 #define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
923 #define IXGBE_MIPAF     0x058B0
924 #define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
925 #define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
926 #define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
927 #define IXGBE_METF(_i)  (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
928 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
929 #define IXGBE_LSWFW     0x15014
930 
931 /* Management Bit Fields and Masks */
932 #define IXGBE_MANC_RCV_TCO_EN	0x00020000 /* Rcv TCO packet enable */
933 
934 /* Firmware Semaphore Register */
935 #define IXGBE_FWSM_MODE_MASK	0xE
936 #define IXGBE_FWSM_FW_MODE_PT	0x4
937 #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE	BIT(5)
938 #define IXGBE_FWSM_EXT_ERR_IND_MASK	0x01F80000
939 #define IXGBE_FWSM_FW_VAL_BIT	BIT(15)
940 
941 /* ARC Subsystem registers */
942 #define IXGBE_HICR      0x15F00
943 #define IXGBE_FWSTS     0x15F0C
944 #define IXGBE_HSMC0R    0x15F04
945 #define IXGBE_HSMC1R    0x15F08
946 #define IXGBE_SWSR      0x15F10
947 #define IXGBE_HFDR      0x15FE8
948 #define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
949 
950 #define IXGBE_HICR_EN              0x01  /* Enable bit - RO */
951 /* Driver sets this bit when done to put command in RAM */
952 #define IXGBE_HICR_C               0x02
953 #define IXGBE_HICR_SV              0x04  /* Status Validity */
954 #define IXGBE_HICR_FW_RESET_ENABLE 0x40
955 #define IXGBE_HICR_FW_RESET        0x80
956 
957 /* PCI-E registers */
958 #define IXGBE_GCR       0x11000
959 #define IXGBE_GTV       0x11004
960 #define IXGBE_FUNCTAG   0x11008
961 #define IXGBE_GLT       0x1100C
962 #define IXGBE_GSCL_1    0x11010
963 #define IXGBE_GSCL_2    0x11014
964 #define IXGBE_GSCL_3    0x11018
965 #define IXGBE_GSCL_4    0x1101C
966 #define IXGBE_GSCN_0    0x11020
967 #define IXGBE_GSCN_1    0x11024
968 #define IXGBE_GSCN_2    0x11028
969 #define IXGBE_GSCN_3    0x1102C
970 #define IXGBE_FACTPS_8259X	0x10150
971 #define IXGBE_FACTPS_X540	IXGBE_FACTPS_8259X
972 #define IXGBE_FACTPS_X550	IXGBE_FACTPS_8259X
973 #define IXGBE_FACTPS_X550EM_x	IXGBE_FACTPS_8259X
974 #define IXGBE_FACTPS_X550EM_a	0x15FEC
975 #define IXGBE_FACTPS(_hw)	IXGBE_BY_MAC((_hw), FACTPS)
976 
977 #define IXGBE_PCIEANACTL  0x11040
978 #define IXGBE_SWSM_8259X	0x10140
979 #define IXGBE_SWSM_X540		IXGBE_SWSM_8259X
980 #define IXGBE_SWSM_X550		IXGBE_SWSM_8259X
981 #define IXGBE_SWSM_X550EM_x	IXGBE_SWSM_8259X
982 #define IXGBE_SWSM_X550EM_a	0x15F70
983 #define IXGBE_SWSM(_hw)		IXGBE_BY_MAC((_hw), SWSM)
984 #define IXGBE_FWSM_8259X	0x10148
985 #define IXGBE_FWSM_X540		IXGBE_FWSM_8259X
986 #define IXGBE_FWSM_X550		IXGBE_FWSM_8259X
987 #define IXGBE_FWSM_X550EM_x	IXGBE_FWSM_8259X
988 #define IXGBE_FWSM_X550EM_a	0x15F74
989 #define IXGBE_FWSM(_hw)		IXGBE_BY_MAC((_hw), FWSM)
990 #define IXGBE_GSSR      0x10160
991 #define IXGBE_MREVID    0x11064
992 #define IXGBE_DCA_ID    0x11070
993 #define IXGBE_DCA_CTRL  0x11074
994 #define IXGBE_SWFW_SYNC_8259X		IXGBE_GSSR
995 #define IXGBE_SWFW_SYNC_X540		IXGBE_SWFW_SYNC_8259X
996 #define IXGBE_SWFW_SYNC_X550		IXGBE_SWFW_SYNC_8259X
997 #define IXGBE_SWFW_SYNC_X550EM_x	IXGBE_SWFW_SYNC_8259X
998 #define IXGBE_SWFW_SYNC_X550EM_a	0x15F78
999 #define IXGBE_SWFW_SYNC(_hw)		IXGBE_BY_MAC((_hw), SWFW_SYNC)
1000 
1001 /* PCIe registers 82599-specific */
1002 #define IXGBE_GCR_EXT           0x11050
1003 #define IXGBE_GSCL_5_82599      0x11030
1004 #define IXGBE_GSCL_6_82599      0x11034
1005 #define IXGBE_GSCL_7_82599      0x11038
1006 #define IXGBE_GSCL_8_82599      0x1103C
1007 #define IXGBE_PHYADR_82599      0x11040
1008 #define IXGBE_PHYDAT_82599      0x11044
1009 #define IXGBE_PHYCTL_82599      0x11048
1010 #define IXGBE_PBACLR_82599      0x11068
1011 
1012 #define IXGBE_CIAA_8259X	0x11088
1013 #define IXGBE_CIAA_X540		IXGBE_CIAA_8259X
1014 #define IXGBE_CIAA_X550		0x11508
1015 #define IXGBE_CIAA_X550EM_x	IXGBE_CIAA_X550
1016 #define IXGBE_CIAA_X550EM_a	IXGBE_CIAA_X550
1017 #define IXGBE_CIAA(_hw)		IXGBE_BY_MAC((_hw), CIAA)
1018 
1019 #define IXGBE_CIAD_8259X	0x1108C
1020 #define IXGBE_CIAD_X540		IXGBE_CIAD_8259X
1021 #define IXGBE_CIAD_X550		0x11510
1022 #define IXGBE_CIAD_X550EM_x	IXGBE_CIAD_X550
1023 #define IXGBE_CIAD_X550EM_a	IXGBE_CIAD_X550
1024 #define IXGBE_CIAD(_hw)		IXGBE_BY_MAC((_hw), CIAD)
1025 
1026 #define IXGBE_PICAUSE           0x110B0
1027 #define IXGBE_PIENA             0x110B8
1028 #define IXGBE_CDQ_MBR_82599     0x110B4
1029 #define IXGBE_PCIESPARE         0x110BC
1030 #define IXGBE_MISC_REG_82599    0x110F0
1031 #define IXGBE_ECC_CTRL_0_82599  0x11100
1032 #define IXGBE_ECC_CTRL_1_82599  0x11104
1033 #define IXGBE_ECC_STATUS_82599  0x110E0
1034 #define IXGBE_BAR_CTRL_82599    0x110F4
1035 
1036 /* PCI Express Control */
1037 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
1038 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
1039 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
1040 #define IXGBE_GCR_CAP_VER2              0x00040000
1041 
1042 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
1043 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
1044 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
1045 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
1046 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
1047 #define IXGBE_GCR_EXT_VT_MODE_MASK      0x00000003
1048 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
1049 					 IXGBE_GCR_EXT_VT_MODE_64)
1050 
1051 /* Time Sync Registers */
1052 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
1053 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
1054 #define IXGBE_RXSTMPL    0x051E8 /* Rx timestamp Low - RO */
1055 #define IXGBE_RXSTMPH    0x051A4 /* Rx timestamp High - RO */
1056 #define IXGBE_RXSATRL    0x051A0 /* Rx timestamp attribute low - RO */
1057 #define IXGBE_RXSATRH    0x051A8 /* Rx timestamp attribute high - RO */
1058 #define IXGBE_RXMTRL     0x05120 /* RX message type register low - RW */
1059 #define IXGBE_TXSTMPL    0x08C04 /* Tx timestamp value Low - RO */
1060 #define IXGBE_TXSTMPH    0x08C08 /* Tx timestamp value High - RO */
1061 #define IXGBE_SYSTIML    0x08C0C /* System time register Low - RO */
1062 #define IXGBE_SYSTIMH    0x08C10 /* System time register High - RO */
1063 #define IXGBE_SYSTIMR    0x08C58 /* System time register Residue - RO */
1064 #define IXGBE_TIMINCA    0x08C14 /* Increment attributes register - RW */
1065 #define IXGBE_TIMADJL    0x08C18 /* Time Adjustment Offset register Low - RW */
1066 #define IXGBE_TIMADJH    0x08C1C /* Time Adjustment Offset register High - RW */
1067 #define IXGBE_TSAUXC     0x08C20 /* TimeSync Auxiliary Control register - RW */
1068 #define IXGBE_TRGTTIML0  0x08C24 /* Target Time Register 0 Low - RW */
1069 #define IXGBE_TRGTTIMH0  0x08C28 /* Target Time Register 0 High - RW */
1070 #define IXGBE_TRGTTIML1  0x08C2C /* Target Time Register 1 Low - RW */
1071 #define IXGBE_TRGTTIMH1  0x08C30 /* Target Time Register 1 High - RW */
1072 #define IXGBE_CLKTIML    0x08C34 /* Clock Out Time Register Low - RW */
1073 #define IXGBE_CLKTIMH    0x08C38 /* Clock Out Time Register High - RW */
1074 #define IXGBE_FREQOUT0   0x08C34 /* Frequency Out 0 Control register - RW */
1075 #define IXGBE_FREQOUT1   0x08C38 /* Frequency Out 1 Control register - RW */
1076 #define IXGBE_AUXSTMPL0  0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1077 #define IXGBE_AUXSTMPH0  0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1078 #define IXGBE_AUXSTMPL1  0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1079 #define IXGBE_AUXSTMPH1  0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1080 #define IXGBE_TSIM       0x08C68 /* TimeSync Interrupt Mask Register - RW */
1081 #define IXGBE_TSSDP      0x0003C /* TimeSync SDP Configuration Register - RW */
1082 
1083 /* Diagnostic Registers */
1084 #define IXGBE_RDSTATCTL   0x02C20
1085 #define IXGBE_RDSTAT(_i)  (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1086 #define IXGBE_RDHMPN      0x02F08
1087 #define IXGBE_RIC_DW(_i)  (0x02F10 + ((_i) * 4))
1088 #define IXGBE_RDPROBE     0x02F20
1089 #define IXGBE_RDMAM       0x02F30
1090 #define IXGBE_RDMAD       0x02F34
1091 #define IXGBE_TDSTATCTL   0x07C20
1092 #define IXGBE_TDSTAT(_i)  (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
1093 #define IXGBE_TDHMPN      0x07F08
1094 #define IXGBE_TDHMPN2     0x082FC
1095 #define IXGBE_TXDESCIC    0x082CC
1096 #define IXGBE_TIC_DW(_i)  (0x07F10 + ((_i) * 4))
1097 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1098 #define IXGBE_TDPROBE     0x07F20
1099 #define IXGBE_TXBUFCTRL   0x0C600
1100 #define IXGBE_TXBUFDATA(_i) (0x0C610 + ((_i) * 4)) /* 4 of these (0-3) */
1101 #define IXGBE_RXBUFCTRL   0x03600
1102 #define IXGBE_RXBUFDATA(_i) (0x03610 + ((_i) * 4)) /* 4 of these (0-3) */
1103 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
1104 #define IXGBE_RFVAL     0x050A4
1105 #define IXGBE_MDFTC1    0x042B8
1106 #define IXGBE_MDFTC2    0x042C0
1107 #define IXGBE_MDFTFIFO1 0x042C4
1108 #define IXGBE_MDFTFIFO2 0x042C8
1109 #define IXGBE_MDFTS     0x042CC
1110 #define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
1111 #define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
1112 #define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
1113 #define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
1114 #define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
1115 #define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
1116 #define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
1117 #define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
1118 #define IXGBE_PCIEECCCTL 0x1106C
1119 #define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
1120 #define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
1121 #define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
1122 #define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
1123 #define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
1124 #define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
1125 #define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
1126 #define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
1127 #define IXGBE_PCIEECCCTL0 0x11100
1128 #define IXGBE_PCIEECCCTL1 0x11104
1129 #define IXGBE_RXDBUECC  0x03F70
1130 #define IXGBE_TXDBUECC  0x0CF70
1131 #define IXGBE_RXDBUEST 0x03F74
1132 #define IXGBE_TXDBUEST 0x0CF74
1133 #define IXGBE_PBTXECC   0x0C300
1134 #define IXGBE_PBRXECC   0x03300
1135 #define IXGBE_GHECCR    0x110B0
1136 
1137 /* MAC Registers */
1138 #define IXGBE_PCS1GCFIG 0x04200
1139 #define IXGBE_PCS1GLCTL 0x04208
1140 #define IXGBE_PCS1GLSTA 0x0420C
1141 #define IXGBE_PCS1GDBG0 0x04210
1142 #define IXGBE_PCS1GDBG1 0x04214
1143 #define IXGBE_PCS1GANA  0x04218
1144 #define IXGBE_PCS1GANLP 0x0421C
1145 #define IXGBE_PCS1GANNP 0x04220
1146 #define IXGBE_PCS1GANLPNP 0x04224
1147 #define IXGBE_HLREG0    0x04240
1148 #define IXGBE_HLREG1    0x04244
1149 #define IXGBE_PAP       0x04248
1150 #define IXGBE_MACA      0x0424C
1151 #define IXGBE_APAE      0x04250
1152 #define IXGBE_ARD       0x04254
1153 #define IXGBE_AIS       0x04258
1154 #define IXGBE_MSCA      0x0425C
1155 #define IXGBE_MSRWD     0x04260
1156 #define IXGBE_MLADD     0x04264
1157 #define IXGBE_MHADD     0x04268
1158 #define IXGBE_MAXFRS    0x04268
1159 #define IXGBE_TREG      0x0426C
1160 #define IXGBE_PCSS1     0x04288
1161 #define IXGBE_PCSS2     0x0428C
1162 #define IXGBE_XPCSS     0x04290
1163 #define IXGBE_MFLCN     0x04294
1164 #define IXGBE_SERDESC   0x04298
1165 #define IXGBE_MAC_SGMII_BUSY 0x04298
1166 #define IXGBE_MACS      0x0429C
1167 #define IXGBE_AUTOC     0x042A0
1168 #define IXGBE_LINKS     0x042A4
1169 #define IXGBE_LINKS2    0x04324
1170 #define IXGBE_AUTOC2    0x042A8
1171 #define IXGBE_AUTOC3    0x042AC
1172 #define IXGBE_ANLP1     0x042B0
1173 #define IXGBE_ANLP2     0x042B4
1174 #define IXGBE_MACC      0x04330
1175 #define IXGBE_ATLASCTL  0x04800
1176 #define IXGBE_MMNGC     0x042D0
1177 #define IXGBE_ANLPNP1   0x042D4
1178 #define IXGBE_ANLPNP2   0x042D8
1179 #define IXGBE_KRPCSFC   0x042E0
1180 #define IXGBE_KRPCSS    0x042E4
1181 #define IXGBE_FECS1     0x042E8
1182 #define IXGBE_FECS2     0x042EC
1183 #define IXGBE_SMADARCTL 0x14F10
1184 #define IXGBE_MPVC      0x04318
1185 #define IXGBE_SGMIIC    0x04314
1186 
1187 /* Statistics Registers */
1188 #define IXGBE_RXNFGPC      0x041B0
1189 #define IXGBE_RXNFGBCL     0x041B4
1190 #define IXGBE_RXNFGBCH     0x041B8
1191 #define IXGBE_RXDGPC       0x02F50
1192 #define IXGBE_RXDGBCL      0x02F54
1193 #define IXGBE_RXDGBCH      0x02F58
1194 #define IXGBE_RXDDGPC      0x02F5C
1195 #define IXGBE_RXDDGBCL     0x02F60
1196 #define IXGBE_RXDDGBCH     0x02F64
1197 #define IXGBE_RXLPBKGPC    0x02F68
1198 #define IXGBE_RXLPBKGBCL   0x02F6C
1199 #define IXGBE_RXLPBKGBCH   0x02F70
1200 #define IXGBE_RXDLPBKGPC   0x02F74
1201 #define IXGBE_RXDLPBKGBCL  0x02F78
1202 #define IXGBE_RXDLPBKGBCH  0x02F7C
1203 #define IXGBE_TXDGPC       0x087A0
1204 #define IXGBE_TXDGBCL      0x087A4
1205 #define IXGBE_TXDGBCH      0x087A8
1206 
1207 #define IXGBE_RXDSTATCTRL 0x02F40
1208 
1209 /* Copper Pond 2 link timeout */
1210 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1211 
1212 /* Omer CORECTL */
1213 #define IXGBE_CORECTL           0x014F00
1214 /* BARCTRL */
1215 #define IXGBE_BARCTRL               0x110F4
1216 #define IXGBE_BARCTRL_FLSIZE        0x0700
1217 #define IXGBE_BARCTRL_FLSIZE_SHIFT  8
1218 #define IXGBE_BARCTRL_CSRSIZE       0x2000
1219 
1220 /* RSCCTL Bit Masks */
1221 #define IXGBE_RSCCTL_RSCEN          0x01
1222 #define IXGBE_RSCCTL_MAXDESC_1      0x00
1223 #define IXGBE_RSCCTL_MAXDESC_4      0x04
1224 #define IXGBE_RSCCTL_MAXDESC_8      0x08
1225 #define IXGBE_RSCCTL_MAXDESC_16     0x0C
1226 
1227 /* RSCDBU Bit Masks */
1228 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1229 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1230 
1231 /* RDRXCTL Bit Masks */
1232 #define IXGBE_RDRXCTL_RDMTS_1_2     0x00000000 /* Rx Desc Min Threshold Size */
1233 #define IXGBE_RDRXCTL_CRCSTRIP      0x00000002 /* CRC Strip */
1234 #define IXGBE_RDRXCTL_PSP           0x00000004 /* Pad small packet */
1235 #define IXGBE_RDRXCTL_MVMEN         0x00000020
1236 #define IXGBE_RDRXCTL_DMAIDONE      0x00000008 /* DMA init cycle done */
1237 #define IXGBE_RDRXCTL_AGGDIS        0x00010000 /* Aggregation disable */
1238 #define IXGBE_RDRXCTL_RSCFRSTSIZE   0x003E0000 /* RSC First packet size */
1239 #define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
1240 #define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
1241 #define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
1242 #define IXGBE_RDRXCTL_MBINTEN       0x10000000
1243 #define IXGBE_RDRXCTL_MDP_EN        0x20000000
1244 
1245 /* RQTC Bit Masks and Shifts */
1246 #define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
1247 #define IXGBE_RQTC_TC0_MASK         (0x7 << 0)
1248 #define IXGBE_RQTC_TC1_MASK         (0x7 << 4)
1249 #define IXGBE_RQTC_TC2_MASK         (0x7 << 8)
1250 #define IXGBE_RQTC_TC3_MASK         (0x7 << 12)
1251 #define IXGBE_RQTC_TC4_MASK         (0x7 << 16)
1252 #define IXGBE_RQTC_TC5_MASK         (0x7 << 20)
1253 #define IXGBE_RQTC_TC6_MASK         (0x7 << 24)
1254 #define IXGBE_RQTC_TC7_MASK         (0x7 << 28)
1255 
1256 /* PSRTYPE.RQPL Bit masks and shift */
1257 #define IXGBE_PSRTYPE_RQPL_MASK     0x7
1258 #define IXGBE_PSRTYPE_RQPL_SHIFT    29
1259 
1260 /* CTRL Bit Masks */
1261 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Primary Disable bit */
1262 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1263 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1264 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1265 
1266 /* FACTPS */
1267 #define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
1268 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1269 
1270 /* MHADD Bit Masks */
1271 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1272 #define IXGBE_MHADD_MFS_SHIFT   16
1273 
1274 /* Extended Device Control */
1275 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1276 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1277 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1278 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1279 
1280 /* Direct Cache Access (DCA) definitions */
1281 #define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
1282 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1283 
1284 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1285 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1286 
1287 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1288 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599  0xFF000000 /* Rx CPUID Mask */
1289 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1290 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
1291 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
1292 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
1293 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
1294 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */
1295 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */
1296 
1297 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1298 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
1299 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1300 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
1301 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
1302 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */
1303 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
1304 #define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
1305 
1306 /* MSCA Bit Masks */
1307 #define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
1308 #define IXGBE_MSCA_NP_ADDR_SHIFT     0
1309 #define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
1310 #define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
1311 #define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
1312 #define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
1313 #define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
1314 #define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
1315 #define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
1316 #define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
1317 #define IXGBE_MSCA_READ              0x0C000000 /* OP CODE 11 (read) */
1318 #define IXGBE_MSCA_READ_AUTOINC      0x08000000 /* OP CODE 10 (read, auto inc)*/
1319 #define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
1320 #define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
1321 #define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
1322 #define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
1323 #define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
1324 #define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
1325 
1326 /* MSRWD bit masks */
1327 #define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
1328 #define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
1329 #define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
1330 #define IXGBE_MSRWD_READ_DATA_SHIFT     16
1331 
1332 /* Atlas registers */
1333 #define IXGBE_ATLAS_PDN_LPBK    0x24
1334 #define IXGBE_ATLAS_PDN_10G     0xB
1335 #define IXGBE_ATLAS_PDN_1G      0xC
1336 #define IXGBE_ATLAS_PDN_AN      0xD
1337 
1338 /* Atlas bit masks */
1339 #define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
1340 #define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
1341 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
1342 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
1343 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
1344 
1345 /* Omer bit masks */
1346 #define IXGBE_CORECTL_WRITE_CMD         0x00010000
1347 
1348 /* MDIO definitions */
1349 
1350 #define IXGBE_MDIO_ZERO_DEV_TYPE		0x0
1351 #define IXGBE_MDIO_PCS_DEV_TYPE		0x3
1352 #define IXGBE_TWINAX_DEV			1
1353 
1354 #define IXGBE_MDIO_COMMAND_TIMEOUT     100 /* PHY Timeout for 1 GB mode */
1355 
1356 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
1357 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1358 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
1359 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
1360 
1361 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT	0xC800 /* AUTO_NEG Vendor Status Reg */
1362 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM  0xCC00 /* AUTO_NEG Vendor TX Reg */
1363 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1364 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC	0x1 /* AUTO_NEG Vendor Tx LSC */
1365 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT	0x3C /* AUTO_NEG EEE Advt Reg */
1366 
1367 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE	 0x0800 /* Set low power mode */
1368 #define IXGBE_AUTO_NEG_LP_STATUS	0xE820 /* AUTO NEG Rx LP Status Reg */
1369 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP	0x8000 /* AUTO NEG Rx LP 1000BaseT */
1370 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3	0xCC02 /* Vendor Alarms 3 Reg */
1371 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
1372 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1373 #define IXGBE_MDIO_POWER_UP_STALL	0x8000 /* Power Up Stall */
1374 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK	0xFF00 /* int std mask */
1375 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG	0xFC00 /* chip std int flag */
1376 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK	0xFF01 /* int chip-wide mask */
1377 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG	0xFC01 /* int chip-wide mask */
1378 #define IXGBE_MDIO_GLOBAL_ALARM_1		0xCC00 /* Global alarm 1 */
1379 #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT	0x0010 /* device fault */
1380 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL	0x4000 /* high temp failure */
1381 #define IXGBE_MDIO_GLOBAL_FAULT_MSG		0xC850 /* global fault msg */
1382 #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP	0x8007 /* high temp failure */
1383 #define IXGBE_MDIO_GLOBAL_INT_MASK		0xD400 /* Global int mask */
1384 /* autoneg vendor alarm int enable */
1385 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN	0x1000
1386 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT		0x4 /* int in Global alarm 1 */
1387 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN	0x1 /* vendor alarm int enable */
1388 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT		0x200 /* vendor alarm2 int mask */
1389 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN	0x4000 /* int high temp enable */
1390 #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN	0x0010 /*int dev fault enable */
1391 
1392 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR	0xC30A /* PHY_XS SDA/SCL Addr Reg */
1393 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA	0xC30B /* PHY_XS SDA/SCL Data Reg */
1394 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT	0xC30C /* PHY_XS SDA/SCL Stat Reg */
1395 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK	0xD401 /* PHY TX Vendor LASI */
1396 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN	0x1 /* PHY TX Vendor LASI enable */
1397 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR	0x9 /* Standard Tx Dis Reg */
1398 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE	0x0001 /* PMD Global Tx Dis */
1399 
1400 /* MII clause 22/28 definitions */
1401 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1402 #define IXGBE_MII_AUTONEG_XNP_TX_REG             0x17   /* 1G XNP Transmit */
1403 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX      0x4000 /* full duplex, bit:14*/
1404 #define IXGBE_MII_1GBASE_T_ADVERTISE             0x8000 /* full duplex, bit:15*/
1405 #define IXGBE_MII_AUTONEG_REG                    0x0
1406 
1407 #define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
1408 #define IXGBE_MAX_PHY_ADDR             32
1409 
1410 /* PHY IDs*/
1411 #define TN1010_PHY_ID    0x00A19410
1412 #define TNX_FW_REV       0xB
1413 #define X540_PHY_ID      0x01540200
1414 #define X550_PHY_ID2	0x01540223
1415 #define X550_PHY_ID3	0x01540221
1416 #define X557_PHY_ID      0x01540240
1417 #define X557_PHY_ID2	0x01540250
1418 #define QT2022_PHY_ID    0x0043A400
1419 #define ATH_PHY_ID       0x03429050
1420 #define AQ_FW_REV        0x20
1421 #define BCM54616S_E_PHY_ID 0x03625D10
1422 
1423 /* Special PHY Init Routine */
1424 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1425 #define IXGBE_PHY_INIT_END_NL    0xFFFF
1426 #define IXGBE_CONTROL_MASK_NL    0xF000
1427 #define IXGBE_DATA_MASK_NL       0x0FFF
1428 #define IXGBE_CONTROL_SHIFT_NL   12
1429 #define IXGBE_DELAY_NL           0
1430 #define IXGBE_DATA_NL            1
1431 #define IXGBE_CONTROL_NL         0x000F
1432 #define IXGBE_CONTROL_EOL_NL     0x0FFF
1433 #define IXGBE_CONTROL_SOL_NL     0x0000
1434 
1435 /* General purpose Interrupt Enable */
1436 #define IXGBE_SDP0_GPIEN_8259X		0x00000001 /* SDP0 */
1437 #define IXGBE_SDP1_GPIEN_8259X		0x00000002 /* SDP1 */
1438 #define IXGBE_SDP2_GPIEN_8259X		0x00000004 /* SDP2 */
1439 #define IXGBE_SDP0_GPIEN_X540		0x00000002 /* SDP0 on X540 and X550 */
1440 #define IXGBE_SDP1_GPIEN_X540		0x00000004 /* SDP1 on X540 and X550 */
1441 #define IXGBE_SDP2_GPIEN_X540		0x00000008 /* SDP2 on X540 and X550 */
1442 #define IXGBE_SDP0_GPIEN_X550		IXGBE_SDP0_GPIEN_X540
1443 #define IXGBE_SDP1_GPIEN_X550		IXGBE_SDP1_GPIEN_X540
1444 #define IXGBE_SDP2_GPIEN_X550		IXGBE_SDP2_GPIEN_X540
1445 #define IXGBE_SDP0_GPIEN_X550EM_x	IXGBE_SDP0_GPIEN_X540
1446 #define IXGBE_SDP1_GPIEN_X550EM_x	IXGBE_SDP1_GPIEN_X540
1447 #define IXGBE_SDP2_GPIEN_X550EM_x	IXGBE_SDP2_GPIEN_X540
1448 #define IXGBE_SDP0_GPIEN_X550EM_a	IXGBE_SDP0_GPIEN_X540
1449 #define IXGBE_SDP1_GPIEN_X550EM_a	IXGBE_SDP1_GPIEN_X540
1450 #define IXGBE_SDP2_GPIEN_X550EM_a	IXGBE_SDP2_GPIEN_X540
1451 #define IXGBE_SDP0_GPIEN(_hw)		IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1452 #define IXGBE_SDP1_GPIEN(_hw)		IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1453 #define IXGBE_SDP2_GPIEN(_hw)		IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1454 
1455 #define IXGBE_GPIE_MSIX_MODE     0x00000010 /* MSI-X mode */
1456 #define IXGBE_GPIE_OCD           0x00000020 /* Other Clear Disable */
1457 #define IXGBE_GPIE_EIMEN         0x00000040 /* Immediate Interrupt Enable */
1458 #define IXGBE_GPIE_EIAME         0x40000000
1459 #define IXGBE_GPIE_PBA_SUPPORT   0x80000000
1460 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1461 #define IXGBE_GPIE_VTMODE_MASK   0x0000C000 /* VT Mode Mask */
1462 #define IXGBE_GPIE_VTMODE_16     0x00004000 /* 16 VFs 8 queues per VF */
1463 #define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
1464 #define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
1465 
1466 /* Packet Buffer Initialization */
1467 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1468 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1469 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1470 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1471 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1472 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
1473 #define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer*/
1474 #define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
1475 
1476 #define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
1477 #define IXGBE_MAX_PB		8
1478 
1479 /* Packet buffer allocation strategies */
1480 enum {
1481 	PBA_STRATEGY_EQUAL	= 0,	/* Distribute PB space equally */
1482 #define PBA_STRATEGY_EQUAL	PBA_STRATEGY_EQUAL
1483 	PBA_STRATEGY_WEIGHTED	= 1,	/* Weight front half of TCs */
1484 #define PBA_STRATEGY_WEIGHTED	PBA_STRATEGY_WEIGHTED
1485 };
1486 
1487 /* Transmit Flow Control status */
1488 #define IXGBE_TFCS_TXOFF         0x00000001
1489 #define IXGBE_TFCS_TXOFF0        0x00000100
1490 #define IXGBE_TFCS_TXOFF1        0x00000200
1491 #define IXGBE_TFCS_TXOFF2        0x00000400
1492 #define IXGBE_TFCS_TXOFF3        0x00000800
1493 #define IXGBE_TFCS_TXOFF4        0x00001000
1494 #define IXGBE_TFCS_TXOFF5        0x00002000
1495 #define IXGBE_TFCS_TXOFF6        0x00004000
1496 #define IXGBE_TFCS_TXOFF7        0x00008000
1497 
1498 /* TCP Timer */
1499 #define IXGBE_TCPTIMER_KS            0x00000100
1500 #define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
1501 #define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
1502 #define IXGBE_TCPTIMER_LOOP          0x00000800
1503 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1504 
1505 /* HLREG0 Bit Masks */
1506 #define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
1507 #define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
1508 #define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
1509 #define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
1510 #define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
1511 #define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
1512 #define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
1513 #define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
1514 #define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
1515 #define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
1516 #define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
1517 #define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
1518 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
1519 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
1520 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
1521 
1522 /* VMD_CTL bitmasks */
1523 #define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
1524 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1525 
1526 /* VT_CTL bitmasks */
1527 #define IXGBE_VT_CTL_DIS_DEFPL  0x20000000 /* disable default pool */
1528 #define IXGBE_VT_CTL_REPLEN     0x40000000 /* replication enabled */
1529 #define IXGBE_VT_CTL_VT_ENABLE  0x00000001  /* Enable VT Mode */
1530 #define IXGBE_VT_CTL_POOL_SHIFT 7
1531 #define IXGBE_VT_CTL_POOL_MASK  (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1532 
1533 /* VMOLR bitmasks */
1534 #define IXGBE_VMOLR_UPE		0x00400000 /* unicast promiscuous */
1535 #define IXGBE_VMOLR_VPE		0x00800000 /* VLAN promiscuous */
1536 #define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
1537 #define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
1538 #define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
1539 #define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
1540 #define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
1541 
1542 /* VFRE bitmask */
1543 #define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
1544 
1545 #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
1546 
1547 /* RDHMPN and TDHMPN bitmasks */
1548 #define IXGBE_RDHMPN_RDICADDR       0x007FF800
1549 #define IXGBE_RDHMPN_RDICRDREQ      0x00800000
1550 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1551 #define IXGBE_TDHMPN_TDICADDR       0x003FF800
1552 #define IXGBE_TDHMPN_TDICRDREQ      0x00800000
1553 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1554 
1555 #define IXGBE_RDMAM_MEM_SEL_SHIFT   13
1556 #define IXGBE_RDMAM_DWORD_SHIFT     9
1557 #define IXGBE_RDMAM_DESC_COMP_FIFO  1
1558 #define IXGBE_RDMAM_DFC_CMD_FIFO    2
1559 #define IXGBE_RDMAM_TCN_STATUS_RAM  4
1560 #define IXGBE_RDMAM_WB_COLL_FIFO    5
1561 #define IXGBE_RDMAM_QSC_CNT_RAM     6
1562 #define IXGBE_RDMAM_QSC_QUEUE_CNT   8
1563 #define IXGBE_RDMAM_QSC_QUEUE_RAM   0xA
1564 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE     135
1565 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT     4
1566 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE      48
1567 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT      7
1568 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE    256
1569 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT    9
1570 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE      8
1571 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT      4
1572 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE       64
1573 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT       4
1574 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE     32
1575 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT     4
1576 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE     128
1577 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT     8
1578 
1579 #define IXGBE_TXDESCIC_READY        0x80000000
1580 
1581 /* Receive Checksum Control */
1582 #define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
1583 #define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
1584 
1585 /* FCRTL Bit Masks */
1586 #define IXGBE_FCRTL_XONE        0x80000000  /* XON enable */
1587 #define IXGBE_FCRTH_FCEN        0x80000000  /* Packet buffer fc enable */
1588 
1589 /* PAP bit masks*/
1590 #define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
1591 
1592 /* RMCS Bit Masks */
1593 #define IXGBE_RMCS_RRM          0x00000002 /* Receive Recycle Mode enable */
1594 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1595 #define IXGBE_RMCS_RAC          0x00000004
1596 #define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1597 #define IXGBE_RMCS_TFCE_802_3X         0x00000008 /* Tx Priority FC ena */
1598 #define IXGBE_RMCS_TFCE_PRIORITY       0x00000010 /* Tx Priority FC ena */
1599 #define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
1600 
1601 /* FCCFG Bit Masks */
1602 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1603 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1604 
1605 /* Interrupt register bitmasks */
1606 
1607 /* Extended Interrupt Cause Read */
1608 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1609 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1610 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1611 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1612 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1613 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1614 #define IXGBE_EICR_FW_EVENT	0x00200000 /* Async FW event */
1615 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1616 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1617 #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1618 #define IXGBE_EICR_GPI_SDP0_8259X	0x01000000 /* Gen Purpose INT on SDP0 */
1619 #define IXGBE_EICR_GPI_SDP1_8259X	0x02000000 /* Gen Purpose INT on SDP1 */
1620 #define IXGBE_EICR_GPI_SDP2_8259X	0x04000000 /* Gen Purpose INT on SDP2 */
1621 #define IXGBE_EICR_GPI_SDP0_X540	0x02000000
1622 #define IXGBE_EICR_GPI_SDP1_X540	0x04000000
1623 #define IXGBE_EICR_GPI_SDP2_X540	0x08000000
1624 #define IXGBE_EICR_GPI_SDP0_X550	IXGBE_EICR_GPI_SDP0_X540
1625 #define IXGBE_EICR_GPI_SDP1_X550	IXGBE_EICR_GPI_SDP1_X540
1626 #define IXGBE_EICR_GPI_SDP2_X550	IXGBE_EICR_GPI_SDP2_X540
1627 #define IXGBE_EICR_GPI_SDP0_X550EM_x	IXGBE_EICR_GPI_SDP0_X540
1628 #define IXGBE_EICR_GPI_SDP1_X550EM_x	IXGBE_EICR_GPI_SDP1_X540
1629 #define IXGBE_EICR_GPI_SDP2_X550EM_x	IXGBE_EICR_GPI_SDP2_X540
1630 #define IXGBE_EICR_GPI_SDP0_X550EM_a	IXGBE_EICR_GPI_SDP0_X540
1631 #define IXGBE_EICR_GPI_SDP1_X550EM_a	IXGBE_EICR_GPI_SDP1_X540
1632 #define IXGBE_EICR_GPI_SDP2_X550EM_a	IXGBE_EICR_GPI_SDP2_X540
1633 #define IXGBE_EICR_GPI_SDP0(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1634 #define IXGBE_EICR_GPI_SDP1(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1635 #define IXGBE_EICR_GPI_SDP2(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1636 
1637 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1638 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1639 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1640 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1641 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1642 
1643 /* Extended Interrupt Cause Set */
1644 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1645 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1646 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1647 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1648 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1649 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1650 #define IXGBE_EICS_FW_EVENT	IXGBE_EICR_FW_EVENT  /* Async FW event */
1651 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1652 #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1653 #define IXGBE_EICS_GPI_SDP0(_hw)	IXGBE_EICR_GPI_SDP0(_hw)
1654 #define IXGBE_EICS_GPI_SDP1(_hw)	IXGBE_EICR_GPI_SDP1(_hw)
1655 #define IXGBE_EICS_GPI_SDP2(_hw)	IXGBE_EICR_GPI_SDP2(_hw)
1656 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1657 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1658 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
1659 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1660 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1661 
1662 /* Extended Interrupt Mask Set */
1663 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1664 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1665 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1666 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1667 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1668 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1669 #define IXGBE_EIMS_FW_EVENT	IXGBE_EICR_FW_EVENT  /* Async FW event */
1670 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1671 #define IXGBE_EIMS_TS           IXGBE_EICR_TS        /* Thermel Sensor Event */
1672 #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1673 #define IXGBE_EIMS_GPI_SDP0(_hw)	IXGBE_EICR_GPI_SDP0(_hw)
1674 #define IXGBE_EIMS_GPI_SDP1(_hw)	IXGBE_EICR_GPI_SDP1(_hw)
1675 #define IXGBE_EIMS_GPI_SDP2(_hw)	IXGBE_EICR_GPI_SDP2(_hw)
1676 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1677 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1678 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
1679 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1680 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1681 
1682 /* Extended Interrupt Mask Clear */
1683 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1684 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1685 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1686 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1687 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1688 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1689 #define IXGBE_EIMC_FW_EVENT	IXGBE_EICR_FW_EVENT  /* Async FW event */
1690 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1691 #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1692 #define IXGBE_EIMC_GPI_SDP0(_hw)	IXGBE_EICR_GPI_SDP0(_hw)
1693 #define IXGBE_EIMC_GPI_SDP1(_hw)	IXGBE_EICR_GPI_SDP1(_hw)
1694 #define IXGBE_EIMC_GPI_SDP2(_hw)	IXGBE_EICR_GPI_SDP2(_hw)
1695 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC       /* ECC Error */
1696 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1697 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Err */
1698 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1699 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1700 
1701 #define IXGBE_EIMS_ENABLE_MASK ( \
1702 				IXGBE_EIMS_RTX_QUEUE       | \
1703 				IXGBE_EIMS_LSC             | \
1704 				IXGBE_EIMS_TCP_TIMER       | \
1705 				IXGBE_EIMS_OTHER)
1706 
1707 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1708 #define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
1709 #define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
1710 #define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
1711 #define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
1712 #define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
1713 #define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
1714 #define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
1715 #define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
1716 #define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
1717 #define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
1718 #define IXGBE_IMIR_SIZE_BP_82599  0x00001000 /* Packet size bypass */
1719 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1720 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1721 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1722 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1723 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1724 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1725 #define IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
1726 #define IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
1727 #define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
1728 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1729 #define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
1730 #define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
1731 
1732 #define IXGBE_MAX_FTQF_FILTERS          128
1733 #define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
1734 #define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
1735 #define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
1736 #define IXGBE_FTQF_PROTOCOL_SCTP        2
1737 #define IXGBE_FTQF_PRIORITY_MASK        0x00000007
1738 #define IXGBE_FTQF_PRIORITY_SHIFT       2
1739 #define IXGBE_FTQF_POOL_MASK            0x0000003F
1740 #define IXGBE_FTQF_POOL_SHIFT           8
1741 #define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
1742 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
1743 #define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
1744 #define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
1745 #define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
1746 #define IXGBE_FTQF_DEST_PORT_MASK       0x17
1747 #define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
1748 #define IXGBE_FTQF_POOL_MASK_EN         0x40000000
1749 #define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
1750 
1751 /* Interrupt clear mask */
1752 #define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
1753 
1754 /* Interrupt Vector Allocation Registers */
1755 #define IXGBE_IVAR_REG_NUM      25
1756 #define IXGBE_IVAR_REG_NUM_82599       64
1757 #define IXGBE_IVAR_TXRX_ENTRY   96
1758 #define IXGBE_IVAR_RX_ENTRY     64
1759 #define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
1760 #define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
1761 #define IXGBE_IVAR_TX_ENTRY     32
1762 
1763 #define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
1764 #define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
1765 
1766 #define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
1767 
1768 #define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
1769 
1770 /* ETYPE Queue Filter/Select Bit Masks */
1771 #define IXGBE_MAX_ETQF_FILTERS  8
1772 #define IXGBE_ETQF_FCOE         0x08000000 /* bit 27 */
1773 #define IXGBE_ETQF_BCN          0x10000000 /* bit 28 */
1774 #define IXGBE_ETQF_TX_ANTISPOOF	0x20000000 /* bit 29 */
1775 #define IXGBE_ETQF_1588         0x40000000 /* bit 30 */
1776 #define IXGBE_ETQF_FILTER_EN    0x80000000 /* bit 31 */
1777 #define IXGBE_ETQF_POOL_ENABLE   BIT(26) /* bit 26 */
1778 #define IXGBE_ETQF_POOL_SHIFT		20
1779 
1780 #define IXGBE_ETQS_RX_QUEUE     0x007F0000 /* bits 22:16 */
1781 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1782 #define IXGBE_ETQS_LLI          0x20000000 /* bit 29 */
1783 #define IXGBE_ETQS_QUEUE_EN     0x80000000 /* bit 31 */
1784 
1785 /*
1786  * ETQF filter list: one static filter per filter consumer. This is
1787  *                   to avoid filter collisions later. Add new filters
1788  *                   here!!
1789  *
1790  * Current filters:
1791  *    EAPOL 802.1x (0x888e): Filter 0
1792  *    FCoE (0x8906):         Filter 2
1793  *    1588 (0x88f7):         Filter 3
1794  *    FIP  (0x8914):         Filter 4
1795  *    LLDP (0x88CC):         Filter 5
1796  *    LACP (0x8809):         Filter 6
1797  *    FC   (0x8808):         Filter 7
1798  */
1799 #define IXGBE_ETQF_FILTER_EAPOL          0
1800 #define IXGBE_ETQF_FILTER_FCOE           2
1801 #define IXGBE_ETQF_FILTER_1588           3
1802 #define IXGBE_ETQF_FILTER_FIP            4
1803 #define IXGBE_ETQF_FILTER_LLDP		 5
1804 #define IXGBE_ETQF_FILTER_LACP		 6
1805 #define IXGBE_ETQF_FILTER_FC		 7
1806 
1807 /* VLAN Control Bit Masks */
1808 #define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
1809 #define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
1810 #define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
1811 #define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
1812 #define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
1813 
1814 /* VLAN pool filtering masks */
1815 #define IXGBE_VLVF_VIEN         0x80000000  /* filter is valid */
1816 #define IXGBE_VLVF_ENTRIES      64
1817 #define IXGBE_VLVF_VLANID_MASK  0x00000FFF
1818 
1819 /* Per VF Port VLAN insertion rules */
1820 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1821 #define IXGBE_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
1822 
1823 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
1824 
1825 /* STATUS Bit Masks */
1826 #define IXGBE_STATUS_LAN_ID         0x0000000C /* LAN ID */
1827 #define IXGBE_STATUS_LAN_ID_SHIFT   2          /* LAN ID Shift*/
1828 #define IXGBE_STATUS_GIO            0x00080000 /* GIO Primary Enable Status */
1829 
1830 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1831 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1832 
1833 /* ESDP Bit Masks */
1834 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1835 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1836 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1837 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1838 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1839 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1840 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1841 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1842 #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */
1843 #define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
1844 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1845 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 Native Function */
1846 #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
1847 
1848 /* LEDCTL Bit Masks */
1849 #define IXGBE_LED_IVRT_BASE      0x00000040
1850 #define IXGBE_LED_BLINK_BASE     0x00000080
1851 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1852 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1853 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1854 #define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1855 #define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1856 #define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1857 #define IXGBE_X557_LED_MANUAL_SET_MASK	BIT(8)
1858 #define IXGBE_X557_MAX_LED_INDEX	3
1859 #define IXGBE_X557_LED_PROVISIONING	0xC430
1860 
1861 /* LED modes */
1862 #define IXGBE_LED_LINK_UP       0x0
1863 #define IXGBE_LED_LINK_10G      0x1
1864 #define IXGBE_LED_MAC           0x2
1865 #define IXGBE_LED_FILTER        0x3
1866 #define IXGBE_LED_LINK_ACTIVE   0x4
1867 #define IXGBE_LED_LINK_1G       0x5
1868 #define IXGBE_LED_ON            0xE
1869 #define IXGBE_LED_OFF           0xF
1870 
1871 /* AUTOC Bit Masks */
1872 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1873 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
1874 #define IXGBE_AUTOC_KX_SUPP     0x40000000
1875 #define IXGBE_AUTOC_PAUSE       0x30000000
1876 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
1877 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
1878 #define IXGBE_AUTOC_RF          0x08000000
1879 #define IXGBE_AUTOC_PD_TMR      0x06000000
1880 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1881 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1882 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1883 #define IXGBE_AUTOC_FECA        0x00040000
1884 #define IXGBE_AUTOC_FECR        0x00020000
1885 #define IXGBE_AUTOC_KR_SUPP     0x00010000
1886 #define IXGBE_AUTOC_AN_RESTART  0x00001000
1887 #define IXGBE_AUTOC_FLU         0x00000001
1888 #define IXGBE_AUTOC_LMS_SHIFT   13
1889 #define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1890 #define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1891 #define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1892 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1893 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1894 #define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1895 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1896 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1897 #define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1898 #define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1899 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1900 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1901 
1902 #define IXGBE_AUTOC_1G_PMA_PMD_MASK    0x00000200
1903 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT   9
1904 #define IXGBE_AUTOC_10G_PMA_PMD_MASK   0x00000180
1905 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT  7
1906 #define IXGBE_AUTOC_10G_XAUI   (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1907 #define IXGBE_AUTOC_10G_KX4    (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1908 #define IXGBE_AUTOC_10G_CX4    (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1909 #define IXGBE_AUTOC_1G_BX      (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1910 #define IXGBE_AUTOC_1G_KX      (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1911 #define IXGBE_AUTOC_1G_SFI     (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1912 #define IXGBE_AUTOC_1G_KX_BX   (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1913 
1914 #define IXGBE_AUTOC2_UPPER_MASK  0xFFFF0000
1915 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK  0x00030000
1916 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1917 #define IXGBE_AUTOC2_10G_KR  (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1918 #define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1919 #define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1920 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK  0x50000000
1921 #define IXGBE_AUTOC2_LINK_DISABLE_MASK        0x70000000
1922 
1923 #define IXGBE_MACC_FLU       0x00000001
1924 #define IXGBE_MACC_FSV_10G   0x00030000
1925 #define IXGBE_MACC_FS        0x00040000
1926 #define IXGBE_MAC_RX2TX_LPBK 0x00000002
1927 
1928 /* Veto Bit definition */
1929 #define IXGBE_MMNGC_MNG_VETO  0x00000001
1930 
1931 /* LINKS Bit Masks */
1932 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
1933 #define IXGBE_LINKS_UP          0x40000000
1934 #define IXGBE_LINKS_SPEED       0x20000000
1935 #define IXGBE_LINKS_MODE        0x18000000
1936 #define IXGBE_LINKS_RX_MODE     0x06000000
1937 #define IXGBE_LINKS_TX_MODE     0x01800000
1938 #define IXGBE_LINKS_XGXS_EN     0x00400000
1939 #define IXGBE_LINKS_SGMII_EN    0x02000000
1940 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
1941 #define IXGBE_LINKS_1G_AN_EN    0x00100000
1942 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
1943 #define IXGBE_LINKS_1G_SYNC     0x00040000
1944 #define IXGBE_LINKS_10G_ALIGN   0x00020000
1945 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1946 #define IXGBE_LINKS_TL_FAULT    0x00001000
1947 #define IXGBE_LINKS_SIGNAL      0x00000F00
1948 
1949 #define IXGBE_LINKS_SPEED_NON_STD   0x08000000
1950 #define IXGBE_LINKS_SPEED_82599     0x30000000
1951 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1952 #define IXGBE_LINKS_SPEED_1G_82599  0x20000000
1953 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1954 #define IXGBE_LINKS_SPEED_10_X550EM_A 0
1955 #define IXGBE_LINK_UP_TIME      90 /* 9.0 Seconds */
1956 #define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
1957 
1958 #define IXGBE_LINKS2_AN_SUPPORTED   0x00000040
1959 
1960 /* PCS1GLSTA Bit Masks */
1961 #define IXGBE_PCS1GLSTA_LINK_OK         1
1962 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
1963 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
1964 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
1965 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
1966 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1967 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
1968 
1969 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
1970 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100
1971 
1972 /* PCS1GLCTL Bit Masks */
1973 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN  0x00040000 /* PCS 1G autoneg to en */
1974 #define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
1975 #define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
1976 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
1977 #define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
1978 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
1979 
1980 /* ANLP1 Bit Masks */
1981 #define IXGBE_ANLP1_PAUSE               0x0C00
1982 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
1983 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
1984 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
1985 
1986 /* SW Semaphore Register bitmasks */
1987 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1988 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1989 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1990 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1991 
1992 /* SW_FW_SYNC/GSSR definitions */
1993 #define IXGBE_GSSR_EEP_SM		0x0001
1994 #define IXGBE_GSSR_PHY0_SM		0x0002
1995 #define IXGBE_GSSR_PHY1_SM		0x0004
1996 #define IXGBE_GSSR_MAC_CSR_SM		0x0008
1997 #define IXGBE_GSSR_FLASH_SM		0x0010
1998 #define IXGBE_GSSR_NVM_UPDATE_SM	0x0200
1999 #define IXGBE_GSSR_SW_MNG_SM		0x0400
2000 #define IXGBE_GSSR_TOKEN_SM	0x40000000 /* SW bit for shared access */
2001 #define IXGBE_GSSR_SHARED_I2C_SM	0x1806 /* Wait for both phys & I2Cs */
2002 #define IXGBE_GSSR_I2C_MASK		0x1800
2003 #define IXGBE_GSSR_NVM_PHY_MASK		0xF
2004 
2005 /* FW Status register bitmask */
2006 #define IXGBE_FWSTS_FWRI    0x00000200 /* Firmware Reset Indication */
2007 
2008 /* EEC Register */
2009 #define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
2010 #define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
2011 #define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
2012 #define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
2013 #define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
2014 #define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
2015 #define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
2016 #define IXGBE_EEC_FWE_SHIFT 4
2017 #define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
2018 #define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
2019 #define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
2020 #define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
2021 #define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
2022 #define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
2023 #define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
2024 /* EEPROM Addressing bits based on type (0-small, 1-large) */
2025 #define IXGBE_EEC_ADDR_SIZE 0x00000400
2026 #define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
2027 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD allows 14 bits for addr. */
2028 
2029 #define IXGBE_EEC_SIZE_SHIFT          11
2030 #define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
2031 #define IXGBE_EEPROM_OPCODE_BITS      8
2032 
2033 /* Part Number String Length */
2034 #define IXGBE_PBANUM_LENGTH 11
2035 
2036 /* Checksum and EEPROM pointers */
2037 #define IXGBE_PBANUM_PTR_GUARD		0xFAFA
2038 #define IXGBE_EEPROM_CHECKSUM		0x3F
2039 #define IXGBE_EEPROM_SUM		0xBABA
2040 #define IXGBE_EEPROM_CTRL_4		0x45
2041 #define IXGBE_EE_CTRL_4_INST_ID		0x10
2042 #define IXGBE_EE_CTRL_4_INST_ID_SHIFT	4
2043 #define IXGBE_PCIE_ANALOG_PTR		0x03
2044 #define IXGBE_ATLAS0_CONFIG_PTR		0x04
2045 #define IXGBE_PHY_PTR			0x04
2046 #define IXGBE_ATLAS1_CONFIG_PTR		0x05
2047 #define IXGBE_OPTION_ROM_PTR		0x05
2048 #define IXGBE_PCIE_GENERAL_PTR		0x06
2049 #define IXGBE_PCIE_CONFIG0_PTR		0x07
2050 #define IXGBE_PCIE_CONFIG1_PTR		0x08
2051 #define IXGBE_CORE0_PTR			0x09
2052 #define IXGBE_CORE1_PTR			0x0A
2053 #define IXGBE_MAC0_PTR			0x0B
2054 #define IXGBE_MAC1_PTR			0x0C
2055 #define IXGBE_CSR0_CONFIG_PTR		0x0D
2056 #define IXGBE_CSR1_CONFIG_PTR		0x0E
2057 #define IXGBE_PCIE_ANALOG_PTR_X550	0x02
2058 #define IXGBE_SHADOW_RAM_SIZE_X550	0x4000
2059 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE	0x24
2060 #define IXGBE_PCIE_CONFIG_SIZE		0x08
2061 #define IXGBE_EEPROM_LAST_WORD		0x41
2062 #define IXGBE_FW_PTR			0x0F
2063 #define IXGBE_PBANUM0_PTR		0x15
2064 #define IXGBE_PBANUM1_PTR		0x16
2065 #define IXGBE_FREE_SPACE_PTR		0X3E
2066 
2067 /* External Thermal Sensor Config */
2068 #define IXGBE_ETS_CFG                   0x26
2069 #define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
2070 #define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
2071 #define IXGBE_ETS_TYPE_MASK             0x0038
2072 #define IXGBE_ETS_TYPE_SHIFT            3
2073 #define IXGBE_ETS_TYPE_EMC              0x000
2074 #define IXGBE_ETS_TYPE_EMC_SHIFTED      0x000
2075 #define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
2076 #define IXGBE_ETS_DATA_LOC_MASK         0x3C00
2077 #define IXGBE_ETS_DATA_LOC_SHIFT        10
2078 #define IXGBE_ETS_DATA_INDEX_MASK       0x0300
2079 #define IXGBE_ETS_DATA_INDEX_SHIFT      8
2080 #define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
2081 
2082 #define IXGBE_SAN_MAC_ADDR_PTR  0x28
2083 #define IXGBE_DEVICE_CAPS       0x2C
2084 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
2085 #define IXGBE_PCIE_MSIX_E610_CAPS	0xB2
2086 #define IXGBE_PCIE_MSIX_82599_CAPS  0x72
2087 #define IXGBE_MAX_MSIX_VECTORS_82599	0x40
2088 #define IXGBE_PCIE_MSIX_82598_CAPS  0x62
2089 #define IXGBE_MAX_MSIX_VECTORS_82598	0x13
2090 
2091 /* MSI-X capability fields masks */
2092 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
2093 
2094 /* Legacy EEPROM word offsets */
2095 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
2096 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030
2097 #define IXGBE_ISCSI_SETUP_PORT_1        0x0034
2098 
2099 /* EEPROM Commands - SPI */
2100 #define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
2101 #define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
2102 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
2103 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
2104 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
2105 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
2106 /* EEPROM reset Write Enable latch */
2107 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
2108 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
2109 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
2110 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
2111 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
2112 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
2113 
2114 /* EEPROM Read Register */
2115 #define IXGBE_EEPROM_RW_REG_DATA   16 /* data offset in EEPROM read reg */
2116 #define IXGBE_EEPROM_RW_REG_DONE   2  /* Offset to READ done bit */
2117 #define IXGBE_EEPROM_RW_REG_START  1  /* First bit to start operation */
2118 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2  /* Shift to the address bits */
2119 #define IXGBE_NVM_POLL_WRITE       1  /* Flag for polling for write complete */
2120 #define IXGBE_NVM_POLL_READ        0  /* Flag for polling for read complete */
2121 
2122 #define NVM_INIT_CTRL_3			0x38
2123 #define NVM_INIT_CTRL_3_LPLU		0x8
2124 #define NVM_INIT_CTRL_3_D10GMP_PORT0	0x40
2125 #define NVM_INIT_CTRL_3_D10GMP_PORT1	0x100
2126 
2127 #define IXGBE_EEPROM_PAGE_SIZE_MAX       128
2128 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
2129 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
2130 
2131 #define IXGBE_EEPROM_CTRL_2	1 /* EEPROM CTRL word 2 */
2132 #define IXGBE_EEPROM_CCD_BIT	2 /* EEPROM Core Clock Disable bit */
2133 
2134 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2135 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
2136 #endif
2137 
2138 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
2139 /* Number of 5 microseconds we wait for EERD read and
2140  * EERW write to complete */
2141 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
2142 #endif
2143 
2144 #ifndef IXGBE_FLUDONE_ATTEMPTS
2145 /* # attempts we wait for flush update to complete */
2146 #define IXGBE_FLUDONE_ATTEMPTS 20000
2147 #endif
2148 
2149 #define IXGBE_PCIE_CTRL2                 0x5   /* PCIe Control 2 Offset */
2150 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE    0x8   /* Dummy Function Enable */
2151 #define IXGBE_PCIE_CTRL2_LAN_DISABLE     0x2   /* LAN PCI Disable */
2152 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT  0x1   /* LAN Disable Select */
2153 
2154 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET  0x0
2155 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET  0x3
2156 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP  0x1
2157 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS  0x2
2158 #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR	BIT(7)
2159 #define IXGBE_FW_LESM_PARAMETERS_PTR     0x2
2160 #define IXGBE_FW_LESM_STATE_1            0x1
2161 #define IXGBE_FW_LESM_STATE_ENABLED      0x8000 /* LESM Enable bit */
2162 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
2163 #define IXGBE_FW_PATCH_VERSION_4         0x7
2164 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR         0x33 /* iSCSI/FCOE block */
2165 #define IXGBE_FCOE_IBA_CAPS_FCOE            0x20 /* FCOE flags */
2166 #define IXGBE_ISCSI_FCOE_BLK_PTR            0x17 /* iSCSI/FCOE block */
2167 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET       0x0  /* FCOE flags */
2168 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE       0x1  /* FCOE flags enable bit */
2169 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR      0x27 /* Alt. SAN MAC block */
2170 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0 /* Alt. SAN MAC capability */
2171 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
2172 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
2173 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7 /* Alt. WWNN prefix offset */
2174 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8 /* Alt. WWPN prefix offset */
2175 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0 /* Alt. SAN MAC exists */
2176 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
2177 
2178 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1  0x4 /* WoL supported on ports 0 & 1 */
2179 #define IXGBE_DEVICE_CAPS_WOL_PORT0    0x8 /* WoL supported on port 0 */
2180 #define IXGBE_DEVICE_CAPS_WOL_MASK     0xC /* Mask for WoL capabilities */
2181 
2182 /* PCI Bus Info */
2183 #define IXGBE_PCI_DEVICE_STATUS   0xAA
2184 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
2185 #define IXGBE_PCI_LINK_STATUS     0xB2
2186 #define IXGBE_PCI_LINK_STATUS_E610	0x82
2187 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2188 #define IXGBE_PCI_LINK_WIDTH      0x3F0
2189 #define IXGBE_PCI_LINK_WIDTH_1    0x10
2190 #define IXGBE_PCI_LINK_WIDTH_2    0x20
2191 #define IXGBE_PCI_LINK_WIDTH_4    0x40
2192 #define IXGBE_PCI_LINK_WIDTH_8    0x80
2193 #define IXGBE_PCI_LINK_SPEED      0xF
2194 #define IXGBE_PCI_LINK_SPEED_2500 0x1
2195 #define IXGBE_PCI_LINK_SPEED_5000 0x2
2196 #define IXGBE_PCI_LINK_SPEED_8000 0x3
2197 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
2198 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
2199 
2200 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK	0xf
2201 #define IXGBE_PCIDEVCTRL2_16_32ms_def	0x0
2202 #define IXGBE_PCIDEVCTRL2_50_100us	0x1
2203 #define IXGBE_PCIDEVCTRL2_1_2ms		0x2
2204 #define IXGBE_PCIDEVCTRL2_16_32ms	0x5
2205 #define IXGBE_PCIDEVCTRL2_65_130ms	0x6
2206 #define IXGBE_PCIDEVCTRL2_260_520ms	0x9
2207 #define IXGBE_PCIDEVCTRL2_1_2s		0xa
2208 #define IXGBE_PCIDEVCTRL2_4_8s		0xd
2209 #define IXGBE_PCIDEVCTRL2_17_34s	0xe
2210 
2211 /* Number of 100 microseconds we wait for PCI Express primary disable */
2212 #define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT	800
2213 
2214 /* RAH */
2215 #define IXGBE_RAH_VIND_MASK     0x003C0000
2216 #define IXGBE_RAH_VIND_SHIFT    18
2217 #define IXGBE_RAH_AV            0x80000000
2218 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
2219 
2220 /* Header split receive */
2221 #define IXGBE_RFCTL_ISCSI_DIS       0x00000001
2222 #define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
2223 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2224 #define IXGBE_RFCTL_RSC_DIS		0x00000020
2225 #define IXGBE_RFCTL_NFSW_DIS        0x00000040
2226 #define IXGBE_RFCTL_NFSR_DIS        0x00000080
2227 #define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
2228 #define IXGBE_RFCTL_NFS_VER_SHIFT   8
2229 #define IXGBE_RFCTL_NFS_VER_2       0
2230 #define IXGBE_RFCTL_NFS_VER_3       1
2231 #define IXGBE_RFCTL_NFS_VER_4       2
2232 #define IXGBE_RFCTL_IPV6_DIS        0x00000400
2233 #define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
2234 #define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
2235 #define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
2236 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2237 
2238 /* Transmit Config masks */
2239 #define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
2240 #define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
2241 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
2242 /* Enable short packet padding to 64 bytes */
2243 #define IXGBE_TX_PAD_ENABLE     0x00000400
2244 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
2245 /* This allows for 16K packets + 4k for vlan */
2246 #define IXGBE_MAX_FRAME_SZ      0x40040000
2247 
2248 #define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
2249 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq# write-back enable */
2250 
2251 /* Receive Config masks */
2252 #define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
2253 #define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
2254 #define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
2255 #define IXGBE_RXDCTL_SWFLSH     0x04000000  /* Rx Desc. write-back flushing */
2256 #define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
2257 #define IXGBE_RXDCTL_RLPML_EN   0x00008000
2258 #define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
2259 
2260 #define IXGBE_TSAUXC_EN_CLK		0x00000004
2261 #define IXGBE_TSAUXC_SYNCLK		0x00000008
2262 #define IXGBE_TSAUXC_SDP0_INT		0x00000040
2263 #define IXGBE_TSAUXC_EN_TT0		0x00000001
2264 #define IXGBE_TSAUXC_EN_TT1		0x00000002
2265 #define IXGBE_TSAUXC_ST0		0x00000010
2266 #define IXGBE_TSAUXC_DISABLE_SYSTIME	0x80000000
2267 
2268 #define IXGBE_TSSDP_TS_SDP0_SEL_MASK	0x000000C0
2269 #define IXGBE_TSSDP_TS_SDP0_CLK0	0x00000080
2270 #define IXGBE_TSSDP_TS_SDP0_EN		0x00000100
2271 
2272 #define IXGBE_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
2273 #define IXGBE_TSYNCTXCTL_ENABLED	0x00000010 /* Tx timestamping enabled */
2274 
2275 #define IXGBE_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
2276 #define IXGBE_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
2277 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2	0x00
2278 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1	0x02
2279 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
2280 #define IXGBE_TSYNCRXCTL_TYPE_ALL	0x08
2281 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
2282 #define IXGBE_TSYNCRXCTL_ENABLED	0x00000010 /* Rx Timestamping enabled */
2283 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN	0x00800000 /* Rx Timestamp in Packet */
2284 
2285 #define IXGBE_TSIM_TXTS			0x00000002
2286 
2287 #define IXGBE_RXMTRL_V1_CTRLT_MASK	0x000000FF
2288 #define IXGBE_RXMTRL_V1_SYNC_MSG	0x00
2289 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG	0x01
2290 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG	0x02
2291 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG	0x03
2292 #define IXGBE_RXMTRL_V1_MGMT_MSG	0x04
2293 
2294 #define IXGBE_RXMTRL_V2_MSGID_MASK		0x0000FF00
2295 #define IXGBE_RXMTRL_V2_SYNC_MSG		0x0000
2296 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG		0x0100
2297 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG		0x0200
2298 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG		0x0300
2299 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG		0x0800
2300 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG		0x0900
2301 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG	0x0A00
2302 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG		0x0B00
2303 #define IXGBE_RXMTRL_V2_SIGNALING_MSG		0x0C00
2304 #define IXGBE_RXMTRL_V2_MGMT_MSG		0x0D00
2305 
2306 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
2307 #define IXGBE_FCTRL_TPE 0x00000080 /* Tag Promiscuous Ena*/
2308 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
2309 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
2310 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
2311 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
2312 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
2313 /* Receive Priority Flow Control Enable */
2314 #define IXGBE_FCTRL_RPFCE 0x00004000
2315 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
2316 #define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
2317 #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
2318 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
2319 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
2320 #define IXGBE_MFLCN_RPFCE_MASK	0x00000FF4 /* Receive FC Mask */
2321 
2322 #define IXGBE_MFLCN_RPFCE_SHIFT		 4
2323 
2324 /* Multiple Receive Queue Control */
2325 #define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
2326 #define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */
2327 #define IXGBE_MRQC_RT8TCEN               0x00000002 /* 8 TC no RSS */
2328 #define IXGBE_MRQC_RT4TCEN               0x00000003 /* 4 TC no RSS */
2329 #define IXGBE_MRQC_RTRSS8TCEN            0x00000004 /* 8 TC w/ RSS */
2330 #define IXGBE_MRQC_RTRSS4TCEN            0x00000005 /* 4 TC w/ RSS */
2331 #define IXGBE_MRQC_VMDQEN                0x00000008 /* VMDq2 64 pools no RSS */
2332 #define IXGBE_MRQC_VMDQRSS32EN           0x0000000A /* VMDq2 32 pools w/ RSS */
2333 #define IXGBE_MRQC_VMDQRSS64EN           0x0000000B /* VMDq2 64 pools w/ RSS */
2334 #define IXGBE_MRQC_VMDQRT8TCEN           0x0000000C /* VMDq2/RT 16 pool 8 TC */
2335 #define IXGBE_MRQC_VMDQRT4TCEN           0x0000000D /* VMDq2/RT 32 pool 4 TC */
2336 #define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
2337 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
2338 #define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
2339 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2340 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
2341 #define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
2342 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
2343 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
2344 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
2345 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2346 #define IXGBE_MRQC_MULTIPLE_RSS          0x00002000
2347 #define IXGBE_MRQC_L3L4TXSWEN            0x00008000
2348 
2349 #define IXGBE_FWSM_TS_ENABLED	0x1
2350 
2351 /* Queue Drop Enable */
2352 #define IXGBE_QDE_ENABLE	0x00000001
2353 #define IXGBE_QDE_HIDE_VLAN	0x00000002
2354 #define IXGBE_QDE_IDX_MASK	0x00007F00
2355 #define IXGBE_QDE_IDX_SHIFT	8
2356 #define IXGBE_QDE_WRITE		0x00010000
2357 
2358 #define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
2359 #define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
2360 #define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
2361 #define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
2362 #define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
2363 #define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
2364 #define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
2365 #define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
2366 #define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
2367 
2368 /* Multiple Transmit Queue Command Register */
2369 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2370 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2371 #define IXGBE_MTQC_NUM_TC_OR_Q  0xC /* Number of TCs or TxQs per pool */
2372 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2373 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2374 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2375 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2376 #define IXGBE_MTQC_4TC_4TQ	0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
2377 
2378 /* Receive Descriptor bit definitions */
2379 #define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
2380 #define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
2381 #define IXGBE_RXD_STAT_FLM      0x04    /* FDir Match */
2382 #define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
2383 #define IXGBE_RXDADV_NEXTP_MASK   0x000FFFF0 /* Next Descriptor Index */
2384 #define IXGBE_RXDADV_NEXTP_SHIFT  0x00000004
2385 #define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
2386 #define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
2387 #define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
2388 #define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
2389 #define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
2390 #define IXGBE_RXD_STAT_OUTERIPCS  0x100 /* Cloud IP xsum calculated */
2391 #define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
2392 #define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
2393 #define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
2394 #define IXGBE_RXD_STAT_LLINT    0x800   /* Pkt caused Low Latency Interrupt */
2395 #define IXGBE_RXD_STAT_TSIP     0x08000 /* Time Stamp in packet buffer */
2396 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2397 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2398 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2399 #define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
2400 #define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
2401 #define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
2402 #define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
2403 #define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
2404 #define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
2405 #define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
2406 #define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
2407 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2408 #define IXGBE_RXDADV_ERR_SHIFT          20         /* RDESC.ERRORS shift */
2409 #define IXGBE_RXDADV_ERR_OUTERIPER	0x04000000 /* CRC IP Header error */
2410 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
2411 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2412 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2413 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2414 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2415 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2416 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2417 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2418 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2419 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2420 #define IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL  0x08000000 /* overlap ERR_PE  */
2421 #define IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH    0x10000000 /* overlap ERR_OSE */
2422 #define IXGBE_RXDADV_ERR_IPSEC_AUTH_FAILED   0x18000000
2423 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2424 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2425 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2426 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2427 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2428 #define IXGBE_RXD_PRI_SHIFT     13
2429 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2430 #define IXGBE_RXD_CFI_SHIFT     12
2431 
2432 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2433 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2434 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2435 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2436 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2437 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2438 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2439 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2440 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2441 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2442 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2443 #define IXGBE_RXDADV_STAT_TS		0x00010000 /* IEEE 1588 Time Stamp */
2444 #define IXGBE_RXDADV_STAT_SECP		0x00020000 /* IPsec/MACsec pkt found */
2445 
2446 /* PSRTYPE bit definitions */
2447 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2448 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2449 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2450 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2451 #define IXGBE_PSRTYPE_L2HDR     0x00001000
2452 
2453 /* SRRCTL bit definitions */
2454 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10     /* so many KBs */
2455 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2456 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2457 #define IXGBE_SRRCTL_DROP_EN            0x10000000
2458 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2459 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2460 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2461 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2462 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
2463 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2464 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2465 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2466 
2467 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2468 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2469 
2470 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2471 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2472 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2473 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2474 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
2475 #define IXGBE_RXDADV_RSCCNT_SHIFT       17
2476 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
2477 #define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
2478 #define IXGBE_RXDADV_SPH                0x8000
2479 
2480 /* RSS Hash results */
2481 #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
2482 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2483 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2484 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2485 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2486 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2487 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2488 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2489 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2490 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2491 
2492 /* RSS Packet Types as indicated in the receive descriptor. */
2493 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2494 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2495 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2496 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2497 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2498 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2499 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2500 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2501 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2502 #define IXGBE_RXDADV_PKTTYPE_VXLAN	0x00000800 /* VXLAN hdr present */
2503 #define IXGBE_RXDADV_PKTTYPE_TUNNEL	0x00010000 /* Tunnel type */
2504 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2505 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2506 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2507 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2508 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2509 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4          /* Right-shift 4 bits */
2510 
2511 /* Masks to determine if packets should be dropped due to frame errors */
2512 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2513 				      IXGBE_RXD_ERR_CE | \
2514 				      IXGBE_RXD_ERR_LE | \
2515 				      IXGBE_RXD_ERR_PE | \
2516 				      IXGBE_RXD_ERR_OSE | \
2517 				      IXGBE_RXD_ERR_USE)
2518 
2519 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2520 				      IXGBE_RXDADV_ERR_CE | \
2521 				      IXGBE_RXDADV_ERR_LE | \
2522 				      IXGBE_RXDADV_ERR_PE | \
2523 				      IXGBE_RXDADV_ERR_OSE | \
2524 				      IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL | \
2525 				      IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH | \
2526 				      IXGBE_RXDADV_ERR_USE)
2527 
2528 /* Multicast bit mask */
2529 #define IXGBE_MCSTCTRL_MFE      0x4
2530 
2531 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2532 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
2533 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
2534 #define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
2535 
2536 /* Vlan-specific macros */
2537 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
2538 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
2539 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
2540 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2541 
2542 /* SR-IOV specific macros */
2543 #define IXGBE_MBVFICR_INDEX(vf_number)   (vf_number >> 4)
2544 #define IXGBE_MBVFICR(_i)		(0x00710 + ((_i) * 4))
2545 #define IXGBE_VFLRE(_i)		((((_i) & 1) ? 0x001C0 : 0x00600))
2546 #define IXGBE_VFLREC(_i)		(0x00700 + ((_i) * 4))
2547 /* Translated register #defines */
2548 #define IXGBE_PVFTDH(P)		(0x06010 + (0x40 * (P)))
2549 #define IXGBE_PVFTDT(P)		(0x06018 + (0x40 * (P)))
2550 #define IXGBE_PVFTXDCTL(P)	(0x06028 + (0x40 * (P)))
2551 #define IXGBE_PVFTDWBAL(P)	(0x06038 + (0x40 * (P)))
2552 #define IXGBE_PVFTDWBAH(P)	(0x0603C + (0x40 * (P)))
2553 #define IXGBE_PVFGPRC(x)	(0x0101C + (0x40 * (x)))
2554 #define IXGBE_PVFGPTC(x)	(0x08300 + (0x04 * (x)))
2555 #define IXGBE_PVFGORC_LSB(x)	(0x01020 + (0x40 * (x)))
2556 #define IXGBE_PVFGORC_MSB(x)	(0x0D020 + (0x40 * (x)))
2557 #define IXGBE_PVFGOTC_LSB(x)	(0x08400 + (0x08 * (x)))
2558 #define IXGBE_PVFGOTC_MSB(x)	(0x08404 + (0x08 * (x)))
2559 #define IXGBE_PVFMPRC(x)	(0x0D01C + (0x40 * (x)))
2560 
2561 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2562 		(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2563 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2564 		(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2565 
2566 #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
2567 		(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2568 #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
2569 		(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2570 
2571 enum ixgbe_fdir_pballoc_type {
2572 	IXGBE_FDIR_PBALLOC_NONE = 0,
2573 	IXGBE_FDIR_PBALLOC_64K  = 1,
2574 	IXGBE_FDIR_PBALLOC_128K = 2,
2575 	IXGBE_FDIR_PBALLOC_256K = 3,
2576 };
2577 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT           16
2578 
2579 /* Flow Director register values */
2580 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2581 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2582 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2583 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2584 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2585 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2586 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2587 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2588 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2589 #define IXGBE_FDIRCTRL_DROP_NO_MATCH		0x00008000
2590 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT		21
2591 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN	0x0001 /* bit 23:21, 001b */
2592 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD		0x0002 /* bit 23:21, 010b */
2593 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2594 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2595 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2596 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2597 
2598 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2599 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2600 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2601 #define IXGBE_FDIRM_VLANID                      0x00000001
2602 #define IXGBE_FDIRM_VLANP                       0x00000002
2603 #define IXGBE_FDIRM_POOL                        0x00000004
2604 #define IXGBE_FDIRM_L4P                         0x00000008
2605 #define IXGBE_FDIRM_FLEX                        0x00000010
2606 #define IXGBE_FDIRM_DIPv6                       0x00000020
2607 
2608 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2609 #define IXGBE_FDIRFREE_FREE_SHIFT               0
2610 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2611 #define IXGBE_FDIRFREE_COLL_SHIFT               16
2612 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2613 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2614 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2615 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2616 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2617 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2618 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2619 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2620 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2621 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2622 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2623 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2624 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2625 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2626 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2627 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2628 
2629 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2630 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2631 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2632 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2633 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2634 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2635 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2636 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2637 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2638 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2639 #define IXGBE_FDIRCMD_IPV6                      0x00000080
2640 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2641 #define IXGBE_FDIRCMD_DROP                      0x00000200
2642 #define IXGBE_FDIRCMD_INT                       0x00000400
2643 #define IXGBE_FDIRCMD_LAST                      0x00000800
2644 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
2645 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2646 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2647 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
2648 #define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT	23
2649 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2650 #define IXGBE_FDIR_INIT_DONE_POLL               10
2651 #define IXGBE_FDIRCMD_CMD_POLL                  10
2652 #define IXGBE_FDIRCMD_TUNNEL_FILTER		0x00800000
2653 
2654 #define IXGBE_FDIR_DROP_QUEUE                   127
2655 
2656 /* Manageablility Host Interface defines */
2657 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH	1792 /* Num of bytes in range */
2658 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH	448 /* Num of dwords in range */
2659 #define IXGBE_HI_COMMAND_TIMEOUT	500 /* Process HI command limit */
2660 #define IXGBE_HI_FLASH_ERASE_TIMEOUT	1000 /* Process Erase command limit */
2661 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT	5000 /* Process Update command limit */
2662 #define IXGBE_HI_FLASH_APPLY_TIMEOUT	0 /* Process Apply command limit */
2663 
2664 /* CEM Support */
2665 #define FW_CEM_HDR_LEN			0x4
2666 #define FW_CEM_CMD_DRIVER_INFO		0xDD
2667 #define FW_CEM_CMD_DRIVER_INFO_LEN	0x5
2668 #define FW_CEM_CMD_RESERVED		0x0
2669 #define FW_CEM_UNUSED_VER		0x0
2670 #define FW_CEM_MAX_RETRIES		3
2671 #define FW_CEM_RESP_STATUS_SUCCESS	0x1
2672 #define FW_CEM_DRIVER_VERSION_SIZE	39 /* +9 would send 48 bytes to fw */
2673 #define FW_READ_SHADOW_RAM_CMD		0x31
2674 #define FW_READ_SHADOW_RAM_LEN		0x6
2675 #define FW_WRITE_SHADOW_RAM_CMD		0x33
2676 #define FW_WRITE_SHADOW_RAM_LEN		0xA /* 8 plus 1 WORD to write */
2677 #define FW_SHADOW_RAM_DUMP_CMD		0x36
2678 #define FW_SHADOW_RAM_DUMP_LEN		0
2679 #define FW_DEFAULT_CHECKSUM		0xFF /* checksum always 0xFF */
2680 #define FW_NVM_DATA_OFFSET		3
2681 #define FW_MAX_READ_BUFFER_SIZE		1024
2682 #define FW_DISABLE_RXEN_CMD		0xDE
2683 #define FW_DISABLE_RXEN_LEN		0x1
2684 #define FW_PHY_MGMT_REQ_CMD		0x20
2685 #define FW_PHY_TOKEN_REQ_CMD		0x0A
2686 #define FW_PHY_TOKEN_REQ_LEN		2
2687 #define FW_PHY_TOKEN_REQ		0
2688 #define FW_PHY_TOKEN_REL		1
2689 #define FW_PHY_TOKEN_OK			1
2690 #define FW_PHY_TOKEN_RETRY		0x80
2691 #define FW_PHY_TOKEN_DELAY		5	/* milliseconds */
2692 #define FW_PHY_TOKEN_WAIT		5	/* seconds */
2693 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
2694 #define FW_INT_PHY_REQ_CMD		0xB
2695 #define FW_INT_PHY_REQ_LEN		10
2696 #define FW_INT_PHY_REQ_READ		0
2697 #define FW_INT_PHY_REQ_WRITE		1
2698 #define FW_PHY_ACT_REQ_CMD		5
2699 #define FW_PHY_ACT_DATA_COUNT		4
2700 #define FW_PHY_ACT_REQ_LEN		(4 + 4 * FW_PHY_ACT_DATA_COUNT)
2701 #define FW_PHY_ACT_INIT_PHY		1
2702 #define FW_PHY_ACT_SETUP_LINK		2
2703 #define FW_PHY_ACT_LINK_SPEED_10	BIT(0)
2704 #define FW_PHY_ACT_LINK_SPEED_100	BIT(1)
2705 #define FW_PHY_ACT_LINK_SPEED_1G	BIT(2)
2706 #define FW_PHY_ACT_LINK_SPEED_2_5G	BIT(3)
2707 #define FW_PHY_ACT_LINK_SPEED_5G	BIT(4)
2708 #define FW_PHY_ACT_LINK_SPEED_10G	BIT(5)
2709 #define FW_PHY_ACT_LINK_SPEED_20G	BIT(6)
2710 #define FW_PHY_ACT_LINK_SPEED_25G	BIT(7)
2711 #define FW_PHY_ACT_LINK_SPEED_40G	BIT(8)
2712 #define FW_PHY_ACT_LINK_SPEED_50G	BIT(9)
2713 #define FW_PHY_ACT_LINK_SPEED_100G	BIT(10)
2714 #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
2715 #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3 << \
2716 					  HW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
2717 #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
2718 #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX	1u
2719 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX	2u
2720 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
2721 #define FW_PHY_ACT_SETUP_LINK_LP	BIT(18)
2722 #define FW_PHY_ACT_SETUP_LINK_HP	BIT(19)
2723 #define FW_PHY_ACT_SETUP_LINK_EEE	BIT(20)
2724 #define FW_PHY_ACT_SETUP_LINK_AN	BIT(22)
2725 #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN	BIT(0)
2726 #define FW_PHY_ACT_GET_LINK_INFO	3
2727 #define FW_PHY_ACT_GET_LINK_INFO_EEE	BIT(19)
2728 #define FW_PHY_ACT_GET_LINK_INFO_FC_TX	BIT(20)
2729 #define FW_PHY_ACT_GET_LINK_INFO_FC_RX	BIT(21)
2730 #define FW_PHY_ACT_GET_LINK_INFO_POWER	BIT(22)
2731 #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE	BIT(24)
2732 #define FW_PHY_ACT_GET_LINK_INFO_TEMP	BIT(25)
2733 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX	BIT(28)
2734 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX	BIT(29)
2735 #define FW_PHY_ACT_FORCE_LINK_DOWN	4
2736 #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF	BIT(0)
2737 #define FW_PHY_ACT_PHY_SW_RESET		5
2738 #define FW_PHY_ACT_PHY_HW_RESET		6
2739 #define FW_PHY_ACT_GET_PHY_INFO		7
2740 #define FW_PHY_ACT_UD_2			0x1002
2741 #define FW_PHY_ACT_UD_2_10G_KR_EEE	BIT(6)
2742 #define FW_PHY_ACT_UD_2_10G_KX4_EEE	BIT(5)
2743 #define FW_PHY_ACT_UD_2_1G_KX_EEE	BIT(4)
2744 #define FW_PHY_ACT_UD_2_10G_T_EEE	BIT(3)
2745 #define FW_PHY_ACT_UD_2_1G_T_EEE	BIT(2)
2746 #define FW_PHY_ACT_UD_2_100M_TX_EEE	BIT(1)
2747 #define FW_PHY_ACT_RETRIES		50
2748 #define FW_PHY_INFO_SPEED_MASK		0xFFFu
2749 #define FW_PHY_INFO_ID_HI_MASK		0xFFFF0000u
2750 #define FW_PHY_INFO_ID_LO_MASK		0x0000FFFFu
2751 
2752 /* There are only 3 options for VFs creation on this device:
2753  * 16 VFs pool with 8 queues each
2754  * 32 VFs pool with 4 queues each
2755  * 64 VFs pool with 2 queues each
2756  *
2757  * That means reading some VF registers that map VF to queue depending on
2758  * chosen option. Define values that help dealing with each scenario.
2759  */
2760 /* Number of queues based on VFs pool */
2761 #define IXGBE_16VFS_QUEUES		8
2762 #define IXGBE_32VFS_QUEUES		4
2763 #define IXGBE_64VFS_QUEUES		2
2764 /* Mask for getting queues bits based on VFs pool */
2765 #define IXGBE_16VFS_BITMASK		GENMASK(IXGBE_16VFS_QUEUES - 1, 0)
2766 #define IXGBE_32VFS_BITMASK		GENMASK(IXGBE_32VFS_QUEUES - 1, 0)
2767 #define IXGBE_64VFS_BITMASK		GENMASK(IXGBE_64VFS_QUEUES - 1, 0)
2768 /* Convert queue index to register number.
2769  * We have 4 registers with 32 queues in each.
2770  */
2771 #define IXGBE_QUEUES_PER_REG		32
2772 #define IXGBE_QUEUES_REG_AMOUNT		4
2773 
2774 /* Host Interface Command Structures */
2775 struct ixgbe_hic_hdr {
2776 	u8 cmd;
2777 	u8 buf_len;
2778 	union {
2779 		u8 cmd_resv;
2780 		u8 ret_status;
2781 	} cmd_or_resp;
2782 	u8 checksum;
2783 };
2784 
2785 struct ixgbe_hic_hdr2_req {
2786 	u8 cmd;
2787 	u8 buf_lenh;
2788 	u8 buf_lenl;
2789 	u8 checksum;
2790 };
2791 
2792 struct ixgbe_hic_hdr2_rsp {
2793 	u8 cmd;
2794 	u8 buf_lenl;
2795 	u8 buf_lenh_status;     /* 7-5: high bits of buf_len, 4-0: status */
2796 	u8 checksum;
2797 };
2798 
2799 union ixgbe_hic_hdr2 {
2800 	struct ixgbe_hic_hdr2_req req;
2801 	struct ixgbe_hic_hdr2_rsp rsp;
2802 };
2803 
2804 struct ixgbe_hic_drv_info {
2805 	struct ixgbe_hic_hdr hdr;
2806 	u8 port_num;
2807 	u8 ver_sub;
2808 	u8 ver_build;
2809 	u8 ver_min;
2810 	u8 ver_maj;
2811 	u8 pad; /* end spacing to ensure length is mult. of dword */
2812 	u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2813 };
2814 
2815 struct ixgbe_hic_drv_info2 {
2816 	struct ixgbe_hic_hdr hdr;
2817 	u8 port_num;
2818 	u8 ver_sub;
2819 	u8 ver_build;
2820 	u8 ver_min;
2821 	u8 ver_maj;
2822 	char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
2823 };
2824 
2825 /* These need to be dword aligned */
2826 struct ixgbe_hic_read_shadow_ram {
2827 	union ixgbe_hic_hdr2 hdr;
2828 	u32 address;
2829 	u16 length;
2830 	u16 pad2;
2831 	u16 data;
2832 	u16 pad3;
2833 };
2834 
2835 struct ixgbe_hic_write_shadow_ram {
2836 	union ixgbe_hic_hdr2 hdr;
2837 	__be32 address;
2838 	__be16 length;
2839 	u16 pad2;
2840 	u16 data;
2841 	u16 pad3;
2842 };
2843 
2844 struct ixgbe_hic_disable_rxen {
2845 	struct ixgbe_hic_hdr hdr;
2846 	u8  port_number;
2847 	u8  pad2;
2848 	u16 pad3;
2849 };
2850 
2851 struct ixgbe_hic_phy_token_req {
2852 	struct ixgbe_hic_hdr hdr;
2853 	u8 port_number;
2854 	u8 command_type;
2855 	u16 pad;
2856 };
2857 
2858 struct ixgbe_hic_internal_phy_req {
2859 	struct ixgbe_hic_hdr hdr;
2860 	u8 port_number;
2861 	u8 command_type;
2862 	__be16 address;
2863 	u16 rsv1;
2864 	__be32 write_data;
2865 	u16 pad;
2866 } __packed;
2867 
2868 struct ixgbe_hic_internal_phy_resp {
2869 	struct ixgbe_hic_hdr hdr;
2870 	__be32 read_data;
2871 };
2872 
2873 struct ixgbe_hic_phy_activity_req {
2874 	struct ixgbe_hic_hdr hdr;
2875 	u8 port_number;
2876 	u8 pad;
2877 	__le16 activity_id;
2878 	__be32 data[FW_PHY_ACT_DATA_COUNT];
2879 };
2880 
2881 struct ixgbe_hic_phy_activity_resp {
2882 	struct ixgbe_hic_hdr hdr;
2883 	__be32 data[FW_PHY_ACT_DATA_COUNT];
2884 };
2885 
2886 /* Transmit Descriptor - Advanced */
2887 union ixgbe_adv_tx_desc {
2888 	struct {
2889 		__le64 buffer_addr;      /* Address of descriptor's data buf */
2890 		__le32 cmd_type_len;
2891 		__le32 olinfo_status;
2892 	} read;
2893 	struct {
2894 		__le64 rsvd;       /* Reserved */
2895 		__le32 nxtseq_seed;
2896 		__le32 status;
2897 	} wb;
2898 };
2899 
2900 /* Receive Descriptor - Advanced */
2901 union ixgbe_adv_rx_desc {
2902 	struct {
2903 		__le64 pkt_addr; /* Packet buffer address */
2904 		__le64 hdr_addr; /* Header buffer address */
2905 	} read;
2906 	struct {
2907 		struct {
2908 			union {
2909 				__le32 data;
2910 				struct {
2911 					__le16 pkt_info; /* RSS, Pkt type */
2912 					__le16 hdr_info; /* Splithdr, hdrlen */
2913 				} hs_rss;
2914 			} lo_dword;
2915 			union {
2916 				__le32 rss; /* RSS Hash */
2917 				struct {
2918 					__le16 ip_id; /* IP id */
2919 					__le16 csum; /* Packet Checksum */
2920 				} csum_ip;
2921 			} hi_dword;
2922 		} lower;
2923 		struct {
2924 			__le32 status_error; /* ext status/error */
2925 			__le16 length; /* Packet length */
2926 			__le16 vlan; /* VLAN tag */
2927 		} upper;
2928 	} wb;  /* writeback */
2929 };
2930 
2931 /* Context descriptors */
2932 struct ixgbe_adv_tx_context_desc {
2933 	__le32 vlan_macip_lens;
2934 	__le32 fceof_saidx;
2935 	__le32 type_tucmd_mlhl;
2936 	__le32 mss_l4len_idx;
2937 };
2938 
2939 enum {
2940 	IXGBE_VLAN_MACIP_LENS_REG	= 0,
2941 	IXGBE_FCEOF_SAIDX_REG		= 1,
2942 	IXGBE_TYPE_TUCMD_MLHL		= 2,
2943 	IXGBE_MSS_L4LEN_IDX		= 3,
2944 };
2945 
2946 /* Adv Transmit Descriptor Config Masks */
2947 #define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buf length(bytes) */
2948 #define IXGBE_ADVTXD_MAC_LINKSEC      0x00040000 /* Insert LinkSec */
2949 #define IXGBE_ADVTXD_MAC_TSTAMP	      0x00080000 /* IEEE 1588 Time Stamp */
2950 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK   0x000003FF /* IPSec SA index */
2951 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK    0x000001FF /* IPSec ESP length */
2952 #define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
2953 #define IXGBE_ADVTXD_DTYP_CTXT	0x2 /* Advanced Context Desc */
2954 #define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
2955 #define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
2956 #define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
2957 #define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
2958 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000    /* DDP hdr type or iSCSI */
2959 #define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2960 #define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
2961 #define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
2962 #define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
2963 #define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED pres in WB */
2964 #define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
2965 #define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
2966 #define IXGBE_ADVTXD_CC         0x00000080 /* Check Context */
2967 #define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
2968 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2969 				 IXGBE_ADVTXD_POPTS_SHIFT)
2970 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2971 				 IXGBE_ADVTXD_POPTS_SHIFT)
2972 #define IXGBE_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
2973 #define IXGBE_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
2974 #define IXGBE_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
2975 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2976 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2977 #define IXGBE_ADVTXD_POPTS_RSV       0x00002000 /* POPTS Reserved */
2978 #define IXGBE_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
2979 #define IXGBE_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
2980 #define IXGBE_ADVTXD_VLAN_SHIFT      16  /* Adv ctxt vlan tag shift */
2981 #define IXGBE_ADVTXD_TUCMD_IPV4      0x00000400  /* IP Packet Type: 1=IPv4 */
2982 #define IXGBE_ADVTXD_TUCMD_IPV6      0x00000000  /* IP Packet Type: 0=IPv6 */
2983 #define IXGBE_ADVTXD_TUCMD_L4T_UDP   0x00000000  /* L4 Packet TYPE of UDP */
2984 #define IXGBE_ADVTXD_TUCMD_L4T_TCP   0x00000800  /* L4 Packet TYPE of TCP */
2985 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP  0x00001000  /* L4 Packet TYPE of SCTP */
2986 #define IXGBE_ADVTXD_TUCMD_L4T_RSV     0x00001800 /* RSV L4 Packet TYPE */
2987 #define IXGBE_ADVTXD_TUCMD_MKRREQ    0x00002000 /*Req requires Markers and CRC*/
2988 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2989 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2990 #define IXGBE_ADVTXT_TUCMD_FCOE      0x00008000       /* FCoE Frame Type */
2991 #define IXGBE_ADVTXD_FCOEF_SOF       (BIT(2) << 10) /* FC SOF index */
2992 #define IXGBE_ADVTXD_FCOEF_PARINC    (BIT(3) << 10) /* Rel_Off in F_CTL */
2993 #define IXGBE_ADVTXD_FCOEF_ORIE      (BIT(4) << 10) /* Orientation: End */
2994 #define IXGBE_ADVTXD_FCOEF_ORIS      (BIT(5) << 10) /* Orientation: Start */
2995 #define IXGBE_ADVTXD_FCOEF_EOF_N     (0u << 10)  /* 00: EOFn */
2996 #define IXGBE_ADVTXD_FCOEF_EOF_T     (1u << 10)  /* 01: EOFt */
2997 #define IXGBE_ADVTXD_FCOEF_EOF_NI    (2u << 10)  /* 10: EOFni */
2998 #define IXGBE_ADVTXD_FCOEF_EOF_A     (3u << 10)  /* 11: EOFa */
2999 #define IXGBE_ADVTXD_FCOEF_EOF_MASK  (3u << 10)  /* FC EOF index */
3000 #define IXGBE_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
3001 #define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
3002 #define IXGBE_ADVTXD_MSS_MASK		GENMASK(31, IXGBE_ADVTXD_MSS_SHIFT)
3003 #define IXGBE_ADVTXD_HEADER_LEN_MASK	GENMASK(8, 0)
3004 
3005 /* Autonegotiation advertised speeds */
3006 typedef u32 ixgbe_autoneg_advertised;
3007 /* Link speed */
3008 typedef u32 ixgbe_link_speed;
3009 #define IXGBE_LINK_SPEED_UNKNOWN	0
3010 #define IXGBE_LINK_SPEED_10_FULL	0x0002
3011 #define IXGBE_LINK_SPEED_100_FULL	0x0008
3012 #define IXGBE_LINK_SPEED_1GB_FULL	0x0020
3013 #define IXGBE_LINK_SPEED_2_5GB_FULL	0x0400
3014 #define IXGBE_LINK_SPEED_5GB_FULL	0x0800
3015 #define IXGBE_LINK_SPEED_10GB_FULL	0x0080
3016 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
3017 					IXGBE_LINK_SPEED_10GB_FULL)
3018 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
3019 					IXGBE_LINK_SPEED_1GB_FULL | \
3020 					IXGBE_LINK_SPEED_10GB_FULL)
3021 
3022 /* Physical layer type */
3023 typedef u64 ixgbe_physical_layer;
3024 #define IXGBE_PHYSICAL_LAYER_UNKNOWN		0
3025 #define IXGBE_PHYSICAL_LAYER_10GBASE_T		0x00001
3026 #define IXGBE_PHYSICAL_LAYER_1000BASE_T		0x00002
3027 #define IXGBE_PHYSICAL_LAYER_100BASE_TX		0x00004
3028 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU	0x00008
3029 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR		0x00010
3030 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM	0x00020
3031 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR		0x00040
3032 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4	0x00080
3033 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4	0x00100
3034 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX	0x00200
3035 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX	0x00400
3036 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR		0x00800
3037 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI	0x01000
3038 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA	0x02000
3039 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX	0x04000
3040 #define IXGBE_PHYSICAL_LAYER_10BASE_T		0x08000
3041 #define IXGBE_PHYSICAL_LAYER_2500BASE_KX	0x10000
3042 #define IXGBE_PHYSICAL_LAYER_2500BASE_T		0x20000
3043 #define IXGBE_PHYSICAL_LAYER_5000BASE_T		0x40000
3044 
3045 /* Flow Control Data Sheet defined values
3046  * Calculation and defines taken from 802.1bb Annex O
3047  */
3048 
3049 /* BitTimes (BT) conversion */
3050 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
3051 #define IXGBE_B2BT(BT) (BT * 8)
3052 
3053 /* Calculate Delay to respond to PFC */
3054 #define IXGBE_PFC_D	672
3055 
3056 /* Calculate Cable Delay */
3057 #define IXGBE_CABLE_DC	5556 /* Delay Copper */
3058 #define IXGBE_CABLE_DO	5000 /* Delay Optical */
3059 
3060 /* Calculate Interface Delay X540 */
3061 #define IXGBE_PHY_DC	25600	/* Delay 10G BASET */
3062 #define IXGBE_MAC_DC	8192	/* Delay Copper XAUI interface */
3063 #define IXGBE_XAUI_DC	(2 * 2048) /* Delay Copper Phy */
3064 
3065 #define IXGBE_ID_X540	(IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
3066 
3067 /* Calculate Interface Delay 82598, 82599 */
3068 #define IXGBE_PHY_D	12800
3069 #define IXGBE_MAC_D	4096
3070 #define IXGBE_XAUI_D	(2 * 1024)
3071 
3072 #define IXGBE_ID	(IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
3073 
3074 /* Calculate Delay incurred from higher layer */
3075 #define IXGBE_HD	6144
3076 
3077 /* Calculate PCI Bus delay for low thresholds */
3078 #define IXGBE_PCI_DELAY	10000
3079 
3080 /* Calculate X540 delay value in bit times */
3081 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3082 			((36 * \
3083 			  (IXGBE_B2BT(_max_frame_link) + \
3084 			   IXGBE_PFC_D + \
3085 			   (2 * IXGBE_CABLE_DC) + \
3086 			   (2 * IXGBE_ID_X540) + \
3087 			   IXGBE_HD) / 25 + 1) + \
3088 			 2 * IXGBE_B2BT(_max_frame_tc))
3089 
3090 /* Calculate 82599, 82598 delay value in bit times */
3091 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3092 			((36 * \
3093 			  (IXGBE_B2BT(_max_frame_link) + \
3094 			   IXGBE_PFC_D + \
3095 			   (2 * IXGBE_CABLE_DC) + \
3096 			   (2 * IXGBE_ID) + \
3097 			   IXGBE_HD) / 25 + 1) + \
3098 			 2 * IXGBE_B2BT(_max_frame_tc))
3099 
3100 /* Calculate low threshold delay values */
3101 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
3102 			(2 * IXGBE_B2BT(_max_frame_tc) + \
3103 			(36 * IXGBE_PCI_DELAY / 25) + 1)
3104 #define IXGBE_LOW_DV(_max_frame_tc) \
3105 			(2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3106 
3107 /* Software ATR hash keys */
3108 #define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
3109 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
3110 
3111 /* Software ATR input stream values and masks */
3112 #define IXGBE_ATR_HASH_MASK		0x7fff
3113 #define IXGBE_ATR_L4TYPE_MASK		0x3
3114 #define IXGBE_ATR_L4TYPE_UDP		0x1
3115 #define IXGBE_ATR_L4TYPE_TCP		0x2
3116 #define IXGBE_ATR_L4TYPE_SCTP		0x3
3117 #define IXGBE_ATR_L4TYPE_IPV6_MASK	0x4
3118 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK	0x10
3119 enum ixgbe_atr_flow_type {
3120 	IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
3121 	IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
3122 	IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
3123 	IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
3124 	IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
3125 	IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
3126 	IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
3127 	IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
3128 };
3129 
3130 /* Flow Director ATR input struct. */
3131 union ixgbe_atr_input {
3132 	/*
3133 	 * Byte layout in order, all values with MSB first:
3134 	 *
3135 	 * vm_pool    - 1 byte
3136 	 * flow_type  - 1 byte
3137 	 * vlan_id    - 2 bytes
3138 	 * src_ip     - 16 bytes
3139 	 * dst_ip     - 16 bytes
3140 	 * src_port   - 2 bytes
3141 	 * dst_port   - 2 bytes
3142 	 * flex_bytes - 2 bytes
3143 	 * bkt_hash   - 2 bytes
3144 	 */
3145 	struct {
3146 		u8     vm_pool;
3147 		u8     flow_type;
3148 		__be16 vlan_id;
3149 		__be32 dst_ip[4];
3150 		__be32 src_ip[4];
3151 		__be16 src_port;
3152 		__be16 dst_port;
3153 		__be16 flex_bytes;
3154 		__be16 bkt_hash;
3155 	} formatted;
3156 	__be32 dword_stream[11];
3157 };
3158 
3159 /* Flow Director compressed ATR hash input struct */
3160 union ixgbe_atr_hash_dword {
3161 	struct {
3162 		u8 vm_pool;
3163 		u8 flow_type;
3164 		__be16 vlan_id;
3165 	} formatted;
3166 	__be32 ip;
3167 	struct {
3168 		__be16 src;
3169 		__be16 dst;
3170 	} port;
3171 	__be16 flex_bytes;
3172 	__be32 dword;
3173 };
3174 
3175 #define IXGBE_MVALS_INIT(m)		\
3176 	IXGBE_CAT(EEC, m),		\
3177 	IXGBE_CAT(FLA, m),		\
3178 	IXGBE_CAT(GRC, m),		\
3179 	IXGBE_CAT(FACTPS, m),		\
3180 	IXGBE_CAT(SWSM, m),		\
3181 	IXGBE_CAT(SWFW_SYNC, m),	\
3182 	IXGBE_CAT(FWSM, m),		\
3183 	IXGBE_CAT(SDP0_GPIEN, m),	\
3184 	IXGBE_CAT(SDP1_GPIEN, m),	\
3185 	IXGBE_CAT(SDP2_GPIEN, m),	\
3186 	IXGBE_CAT(EICR_GPI_SDP0, m),	\
3187 	IXGBE_CAT(EICR_GPI_SDP1, m),	\
3188 	IXGBE_CAT(EICR_GPI_SDP2, m),	\
3189 	IXGBE_CAT(CIAA, m),		\
3190 	IXGBE_CAT(CIAD, m),		\
3191 	IXGBE_CAT(I2C_CLK_IN, m),	\
3192 	IXGBE_CAT(I2C_CLK_OUT, m),	\
3193 	IXGBE_CAT(I2C_DATA_IN, m),	\
3194 	IXGBE_CAT(I2C_DATA_OUT, m),	\
3195 	IXGBE_CAT(I2C_DATA_OE_N_EN, m),	\
3196 	IXGBE_CAT(I2C_BB_EN, m),	\
3197 	IXGBE_CAT(I2C_CLK_OE_N_EN, m),	\
3198 	IXGBE_CAT(I2CCTL, m)
3199 
3200 enum ixgbe_mvals {
3201 	IXGBE_MVALS_INIT(IDX),
3202 	IXGBE_MVALS_IDX_LIMIT
3203 };
3204 
3205 enum ixgbe_eeprom_type {
3206 	ixgbe_eeprom_uninitialized = 0,
3207 	ixgbe_eeprom_spi,
3208 	ixgbe_flash,
3209 	ixgbe_eeprom_none /* No NVM support */
3210 };
3211 
3212 enum ixgbe_mac_type {
3213 	ixgbe_mac_unknown = 0,
3214 	ixgbe_mac_82598EB,
3215 	ixgbe_mac_82599EB,
3216 	ixgbe_mac_X540,
3217 	ixgbe_mac_X550,
3218 	ixgbe_mac_X550EM_x,
3219 	ixgbe_mac_x550em_a,
3220 	ixgbe_mac_e610,
3221 	ixgbe_mac_e610_vf,
3222 	ixgbe_num_macs
3223 };
3224 
3225 enum ixgbe_phy_type {
3226 	ixgbe_phy_unknown = 0,
3227 	ixgbe_phy_none,
3228 	ixgbe_phy_tn,
3229 	ixgbe_phy_aq,
3230 	ixgbe_phy_x550em_kr,
3231 	ixgbe_phy_x550em_kx4,
3232 	ixgbe_phy_x550em_xfi,
3233 	ixgbe_phy_x550em_ext_t,
3234 	ixgbe_phy_ext_1g_t,
3235 	ixgbe_phy_cu_unknown,
3236 	ixgbe_phy_qt,
3237 	ixgbe_phy_xaui,
3238 	ixgbe_phy_nl,
3239 	ixgbe_phy_sfp_passive_tyco,
3240 	ixgbe_phy_sfp_passive_unknown,
3241 	ixgbe_phy_sfp_active_unknown,
3242 	ixgbe_phy_sfp_avago,
3243 	ixgbe_phy_sfp_ftl,
3244 	ixgbe_phy_sfp_ftl_active,
3245 	ixgbe_phy_sfp_unknown,
3246 	ixgbe_phy_sfp_intel,
3247 	ixgbe_phy_qsfp_passive_unknown,
3248 	ixgbe_phy_qsfp_active_unknown,
3249 	ixgbe_phy_qsfp_intel,
3250 	ixgbe_phy_qsfp_unknown,
3251 	ixgbe_phy_sfp_unsupported,
3252 	ixgbe_phy_sgmii,
3253 	ixgbe_phy_fw,
3254 	ixgbe_phy_generic
3255 };
3256 
3257 /*
3258  * SFP+ module type IDs:
3259  *
3260  * ID   Module Type
3261  * =============
3262  * 0    SFP_DA_CU
3263  * 1    SFP_SR
3264  * 2    SFP_LR
3265  * 3    SFP_DA_CU_CORE0 - 82599-specific
3266  * 4    SFP_DA_CU_CORE1 - 82599-specific
3267  * 5    SFP_SR/LR_CORE0 - 82599-specific
3268  * 6    SFP_SR/LR_CORE1 - 82599-specific
3269  */
3270 enum ixgbe_sfp_type {
3271 	ixgbe_sfp_type_da_cu = 0,
3272 	ixgbe_sfp_type_sr = 1,
3273 	ixgbe_sfp_type_lr = 2,
3274 	ixgbe_sfp_type_da_cu_core0 = 3,
3275 	ixgbe_sfp_type_da_cu_core1 = 4,
3276 	ixgbe_sfp_type_srlr_core0 = 5,
3277 	ixgbe_sfp_type_srlr_core1 = 6,
3278 	ixgbe_sfp_type_da_act_lmt_core0 = 7,
3279 	ixgbe_sfp_type_da_act_lmt_core1 = 8,
3280 	ixgbe_sfp_type_1g_cu_core0 = 9,
3281 	ixgbe_sfp_type_1g_cu_core1 = 10,
3282 	ixgbe_sfp_type_1g_sx_core0 = 11,
3283 	ixgbe_sfp_type_1g_sx_core1 = 12,
3284 	ixgbe_sfp_type_1g_lx_core0 = 13,
3285 	ixgbe_sfp_type_1g_lx_core1 = 14,
3286 	ixgbe_sfp_type_1g_bx_core0 = 15,
3287 	ixgbe_sfp_type_1g_bx_core1 = 16,
3288 
3289 	ixgbe_sfp_type_not_present = 0xFFFE,
3290 	ixgbe_sfp_type_unknown = 0xFFFF
3291 };
3292 
3293 enum ixgbe_media_type {
3294 	ixgbe_media_type_unknown = 0,
3295 	ixgbe_media_type_fiber,
3296 	ixgbe_media_type_fiber_qsfp,
3297 	ixgbe_media_type_fiber_lco,
3298 	ixgbe_media_type_copper,
3299 	ixgbe_media_type_backplane,
3300 	ixgbe_media_type_cx4,
3301 	ixgbe_media_type_virtual,
3302 	ixgbe_media_type_da,
3303 	ixgbe_media_type_aui,
3304 };
3305 
3306 /* Flow Control Settings */
3307 enum ixgbe_fc_mode {
3308 	ixgbe_fc_none = 0,
3309 	ixgbe_fc_rx_pause,
3310 	ixgbe_fc_tx_pause,
3311 	ixgbe_fc_full,
3312 	ixgbe_fc_default,
3313 	ixgbe_fc_pfc,
3314 };
3315 
3316 /* Smart Speed Settings */
3317 #define IXGBE_SMARTSPEED_MAX_RETRIES	3
3318 enum ixgbe_smart_speed {
3319 	ixgbe_smart_speed_auto = 0,
3320 	ixgbe_smart_speed_on,
3321 	ixgbe_smart_speed_off
3322 };
3323 
3324 /* PCI bus types */
3325 enum ixgbe_bus_type {
3326 	ixgbe_bus_type_unknown = 0,
3327 	ixgbe_bus_type_pci_express,
3328 	ixgbe_bus_type_internal,
3329 	ixgbe_bus_type_reserved
3330 };
3331 
3332 /* PCI bus speeds */
3333 enum ixgbe_bus_speed {
3334 	ixgbe_bus_speed_unknown = 0,
3335 	ixgbe_bus_speed_33      = 33,
3336 	ixgbe_bus_speed_66      = 66,
3337 	ixgbe_bus_speed_100     = 100,
3338 	ixgbe_bus_speed_120     = 120,
3339 	ixgbe_bus_speed_133     = 133,
3340 	ixgbe_bus_speed_2500    = 2500,
3341 	ixgbe_bus_speed_5000    = 5000,
3342 	ixgbe_bus_speed_8000    = 8000,
3343 	ixgbe_bus_speed_reserved
3344 };
3345 
3346 /* PCI bus widths */
3347 enum ixgbe_bus_width {
3348 	ixgbe_bus_width_unknown = 0,
3349 	ixgbe_bus_width_pcie_x1 = 1,
3350 	ixgbe_bus_width_pcie_x2 = 2,
3351 	ixgbe_bus_width_pcie_x4 = 4,
3352 	ixgbe_bus_width_pcie_x8 = 8,
3353 	ixgbe_bus_width_32      = 32,
3354 	ixgbe_bus_width_64      = 64,
3355 	ixgbe_bus_width_reserved
3356 };
3357 
3358 struct ixgbe_addr_filter_info {
3359 	u32 num_mc_addrs;
3360 	u32 rar_used_count;
3361 	u32 mta_in_use;
3362 	u32 overflow_promisc;
3363 	bool uc_set_promisc;
3364 	bool user_set_promisc;
3365 };
3366 
3367 /* Bus parameters */
3368 struct ixgbe_bus_info {
3369 	enum ixgbe_bus_speed speed;
3370 	enum ixgbe_bus_width width;
3371 	enum ixgbe_bus_type type;
3372 
3373 	u8 func;
3374 	u8 lan_id;
3375 	u8 instance_id;
3376 };
3377 
3378 /* Flow control parameters */
3379 struct ixgbe_fc_info {
3380 	u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
3381 	u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */
3382 	u16 pause_time; /* Flow Control Pause timer */
3383 	bool send_xon; /* Flow control send XON */
3384 	bool strict_ieee; /* Strict IEEE mode */
3385 	bool disable_fc_autoneg; /* Do not autonegotiate FC */
3386 	bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
3387 	enum ixgbe_fc_mode current_mode; /* FC mode in effect */
3388 	enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
3389 };
3390 
3391 /* Statistics counters collected by the MAC */
3392 struct ixgbe_hw_stats {
3393 	u64 crcerrs;
3394 	u64 illerrc;
3395 	u64 errbc;
3396 	u64 mspdc;
3397 	u64 mpctotal;
3398 	u64 mpc[8];
3399 	u64 mlfc;
3400 	u64 mrfc;
3401 	u64 rlec;
3402 	u64 lxontxc;
3403 	u64 lxonrxc;
3404 	u64 lxofftxc;
3405 	u64 lxoffrxc;
3406 	u64 pxontxc[8];
3407 	u64 pxonrxc[8];
3408 	u64 pxofftxc[8];
3409 	u64 pxoffrxc[8];
3410 	u64 prc64;
3411 	u64 prc127;
3412 	u64 prc255;
3413 	u64 prc511;
3414 	u64 prc1023;
3415 	u64 prc1522;
3416 	u64 gprc;
3417 	u64 bprc;
3418 	u64 mprc;
3419 	u64 gptc;
3420 	u64 gorc;
3421 	u64 gotc;
3422 	u64 rnbc[8];
3423 	u64 ruc;
3424 	u64 rfc;
3425 	u64 roc;
3426 	u64 rjc;
3427 	u64 mngprc;
3428 	u64 mngpdc;
3429 	u64 mngptc;
3430 	u64 tor;
3431 	u64 tpr;
3432 	u64 tpt;
3433 	u64 ptc64;
3434 	u64 ptc127;
3435 	u64 ptc255;
3436 	u64 ptc511;
3437 	u64 ptc1023;
3438 	u64 ptc1522;
3439 	u64 mptc;
3440 	u64 bptc;
3441 	u64 xec;
3442 	u64 rqsmr[16];
3443 	u64 tqsmr[8];
3444 	u64 qprc[16];
3445 	u64 qptc[16];
3446 	u64 qbrc[16];
3447 	u64 qbtc[16];
3448 	u64 qprdc[16];
3449 	u64 pxon2offc[8];
3450 	u64 fdirustat_add;
3451 	u64 fdirustat_remove;
3452 	u64 fdirfstat_fadd;
3453 	u64 fdirfstat_fremove;
3454 	u64 fdirmatch;
3455 	u64 fdirmiss;
3456 	u64 fccrc;
3457 	u64 fcoerpdc;
3458 	u64 fcoeprc;
3459 	u64 fcoeptc;
3460 	u64 fcoedwrc;
3461 	u64 fcoedwtc;
3462 	u64 fcoe_noddp;
3463 	u64 fcoe_noddp_ext_buff;
3464 	u64 b2ospc;
3465 	u64 b2ogprc;
3466 	u64 o2bgptc;
3467 	u64 o2bspc;
3468 };
3469 
3470 /* forward declaration */
3471 struct ixgbe_hw;
3472 
3473 /* Function pointer table */
3474 struct ixgbe_eeprom_operations {
3475 	int (*init_params)(struct ixgbe_hw *);
3476 	int (*read)(struct ixgbe_hw *, u16, u16 *);
3477 	int (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3478 	int (*write)(struct ixgbe_hw *, u16, u16);
3479 	int (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3480 	int (*validate_checksum)(struct ixgbe_hw *, u16 *);
3481 	int (*update_checksum)(struct ixgbe_hw *);
3482 	int (*calc_checksum)(struct ixgbe_hw *);
3483 	int (*read_pba_string)(struct ixgbe_hw *hw, u8 *pba_num,
3484 			       u32 pba_num_size);
3485 };
3486 
3487 struct ixgbe_mac_operations {
3488 	int (*init_hw)(struct ixgbe_hw *);
3489 	int (*reset_hw)(struct ixgbe_hw *);
3490 	int (*start_hw)(struct ixgbe_hw *);
3491 	int (*clear_hw_cntrs)(struct ixgbe_hw *);
3492 	enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3493 	int (*get_fw_ver)(struct ixgbe_hw *hw);
3494 	int (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3495 	int (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3496 	int (*get_device_caps)(struct ixgbe_hw *, u16 *);
3497 	int (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3498 	int (*stop_adapter)(struct ixgbe_hw *);
3499 	int (*get_bus_info)(struct ixgbe_hw *);
3500 	void (*set_lan_id)(struct ixgbe_hw *);
3501 	int (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3502 	int (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3503 	int (*setup_sfp)(struct ixgbe_hw *);
3504 	int (*disable_rx_buff)(struct ixgbe_hw *);
3505 	int (*enable_rx_buff)(struct ixgbe_hw *);
3506 	int (*enable_rx_dma)(struct ixgbe_hw *, u32);
3507 	int (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3508 	void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3509 	void (*init_swfw_sync)(struct ixgbe_hw *);
3510 	int (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3511 	int (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3512 
3513 	/* Link */
3514 	void (*disable_tx_laser)(struct ixgbe_hw *);
3515 	void (*enable_tx_laser)(struct ixgbe_hw *);
3516 	void (*flap_tx_laser)(struct ixgbe_hw *);
3517 	void (*stop_link_on_d3)(struct ixgbe_hw *);
3518 	int (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3519 	int (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3520 	int (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3521 	int (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3522 				     bool *);
3523 	void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3524 
3525 	/* Packet Buffer Manipulation */
3526 	void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
3527 
3528 	/* LED */
3529 	int (*led_on)(struct ixgbe_hw *, u32);
3530 	int (*led_off)(struct ixgbe_hw *, u32);
3531 	int (*blink_led_start)(struct ixgbe_hw *, u32);
3532 	int (*blink_led_stop)(struct ixgbe_hw *, u32);
3533 	int (*init_led_link_act)(struct ixgbe_hw *);
3534 
3535 	/* RAR, Multicast, VLAN */
3536 	int (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3537 	int (*clear_rar)(struct ixgbe_hw *, u32);
3538 	int (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3539 	int (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3540 	int (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3541 	int (*init_rx_addrs)(struct ixgbe_hw *);
3542 	int (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
3543 	int (*enable_mc)(struct ixgbe_hw *);
3544 	int (*disable_mc)(struct ixgbe_hw *);
3545 	int (*clear_vfta)(struct ixgbe_hw *);
3546 	int (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3547 	int (*init_uta_tables)(struct ixgbe_hw *);
3548 	void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3549 	void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3550 
3551 	/* Flow Control */
3552 	int (*fc_enable)(struct ixgbe_hw *);
3553 	int (*setup_fc)(struct ixgbe_hw *);
3554 	void (*fc_autoneg)(struct ixgbe_hw *);
3555 
3556 	/* Manageability interface */
3557 	int (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
3558 			      const char *);
3559 	int (*get_thermal_sensor_data)(struct ixgbe_hw *);
3560 	int (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
3561 	bool (*fw_recovery_mode)(struct ixgbe_hw *hw);
3562 	bool (*fw_rollback_mode)(struct ixgbe_hw *hw);
3563 	int (*get_nvm_ver)(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);
3564 	void (*disable_rx)(struct ixgbe_hw *hw);
3565 	void (*enable_rx)(struct ixgbe_hw *hw);
3566 	void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3567 					   unsigned int);
3568 	void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3569 
3570 	/* DMA Coalescing */
3571 	int (*dmac_config)(struct ixgbe_hw *hw);
3572 	int (*dmac_update_tcs)(struct ixgbe_hw *hw);
3573 	int (*dmac_config_tcs)(struct ixgbe_hw *hw);
3574 	int (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
3575 	int (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
3576 
3577 	/* MDD events */
3578 	void (*enable_mdd)(struct ixgbe_hw *hw);
3579 	void (*disable_mdd)(struct ixgbe_hw *hw);
3580 	void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);
3581 	void (*handle_mdd)(struct ixgbe_hw *hw, unsigned long *vf_bitmap);
3582 };
3583 
3584 struct ixgbe_phy_operations {
3585 	int (*identify)(struct ixgbe_hw *);
3586 	int (*identify_sfp)(struct ixgbe_hw *);
3587 	int (*init)(struct ixgbe_hw *);
3588 	int (*reset)(struct ixgbe_hw *);
3589 	int (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3590 	int (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3591 	int (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3592 	int (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3593 	int (*setup_link)(struct ixgbe_hw *);
3594 	int (*setup_internal_link)(struct ixgbe_hw *);
3595 	int (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3596 	int (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3597 	int (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3598 	int (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3599 	int (*read_i2c_sff8472)(struct ixgbe_hw *, u8, u8 *);
3600 	int (*read_i2c_eeprom)(struct ixgbe_hw *, u8, u8 *);
3601 	int (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3602 	bool (*check_overtemp)(struct ixgbe_hw *);
3603 	int (*set_phy_power)(struct ixgbe_hw *, bool on);
3604 	int (*enter_lplu)(struct ixgbe_hw *);
3605 	int (*handle_lasi)(struct ixgbe_hw *hw, bool *);
3606 	int (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3607 				      u8 *value);
3608 	int (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3609 				       u8 value);
3610 };
3611 
3612 struct ixgbe_link_operations {
3613 	int (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3614 	int (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3615 				  u16 *val);
3616 	int (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3617 	int (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3618 				   u16 val);
3619 };
3620 
3621 struct ixgbe_link_info {
3622 	struct ixgbe_link_operations ops;
3623 	u8 addr;
3624 	struct ixgbe_link_status link_info;
3625 	struct ixgbe_link_status link_info_old;
3626 	u8 get_link_info;
3627 };
3628 
3629 struct ixgbe_eeprom_info {
3630 	struct ixgbe_eeprom_operations  ops;
3631 	enum ixgbe_eeprom_type          type;
3632 	u32                             semaphore_delay;
3633 	u16                             word_size;
3634 	u16                             address_bits;
3635 	u16                             word_page_size;
3636 	u16				ctrl_word_3;
3637 };
3638 
3639 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
3640 struct ixgbe_mac_info {
3641 	struct ixgbe_mac_operations     ops;
3642 	enum ixgbe_mac_type             type;
3643 	u8                              addr[ETH_ALEN];
3644 	u8                              perm_addr[ETH_ALEN];
3645 	u8                              san_addr[ETH_ALEN];
3646 	/* prefix for World Wide Node Name (WWNN) */
3647 	u16                             wwnn_prefix;
3648 	/* prefix for World Wide Port Name (WWPN) */
3649 	u16                             wwpn_prefix;
3650 	u16				max_msix_vectors;
3651 #define IXGBE_MAX_MTA			128
3652 	u32				mta_shadow[IXGBE_MAX_MTA];
3653 	s32                             mc_filter_type;
3654 	u32                             mcft_size;
3655 	u32                             vft_size;
3656 	u32                             num_rar_entries;
3657 	u32                             rar_highwater;
3658 	u32				rx_pb_size;
3659 	u32                             max_tx_queues;
3660 	u32                             max_rx_queues;
3661 	u32                             orig_autoc;
3662 	u32                             orig_autoc2;
3663 	bool                            orig_link_settings_stored;
3664 	bool                            autotry_restart;
3665 	u8                              flags;
3666 	u8				san_mac_rar_index;
3667 	struct ixgbe_thermal_sensor_data  thermal_sensor_data;
3668 	bool				set_lben;
3669 	u32				max_link_up_time;
3670 	u8				led_link_act;
3671 };
3672 
3673 struct ixgbe_phy_info {
3674 	struct ixgbe_phy_operations     ops;
3675 	struct mdio_if_info		mdio;
3676 	enum ixgbe_phy_type             type;
3677 	u32                             id;
3678 	enum ixgbe_sfp_type             sfp_type;
3679 	bool                            sfp_setup_needed;
3680 	u32                             revision;
3681 	enum ixgbe_media_type           media_type;
3682 	u32				phy_semaphore_mask;
3683 	bool                            reset_disable;
3684 	ixgbe_autoneg_advertised        autoneg_advertised;
3685 	ixgbe_link_speed		speeds_supported;
3686 	ixgbe_link_speed		eee_speeds_supported;
3687 	ixgbe_link_speed		eee_speeds_advertised;
3688 	enum ixgbe_smart_speed          smart_speed;
3689 	bool                            smart_speed_active;
3690 	bool                            multispeed_fiber;
3691 	bool                            reset_if_overtemp;
3692 	bool                            qsfp_shared_i2c_bus;
3693 	u32				nw_mng_if_sel;
3694 	u64				phy_type_low;
3695 	u64				phy_type_high;
3696 	u16				curr_user_speed_req;
3697 	struct ixgbe_aci_cmd_set_phy_cfg_data curr_user_phy_cfg;
3698 };
3699 
3700 struct ixgbe_mbx_stats {
3701 	u32 msgs_tx;
3702 	u32 msgs_rx;
3703 
3704 	u32 acks;
3705 	u32 reqs;
3706 	u32 rsts;
3707 };
3708 
3709 struct ixgbe_mbx_operations;
3710 
3711 struct ixgbe_mbx_info {
3712 	const struct ixgbe_mbx_operations *ops;
3713 	struct ixgbe_mbx_stats stats;
3714 	u32 timeout;
3715 	u32 usec_delay;
3716 	u32 v2p_mailbox;
3717 	u16 size;
3718 };
3719 
3720 struct ixgbe_hw {
3721 	u8 __iomem			*hw_addr;
3722 	void				*back;
3723 	struct ixgbe_mac_info		mac;
3724 	struct ixgbe_addr_filter_info	addr_ctrl;
3725 	struct ixgbe_fc_info		fc;
3726 	struct ixgbe_phy_info		phy;
3727 	struct ixgbe_link_info		link;
3728 	struct ixgbe_eeprom_info	eeprom;
3729 	struct ixgbe_bus_info		bus;
3730 	struct ixgbe_mbx_info		mbx;
3731 	const u32			*mvals;
3732 	u16				device_id;
3733 	u16				vendor_id;
3734 	u16				subsystem_device_id;
3735 	u16				subsystem_vendor_id;
3736 	u8				revision_id;
3737 	bool				adapter_stopped;
3738 	bool				force_full_reset;
3739 	bool				allow_unsupported_sfp;
3740 	bool				wol_enabled;
3741 	bool				need_crosstalk_fix;
3742 	u8				api_branch;
3743 	u8				api_maj_ver;
3744 	u8				api_min_ver;
3745 	u8				api_patch;
3746 	u8				fw_branch;
3747 	u8				fw_maj_ver;
3748 	u8				fw_min_ver;
3749 	u8				fw_patch;
3750 	u32				fw_build;
3751 	struct ixgbe_aci_info		aci;
3752 	struct ixgbe_flash_info		flash;
3753 	struct ixgbe_hw_dev_caps	dev_caps;
3754 	struct ixgbe_hw_func_caps	func_caps;
3755 };
3756 
3757 struct ixgbe_info {
3758 	enum ixgbe_mac_type		mac;
3759 	int				(*get_invariants)(struct ixgbe_hw *);
3760 	const struct ixgbe_mac_operations	*mac_ops;
3761 	const struct ixgbe_eeprom_operations	*eeprom_ops;
3762 	const struct ixgbe_phy_operations	*phy_ops;
3763 	const struct ixgbe_mbx_operations	*mbx_ops;
3764 	const struct ixgbe_link_operations	*link_ops;
3765 	const u32			*mvals;
3766 };
3767 
3768 #define IXGBE_FUSES0_GROUP(_i)		(0x11158 + ((_i) * 4))
3769 #define IXGBE_FUSES0_300MHZ		BIT(5)
3770 #define IXGBE_FUSES0_REV_MASK		(3u << 6)
3771 
3772 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)	((P) ? 0x8010 : 0x4010)
3773 #define IXGBE_KRM_LINK_S1(P)		((P) ? 0x8200 : 0x4200)
3774 #define IXGBE_KRM_LINK_CTRL_1(P)	((P) ? 0x820C : 0x420C)
3775 #define IXGBE_KRM_AN_CNTL_1(P)		((P) ? 0x822C : 0x422C)
3776 #define IXGBE_KRM_AN_CNTL_8(P)		((P) ? 0x8248 : 0x4248)
3777 #define IXGBE_KRM_SGMII_CTRL(P)		((P) ? 0x82A0 : 0x42A0)
3778 #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P)	((P) ? 0x836C : 0x436C)
3779 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P)	((P) ? 0x8634 : 0x4634)
3780 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P)	((P) ? 0x8638 : 0x4638)
3781 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)	((P) ? 0x8B00 : 0x4B00)
3782 #define IXGBE_KRM_PMD_DFX_BURNIN(P)	((P) ? 0x8E00 : 0x4E00)
3783 #define IXGBE_KRM_PMD_FLX_MASK_ST20(P)	((P) ? 0x9054 : 0x5054)
3784 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)	((P) ? 0x9520 : 0x5520)
3785 #define IXGBE_KRM_RX_ANA_CTL(P)		((P) ? 0x9A00 : 0x5A00)
3786 
3787 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA		~(0x3 << 20)
3788 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR		BIT(20)
3789 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR		(0x2 << 20)
3790 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN		BIT(25)
3791 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN		BIT(26)
3792 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN		BIT(27)
3793 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M		~(0x7 << 28)
3794 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M		BIT(28)
3795 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G		(0x2 << 28)
3796 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G		(0x3 << 28)
3797 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN		(0x4 << 28)
3798 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G		(0x7 << 28)
3799 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK		(0x7 << 28)
3800 #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART	BIT(31)
3801 
3802 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B		BIT(9)
3803 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS		BIT(11)
3804 
3805 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK	(7u << 8)
3806 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G	(2u << 8)
3807 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G	(4u << 8)
3808 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN		BIT(12)
3809 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN	BIT(13)
3810 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ		BIT(14)
3811 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC		BIT(15)
3812 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX		BIT(16)
3813 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR		BIT(18)
3814 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX		BIT(24)
3815 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR		BIT(26)
3816 #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE		BIT(28)
3817 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE		BIT(29)
3818 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART		BIT(31)
3819 
3820 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE			BIT(28)
3821 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE			BIT(29)
3822 
3823 #define IXGBE_KRM_AN_CNTL_8_LINEAR			BIT(0)
3824 #define IXGBE_KRM_AN_CNTL_8_LIMITING			BIT(1)
3825 
3826 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE		BIT(10)
3827 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE		BIT(11)
3828 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D	BIT(12)
3829 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D		BIT(19)
3830 
3831 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN			BIT(6)
3832 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN		BIT(15)
3833 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN		BIT(16)
3834 
3835 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL	BIT(4)
3836 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS	BIT(2)
3837 
3838 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK	(3u << 16)
3839 
3840 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN	BIT(1)
3841 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN	BIT(2)
3842 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN		BIT(3)
3843 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN		BIT(31)
3844 
3845 #define IXGBE_SB_IOSF_INDIRECT_CTRL		0x00011144
3846 #define IXGBE_SB_IOSF_INDIRECT_DATA		0x00011148
3847 
3848 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT		0
3849 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK		0xFF
3850 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT	18
3851 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
3852 				(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
3853 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT	20
3854 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
3855 				(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
3856 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT	28
3857 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK	0x7
3858 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT		31
3859 #define IXGBE_SB_IOSF_CTRL_BUSY		BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
3860 #define IXGBE_SB_IOSF_TARGET_KR_PHY	0
3861 
3862 #define IXGBE_NW_MNG_IF_SEL		0x00011178
3863 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT		BIT(1)
3864 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M	BIT(17)
3865 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M	BIT(18)
3866 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G	BIT(19)
3867 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G	BIT(20)
3868 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G	BIT(21)
3869 #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE	BIT(25)
3870 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE	BIT(24) /* X552 only */
3871 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT	3
3872 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD	\
3873 				(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
3874 #endif /* _IXGBE_TYPE_H_ */
3875