1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #ifndef IRDMA_MAIN_H 4 #define IRDMA_MAIN_H 5 6 #include <linux/ip.h> 7 #include <linux/tcp.h> 8 #include <linux/if_vlan.h> 9 #include <net/addrconf.h> 10 #include <net/netevent.h> 11 #include <net/tcp.h> 12 #include <net/ip6_route.h> 13 #include <net/flow.h> 14 #include <net/secure_seq.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/inetdevice.h> 18 #include <linux/spinlock.h> 19 #include <linux/kernel.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/workqueue.h> 24 #include <linux/slab.h> 25 #include <linux/io.h> 26 #include <linux/iopoll.h> 27 #include <linux/crc32c.h> 28 #include <linux/kthread.h> 29 #ifndef CONFIG_64BIT 30 #include <linux/io-64-nonatomic-lo-hi.h> 31 #endif 32 #include <linux/auxiliary_bus.h> 33 #include <linux/net/intel/iidc_rdma.h> 34 #include <rdma/ib_smi.h> 35 #include <rdma/ib_verbs.h> 36 #include <rdma/ib_pack.h> 37 #include <rdma/rdma_cm.h> 38 #include <rdma/iw_cm.h> 39 #include <rdma/ib_user_verbs.h> 40 #include <rdma/ib_umem.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/uverbs_ioctl.h> 43 #include "osdep.h" 44 #include "defs.h" 45 #include "hmc.h" 46 #include "type.h" 47 #include "ws.h" 48 #include "protos.h" 49 #include "pble.h" 50 #include "cm.h" 51 #include <rdma/irdma-abi.h> 52 #include "verbs.h" 53 #include "user.h" 54 #include "puda.h" 55 56 extern struct auxiliary_driver i40iw_auxiliary_drv; 57 extern struct iidc_rdma_core_auxiliary_drv icrdma_core_auxiliary_drv; 58 extern struct iidc_rdma_core_auxiliary_drv ig3rdma_core_auxiliary_drv; 59 60 #define IRDMA_FW_VER_DEFAULT 2 61 #define IRDMA_HW_VER 2 62 63 #define IRDMA_ARP_ADD 1 64 #define IRDMA_ARP_DELETE 2 65 #define IRDMA_ARP_RESOLVE 3 66 67 #define IRDMA_MACIP_ADD 1 68 #define IRDMA_MACIP_DELETE 2 69 70 #define IW_GEN_3_CCQ_SIZE (2 * IRDMA_CQP_SW_SQSIZE_2048 + 2) 71 #define IW_CCQ_SIZE (IRDMA_CQP_SW_SQSIZE_2048 + 2) 72 #define IW_CEQ_SIZE 2048 73 #define IW_AEQ_SIZE 2048 74 75 #define RX_BUF_SIZE (1536 + 8) 76 #define IW_REG0_SIZE (4 * 1024) 77 #define IW_TX_TIMEOUT (6 * HZ) 78 #define IW_FIRST_QPN 1 79 80 #define IW_SW_CONTEXT_ALIGN 1024 81 82 #define MAX_DPC_ITERATIONS 128 83 84 #define IRDMA_EVENT_TIMEOUT_MS 5000 85 #define IRDMA_VCHNL_EVENT_TIMEOUT 100000 86 #define IRDMA_RST_TIMEOUT_HZ 4 87 88 #define IRDMA_NO_QSET 0xffff 89 90 #define IW_CFG_FPM_QP_COUNT 32768 91 #define IRDMA_MAX_PAGES_PER_FMR 262144 92 #define IRDMA_MIN_PAGES_PER_FMR 1 93 #define IRDMA_CQP_COMPL_RQ_WQE_FLUSHED 2 94 #define IRDMA_CQP_COMPL_SQ_WQE_FLUSHED 3 95 96 #define IRDMA_Q_TYPE_PE_AEQ 0x80 97 #define IRDMA_Q_INVALID_IDX 0xffff 98 #define IRDMA_REM_ENDPOINT_TRK_QPID 3 99 100 #define IRDMA_DRV_OPT_ENA_MPA_VER_0 0x00000001 101 #define IRDMA_DRV_OPT_DISABLE_MPA_CRC 0x00000002 102 #define IRDMA_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004 103 #define IRDMA_DRV_OPT_DISABLE_INTF 0x00000008 104 #define IRDMA_DRV_OPT_ENA_MSI 0x00000010 105 #define IRDMA_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020 106 #define IRDMA_DRV_OPT_NO_INLINE_DATA 0x00000080 107 #define IRDMA_DRV_OPT_DISABLE_INT_MOD 0x00000100 108 #define IRDMA_DRV_OPT_DISABLE_VIRT_WQ 0x00000200 109 #define IRDMA_DRV_OPT_ENA_PAU 0x00000400 110 #define IRDMA_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800 111 112 #define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types) 113 #define IRDMA_ROCE_CWND_DEFAULT 0x400 114 #define IRDMA_ROCE_ACKCREDS_DEFAULT 0x1E 115 116 #define IRDMA_FLUSH_SQ BIT(0) 117 #define IRDMA_FLUSH_RQ BIT(1) 118 #define IRDMA_REFLUSH BIT(2) 119 #define IRDMA_FLUSH_WAIT BIT(3) 120 121 #define IRDMA_IRQ_NAME_STR_LEN (64) 122 123 #define IRDMA_NUM_AEQ_MSIX 1 124 #define IRDMA_MIN_MSIX 2 125 126 enum init_completion_state { 127 INVALID_STATE = 0, 128 INITIAL_STATE, 129 CQP_CREATED, 130 HMC_OBJS_CREATED, 131 HW_RSRC_INITIALIZED, 132 CCQ_CREATED, 133 CEQ0_CREATED, 134 CEQS_CREATED, 135 PBLE_CHUNK_MEM, 136 AEQ_CREATED, 137 ILQ_CREATED, 138 IEQ_CREATED, /* Last state of probe */ 139 IP_ADDR_REGISTERED, /* Last state of open */ 140 }; 141 142 struct irdma_rsrc_limits { 143 u32 qplimit; 144 u32 mrlimit; 145 u32 cqlimit; 146 }; 147 148 struct irdma_cqp_err_info { 149 u16 maj; 150 u16 min; 151 const char *desc; 152 }; 153 154 struct irdma_cqp_compl_info { 155 u32 op_ret_val; 156 u16 maj_err_code; 157 u16 min_err_code; 158 bool error; 159 u8 op_code; 160 }; 161 162 struct irdma_cqp_request { 163 struct cqp_cmds_info info; 164 wait_queue_head_t waitq; 165 struct list_head list; 166 refcount_t refcnt; 167 void (*callback_fcn)(struct irdma_cqp_request *cqp_request); 168 void *param; 169 struct irdma_cqp_compl_info compl_info; 170 bool request_done; /* READ/WRITE_ONCE macros operate on it */ 171 bool waiting:1; 172 bool dynamic:1; 173 bool pending:1; 174 }; 175 176 struct irdma_cqp { 177 struct irdma_sc_cqp sc_cqp; 178 spinlock_t req_lock; /* protect CQP request list */ 179 spinlock_t compl_lock; /* protect CQP completion processing */ 180 wait_queue_head_t waitq; 181 wait_queue_head_t remove_wq; 182 struct irdma_dma_mem sq; 183 struct irdma_dma_mem host_ctx; 184 u64 *scratch_array; 185 struct irdma_cqp_request *cqp_requests; 186 struct irdma_ooo_cqp_op *oop_op_array; 187 struct list_head cqp_avail_reqs; 188 struct list_head cqp_pending_reqs; 189 }; 190 191 struct irdma_ccq { 192 struct irdma_sc_cq sc_cq; 193 struct irdma_dma_mem mem_cq; 194 struct irdma_dma_mem shadow_area; 195 }; 196 197 struct irdma_ceq { 198 struct irdma_sc_ceq sc_ceq; 199 struct irdma_dma_mem mem; 200 u32 irq; 201 u32 msix_idx; 202 struct irdma_pci_f *rf; 203 struct tasklet_struct dpc_tasklet; 204 spinlock_t ce_lock; /* sync cq destroy with cq completion event notification */ 205 }; 206 207 struct irdma_aeq { 208 struct irdma_sc_aeq sc_aeq; 209 struct irdma_dma_mem mem; 210 struct irdma_pble_alloc palloc; 211 bool virtual_map; 212 }; 213 214 struct irdma_arp_entry { 215 u32 ip_addr[4]; 216 u8 mac_addr[ETH_ALEN]; 217 }; 218 219 struct irdma_msix_vector { 220 u32 idx; 221 u32 irq; 222 u32 cpu_affinity; 223 u32 ceq_id; 224 cpumask_t mask; 225 char name[IRDMA_IRQ_NAME_STR_LEN]; 226 }; 227 228 struct irdma_mc_table_info { 229 u32 mgn; 230 u32 dest_ip[4]; 231 bool lan_fwd:1; 232 bool ipv4_valid:1; 233 }; 234 235 struct mc_table_list { 236 struct list_head list; 237 struct irdma_mc_table_info mc_info; 238 struct irdma_mcast_grp_info mc_grp_ctx; 239 }; 240 241 struct irdma_qv_info { 242 u32 v_idx; /* msix_vector */ 243 u16 ceq_idx; 244 u16 aeq_idx; 245 u8 itr_idx; 246 }; 247 248 struct irdma_qvlist_info { 249 u32 num_vectors; 250 struct irdma_qv_info qv_info[] __counted_by(num_vectors); 251 }; 252 253 struct irdma_gen_ops { 254 void (*request_reset)(struct irdma_pci_f *rf); 255 int (*register_qset)(struct irdma_sc_vsi *vsi, 256 struct irdma_ws_node *tc_node); 257 void (*unregister_qset)(struct irdma_sc_vsi *vsi, 258 struct irdma_ws_node *tc_node); 259 }; 260 261 struct irdma_pci_f { 262 bool reset:1; 263 bool rsrc_created:1; 264 bool msix_shared:1; 265 bool hwqp1_rsvd:1; 266 u8 rsrc_profile; 267 u8 *hmc_info_mem; 268 u8 *mem_rsrc; 269 u8 rdma_ver; 270 u8 rst_to; 271 u8 pf_id; 272 enum irdma_protocol_used protocol_used; 273 u32 sd_type; 274 u32 msix_count; 275 u32 max_mr; 276 u32 max_qp; 277 u32 max_cq; 278 u32 max_srq; 279 u32 next_srq; 280 u32 max_ah; 281 u32 next_ah; 282 u32 max_mcg; 283 u32 next_mcg; 284 u32 max_pd; 285 u32 next_qp; 286 u32 next_cq; 287 u32 next_pd; 288 u32 max_mr_size; 289 u32 max_cqe; 290 u32 mr_stagmask; 291 u32 used_pds; 292 u32 used_cqs; 293 u32 used_srqs; 294 u32 used_mrs; 295 u32 used_qps; 296 u32 arp_table_size; 297 u32 next_arp_index; 298 u32 ceqs_count; 299 u32 next_ws_node_id; 300 u32 max_ws_node_id; 301 u32 limits_sel; 302 unsigned long *allocated_ws_nodes; 303 unsigned long *allocated_qps; 304 unsigned long *allocated_cqs; 305 unsigned long *allocated_srqs; 306 unsigned long *allocated_mrs; 307 unsigned long *allocated_pds; 308 unsigned long *allocated_mcgs; 309 unsigned long *allocated_ahs; 310 unsigned long *allocated_arps; 311 enum init_completion_state init_state; 312 struct irdma_sc_dev sc_dev; 313 struct pci_dev *pcidev; 314 void *cdev; 315 struct irdma_hw hw; 316 struct irdma_cqp cqp; 317 struct irdma_ccq ccq; 318 struct irdma_aeq aeq; 319 struct irdma_ceq *ceqlist; 320 struct irdma_hmc_pble_rsrc *pble_rsrc; 321 struct irdma_arp_entry *arp_table; 322 spinlock_t arp_lock; /*protect ARP table access*/ 323 spinlock_t rsrc_lock; /* protect HW resource array access */ 324 spinlock_t qptable_lock; /*protect QP table access*/ 325 spinlock_t cqtable_lock; /*protect CQ table access*/ 326 struct irdma_qp **qp_table; 327 struct irdma_cq **cq_table; 328 spinlock_t qh_list_lock; /* protect mc_qht_list */ 329 struct mc_table_list mc_qht_list; 330 struct irdma_msix_vector *iw_msixtbl; 331 struct irdma_qvlist_info *iw_qvlist; 332 struct tasklet_struct dpc_tasklet; 333 struct msix_entry *msix_entries; 334 struct irdma_dma_mem obj_mem; 335 struct irdma_dma_mem obj_next; 336 atomic_t vchnl_msgs; 337 wait_queue_head_t vchnl_waitq; 338 struct workqueue_struct *cqp_cmpl_wq; 339 struct work_struct cqp_cmpl_work; 340 struct workqueue_struct *vchnl_wq; 341 struct irdma_sc_vsi default_vsi; 342 void *back_fcn; 343 struct irdma_gen_ops gen_ops; 344 struct irdma_device *iwdev; 345 DECLARE_HASHTABLE(ah_hash_tbl, 8); 346 struct mutex ah_tbl_lock; /* protect AH hash table access */ 347 }; 348 349 struct irdma_device { 350 struct ib_device ibdev; 351 struct irdma_pci_f *rf; 352 struct net_device *netdev; 353 struct workqueue_struct *cleanup_wq; 354 struct irdma_sc_vsi vsi; 355 struct irdma_cm_core cm_core; 356 u32 roce_cwnd; 357 u32 roce_ackcreds; 358 u32 vendor_id; 359 u32 vendor_part_id; 360 u32 push_mode; 361 u32 rcv_wnd; 362 u16 mac_ip_table_idx; 363 u16 vsi_num; 364 u16 vport_id; 365 u8 rcv_wscale; 366 u8 iw_status; 367 bool roce_mode:1; 368 bool roce_dcqcn_en:1; 369 bool dcb_vlan_mode:1; 370 bool iw_ooo:1; 371 bool is_vport:1; 372 enum init_completion_state init_state; 373 374 wait_queue_head_t suspend_wq; 375 }; 376 377 static inline struct irdma_device *to_iwdev(struct ib_device *ibdev) 378 { 379 return container_of(ibdev, struct irdma_device, ibdev); 380 } 381 382 static inline struct irdma_ucontext *to_ucontext(struct ib_ucontext *ibucontext) 383 { 384 return container_of(ibucontext, struct irdma_ucontext, ibucontext); 385 } 386 387 static inline struct irdma_user_mmap_entry * 388 to_irdma_mmap_entry(struct rdma_user_mmap_entry *rdma_entry) 389 { 390 return container_of(rdma_entry, struct irdma_user_mmap_entry, 391 rdma_entry); 392 } 393 394 static inline struct irdma_pd *to_iwpd(struct ib_pd *ibpd) 395 { 396 return container_of(ibpd, struct irdma_pd, ibpd); 397 } 398 399 static inline struct irdma_ah *to_iwah(struct ib_ah *ibah) 400 { 401 return container_of(ibah, struct irdma_ah, ibah); 402 } 403 404 static inline struct irdma_mr *to_iwmr(struct ib_mr *ibmr) 405 { 406 return container_of(ibmr, struct irdma_mr, ibmr); 407 } 408 409 static inline struct irdma_mr *to_iwmw(struct ib_mw *ibmw) 410 { 411 return container_of(ibmw, struct irdma_mr, ibmw); 412 } 413 414 static inline struct irdma_cq *to_iwcq(struct ib_cq *ibcq) 415 { 416 return container_of(ibcq, struct irdma_cq, ibcq); 417 } 418 419 static inline struct irdma_qp *to_iwqp(struct ib_qp *ibqp) 420 { 421 return container_of(ibqp, struct irdma_qp, ibqp); 422 } 423 424 static inline struct irdma_pci_f *dev_to_rf(struct irdma_sc_dev *dev) 425 { 426 return container_of(dev, struct irdma_pci_f, sc_dev); 427 } 428 429 static inline struct irdma_srq *to_iwsrq(struct ib_srq *ibsrq) 430 { 431 return container_of(ibsrq, struct irdma_srq, ibsrq); 432 } 433 434 /** 435 * irdma_alloc_resource - allocate a resource 436 * @iwdev: device pointer 437 * @resource_array: resource bit array: 438 * @max_resources: maximum resource number 439 * @req_resources_num: Allocated resource number 440 * @next: next free id 441 **/ 442 static inline int irdma_alloc_rsrc(struct irdma_pci_f *rf, 443 unsigned long *rsrc_array, u32 max_rsrc, 444 u32 *req_rsrc_num, u32 *next) 445 { 446 u32 rsrc_num; 447 unsigned long flags; 448 449 spin_lock_irqsave(&rf->rsrc_lock, flags); 450 rsrc_num = find_next_zero_bit(rsrc_array, max_rsrc, *next); 451 if (rsrc_num >= max_rsrc) { 452 rsrc_num = find_first_zero_bit(rsrc_array, max_rsrc); 453 if (rsrc_num >= max_rsrc) { 454 spin_unlock_irqrestore(&rf->rsrc_lock, flags); 455 ibdev_dbg(&rf->iwdev->ibdev, 456 "ERR: resource [%d] allocation failed\n", 457 rsrc_num); 458 return -EOVERFLOW; 459 } 460 } 461 __set_bit(rsrc_num, rsrc_array); 462 *next = rsrc_num + 1; 463 if (*next == max_rsrc) 464 *next = 0; 465 *req_rsrc_num = rsrc_num; 466 spin_unlock_irqrestore(&rf->rsrc_lock, flags); 467 468 return 0; 469 } 470 471 /** 472 * irdma_free_resource - free a resource 473 * @iwdev: device pointer 474 * @resource_array: resource array for the resource_num 475 * @resource_num: resource number to free 476 **/ 477 static inline void irdma_free_rsrc(struct irdma_pci_f *rf, 478 unsigned long *rsrc_array, u32 rsrc_num) 479 { 480 unsigned long flags; 481 482 spin_lock_irqsave(&rf->rsrc_lock, flags); 483 __clear_bit(rsrc_num, rsrc_array); 484 spin_unlock_irqrestore(&rf->rsrc_lock, flags); 485 } 486 487 int irdma_ctrl_init_hw(struct irdma_pci_f *rf); 488 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf); 489 int irdma_rt_init_hw(struct irdma_device *iwdev, 490 struct irdma_l2params *l2params); 491 void irdma_rt_deinit_hw(struct irdma_device *iwdev); 492 void irdma_qp_add_ref(struct ib_qp *ibqp); 493 void irdma_qp_rem_ref(struct ib_qp *ibqp); 494 void irdma_free_lsmm_rsrc(struct irdma_qp *iwqp); 495 struct ib_qp *irdma_get_qp(struct ib_device *ibdev, int qpn); 496 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask); 497 void irdma_manage_arp_cache(struct irdma_pci_f *rf, 498 const unsigned char *mac_addr, 499 u32 *ip_addr, bool ipv4, u32 action); 500 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port); 501 void irdma_del_apbvt(struct irdma_device *iwdev, 502 struct irdma_apbvt_entry *entry); 503 struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp, 504 bool wait); 505 void irdma_free_cqp_request(struct irdma_cqp *cqp, 506 struct irdma_cqp_request *cqp_request); 507 void irdma_put_cqp_request(struct irdma_cqp *cqp, 508 struct irdma_cqp_request *cqp_request); 509 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx); 510 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx); 511 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx); 512 513 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf); 514 void irdma_port_ibevent(struct irdma_device *iwdev); 515 void irdma_cm_disconn(struct irdma_qp *qp); 516 517 bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd, 518 u16 maj_err_code, u16 min_err_code); 519 int irdma_handle_cqp_op(struct irdma_pci_f *rf, 520 struct irdma_cqp_request *cqp_request); 521 522 int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 523 struct ib_udata *udata); 524 int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr, 525 int attr_mask, struct ib_udata *udata); 526 void irdma_cq_add_ref(struct ib_cq *ibcq); 527 void irdma_cq_rem_ref(struct ib_cq *ibcq); 528 void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq); 529 void irdma_srq_event(struct irdma_sc_srq *srq); 530 void irdma_srq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_srq *srq); 531 void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf); 532 int irdma_get_timeout_threshold(struct irdma_sc_dev *dev); 533 int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp, 534 struct irdma_modify_qp_info *info, bool wait); 535 int irdma_qp_suspend_resume(struct irdma_sc_qp *qp, bool suspend); 536 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 537 enum irdma_quad_entry_type etype, 538 enum irdma_quad_hash_manage_type mtype, void *cmnode, 539 bool wait); 540 void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf); 541 void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp); 542 void irdma_free_qp_rsrc(struct irdma_qp *iwqp); 543 int irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver); 544 void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core); 545 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 546 u8 term_len); 547 int irdma_send_syn(struct irdma_cm_node *cm_node, u32 sendack); 548 int irdma_send_reset(struct irdma_cm_node *cm_node); 549 struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core, 550 u16 rem_port, u32 *rem_addr, u16 loc_port, 551 u32 *loc_addr, u16 vlan_id); 552 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 553 struct irdma_qp_flush_info *info, bool wait); 554 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 555 struct irdma_gen_ae_info *info, bool wait); 556 void irdma_copy_ip_ntohl(u32 *dst, __be32 *src); 557 void irdma_copy_ip_htonl(__be32 *dst, u32 *src); 558 u16 irdma_get_vlan_ipv4(u32 *addr); 559 void irdma_get_vlan_mac_ipv6(u32 *addr, u16 *vlan_id, u8 *mac); 560 struct ib_mr *irdma_reg_phys_mr(struct ib_pd *ib_pd, u64 addr, u64 size, 561 int acc, u64 *iova_start, bool dma_mr); 562 int irdma_upload_qp_context(struct irdma_qp *iwqp, bool freeze, bool raw); 563 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq); 564 int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd, 565 bool wait, 566 void (*callback_fcn)(struct irdma_cqp_request *cqp_request), 567 void *cb_param); 568 void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request); 569 int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event, 570 void *ptr); 571 int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event, 572 void *ptr); 573 int irdma_net_event(struct notifier_block *notifier, unsigned long event, 574 void *ptr); 575 int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event, 576 void *ptr); 577 void irdma_add_ip(struct irdma_device *iwdev); 578 void cqp_compl_worker(struct work_struct *work); 579 void irdma_log_invalid_mtu(u16 mtu, struct irdma_sc_dev *dev); 580 #endif /* IRDMA_MAIN_H */ 581