1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 enum iwl_rx_mpdu_mac_phy_band { 197 /* whether or not this is MAC or LINK depends on the API */ 198 IWL_RX_MPDU_MAC_PHY_BAND_MAC_MASK = 0x0f, 199 IWL_RX_MPDU_MAC_PHY_BAND_LINK_MASK = 0x0f, 200 IWL_RX_MPDU_MAC_PHY_BAND_PHY_MASK = 0x30, 201 IWL_RX_MPDU_MAC_PHY_BAND_BAND_MASK = 0xc0, 202 }; 203 204 enum iwl_rx_l3_proto_values { 205 IWL_RX_L3_TYPE_NONE, 206 IWL_RX_L3_TYPE_IPV4, 207 IWL_RX_L3_TYPE_IPV4_FRAG, 208 IWL_RX_L3_TYPE_IPV6_FRAG, 209 IWL_RX_L3_TYPE_IPV6, 210 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 211 IWL_RX_L3_TYPE_ARP, 212 IWL_RX_L3_TYPE_EAPOL, 213 }; 214 215 #define IWL_RX_L3_PROTO_POS 4 216 217 enum iwl_rx_l3l4_flags { 218 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 219 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 220 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 221 IWL_RX_L3L4_TCP_ACK = BIT(3), 222 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 223 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 224 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 225 }; 226 227 enum iwl_rx_mpdu_status { 228 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 229 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 230 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 231 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 232 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 233 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 234 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 235 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 236 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 237 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 238 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 239 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 240 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 241 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 242 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 243 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 244 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 245 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 246 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 247 248 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 249 250 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 251 }; 252 253 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 254 255 enum iwl_rx_mpdu_reorder_data { 256 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 257 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 258 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 259 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 260 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 261 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 262 }; 263 264 enum iwl_rx_mpdu_phy_info { 265 IWL_RX_MPDU_PHY_EOF_INDICATION = BIT(0), 266 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 267 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 268 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 269 /* short preamble is only for CCK, for non-CCK overridden by this */ 270 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 271 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 272 }; 273 274 enum iwl_rx_mpdu_mac_info { 275 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 276 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 277 }; 278 279 /* TSF overload low dword */ 280 enum iwl_rx_phy_he_data0 { 281 /* info type: HE any */ 282 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 283 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 284 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 285 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 286 /* 1 bit reserved */ 287 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 288 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 289 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 290 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 291 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 292 /* 6 bits reserved */ 293 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 294 }; 295 296 /* TSF overload low dword */ 297 enum iwl_rx_phy_eht_data0 { 298 /* info type: EHT any */ 299 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 300 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 301 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 302 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 303 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 304 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 305 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 306 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 307 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 308 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 309 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 310 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 311 /* 2 bits reserved */ 312 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 313 }; 314 315 enum iwl_rx_phy_info_type { 316 IWL_RX_PHY_INFO_TYPE_NONE = 0, 317 IWL_RX_PHY_INFO_TYPE_CCK = 1, 318 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 319 IWL_RX_PHY_INFO_TYPE_HT = 3, 320 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 321 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 322 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 323 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 324 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 325 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 326 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 327 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 328 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 329 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 330 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 331 }; 332 333 /* TSF overload high dword */ 334 enum iwl_rx_phy_common_data1 { 335 /* 336 * check this first - if TSF overload is set, 337 * see &enum iwl_rx_phy_info_type 338 */ 339 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 340 341 /* info type: HT/VHT/HE/EHT any */ 342 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 343 }; 344 345 /* TSF overload high dword For HE rates*/ 346 enum iwl_rx_phy_he_data1 { 347 /* info type: HE MU/MU-EXT */ 348 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 349 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 350 351 /* info type: HE any */ 352 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 353 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 354 /* trigger encoded */ 355 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 356 357 /* info type: HE TB/TX-EXT */ 358 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 359 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 360 }; 361 362 /* TSF overload high dword For EHT-MU/TB rates*/ 363 enum iwl_rx_phy_eht_data1 { 364 /* info type: EHT-MU */ 365 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 366 /* info type: EHT-TB */ 367 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 368 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 369 370 /* info type: EHT any */ 371 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 372 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 373 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 374 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 375 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 376 }; 377 378 /* goes into Metadata DW 7 (Qu) or 8 (So or higher) */ 379 enum iwl_rx_phy_he_data2 { 380 /* info type: HE MU-EXT */ 381 /* the a1/a2/... is what the PHY/firmware calls the values */ 382 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 383 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 384 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 385 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 386 387 /* info type: HE TB-EXT */ 388 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 389 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 390 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 391 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 392 }; 393 394 /* goes into Metadata DW 8 (Qu) or 7 (So or higher) */ 395 enum iwl_rx_phy_he_data3 { 396 /* info type: HE MU-EXT */ 397 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 398 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 399 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 400 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 401 }; 402 403 /* goes into Metadata DW 4 high 16 bits */ 404 enum iwl_rx_phy_he_he_data4 { 405 /* info type: HE MU-EXT */ 406 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 407 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 408 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 409 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 410 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 411 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 412 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 413 }; 414 415 /* goes into Metadata DW 8 (Qu has no EHT) */ 416 enum iwl_rx_phy_eht_data2 { 417 /* info type: EHT-MU-EXT */ 418 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 419 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 420 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 421 422 /* info type: EHT-TB-EXT */ 423 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 424 }; 425 426 /* goes into Metadata DW 7 (Qu has no EHT) */ 427 enum iwl_rx_phy_eht_data3 { 428 /* note: low 8 bits cannot be used */ 429 /* info type: EHT-MU-EXT */ 430 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 431 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 432 }; 433 434 /* goes into Metadata DW 4 */ 435 enum iwl_rx_phy_eht_data4 { 436 /* info type: EHT-MU-EXT */ 437 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 438 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 439 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 440 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000, 441 }; 442 443 /* goes into Metadata DW 16 */ 444 enum iwl_rx_phy_data5 { 445 /* info type: EHT any */ 446 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 447 /* info type: EHT-TB */ 448 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 449 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 450 /* info type: EHT-MU */ 451 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 452 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 453 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 454 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 455 }; 456 457 /** 458 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 459 */ 460 struct iwl_rx_mpdu_desc_v1 { 461 /* DW7 - carries rss_hash only when rpa_en == 1 */ 462 union { 463 /** 464 * @rss_hash: RSS hash value 465 */ 466 __le32 rss_hash; 467 468 /** 469 * @phy_data2: depends on info type (see @phy_data1) 470 */ 471 __le32 phy_data2; 472 }; 473 474 /* DW8 - carries filter_match only when rpa_en == 1 */ 475 union { 476 /** 477 * @filter_match: filter match value 478 */ 479 __le32 filter_match; 480 481 /** 482 * @phy_data3: depends on info type (see @phy_data1) 483 */ 484 __le32 phy_data3; 485 }; 486 487 /* DW9 */ 488 /** 489 * @rate_n_flags: RX rate/flags encoding 490 */ 491 __le32 rate_n_flags; 492 /* DW10 */ 493 /** 494 * @energy_a: energy chain A 495 */ 496 u8 energy_a; 497 /** 498 * @energy_b: energy chain B 499 */ 500 u8 energy_b; 501 /** 502 * @channel: channel number 503 */ 504 u8 channel; 505 /** 506 * @mac_context: MAC context mask 507 */ 508 u8 mac_context; 509 /* DW11 */ 510 /** 511 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 512 */ 513 __le32 gp2_on_air_rise; 514 /* DW12 & DW13 */ 515 union { 516 /** 517 * @tsf_on_air_rise: 518 * TSF value on air rise (INA), only valid if 519 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 520 */ 521 __le64 tsf_on_air_rise; 522 523 struct { 524 /** 525 * @phy_data0: depends on info_type, see @phy_data1 526 */ 527 __le32 phy_data0; 528 /** 529 * @phy_data1: valid only if 530 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 531 * see &enum iwl_rx_phy_common_data1 or 532 * &enum iwl_rx_phy_he_data1 or 533 * &enum iwl_rx_phy_eht_data1. 534 */ 535 __le32 phy_data1; 536 }; 537 }; 538 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 539 540 /** 541 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 542 */ 543 struct iwl_rx_mpdu_desc_v3 { 544 /* DW7 - carries filter_match only when rpa_en == 1 */ 545 union { 546 /** 547 * @filter_match: filter match value 548 */ 549 __le32 filter_match; 550 551 /** 552 * @phy_data3: depends on info type (see @phy_data1) 553 */ 554 __le32 phy_data3; 555 }; 556 557 /* DW8 - carries rss_hash only when rpa_en == 1 */ 558 union { 559 /** 560 * @rss_hash: RSS hash value 561 */ 562 __le32 rss_hash; 563 564 /** 565 * @phy_data2: depends on info type (see @phy_data1) 566 */ 567 __le32 phy_data2; 568 }; 569 /* DW9 */ 570 /** 571 * @partial_hash: 31:0 ip/tcp header hash 572 * w/o some fields (such as IP SRC addr) 573 */ 574 __le32 partial_hash; 575 /* DW10 */ 576 /** 577 * @raw_xsum: raw xsum value 578 */ 579 __be16 raw_xsum; 580 /** 581 * @reserved_xsum: reserved high bits in the raw checksum 582 */ 583 __le16 reserved_xsum; 584 /* DW11 */ 585 /** 586 * @rate_n_flags: RX rate/flags encoding 587 */ 588 __le32 rate_n_flags; 589 /* DW12 */ 590 /** 591 * @energy_a: energy chain A 592 */ 593 u8 energy_a; 594 /** 595 * @energy_b: energy chain B 596 */ 597 u8 energy_b; 598 /** 599 * @channel: channel number 600 */ 601 u8 channel; 602 /** 603 * @mac_context: MAC context mask 604 */ 605 u8 mac_context; 606 /* DW13 */ 607 /** 608 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 609 */ 610 __le32 gp2_on_air_rise; 611 /* DW14 & DW15 */ 612 union { 613 /** 614 * @tsf_on_air_rise: 615 * TSF value on air rise (INA), only valid if 616 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 617 */ 618 __le64 tsf_on_air_rise; 619 620 struct { 621 /** 622 * @phy_data0: depends on info_type, see @phy_data1 623 */ 624 __le32 phy_data0; 625 /** 626 * @phy_data1: valid only if 627 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 628 * see &enum iwl_rx_phy_data1. 629 */ 630 __le32 phy_data1; 631 }; 632 }; 633 /* DW16 */ 634 /** 635 * @phy_data5: valid only if 636 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 637 * see &enum iwl_rx_phy_data5. 638 */ 639 __le32 phy_data5; 640 /* DW17 */ 641 /** 642 * @reserved: reserved 643 */ 644 __le32 reserved[1]; 645 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 646 * RX_MPDU_RES_START_API_S_VER_5, 647 * RX_MPDU_RES_START_API_S_VER_6 648 */ 649 650 /** 651 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 652 */ 653 struct iwl_rx_mpdu_desc { 654 /* DW2 */ 655 /** 656 * @mpdu_len: MPDU length 657 */ 658 __le16 mpdu_len; 659 /** 660 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 661 */ 662 u8 mac_flags1; 663 /** 664 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 665 */ 666 u8 mac_flags2; 667 /* DW3 */ 668 /** 669 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 670 */ 671 u8 amsdu_info; 672 /** 673 * @phy_info: &enum iwl_rx_mpdu_phy_info 674 */ 675 __le16 phy_info; 676 /** 677 * @mac_phy_band: MAC/link ID, PHY ID, band; 678 * see &enum iwl_rx_mpdu_mac_phy_band 679 */ 680 u8 mac_phy_band; 681 /* DW4 */ 682 union { 683 struct { 684 /* carries csum data only when rpa_en == 1 */ 685 /** 686 * @raw_csum: raw checksum (alledgedly unreliable) 687 */ 688 __le16 raw_csum; 689 690 union { 691 /** 692 * @l3l4_flags: &enum iwl_rx_l3l4_flags 693 */ 694 __le16 l3l4_flags; 695 696 /** 697 * @phy_data4: depends on info type, see phy_data1 698 */ 699 __le16 phy_data4; 700 }; 701 }; 702 /** 703 * @phy_eht_data4: depends on info type, see phy_data1 704 */ 705 __le32 phy_eht_data4; 706 }; 707 /* DW5 */ 708 /** 709 * @status: &enum iwl_rx_mpdu_status 710 */ 711 __le32 status; 712 713 /* DW6 */ 714 /** 715 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 716 */ 717 __le32 reorder_data; 718 719 union { 720 /** 721 * @v1: version 1 of the remaining RX descriptor, 722 * see &struct iwl_rx_mpdu_desc_v1 723 */ 724 struct iwl_rx_mpdu_desc_v1 v1; 725 /** 726 * @v3: version 3 of the remaining RX descriptor, 727 * see &struct iwl_rx_mpdu_desc_v3 728 */ 729 struct iwl_rx_mpdu_desc_v3 v3; 730 }; 731 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 732 * RX_MPDU_RES_START_API_S_VER_4, 733 * RX_MPDU_RES_START_API_S_VER_5, 734 * RX_MPDU_RES_START_API_S_VER_6 735 */ 736 737 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 738 739 #define RX_NO_DATA_CHAIN_A_POS 0 740 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 741 #define RX_NO_DATA_CHAIN_B_POS 8 742 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 743 #define RX_NO_DATA_CHANNEL_POS 16 744 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 745 746 #define RX_NO_DATA_INFO_TYPE_POS 0 747 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 748 #define RX_NO_DATA_INFO_TYPE_NONE 0 749 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 750 #define RX_NO_DATA_INFO_TYPE_NDP 2 751 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 752 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 753 754 #define RX_NO_DATA_INFO_ERR_POS 8 755 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 756 #define RX_NO_DATA_INFO_ERR_NONE 0 757 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 758 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 759 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 760 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 761 #define RX_NO_DATA_INFO_LOW_ENERGY 5 762 763 #define RX_NO_DATA_FRAME_TIME_POS 0 764 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 765 766 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 767 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 768 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 769 770 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 771 enum iwl_rx_usig_a1 { 772 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 773 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 774 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 775 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 776 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 777 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 778 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 779 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 780 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 781 IWL_RX_USIG_A1_RDY = 0x80000000, 782 }; 783 784 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 785 enum iwl_rx_usig_a2_eht { 786 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 787 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 788 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 789 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 790 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 791 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 792 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 793 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 794 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 795 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 796 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 797 }; 798 799 /** 800 * struct iwl_rx_no_data - RX no data descriptor 801 * @info: 7:0 frame type, 15:8 RX error type 802 * @rssi: 7:0 energy chain-A, 803 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 804 * @on_air_rise_time: GP2 during on air rise 805 * @fr_time: frame time 806 * @rate: rate/mcs of frame 807 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 808 * based on &enum iwl_rx_phy_info_type 809 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 810 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 811 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 812 */ 813 struct iwl_rx_no_data { 814 __le32 info; 815 __le32 rssi; 816 __le32 on_air_rise_time; 817 __le32 fr_time; 818 __le32 rate; 819 __le32 phy_info[2]; 820 __le32 rx_vec[2]; 821 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 822 RX_NO_DATA_NTFY_API_S_VER_2 */ 823 824 /** 825 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 826 * @info: 7:0 frame type, 15:8 RX error type 827 * @rssi: 7:0 energy chain-A, 828 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 829 * @on_air_rise_time: GP2 during on air rise 830 * @fr_time: frame time 831 * @rate: rate/mcs of frame, format depends on the notification version 832 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 833 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 834 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 835 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 836 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 837 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 838 */ 839 struct iwl_rx_no_data_ver_3 { 840 __le32 info; 841 __le32 rssi; 842 __le32 on_air_rise_time; 843 __le32 fr_time; 844 __le32 rate; 845 __le32 phy_info[2]; 846 __le32 rx_vec[4]; 847 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_3, _VER_4 */ 848 849 struct iwl_frame_release { 850 u8 baid; 851 u8 reserved; 852 __le16 nssn; 853 }; 854 855 /** 856 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 857 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 858 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 859 */ 860 enum iwl_bar_frame_release_sta_tid { 861 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 862 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 863 }; 864 865 /** 866 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 867 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 868 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 869 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 870 */ 871 enum iwl_bar_frame_release_ba_info { 872 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 873 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 874 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 875 }; 876 877 /** 878 * struct iwl_bar_frame_release - frame release from BAR info 879 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 880 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 881 */ 882 struct iwl_bar_frame_release { 883 __le32 sta_tid; 884 __le32 ba_info; 885 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 886 887 enum iwl_rss_hash_func_en { 888 IWL_RSS_HASH_TYPE_IPV4_TCP, 889 IWL_RSS_HASH_TYPE_IPV4_UDP, 890 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 891 IWL_RSS_HASH_TYPE_IPV6_TCP, 892 IWL_RSS_HASH_TYPE_IPV6_UDP, 893 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 894 }; 895 896 #define IWL_RSS_HASH_KEY_CNT 10 897 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 898 #define IWL_RSS_ENABLE 1 899 900 /** 901 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 902 * 903 * @flags: 1 - enable, 0 - disable 904 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 905 * @reserved: reserved 906 * @secret_key: 320 bit input of random key configuration from driver 907 * @indirection_table: indirection table 908 */ 909 struct iwl_rss_config_cmd { 910 __le32 flags; 911 u8 hash_mask; 912 u8 reserved[3]; 913 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 914 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 915 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 916 917 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 918 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 919 920 /** 921 * struct iwl_rxq_sync_cmd - RXQ notification trigger 922 * 923 * @flags: flags of the notification. bit 0:3 are the sender queue 924 * @rxq_mask: rx queues to send the notification on 925 * @count: number of bytes in payload, should be DWORD aligned 926 * @payload: data to send to rx queues 927 */ 928 struct iwl_rxq_sync_cmd { 929 __le32 flags; 930 __le32 rxq_mask; 931 __le32 count; 932 u8 payload[]; 933 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 934 935 /** 936 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 937 * sync command 938 * 939 * @count: number of bytes in payload 940 * @payload: data to send to rx queues 941 */ 942 struct iwl_rxq_sync_notification { 943 __le32 count; 944 u8 payload[]; 945 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 946 947 /** 948 * enum iwl_mvm_pm_event - type of station PM event 949 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 950 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 951 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 952 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 953 */ 954 enum iwl_mvm_pm_event { 955 IWL_MVM_PM_EVENT_AWAKE, 956 IWL_MVM_PM_EVENT_ASLEEP, 957 IWL_MVM_PM_EVENT_UAPSD, 958 IWL_MVM_PM_EVENT_PS_POLL, 959 }; /* PEER_PM_NTFY_API_E_VER_1 */ 960 961 /** 962 * struct iwl_mvm_pm_state_notification - station PM state notification 963 * @sta_id: station ID of the station changing state 964 * @type: the new powersave state, see &enum iwl_mvm_pm_event 965 */ 966 struct iwl_mvm_pm_state_notification { 967 u8 sta_id; 968 u8 type; 969 /* private: */ 970 __le16 reserved; 971 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 972 973 #define BA_WINDOW_STREAMS_MAX 16 974 #define BA_WINDOW_STATUS_TID_MSK 0x000F 975 #define BA_WINDOW_STATUS_STA_ID_POS 4 976 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 977 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 978 979 /** 980 * struct iwl_ba_window_status_notif - reordering window's status notification 981 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 982 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 983 * @start_seq_num: the start sequence number of the bitmap 984 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 985 */ 986 struct iwl_ba_window_status_notif { 987 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 988 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 989 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 990 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 991 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 992 993 /** 994 * struct iwl_rfh_queue_data - RX queue configuration 995 * @q_num: Q num 996 * @enable: enable queue 997 * @reserved: alignment 998 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 999 * @fr_bd_cb: DMA address of freeRB table 1000 * @ur_bd_cb: DMA address of used RB table 1001 * @fr_bd_wid: Initial index of the free table 1002 */ 1003 struct iwl_rfh_queue_data { 1004 u8 q_num; 1005 u8 enable; 1006 __le16 reserved; 1007 __le64 urbd_stts_wrptr; 1008 __le64 fr_bd_cb; 1009 __le64 ur_bd_cb; 1010 __le32 fr_bd_wid; 1011 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 1012 1013 /** 1014 * struct iwl_rfh_queue_config - RX queue configuration 1015 * @num_queues: number of queues configured 1016 * @reserved: alignment 1017 * @data: DMA addresses per-queue 1018 */ 1019 struct iwl_rfh_queue_config { 1020 u8 num_queues; 1021 u8 reserved[3]; 1022 struct iwl_rfh_queue_data data[]; 1023 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1024 1025 /** 1026 * struct iwl_beacon_filter_notif_v1 - beacon filter notification 1027 * @average_energy: average energy for the received beacon 1028 * @mac_id: MAC ID the beacon was received for 1029 */ 1030 struct iwl_beacon_filter_notif_v1 { 1031 __le32 average_energy; 1032 __le32 mac_id; 1033 } __packed; /* BEACON_FILTER_IN_NTFY_API_S_VER_1 */ 1034 1035 /** 1036 * struct iwl_beacon_filter_notif - beacon filter notification 1037 * @average_energy: average energy for the received beacon 1038 * @link_id: link ID the beacon was received for 1039 */ 1040 struct iwl_beacon_filter_notif { 1041 __le32 average_energy; 1042 __le32 link_id; 1043 } __packed; /* BEACON_FILTER_IN_NTFY_API_S_VER_2 */ 1044 1045 union iwl_legacy_sig { 1046 #define OFDM_RX_LEGACY_LENGTH 0x00000fff 1047 #define OFDM_RX_RATE 0x0000f000 1048 __le32 ofdm; 1049 #define CCK_CRFR_SHORT_PREAMBLE 0x00000040 1050 __le32 cck; 1051 }; 1052 1053 struct iwl_ht_sigs { 1054 #define OFDM_RX_FRAME_HT_MCS 0x0000007f 1055 #define OFDM_RX_FRAME_HT_BANDWIDTH 0x00000080 1056 #define OFDM_RX_FRAME_HT_LENGTH 0x03ffff00 1057 __le32 a1; 1058 __le32 a2; 1059 }; 1060 1061 struct iwl_vht_sigs { 1062 #define OFDM_RX_FRAME_VHT_NUM_OF_DATA_SYM 0x000007ff 1063 #define OFDM_RX_FRAME_VHT_NUM_OF_DATA_SYM_VALID 0x80000000 1064 __le32 a0; 1065 __le32 a1, a2; 1066 }; 1067 1068 struct iwl_he_sigs { 1069 #define OFDM_RX_FRAME_HE_BEAM_CHANGE 0x00000001 1070 #define OFDM_RX_FRAME_HE_UL_FLAG 0x00000002 1071 #define OFDM_RX_FRAME_HE_MCS 0x0000003c 1072 #define OFDM_RX_FRAME_HE_DCM 0x00000040 1073 #define OFDM_RX_FRAME_HE_BSS_COLOR 0x00001f80 1074 #define OFDM_RX_FRAME_HE_SPATIAL_REUSE 0x0001e000 1075 #define OFDM_RX_FRAME_HE_BANDWIDTH 0x00060000 1076 #define OFDM_RX_FRAME_HE_SU_EXT_BW10 0x00080000 1077 #define OFDM_RX_FRAME_HE_GI_LTF_TYPE 0x00700000 1078 #define OFDM_RX_FRAME_HE_NSTS 0x03800000 1079 #define OFDM_RX_FRAME_HE_PRMBL_PUNC_TYPE 0x0c000000 1080 __le32 a1; 1081 #define OFDM_RX_FRAME_HE_TXOP_DURATION 0x0000007f 1082 #define OFDM_RX_FRAME_HE_CODING 0x00000080 1083 #define OFDM_RX_FRAME_HE_CODING_EXTRA_SYM 0x00000100 1084 #define OFDM_RX_FRAME_HE_STBC 0x00000200 1085 #define OFDM_RX_FRAME_HE_BF 0x00000400 1086 #define OFDM_RX_FRAME_HE_PRE_FEC_PAD_FACTOR 0x00001800 1087 #define OFDM_RX_FRAME_HE_PE_DISAMBIG 0x00002000 1088 #define OFDM_RX_FRAME_HE_DOPPLER 0x00004000 1089 #define OFDM_RX_FRAME_HE_TYPE 0x00038000 1090 #define OFDM_RX_FRAME_HE_MU_NUM_OF_SIGB_SYM_OR_USER_NUM 0x003c0000 1091 #define OFDM_RX_FRAME_HE_MU_SIGB_COMP 0x00400000 1092 #define OFDM_RX_FRAME_HE_MU_NUM_OF_LTF_SYM 0x03800000 1093 __le32 a2; 1094 #define OFDM_RX_FRAME_HE_NUM_OF_DATA_SYM 0x000007ff 1095 #define OFDM_RX_FRAME_HE_PE_DURATION 0x00003800 1096 #define OFDM_RX_FRAME_HE_NUM_OF_DATA_SYM_VALID 0x80000000 1097 __le32 a3; 1098 #define OFDM_RX_FRAME_HE_SIGB_STA_ID_FOUND 0x00000001 1099 #define OFDM_RX_FRAME_HE_SIGB_STA_ID_INDX 0x0000000e 1100 #define OFDM_RX_FRAME_HE_SIGB_NSTS 0x00000070 1101 #define OFDM_RX_FRAME_HE_SIGB_BF 0x00000080 1102 #define OFDM_RX_FRAME_HE_SIGB_MCS 0x00000f00 1103 #define OFDM_RX_FRAME_HE_SIGB_DCM 0x00001000 1104 #define OFDM_RX_FRAME_HE_SIGB_CODING 0x00002000 1105 #define OFDM_RX_FRAME_HE_SIGB_SPATIAL_CONFIG 0x0003c000 1106 #define OFDM_RX_FRAME_HE_SIGB_STA_RU 0x03fc0000 1107 #define OFDM_RX_FRAME_HE_SIGB_NUM_OF_SYM 0x3c000000 1108 #define OFDM_RX_FRAME_HE_SIGB_CRC_OK 0x40000000 1109 __le32 b; 1110 /* index 0 */ 1111 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_A1 0x000000ff 1112 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_A2 0x0000ff00 1113 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_B1 0x00ff0000 1114 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_B2 0xff000000 1115 /* index 1 */ 1116 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_C1 0x000000ff 1117 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_C2 0x0000ff00 1118 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_D1 0x00ff0000 1119 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_D2 0xff000000 1120 /* index 2 */ 1121 #define OFDM_RX_FRAME_HE_CENTER_RU_CC1 0x00000001 1122 #define OFDM_RX_FRAME_HE_CENTER_RU_CC2 0x00000002 1123 #define OFDM_RX_FRAME_HE_COMMON_CC1_CRC_OK 0x00000004 1124 #define OFDM_RX_FRAME_HE_COMMON_CC2_CRC_OK 0x00000008 1125 __le32 cmn[3]; 1126 }; 1127 1128 struct iwl_he_tb_sigs { 1129 #define OFDM_RX_HE_TRIG_FORMAT 0x00000001 1130 #define OFDM_RX_HE_TRIG_BSS_COLOR 0x0000007e 1131 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_1 0x00000780 1132 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_2 0x00007800 1133 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_3 0x00078000 1134 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_4 0x00780000 1135 #define OFDM_RX_HE_TRIG_BANDWIDTH 0x03000000 1136 __le32 a1; 1137 #define OFDM_RX_HE_TRIG_TXOP_DURATION 0x0000007f 1138 #define OFDM_RX_HE_TRIG_SIG2_RESERVED 0x0000ff80 1139 #define OFDM_RX_HE_TRIG_FORMAT_ERR 0x08000000 1140 #define OFDM_RX_HE_TRIG_BW_ERR 0x10000000 1141 #define OFDM_RX_HE_TRIG_LEGACY_LENGTH_ERR 0x20000000 1142 #define OFDM_RX_HE_TRIG_CRC_OK 0x40000000 1143 __le32 a2; 1144 #define OFDM_UCODE_TRIG_BASE_RX_LGCY_LENGTH 0x00000fff 1145 #define OFDM_UCODE_TRIG_BASE_RX_BANDWIDTH 0x00007000 1146 #define OFDM_UCODE_TRIG_BASE_PS160 0x00008000 1147 #define OFDM_UCODE_EHT_TRIG_CONTROL_CHANNEL 0x000f0000 1148 __le32 tb_rx0; 1149 #define OFDM_UCODE_TRIG_BASE_RX_MCS 0x0000000f 1150 #define OFDM_UCODE_TRIG_BASE_RX_DCM 0x00000010 1151 #define OFDM_UCODE_TRIG_BASE_RX_GI_LTF_TYPE 0x00000060 1152 #define OFDM_UCODE_TRIG_BASE_RX_NSTS 0x00000380 1153 #define OFDM_UCODE_TRIG_BASE_RX_CODING 0x00000400 1154 #define OFDM_UCODE_TRIG_BASE_RX_CODING_EXTRA_SYM 0x00000800 1155 #define OFDM_UCODE_TRIG_BASE_RX_STBC 0x00001000 1156 #define OFDM_UCODE_TRIG_BASE_RX_PRE_FEC_PAD_FACTOR 0x00006000 1157 #define OFDM_UCODE_TRIG_BASE_RX_PE_DISAMBIG 0x00008000 1158 #define OFDM_UCODE_TRIG_BASE_RX_DOPPLER 0x00010000 1159 #define OFDM_UCODE_TRIG_BASE_RX_RU 0x01fe0000 1160 #define OFDM_UCODE_TRIG_BASE_RX_RU_P80 0x00020000 1161 #define OFDM_UCODE_TRIG_BASE_RX_NUM_OF_LTF_SYM 0x0e000000 1162 #define OFDM_UCODE_TRIG_BASE_RX_LTF_PILOT_TYPE 0x10000000 1163 #define OFDM_UCODE_TRIG_BASE_RX_LOWEST_SS_ALLOCATION 0xe0000000 1164 __le32 tb_rx1; 1165 }; 1166 1167 struct iwl_eht_sigs { 1168 #define OFDM_RX_FRAME_ENHANCED_WIFI_VER_ID 0x00000007 1169 #define OFDM_RX_FRAME_ENHANCED_WIFI_BANDWIDTH 0x00000038 1170 #define OFDM_RX_FRAME_ENHANCED_WIFI_UL_FLAG 0x00000040 1171 #define OFDM_RX_FRAME_ENHANCED_WIFI_BSS_COLOR 0x00001f80 1172 #define OFDM_RX_FRAME_ENHANCED_WIFI_TXOP_DURATION 0x000fe000 1173 #define OFDM_RX_FRAME_EHT_USIG1_DISREGARD 0x01f00000 1174 #define OFDM_RX_FRAME_EHT_USIG1_VALIDATE 0x02000000 1175 #define OFDM_RX_FRAME_EHT_BW320_SLOT 0x04000000 1176 #define OFDM_RX_FRAME_EHT_TYPE 0x18000000 1177 #define OFDM_RX_FRAME_ENHANCED_ER_NO_STREAMS 0x20000000 1178 __le32 usig_a1; 1179 #define OFDM_RX_FRAME_EHT_PPDU_TYPE 0x00000003 1180 #define OFDM_RX_FRAME_EHT_USIG2_VALIDATE_B2 0x00000004 1181 #define OFDM_RX_FRAME_EHT_PUNC_CHANNEL 0x000000f8 1182 #define OFDM_RX_FRAME_EHT_USIG2_VALIDATE_B8 0x00000100 1183 #define OFDM_RX_FRAME_EHT_SIG_MCS 0x00000600 1184 #define OFDM_RX_FRAME_EHT_SIG_SYM_NUM 0x0000f800 1185 #define OFDM_RX_FRAME_EHT_TRIG_SPATIAL_REUSE_1 0x000f0000 1186 #define OFDM_RX_FRAME_EHT_TRIG_SPATIAL_REUSE_2 0x00f00000 1187 #define OFDM_RX_FRAME_EHT_TRIG_USIG2_DISREGARD 0x1f000000 1188 #define OFDM_RX_FRAME_EHT_TRIG_NO_STREAMS 0x20000000 1189 #define OFDM_RX_USIG_CRC_OK 0x40000000 1190 __le32 usig_a2_eht; 1191 #define OFDM_RX_FRAME_EHT_SPATIAL_REUSE 0x0000000f 1192 #define OFDM_RX_FRAME_EHT_GI_LTF_TYPE 0x00000030 1193 #define OFDM_RX_FRAME_EHT_NUM_OF_LTF_SYM 0x000001c0 1194 #define OFDM_RX_FRAME_EHT_CODING_EXTRA_SYM 0x00000200 1195 #define OFDM_RX_FRAME_EHT_PRE_FEC_PAD_FACTOR 0x00000c00 1196 #define OFDM_RX_FRAME_EHT_PE_DISAMBIG 0x00001000 1197 #define OFDM_RX_FRAME_EHT_USIG_OVF_DISREGARD 0x0001e000 1198 #define OFDM_RX_FRAME_EHT_NUM_OF_USERS 0x000e0000 1199 #define OFDM_RX_FRAME_EHT_NSTS 0x00f00000 1200 #define OFDM_RX_FRAME_EHT_BF 0x01000000 1201 #define OFDM_RX_FRAME_EHT_USIG_OVF_NDP_DISREGARD 0x06000000 1202 #define OFDM_RX_FRAME_EHTSIG_COMM_CC1_CRC_OK 0x08000000 1203 #define OFDM_RX_FRAME_EHTSIG_COMM_CC2_CRC_OK 0x10000000 1204 #define OFDM_RX_FRAME_EHT_NON_VALID_RU_ALLOC 0x20000000 1205 #define OFDM_RX_FRAME_EHT_NO_STREAMS 0x40000000 1206 __le32 b1; 1207 #define OFDM_RX_FRAME_EHT_MATCH_ID_FOUND 0x00000001 1208 #define OFDM_RX_FRAME_EHT_ID_INDX 0x0000000e 1209 #define OFDM_RX_FRAME_EHT_MCS 0x000000f0 1210 #define OFDM_RX_FRAME_EHT_CODING 0x00000100 1211 #define OFDM_RX_FRAME_EHT_SPATIAL_CONFIG 0x00007e00 1212 #define OFDM_RX_FRAME_EHT_STA_RU 0x007f8000 1213 #define OFDM_RX_FRAME_EHT_STA_RU_P80 0x00008000 1214 #define OFDM_RX_FRAME_EHT_STA_RU_PS160 0x00800000 1215 #define OFDM_RX_FRAME_EHT_USER_FIELD_CRC_OK 0x40000000 1216 __le32 b2; 1217 #define OFDM_RX_FRAME_EHT_NUM_OF_DATA_SYM 0x000007ff 1218 #define OFDM_RX_FRAME_EHT_PE_DURATION 0x00003800 1219 #define OFDM_RX_FRAME_EHT_NUM_OF_DATA_SYM_VALID 0x80000000 1220 __le32 sig2; 1221 #define OFDM_RX_FRAME_EHT_RU_ALLOC_0_A1 0x000001ff 1222 #define OFDM_RX_FRAME_EHT_RU_ALLOC_0_A2 0x0003fe00 1223 #define OFDM_RX_FRAME_EHT_RU_ALLOC_0_A3 0x07fc0000 1224 #define OFDM_RX_FRAME_EHT_RU_ALLOC_1_B1 0x000001ff 1225 #define OFDM_RX_FRAME_EHT_RU_ALLOC_1_B2 0x0003fe00 1226 #define OFDM_RX_FRAME_EHT_RU_ALLOC_1_B3 0x07fc0000 1227 #define OFDM_RX_FRAME_EHT_RU_ALLOC_2_C1 0x000001ff 1228 #define OFDM_RX_FRAME_EHT_RU_ALLOC_2_C2 0x0003fe00 1229 #define OFDM_RX_FRAME_EHT_RU_ALLOC_2_C3 0x07fc0000 1230 #define OFDM_RX_FRAME_EHT_RU_ALLOC_3_D1 0x000001ff 1231 #define OFDM_RX_FRAME_EHT_RU_ALLOC_3_D2 0x0003fe00 1232 #define OFDM_RX_FRAME_EHT_RU_ALLOC_3_D3 0x07fc0000 1233 #define OFDM_RX_FRAME_EHT_RU_ALLOC_4_A4 0x000001ff 1234 #define OFDM_RX_FRAME_EHT_RU_ALLOC_4_B4 0x0003fe00 1235 #define OFDM_RX_FRAME_EHT_RU_ALLOC_5_C4 0x000001ff 1236 #define OFDM_RX_FRAME_EHT_RU_ALLOC_5_D4 0x0003fe00 1237 __le32 cmn[6]; 1238 #define OFDM_RX_FRAME_EHT_USER_FIELD_ID 0x000007ff 1239 __le32 user_id; 1240 }; 1241 1242 struct iwl_eht_tb_sigs { 1243 /* same as non-TB above */ 1244 __le32 usig_a1, usig_a2_eht; 1245 /* same as HE TB above */ 1246 __le32 tb_rx0, tb_rx1; 1247 }; 1248 1249 struct iwl_uhr_sigs { 1250 __le32 usig_a1, usig_a1_uhr, usig_a2_uhr, b1, b2; 1251 __le32 sig2; 1252 __le32 cmn[6]; 1253 __le32 user_id; 1254 }; 1255 1256 struct iwl_uhr_tb_sigs { 1257 __le32 usig_a1, usig_a2_uhr, tb_rx0, tb_rx1; 1258 }; 1259 1260 struct iwl_uhr_elr_sigs { 1261 __le32 usig_a1, usig_a2_uhr; 1262 __le32 uhr_sig_elr1, uhr_sig_elr2; 1263 }; 1264 1265 union iwl_sigs { 1266 struct iwl_ht_sigs ht; 1267 struct iwl_vht_sigs vht; 1268 struct iwl_he_sigs he; 1269 struct iwl_he_tb_sigs he_tb; 1270 struct iwl_eht_sigs eht; 1271 struct iwl_eht_tb_sigs eht_tb; 1272 struct iwl_uhr_sigs uhr; 1273 struct iwl_uhr_tb_sigs uhr_tb; 1274 struct iwl_uhr_elr_sigs uhr_elr; 1275 }; 1276 1277 enum iwl_sniffer_status { 1278 IWL_SNIF_STAT_PLCP_RX_OK = 0, 1279 IWL_SNIF_STAT_AID_NOT_FOR_US = 1, 1280 IWL_SNIF_STAT_PLCP_RX_LSIG_ERR = 2, 1281 IWL_SNIF_STAT_PLCP_RX_SIGA_ERR = 3, 1282 IWL_SNIF_STAT_PLCP_RX_SIGB_ERR = 4, 1283 IWL_SNIF_STAT_UNEXPECTED_TB = 5, 1284 IWL_SNIF_STAT_UNSUPPORTED_RATE = 6, 1285 IWL_SNIF_STAT_UNKNOWN_ERROR = 7, 1286 }; /* AIR_SNIFFER_STATUS_E_VER_1 */ 1287 1288 enum iwl_sniffer_flags { 1289 IWL_SNIF_FLAG_VALID_TB_RX = BIT(0), 1290 IWL_SNIF_FLAG_VALID_RU = BIT(1), 1291 }; /* AIR_SNIFFER_FLAGS_E_VER_1 */ 1292 1293 /** 1294 * struct iwl_rx_phy_air_sniffer_ntfy - air sniffer notification 1295 * 1296 * @status: &enum iwl_sniffer_status 1297 * @flags: &enum iwl_sniffer_flags 1298 * @reserved1: reserved 1299 * @rssi_a: energy chain-A in negative dBm, measured at FINA time 1300 * @rssi_b: energy chain-B in negative dBm, measured at FINA time 1301 * @channel: channel number 1302 * @band: band information, PHY_BAND_* 1303 * @on_air_rise_time: GP2 at on air rise 1304 * @frame_time: frame time in us 1305 * @rate: RATE_MCS_* 1306 * @bytecount: byte count for legay and HT, otherwise number of symbols 1307 * @legacy_sig: CCK signal information if %RATE_MCS_MOD_TYPE_MSK in @rate is 1308 * %RATE_MCS_MOD_TYPE_CCK, otherwise OFDM signal information 1309 * @sigs: PHY signal information, depending on %RATE_MCS_MOD_TYPE_MSK in @rate 1310 * @reserved2: reserved 1311 * 1312 * Sent for every frame and before the normal RX command if data is included. 1313 */ 1314 struct iwl_rx_phy_air_sniffer_ntfy { 1315 u8 status; 1316 u8 flags; 1317 u8 reserved1[2]; 1318 u8 rssi_a, rssi_b; 1319 u8 channel, band; 1320 __le32 on_air_rise_time; 1321 __le32 frame_time; 1322 /* note: MCS in rate is not valid for MU-VHT */ 1323 __le32 rate; 1324 __le32 bytecount; 1325 union iwl_legacy_sig legacy_sig; 1326 union iwl_sigs sigs; 1327 __le32 reserved2; 1328 }; /* RX_PHY_AIR_SNIFFER_NTFY_API_S_VER_1 */ 1329 1330 #endif /* __iwl_fw_api_rx_h__ */ 1331