1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2024-2026 Intel Corporation 4 */ 5 #ifndef __iwl_mld_constants_h__ 6 #define __iwl_mld_constants_h__ 7 8 #define IWL_MLD_MISSED_BEACONS_SINCE_RX_THOLD 6 9 #define IWL_MLD_MISSED_BEACONS_THRESHOLD 8 10 #define IWL_MLD_MISSED_BEACONS_THRESHOLD_LONG 19 11 #define IWL_MLD_BCN_LOSS_EXIT_ESR_THRESH_2_LINKS 5 12 #define IWL_MLD_BCN_LOSS_EXIT_ESR_THRESH 15 13 #define IWL_MLD_BCN_LOSS_EXIT_ESR_THRESH_BSS_PARAM_CHANGED 11 14 #define IWL_MLD_LOW_RSSI_MLO_SCAN_THRESH -72 15 16 #define IWL_MLD_DEFAULT_PS_TX_DATA_TIMEOUT (100 * USEC_PER_MSEC) 17 #define IWL_MLD_DEFAULT_PS_RX_DATA_TIMEOUT (100 * USEC_PER_MSEC) 18 #define IWL_MLD_WOWLAN_PS_TX_DATA_TIMEOUT (10 * USEC_PER_MSEC) 19 #define IWL_MLD_WOWLAN_PS_RX_DATA_TIMEOUT (10 * USEC_PER_MSEC) 20 #define IWL_MLD_SHORT_PS_TX_DATA_TIMEOUT (2 * 1024) /* defined in TU */ 21 #define IWL_MLD_SHORT_PS_RX_DATA_TIMEOUT (40 * 1024) /* defined in TU */ 22 23 #define IWL_MLD_UAPSD_RX_DATA_TIMEOUT (50 * USEC_PER_MSEC) 24 #define IWL_MLD_UAPSD_TX_DATA_TIMEOUT (50 * USEC_PER_MSEC) 25 26 #define IWL_MLD_PS_SNOOZE_INTERVAL 25 27 #define IWL_MLD_PS_SNOOZE_INTERVAL 25 28 #define IWL_MLD_PS_SNOOZE_WINDOW 50 29 30 #define IWL_MLD_PS_SNOOZE_HEAVY_TX_THLD_PACKETS 30 31 #define IWL_MLD_PS_SNOOZE_HEAVY_RX_THLD_PACKETS 20 32 33 #define IWL_MLD_PS_HEAVY_TX_THLD_PERCENT 50 34 #define IWL_MLD_PS_HEAVY_RX_THLD_PERCENT 50 35 #define IWL_MLD_PS_HEAVY_TX_THLD_PACKETS 20 36 #define IWL_MLD_PS_HEAVY_RX_THLD_PACKETS 8 37 38 #define IWL_MLD_TRIGGER_LINK_SEL_TIME_SEC 30 39 40 #define IWL_MLD_TPT_COUNT_WINDOW (5 * HZ) 41 42 #define IWL_MLD_DIS_RANDOM_FW_ID false 43 #define IWL_MLD_D3_DEBUG false 44 #define IWL_MLD_NON_TRANSMITTING_AP false 45 #define IWL_MLD_6GHZ_PASSIVE_SCAN_TIMEOUT 3000 /* in seconds */ 46 #define IWL_MLD_6GHZ_PASSIVE_SCAN_ASSOC_TIMEOUT 60 /* in seconds */ 47 #define IWL_MLD_CONN_LISTEN_INTERVAL 10 48 #define IWL_MLD_ADAPTIVE_DWELL_NUM_APS_OVERRIDE 0 49 #define IWL_MLD_AUTO_EML_ENABLE true 50 51 #define IWL_MLD_HIGH_RSSI_THRESH_20MHZ -67 52 #define IWL_MLD_LOW_RSSI_THRESH_20MHZ -72 53 #define IWL_MLD_HIGH_RSSI_THRESH_40MHZ -64 54 #define IWL_MLD_LOW_RSSI_THRESH_40MHZ -72 55 #define IWL_MLD_HIGH_RSSI_THRESH_80MHZ -61 56 #define IWL_MLD_LOW_RSSI_THRESH_80MHZ -72 57 #define IWL_MLD_HIGH_RSSI_THRESH_160MHZ -58 58 #define IWL_MLD_LOW_RSSI_THRESH_160MHZ -72 59 60 #define IWL_MLD_ENTER_EMLSR_TPT_THRESH 400 61 #define IWL_MLD_EXIT_EMLSR_CHAN_LOAD 2 /* in percentage */ 62 63 #define IWL_MLD_FTM_INITIATOR_ALGO IWL_TOF_ALGO_TYPE_MAX_LIKE 64 #define IWL_MLD_FTM_INITIATOR_DYNACK true 65 #define IWL_MLD_FTM_LMR_FEEDBACK_TERMINATE false 66 #define IWL_MLD_FTM_TEST_INCORRECT_SAC false 67 #define IWL_MLD_FTM_R2I_MAX_REP 7 68 #define IWL_MLD_FTM_I2R_MAX_REP 7 69 #define IWL_MLD_FTM_R2I_MAX_STS 1 70 #define IWL_MLD_FTM_I2R_MAX_STS 1 71 #define IWL_MLD_FTM_R2I_MAX_TOTAL_LTF 3 72 #define IWL_MLD_FTM_I2R_MAX_TOTAL_LTF 3 73 #define IWL_MLD_FTM_RESP_NDP_SUPPORT true 74 #define IWL_MLD_FTM_RESP_LMR_FEEDBACK_SUPPORT true 75 #define IWL_MLD_FTM_NON_TB_MIN_TIME_BETWEEN_MSR 7 76 #define IWL_MLD_FTM_NON_TB_MAX_TIME_BETWEEN_MSR 1000 77 #define IWL_MLD_STA_EXT_CAPA_SIZE 9 78 #define IWL_MLD_EXT_CAPA_NUM_IFTYPES 1 79 80 #endif /* __iwl_mld_constants_h__ */ 81