1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STM32 Independent Watchdog
4 *
5 * Copyright (C) STMicroelectronics 2017
6 * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
7 *
8 * This driver is based on tegra_wdt.c
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/watchdog.h>
23
24 #define DEFAULT_TIMEOUT 10
25
26 /* IWDG registers */
27 #define IWDG_KR 0x00 /* Key register */
28 #define IWDG_PR 0x04 /* Prescaler Register */
29 #define IWDG_RLR 0x08 /* ReLoad Register */
30 #define IWDG_SR 0x0C /* Status Register */
31 #define IWDG_WINR 0x10 /* Windows Register */
32 #define IWDG_EWCR 0x14 /* Early Wake-up Register */
33
34 /* IWDG_KR register bit mask */
35 #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
36 #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
37 #define KR_KEY_EWA 0x5555 /* write access enable */
38 #define KR_KEY_DWA 0x0000 /* write access disable */
39
40 /* IWDG_PR register */
41 #define PR_SHIFT 2
42 #define PR_MIN BIT(PR_SHIFT)
43
44 /* IWDG_RLR register values */
45 #define RLR_MIN 0x2 /* min value recommended */
46 #define RLR_MAX GENMASK(11, 0) /* max value of reload register */
47
48 /* IWDG_SR register bit mask */
49 #define SR_PVU BIT(0) /* Watchdog prescaler value update */
50 #define SR_RVU BIT(1) /* Watchdog counter reload value update */
51
52 #define EWCR_EWIT GENMASK(11, 0) /* Watchdog counter window value */
53 #define EWCR_EWIC BIT(14) /* Watchdog early interrupt acknowledge */
54 #define EWCR_EWIE BIT(15) /* Watchdog early interrupt enable */
55
56 /* set timeout to 100000 us */
57 #define TIMEOUT_US 100000
58 #define SLEEP_US 1000
59
60 struct stm32_iwdg_data {
61 bool has_pclk;
62 bool has_early_wakeup;
63 u32 max_prescaler;
64 };
65
66 static const struct stm32_iwdg_data stm32_iwdg_data = {
67 .has_pclk = false,
68 .has_early_wakeup = false,
69 .max_prescaler = 256,
70 };
71
72 static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
73 .has_pclk = true,
74 .has_early_wakeup = true,
75 .max_prescaler = 1024,
76 };
77
78 struct stm32_iwdg {
79 struct watchdog_device wdd;
80 const struct stm32_iwdg_data *data;
81 void __iomem *regs;
82 struct clk *clk_lsi;
83 struct clk *clk_pclk;
84 unsigned int rate;
85 };
86
reg_read(void __iomem * base,u32 reg)87 static inline u32 reg_read(void __iomem *base, u32 reg)
88 {
89 return readl_relaxed(base + reg);
90 }
91
reg_write(void __iomem * base,u32 reg,u32 val)92 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
93 {
94 writel_relaxed(val, base + reg);
95 }
96
stm32_iwdg_start(struct watchdog_device * wdd)97 static int stm32_iwdg_start(struct watchdog_device *wdd)
98 {
99 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
100 u32 tout, ptot, presc, iwdg_rlr, iwdg_ewcr, iwdg_pr, iwdg_sr;
101 int ret;
102
103 dev_dbg(wdd->parent, "%s\n", __func__);
104
105 if (!wdd->pretimeout)
106 wdd->pretimeout = 3 * wdd->timeout / 4;
107
108 tout = clamp_t(unsigned int, wdd->timeout,
109 wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
110 ptot = clamp_t(unsigned int, tout - wdd->pretimeout,
111 wdd->min_timeout, tout);
112
113 presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
114
115 /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
116 presc = roundup_pow_of_two(presc);
117 iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
118 iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
119 iwdg_ewcr = ((ptot * wdt->rate) / presc) - 1;
120
121 /* enable write access */
122 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
123
124 /* set prescaler & reload registers */
125 reg_write(wdt->regs, IWDG_PR, iwdg_pr);
126 reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
127 if (wdt->data->has_early_wakeup)
128 reg_write(wdt->regs, IWDG_EWCR, iwdg_ewcr | EWCR_EWIE);
129 reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
130
131 /* wait for the registers to be updated (max 100ms) */
132 ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
133 !(iwdg_sr & (SR_PVU | SR_RVU)),
134 SLEEP_US, TIMEOUT_US);
135 if (ret) {
136 dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
137 return ret;
138 }
139
140 /* reload watchdog */
141 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
142
143 return 0;
144 }
145
stm32_iwdg_ping(struct watchdog_device * wdd)146 static int stm32_iwdg_ping(struct watchdog_device *wdd)
147 {
148 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
149
150 dev_dbg(wdd->parent, "%s\n", __func__);
151
152 /* reload watchdog */
153 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
154
155 return 0;
156 }
157
stm32_iwdg_set_timeout(struct watchdog_device * wdd,unsigned int timeout)158 static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
159 unsigned int timeout)
160 {
161 dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
162
163 wdd->timeout = timeout;
164
165 if (watchdog_active(wdd))
166 return stm32_iwdg_start(wdd);
167
168 return 0;
169 }
170
stm32_iwdg_set_pretimeout(struct watchdog_device * wdd,unsigned int pretimeout)171 static int stm32_iwdg_set_pretimeout(struct watchdog_device *wdd,
172 unsigned int pretimeout)
173 {
174 dev_dbg(wdd->parent, "%s pretimeout: %d sec\n", __func__, pretimeout);
175
176 wdd->pretimeout = pretimeout;
177
178 if (watchdog_active(wdd))
179 return stm32_iwdg_start(wdd);
180
181 return 0;
182 }
183
stm32_iwdg_isr(int irq,void * wdog_arg)184 static irqreturn_t stm32_iwdg_isr(int irq, void *wdog_arg)
185 {
186 struct watchdog_device *wdd = wdog_arg;
187 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
188 u32 reg;
189
190 reg = reg_read(wdt->regs, IWDG_EWCR);
191 reg |= EWCR_EWIC;
192 reg_write(wdt->regs, IWDG_EWCR, reg);
193
194 watchdog_notify_pretimeout(wdd);
195
196 return IRQ_HANDLED;
197 }
198
stm32_clk_disable_unprepare(void * data)199 static void stm32_clk_disable_unprepare(void *data)
200 {
201 clk_disable_unprepare(data);
202 }
203
stm32_iwdg_clk_init(struct platform_device * pdev,struct stm32_iwdg * wdt)204 static int stm32_iwdg_clk_init(struct platform_device *pdev,
205 struct stm32_iwdg *wdt)
206 {
207 struct device *dev = &pdev->dev;
208 u32 ret;
209
210 wdt->clk_lsi = devm_clk_get(dev, "lsi");
211 if (IS_ERR(wdt->clk_lsi))
212 return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
213
214 /* optional peripheral clock */
215 if (wdt->data->has_pclk) {
216 wdt->clk_pclk = devm_clk_get(dev, "pclk");
217 if (IS_ERR(wdt->clk_pclk))
218 return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
219 "Unable to get pclk clock\n");
220
221 ret = clk_prepare_enable(wdt->clk_pclk);
222 if (ret) {
223 dev_err(dev, "Unable to prepare pclk clock\n");
224 return ret;
225 }
226 ret = devm_add_action_or_reset(dev,
227 stm32_clk_disable_unprepare,
228 wdt->clk_pclk);
229 if (ret)
230 return ret;
231 }
232
233 ret = clk_prepare_enable(wdt->clk_lsi);
234 if (ret) {
235 dev_err(dev, "Unable to prepare lsi clock\n");
236 return ret;
237 }
238 ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
239 wdt->clk_lsi);
240 if (ret)
241 return ret;
242
243 wdt->rate = clk_get_rate(wdt->clk_lsi);
244
245 return 0;
246 }
247
248 static const struct watchdog_info stm32_iwdg_info = {
249 .options = WDIOF_SETTIMEOUT |
250 WDIOF_MAGICCLOSE |
251 WDIOF_KEEPALIVEPING,
252 .identity = "STM32 Independent Watchdog",
253 };
254
255 static const struct watchdog_info stm32_iwdg_preinfo = {
256 .options = WDIOF_SETTIMEOUT |
257 WDIOF_MAGICCLOSE |
258 WDIOF_KEEPALIVEPING |
259 WDIOF_PRETIMEOUT,
260 .identity = "STM32 Independent Watchdog",
261 };
262
263 static const struct watchdog_ops stm32_iwdg_ops = {
264 .owner = THIS_MODULE,
265 .start = stm32_iwdg_start,
266 .ping = stm32_iwdg_ping,
267 .set_timeout = stm32_iwdg_set_timeout,
268 .set_pretimeout = stm32_iwdg_set_pretimeout,
269 };
270
271 static const struct of_device_id stm32_iwdg_of_match[] = {
272 { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
273 { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
274 { /* end node */ }
275 };
276 MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
277
stm32_iwdg_irq_init(struct platform_device * pdev,struct stm32_iwdg * wdt)278 static int stm32_iwdg_irq_init(struct platform_device *pdev,
279 struct stm32_iwdg *wdt)
280 {
281 struct device_node *np = pdev->dev.of_node;
282 struct watchdog_device *wdd = &wdt->wdd;
283 struct device *dev = &pdev->dev;
284 int irq, ret;
285
286 if (!wdt->data->has_early_wakeup)
287 return 0;
288
289 irq = platform_get_irq(pdev, 0);
290 if (irq <= 0)
291 return 0;
292
293 if (of_property_read_bool(np, "wakeup-source")) {
294 ret = device_init_wakeup(dev, true);
295 if (ret)
296 return ret;
297
298 ret = dev_pm_set_wake_irq(dev, irq);
299 if (ret)
300 return ret;
301 }
302
303 ret = devm_request_irq(dev, irq, stm32_iwdg_isr, 0,
304 dev_name(dev), wdd);
305 if (ret)
306 return ret;
307
308 wdd->info = &stm32_iwdg_preinfo;
309 return 0;
310 }
311
stm32_iwdg_probe(struct platform_device * pdev)312 static int stm32_iwdg_probe(struct platform_device *pdev)
313 {
314 struct device *dev = &pdev->dev;
315 struct watchdog_device *wdd;
316 struct stm32_iwdg *wdt;
317 int ret;
318
319 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
320 if (!wdt)
321 return -ENOMEM;
322
323 wdt->data = of_device_get_match_data(&pdev->dev);
324 if (!wdt->data)
325 return -ENODEV;
326
327 /* This is the timer base. */
328 wdt->regs = devm_platform_ioremap_resource(pdev, 0);
329 if (IS_ERR(wdt->regs))
330 return PTR_ERR(wdt->regs);
331
332 ret = stm32_iwdg_clk_init(pdev, wdt);
333 if (ret)
334 return ret;
335
336 /* Initialize struct watchdog_device. */
337 wdd = &wdt->wdd;
338 wdd->parent = dev;
339 wdd->info = &stm32_iwdg_info;
340 wdd->ops = &stm32_iwdg_ops;
341 wdd->timeout = DEFAULT_TIMEOUT;
342 wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
343 wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
344 1000) / wdt->rate;
345
346 /* Initialize IRQ, this might override wdd->info, hence it is here. */
347 ret = stm32_iwdg_irq_init(pdev, wdt);
348 if (ret)
349 return ret;
350
351 watchdog_set_drvdata(wdd, wdt);
352 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
353 watchdog_init_timeout(wdd, 0, dev);
354
355 /*
356 * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
357 * (Means U-Boot/bootloaders leaves the watchdog running)
358 * When we get here we should make a decision to prevent
359 * any side effects before user space daemon will take care of it.
360 * The best option, taking into consideration that there is no
361 * way to read values back from hardware, is to enforce watchdog
362 * being run with deterministic values.
363 */
364 if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
365 ret = stm32_iwdg_start(wdd);
366 if (ret)
367 return ret;
368
369 /* Make sure the watchdog is serviced */
370 set_bit(WDOG_HW_RUNNING, &wdd->status);
371 }
372
373 ret = devm_watchdog_register_device(dev, wdd);
374 if (ret)
375 return ret;
376
377 platform_set_drvdata(pdev, wdt);
378
379 return 0;
380 }
381
382 static struct platform_driver stm32_iwdg_driver = {
383 .probe = stm32_iwdg_probe,
384 .driver = {
385 .name = "iwdg",
386 .of_match_table = stm32_iwdg_of_match,
387 },
388 };
389 module_platform_driver(stm32_iwdg_driver);
390
391 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
392 MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
393 MODULE_LICENSE("GPL v2");
394