1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2018 Linaro Limited, All rights reserved.
4 * Author: Mike Leach <mike.leach@linaro.org>
5 */
6
7 #ifndef _CORESIGHT_CORESIGHT_CTI_H
8 #define _CORESIGHT_CORESIGHT_CTI_H
9
10 #include <linux/coresight.h>
11 #include <linux/device.h>
12 #include <linux/list.h>
13 #include <linux/spinlock.h>
14 #include <linux/sysfs.h>
15 #include <linux/types.h>
16
17 #include "coresight-priv.h"
18
19 struct fwnode_handle;
20
21 /*
22 * Device registers
23 * 0x000 - 0x144: CTI programming and status
24 * 0xEDC - 0xEF8: CTI integration test.
25 * 0xF00 - 0xFFC: Coresight management registers.
26 */
27 /* CTI programming registers */
28 #define CTICONTROL 0x000
29 #define CTIINTACK 0x010
30 #define CTIAPPSET 0x014
31 #define CTIAPPCLEAR 0x018
32 #define CTIAPPPULSE 0x01C
33 #define CTIINEN(n) (0x020 + (4 * n))
34 #define CTIOUTEN(n) (0x0A0 + (4 * n))
35 #define CTITRIGINSTATUS 0x130
36 #define CTITRIGOUTSTATUS 0x134
37 #define CTICHINSTATUS 0x138
38 #define CTICHOUTSTATUS 0x13C
39 #define CTIGATE 0x140
40 #define ASICCTL 0x144
41 /* Integration test registers */
42 #define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/
43 #define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/
44 #define ITCHOUT 0xEE4 /* WO RW-600 */
45 #define ITTRIGOUT 0xEE8 /* WO RW-600 */
46 #define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/
47 #define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/
48 #define ITCHIN 0xEF4 /* RO */
49 #define ITTRIGIN 0xEF8 /* RO */
50 /* management registers */
51 #define CTIDEVAFF0 0xFA8
52 #define CTIDEVAFF1 0xFAC
53
54 /*
55 * CTI CSSoc 600 has a max of 32 trigger signals per direction.
56 * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
57 * Max of in and out defined in the DEVID register.
58 * - pick up actual number used from .dts parameters if present.
59 */
60 #define CTIINOUTEN_MAX 32
61
62 /**
63 * Group of related trigger signals
64 *
65 * @nr_sigs: number of signals in the group.
66 * @used_mask: bitmask representing the signal indexes in the group.
67 * @sig_types: array of types for the signals, length nr_sigs.
68 */
69 struct cti_trig_grp {
70 int nr_sigs;
71 u32 used_mask;
72 int sig_types[];
73 };
74
75 /**
76 * Trigger connection - connection between a CTI and other (coresight) device
77 * lists input and output trigger signals for the device
78 *
79 * @con_in: connected CTIIN signals for the device.
80 * @con_out: connected CTIOUT signals for the device.
81 * @con_dev: coresight device connected to the CTI, NULL if not CS device
82 * @con_dev_name: name of connected device (CS or CPU)
83 * @node: entry node in list of connections.
84 * @con_attrs: Dynamic sysfs attributes specific to this connection.
85 * @attr_group: Dynamic attribute group created for this connection.
86 */
87 struct cti_trig_con {
88 struct cti_trig_grp *con_in;
89 struct cti_trig_grp *con_out;
90 struct coresight_device *con_dev;
91 const char *con_dev_name;
92 struct list_head node;
93 struct attribute **con_attrs;
94 struct attribute_group *attr_group;
95 };
96
97 /**
98 * struct cti_device - description of CTI device properties.
99 *
100 * @nt_trig_con: Number of external devices connected to this device.
101 * @ctm_id: which CTM this device is connected to (by default it is
102 * assumed there is a single CTM per SoC, ID 0).
103 * @trig_cons: list of connections to this device.
104 * @cpu: CPU ID if associated with CPU, -1 otherwise.
105 * @con_groups: combined static and dynamic sysfs groups for trigger
106 * connections.
107 */
108 struct cti_device {
109 int nr_trig_con;
110 u32 ctm_id;
111 struct list_head trig_cons;
112 int cpu;
113 const struct attribute_group **con_groups;
114 };
115
116 /**
117 * struct cti_config - configuration of the CTI device hardware
118 *
119 * @nr_trig_max: Max number of trigger signals implemented on device.
120 * (max of trig_in or trig_out) - from ID register.
121 * @nr_ctm_channels: number of available CTM channels - from ID register.
122 * @enable_req_count: CTI is enabled alongside >=1 associated devices.
123 * @hw_enabled: true if hw is currently enabled.
124 * @hw_powered: true if associated cpu powered on, or no cpu.
125 * @trig_in_use: bitfield of in triggers registered as in use.
126 * @trig_out_use: bitfield of out triggers registered as in use.
127 * @trig_out_filter: bitfield of out triggers that are blocked if filter
128 * enabled. Typically this would be dbgreq / restart on
129 * a core CTI.
130 * @trig_filter_enable: 1 if filtering enabled.
131 * @xtrig_rchan_sel: channel selection for xtrigger connection show.
132 * @ctiappset: CTI Software application channel set.
133 * @ctiinout_sel: register selector for INEN and OUTEN regs.
134 * @ctiinen: enable input trigger to a channel.
135 * @ctiouten: enable output trigger from a channel.
136 * @ctigate: gate channel output from CTI to CTM.
137 * @asicctl: asic control register.
138 */
139 struct cti_config {
140 /* hardware description */
141 int nr_ctm_channels;
142 int nr_trig_max;
143
144 /* cti enable control */
145 int enable_req_count;
146 bool hw_enabled;
147 bool hw_powered;
148
149 /* registered triggers and filtering */
150 u32 trig_in_use;
151 u32 trig_out_use;
152 u32 trig_out_filter;
153 bool trig_filter_enable;
154 u8 xtrig_rchan_sel;
155
156 /* cti cross trig programmable regs */
157 u32 ctiappset;
158 u8 ctiinout_sel;
159 u32 ctiinen[CTIINOUTEN_MAX];
160 u32 ctiouten[CTIINOUTEN_MAX];
161 u32 ctigate;
162 u32 asicctl;
163 };
164
165 /**
166 * struct cti_drvdata - specifics for the CTI device
167 * @base: Memory mapped base address for this component..
168 * @csdev: Standard CoreSight device information.
169 * @ctidev: Extra information needed by the CTI/CTM framework.
170 * @spinlock: Control data access to one at a time.
171 * @config: Configuration data for this CTI device.
172 * @node: List entry of this device in the list of CTI devices.
173 * @csdev_release: release function for underlying coresight_device.
174 */
175 struct cti_drvdata {
176 void __iomem *base;
177 struct coresight_device *csdev;
178 struct cti_device ctidev;
179 raw_spinlock_t spinlock;
180 struct cti_config config;
181 struct list_head node;
182 void (*csdev_release)(struct device *dev);
183 };
184
185 /*
186 * Channel operation types.
187 */
188 enum cti_chan_op {
189 CTI_CHAN_ATTACH,
190 CTI_CHAN_DETACH,
191 };
192
193 enum cti_trig_dir {
194 CTI_TRIG_IN,
195 CTI_TRIG_OUT,
196 };
197
198 enum cti_chan_gate_op {
199 CTI_GATE_CHAN_ENABLE,
200 CTI_GATE_CHAN_DISABLE,
201 };
202
203 enum cti_chan_set_op {
204 CTI_CHAN_SET,
205 CTI_CHAN_CLR,
206 CTI_CHAN_PULSE,
207 };
208
209 /* private cti driver fns & vars */
210 extern const struct attribute_group *coresight_cti_groups[];
211 int cti_add_default_connection(struct device *dev,
212 struct cti_drvdata *drvdata);
213 int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,
214 struct cti_trig_con *tc,
215 struct coresight_device *csdev,
216 const char *assoc_dev_name);
217 struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
218 int out_sigs);
219 int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *data);
220 int cti_disable(struct coresight_device *csdev, void *data);
221 void cti_write_all_hw_regs(struct cti_drvdata *drvdata);
222 void cti_write_intack(struct device *dev, u32 ackval);
223 void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value);
224 int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
225 enum cti_trig_dir direction, u32 channel_idx,
226 u32 trigger_idx);
227 int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op,
228 u32 channel_idx);
229 int cti_channel_setop(struct device *dev, enum cti_chan_set_op op,
230 u32 channel_idx);
231 int cti_create_cons_sysfs(struct device *dev, struct cti_drvdata *drvdata);
232 struct coresight_platform_data *
233 coresight_cti_get_platform_data(struct device *dev);
234 const char *cti_plat_get_node_name(struct fwnode_handle *fwnode);
235
236 /* cti powered and enabled */
cti_active(struct cti_config * cfg)237 static inline bool cti_active(struct cti_config *cfg)
238 {
239 return cfg->hw_powered && cfg->hw_enabled;
240 }
241
242 #endif /* _CORESIGHT_CORESIGHT_CTI_H */
243