1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 BayLibre, SAS 4 * Author: Phong LE <ple@baylibre.com> 5 * Copyright (C) 2018-2019, Artem Mygaiev 6 * Copyright (C) 2017, Fresco Logic, Incorporated. 7 * 8 */ 9 10 #include <linux/media-bus-format.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/bitfield.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <linux/of_graph.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/regulator/consumer.h> 22 23 #include <drm/display/drm_hdmi_helper.h> 24 #include <drm/display/drm_hdmi_state_helper.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_modes.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_probe_helper.h> 31 32 #include <sound/hdmi-codec.h> 33 34 #define IT66121_VENDOR_ID0_REG 0x00 35 #define IT66121_VENDOR_ID1_REG 0x01 36 #define IT66121_DEVICE_ID0_REG 0x02 37 #define IT66121_DEVICE_ID1_REG 0x03 38 39 #define IT66121_REVISION_MASK GENMASK(7, 4) 40 #define IT66121_DEVICE_ID1_MASK GENMASK(3, 0) 41 42 #define IT66121_MASTER_SEL_REG 0x10 43 #define IT66121_MASTER_SEL_HOST BIT(0) 44 45 #define IT66121_AFE_DRV_REG 0x61 46 #define IT66121_AFE_DRV_RST BIT(4) 47 #define IT66121_AFE_DRV_PWD BIT(5) 48 49 #define IT66121_INPUT_MODE_REG 0x70 50 #define IT66121_INPUT_MODE_RGB (0 << 6) 51 #define IT66121_INPUT_MODE_YUV422 BIT(6) 52 #define IT66121_INPUT_MODE_YUV444 (2 << 6) 53 #define IT66121_INPUT_MODE_CCIR656 BIT(4) 54 #define IT66121_INPUT_MODE_SYNCEMB BIT(3) 55 #define IT66121_INPUT_MODE_DDR BIT(2) 56 57 #define IT66121_INPUT_CSC_REG 0x72 58 #define IT66121_INPUT_CSC_ENDITHER BIT(7) 59 #define IT66121_INPUT_CSC_ENUDFILTER BIT(6) 60 #define IT66121_INPUT_CSC_DNFREE_GO BIT(5) 61 #define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 62 #define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 63 #define IT66121_INPUT_CSC_NO_CONV 0x00 64 65 #define IT66121_AFE_XP_REG 0x62 66 #define IT66121_AFE_XP_GAINBIT BIT(7) 67 #define IT66121_AFE_XP_PWDPLL BIT(6) 68 #define IT66121_AFE_XP_ENI BIT(5) 69 #define IT66121_AFE_XP_ENO BIT(4) 70 #define IT66121_AFE_XP_RESETB BIT(3) 71 #define IT66121_AFE_XP_PWDI BIT(2) 72 #define IT6610_AFE_XP_BYPASS BIT(0) 73 74 #define IT66121_AFE_IP_REG 0x64 75 #define IT66121_AFE_IP_GAINBIT BIT(7) 76 #define IT66121_AFE_IP_PWDPLL BIT(6) 77 #define IT66121_AFE_IP_CKSEL_05 (0 << 4) 78 #define IT66121_AFE_IP_CKSEL_1 BIT(4) 79 #define IT66121_AFE_IP_CKSEL_2 (2 << 4) 80 #define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) 81 #define IT66121_AFE_IP_ER0 BIT(3) 82 #define IT66121_AFE_IP_RESETB BIT(2) 83 #define IT66121_AFE_IP_ENC BIT(1) 84 #define IT66121_AFE_IP_EC1 BIT(0) 85 86 #define IT66121_AFE_XP_EC1_REG 0x68 87 #define IT66121_AFE_XP_EC1_LOWCLK BIT(4) 88 89 #define IT66121_SW_RST_REG 0x04 90 #define IT66121_SW_RST_REF BIT(5) 91 #define IT66121_SW_RST_AREF BIT(4) 92 #define IT66121_SW_RST_VID BIT(3) 93 #define IT66121_SW_RST_AUD BIT(2) 94 #define IT66121_SW_RST_HDCP BIT(0) 95 96 #define IT66121_DDC_COMMAND_REG 0x15 97 #define IT66121_DDC_COMMAND_BURST_READ 0x0 98 #define IT66121_DDC_COMMAND_EDID_READ 0x3 99 #define IT66121_DDC_COMMAND_FIFO_CLR 0x9 100 #define IT66121_DDC_COMMAND_SCL_PULSE 0xA 101 #define IT66121_DDC_COMMAND_ABORT 0xF 102 103 #define IT66121_HDCP_REG 0x20 104 #define IT66121_HDCP_CPDESIRED BIT(0) 105 #define IT66121_HDCP_EN1P1FEAT BIT(1) 106 107 #define IT66121_INT_STATUS1_REG 0x06 108 #define IT66121_INT_STATUS1_AUD_OVF BIT(7) 109 #define IT66121_INT_STATUS1_DDC_NOACK BIT(5) 110 #define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4) 111 #define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2) 112 #define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1) 113 #define IT66121_INT_STATUS1_HPD_STATUS BIT(0) 114 115 #define IT66121_DDC_HEADER_REG 0x11 116 #define IT66121_DDC_HEADER_HDCP 0x74 117 #define IT66121_DDC_HEADER_EDID 0xA0 118 119 #define IT66121_DDC_OFFSET_REG 0x12 120 #define IT66121_DDC_BYTE_REG 0x13 121 #define IT66121_DDC_SEGMENT_REG 0x14 122 #define IT66121_DDC_RD_FIFO_REG 0x17 123 124 #define IT66121_CLK_BANK_REG 0x0F 125 #define IT66121_CLK_BANK_PWROFF_RCLK BIT(6) 126 #define IT66121_CLK_BANK_PWROFF_ACLK BIT(5) 127 #define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4) 128 #define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3) 129 #define IT66121_CLK_BANK_0 0 130 #define IT66121_CLK_BANK_1 1 131 132 #define IT66121_INT_REG 0x05 133 #define IT66121_INT_ACTIVE_HIGH BIT(7) 134 #define IT66121_INT_OPEN_DRAIN BIT(6) 135 #define IT66121_INT_TX_CLK_OFF BIT(0) 136 137 #define IT66121_INT_MASK1_REG 0x09 138 #define IT66121_INT_MASK1_AUD_OVF BIT(7) 139 #define IT66121_INT_MASK1_DDC_NOACK BIT(5) 140 #define IT66121_INT_MASK1_DDC_FIFOERR BIT(4) 141 #define IT66121_INT_MASK1_DDC_BUSHANG BIT(2) 142 #define IT66121_INT_MASK1_RX_SENS BIT(1) 143 #define IT66121_INT_MASK1_HPD BIT(0) 144 145 #define IT66121_INT_CLR1_REG 0x0C 146 #define IT66121_INT_CLR1_PKTACP BIT(7) 147 #define IT66121_INT_CLR1_PKTNULL BIT(6) 148 #define IT66121_INT_CLR1_PKTGEN BIT(5) 149 #define IT66121_INT_CLR1_KSVLISTCHK BIT(4) 150 #define IT66121_INT_CLR1_AUTHDONE BIT(3) 151 #define IT66121_INT_CLR1_AUTHFAIL BIT(2) 152 #define IT66121_INT_CLR1_RX_SENS BIT(1) 153 #define IT66121_INT_CLR1_HPD BIT(0) 154 155 #define IT66121_AV_MUTE_REG 0xC1 156 #define IT66121_AV_MUTE_ON BIT(0) 157 #define IT66121_AV_MUTE_BLUESCR BIT(1) 158 159 #define IT66121_PKT_CTS_CTRL_REG 0xC5 160 #define IT66121_PKT_CTS_CTRL_SEL BIT(1) 161 162 #define IT66121_PKT_GEN_CTRL_REG 0xC6 163 #define IT66121_PKT_GEN_CTRL_ON BIT(0) 164 #define IT66121_PKT_GEN_CTRL_RPT BIT(1) 165 166 #define IT66121_PKT_NULL_CTRL_REG 0xC9 167 #define IT66121_PKT_NULL_CTRL_ON BIT(0) 168 #define IT66121_PKT_NULL_CTRL_RPT BIT(1) 169 170 /* Null packet data registers (used for HDMI Vendor Specific InfoFrame) */ 171 #define IT66121_PKT_NULL_HB(n) (0x138 + (n)) 172 #define IT66121_PKT_NULL_PB(n) (0x13B + (n)) 173 174 #define IT66121_AVIINFO_DB1_REG 0x158 175 #define IT66121_AVIINFO_DB2_REG 0x159 176 #define IT66121_AVIINFO_DB3_REG 0x15A 177 #define IT66121_AVIINFO_DB4_REG 0x15B 178 #define IT66121_AVIINFO_DB5_REG 0x15C 179 #define IT66121_AVIINFO_CSUM_REG 0x15D 180 #define IT66121_AVIINFO_DB6_REG 0x15E 181 #define IT66121_AVIINFO_DB7_REG 0x15F 182 #define IT66121_AVIINFO_DB8_REG 0x160 183 #define IT66121_AVIINFO_DB9_REG 0x161 184 #define IT66121_AVIINFO_DB10_REG 0x162 185 #define IT66121_AVIINFO_DB11_REG 0x163 186 #define IT66121_AVIINFO_DB12_REG 0x164 187 #define IT66121_AVIINFO_DB13_REG 0x165 188 189 #define IT66121_AVI_INFO_PKT_REG 0xCD 190 #define IT66121_AVI_INFO_PKT_ON BIT(0) 191 #define IT66121_AVI_INFO_PKT_RPT BIT(1) 192 193 #define IT66121_AUD_INFO_PKT_REG 0xCE 194 #define IT66121_AUD_INFO_PKT_ON BIT(0) 195 #define IT66121_AUD_INFO_PKT_RPT BIT(1) 196 197 #define IT66121_AUD_INFO_DB1_REG 0x168 198 #define IT66121_AUD_INFO_CSUM_REG 0x16D 199 200 #define IT66121_HDMI_MODE_REG 0xC0 201 #define IT66121_HDMI_MODE_HDMI BIT(0) 202 #define IT66121_HDMI_MODE_DVI 0 203 204 #define IT66121_SYS_STATUS_REG 0x0E 205 #define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7) 206 #define IT66121_SYS_STATUS_HPDETECT BIT(6) 207 #define IT66121_SYS_STATUS_SENDECTECT BIT(5) 208 #define IT66121_SYS_STATUS_VID_STABLE BIT(4) 209 #define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1) 210 #define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0) 211 212 #define IT66121_DDC_STATUS_REG 0x16 213 #define IT66121_DDC_STATUS_TX_DONE BIT(7) 214 #define IT66121_DDC_STATUS_ACTIVE BIT(6) 215 #define IT66121_DDC_STATUS_NOACK BIT(5) 216 #define IT66121_DDC_STATUS_WAIT_BUS BIT(4) 217 #define IT66121_DDC_STATUS_ARBI_LOSE BIT(3) 218 #define IT66121_DDC_STATUS_FIFO_FULL BIT(2) 219 #define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1) 220 #define IT66121_DDC_STATUS_FIFO_VALID BIT(0) 221 222 #define IT66121_EDID_SLEEP_US 20000 223 #define IT66121_EDID_TIMEOUT_US 200000 224 #define IT66121_EDID_FIFO_SIZE 32 225 226 #define IT66121_CLK_CTRL0_REG 0x58 227 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING BIT(4) 228 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK GENMASK(3, 2) 229 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS (0 << 2) 230 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS BIT(2) 231 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS (2 << 2) 232 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS (3 << 2) 233 #define IT66121_CLK_CTRL0_AUTO_IPCLK BIT(0) 234 #define IT66121_CLK_STATUS1_REG 0x5E 235 #define IT66121_CLK_STATUS2_REG 0x5F 236 237 #define IT66121_AUD_CTRL0_REG 0xE0 238 #define IT66121_AUD_SWL (3 << 6) 239 #define IT66121_AUD_16BIT (0 << 6) 240 #define IT66121_AUD_18BIT BIT(6) 241 #define IT66121_AUD_20BIT (2 << 6) 242 #define IT66121_AUD_24BIT (3 << 6) 243 #define IT66121_AUD_SPDIFTC BIT(5) 244 #define IT66121_AUD_SPDIF BIT(4) 245 #define IT66121_AUD_I2S (0 << 4) 246 #define IT66121_AUD_EN_I2S3 BIT(3) 247 #define IT66121_AUD_EN_I2S2 BIT(2) 248 #define IT66121_AUD_EN_I2S1 BIT(1) 249 #define IT66121_AUD_EN_I2S0 BIT(0) 250 #define IT66121_AUD_CTRL0_AUD_SEL BIT(4) 251 252 #define IT66121_AUD_CTRL1_REG 0xE1 253 #define IT66121_AUD_FIFOMAP_REG 0xE2 254 #define IT66121_AUD_CTRL3_REG 0xE3 255 #define IT66121_AUD_SRCVALID_FLAT_REG 0xE4 256 #define IT66121_AUD_FLAT_SRC0 BIT(4) 257 #define IT66121_AUD_FLAT_SRC1 BIT(5) 258 #define IT66121_AUD_FLAT_SRC2 BIT(6) 259 #define IT66121_AUD_FLAT_SRC3 BIT(7) 260 #define IT66121_AUD_HDAUDIO_REG 0xE5 261 262 #define IT66121_AUD_PKT_CTS0_REG 0x130 263 #define IT66121_AUD_PKT_CTS1_REG 0x131 264 #define IT66121_AUD_PKT_CTS2_REG 0x132 265 #define IT66121_AUD_PKT_N0_REG 0x133 266 #define IT66121_AUD_PKT_N1_REG 0x134 267 #define IT66121_AUD_PKT_N2_REG 0x135 268 269 #define IT66121_AUD_CHST_MODE_REG 0x191 270 #define IT66121_AUD_CHST_CAT_REG 0x192 271 #define IT66121_AUD_CHST_SRCNUM_REG 0x193 272 #define IT66121_AUD_CHST_CHTNUM_REG 0x194 273 #define IT66121_AUD_CHST_CA_FS_REG 0x198 274 #define IT66121_AUD_CHST_OFS_WL_REG 0x199 275 276 #define IT66121_AUD_PKT_CTS_CNT0_REG 0x1A0 277 #define IT66121_AUD_PKT_CTS_CNT1_REG 0x1A1 278 #define IT66121_AUD_PKT_CTS_CNT2_REG 0x1A2 279 280 #define IT66121_AUD_FS_22P05K 0x4 281 #define IT66121_AUD_FS_44P1K 0x0 282 #define IT66121_AUD_FS_88P2K 0x8 283 #define IT66121_AUD_FS_176P4K 0xC 284 #define IT66121_AUD_FS_24K 0x6 285 #define IT66121_AUD_FS_48K 0x2 286 #define IT66121_AUD_FS_96K 0xA 287 #define IT66121_AUD_FS_192K 0xE 288 #define IT66121_AUD_FS_768K 0x9 289 #define IT66121_AUD_FS_32K 0x3 290 #define IT66121_AUD_FS_OTHER 0x1 291 292 #define IT66121_AUD_SWL_21BIT 0xD 293 #define IT66121_AUD_SWL_24BIT 0xB 294 #define IT66121_AUD_SWL_23BIT 0x9 295 #define IT66121_AUD_SWL_22BIT 0x5 296 #define IT66121_AUD_SWL_20BIT 0x3 297 #define IT66121_AUD_SWL_17BIT 0xC 298 #define IT66121_AUD_SWL_19BIT 0x8 299 #define IT66121_AUD_SWL_18BIT 0x4 300 #define IT66121_AUD_SWL_16BIT 0x2 301 #define IT66121_AUD_SWL_NOT_INDICATED 0x0 302 303 #define IT66121_AFE_CLK_HIGH 80000 /* Khz */ 304 305 enum chip_id { 306 ID_IT6610, 307 ID_IT66121, 308 ID_IT66122, 309 }; 310 311 struct it66121_chip_info { 312 enum chip_id id; 313 u16 vid, pid; 314 }; 315 316 struct it66121_ctx { 317 struct regmap *regmap; 318 struct drm_bridge bridge; 319 struct device *dev; 320 struct gpio_desc *gpio_reset; 321 struct i2c_client *client; 322 u32 bus_width; 323 struct mutex lock; /* Protects fields below and device registers */ 324 struct { 325 u8 ch_enable; 326 u8 fs; 327 u8 swl; 328 bool auto_cts; 329 } audio; 330 enum chip_id id; 331 }; 332 333 static const struct regmap_range_cfg it66121_regmap_banks[] = { 334 { 335 .name = "it66121", 336 .range_min = 0x00, 337 .range_max = 0x1FF, 338 .selector_reg = IT66121_CLK_BANK_REG, 339 .selector_mask = 0x1, 340 .selector_shift = 0, 341 .window_start = 0x00, 342 .window_len = 0x100, 343 }, 344 }; 345 346 static const struct regmap_config it66121_regmap_config = { 347 .val_bits = 8, 348 .reg_bits = 8, 349 .max_register = 0x1FF, 350 .ranges = it66121_regmap_banks, 351 .num_ranges = ARRAY_SIZE(it66121_regmap_banks), 352 }; 353 354 static void it66121_hw_reset(struct it66121_ctx *ctx) 355 { 356 gpiod_set_value(ctx->gpio_reset, 1); 357 msleep(20); 358 gpiod_set_value(ctx->gpio_reset, 0); 359 } 360 361 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx) 362 { 363 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST); 364 } 365 366 static inline int it66121_fire_afe(struct it66121_ctx *ctx) 367 { 368 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0); 369 } 370 371 /* TOFIX: Handle YCbCr Input & Output */ 372 static int it66121_configure_input(struct it66121_ctx *ctx) 373 { 374 int ret; 375 u8 mode = IT66121_INPUT_MODE_RGB; 376 377 if (ctx->bus_width == 12) 378 mode |= IT66121_INPUT_MODE_DDR; 379 380 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode); 381 if (ret) 382 return ret; 383 384 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV); 385 } 386 387 /** 388 * it66121_configure_afe() - Configure the analog front end 389 * @ctx: it66121_ctx object 390 * @mode: mode to configure 391 * 392 * RETURNS: 393 * zero if success, a negative error code otherwise. 394 */ 395 static int it66121_configure_afe(struct it66121_ctx *ctx, 396 const struct drm_display_mode *mode) 397 { 398 int ret; 399 400 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 401 IT66121_AFE_DRV_RST); 402 if (ret) 403 return ret; 404 405 if (mode->clock > IT66121_AFE_CLK_HIGH) { 406 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 407 IT66121_AFE_XP_GAINBIT | 408 IT66121_AFE_XP_ENO, 409 IT66121_AFE_XP_GAINBIT); 410 if (ret) 411 return ret; 412 413 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 414 IT66121_AFE_IP_GAINBIT | 415 IT66121_AFE_IP_ER0, 416 IT66121_AFE_IP_GAINBIT); 417 if (ret) 418 return ret; 419 420 if (ctx->id == ID_IT66121 || ctx->id == ID_IT66122) { 421 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 422 IT66121_AFE_IP_EC1, 0); 423 if (ret) 424 return ret; 425 426 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 427 IT66121_AFE_XP_EC1_LOWCLK, 0x80); 428 if (ret) 429 return ret; 430 } 431 } else { 432 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 433 IT66121_AFE_XP_GAINBIT | 434 IT66121_AFE_XP_ENO, 435 IT66121_AFE_XP_ENO); 436 if (ret) 437 return ret; 438 439 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 440 IT66121_AFE_IP_GAINBIT | 441 IT66121_AFE_IP_ER0, 442 IT66121_AFE_IP_ER0); 443 if (ret) 444 return ret; 445 446 if (ctx->id == ID_IT66121 || ctx->id == ID_IT66122) { 447 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 448 IT66121_AFE_IP_EC1, 449 IT66121_AFE_IP_EC1); 450 if (ret) 451 return ret; 452 453 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 454 IT66121_AFE_XP_EC1_LOWCLK, 455 IT66121_AFE_XP_EC1_LOWCLK); 456 if (ret) 457 return ret; 458 } 459 } 460 461 /* Clear reset flags */ 462 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 463 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0); 464 if (ret) 465 return ret; 466 467 if (ctx->id == ID_IT6610) { 468 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 469 IT6610_AFE_XP_BYPASS, 470 IT6610_AFE_XP_BYPASS); 471 if (ret) 472 return ret; 473 } 474 475 return it66121_fire_afe(ctx); 476 } 477 478 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx) 479 { 480 int ret, val; 481 u32 error = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS | 482 IT66121_DDC_STATUS_ARBI_LOSE; 483 u32 done = IT66121_DDC_STATUS_TX_DONE; 484 485 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, 486 val & (error | done), IT66121_EDID_SLEEP_US, 487 IT66121_EDID_TIMEOUT_US); 488 if (ret) 489 return ret; 490 491 if (val & error) 492 return -EAGAIN; 493 494 return 0; 495 } 496 497 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx) 498 { 499 int ret; 500 unsigned int swreset, cpdesire; 501 502 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset); 503 if (ret) 504 return ret; 505 506 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire); 507 if (ret) 508 return ret; 509 510 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG, 511 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF)); 512 if (ret) 513 return ret; 514 515 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG, 516 (swreset | IT66121_SW_RST_HDCP)); 517 if (ret) 518 return ret; 519 520 ret = it66121_preamble_ddc(ctx); 521 if (ret) 522 return ret; 523 524 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 525 IT66121_DDC_COMMAND_ABORT); 526 if (ret) 527 return ret; 528 529 return it66121_wait_ddc_ready(ctx); 530 } 531 532 static int it66121_get_edid_block(void *context, u8 *buf, 533 unsigned int block, size_t len) 534 { 535 struct it66121_ctx *ctx = context; 536 int remain = len; 537 int offset = 0; 538 int ret, cnt; 539 540 offset = (block % 2) * len; 541 block = block / 2; 542 543 while (remain > 0) { 544 cnt = (remain > IT66121_EDID_FIFO_SIZE) ? 545 IT66121_EDID_FIFO_SIZE : remain; 546 547 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 548 IT66121_DDC_COMMAND_FIFO_CLR); 549 if (ret) 550 return ret; 551 552 ret = it66121_wait_ddc_ready(ctx); 553 if (ret) 554 return ret; 555 556 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset); 557 if (ret) 558 return ret; 559 560 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt); 561 if (ret) 562 return ret; 563 564 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block); 565 if (ret) 566 return ret; 567 568 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 569 IT66121_DDC_COMMAND_EDID_READ); 570 if (ret) 571 return ret; 572 573 offset += cnt; 574 remain -= cnt; 575 576 ret = it66121_wait_ddc_ready(ctx); 577 if (ret) { 578 it66121_abort_ddc_ops(ctx); 579 return ret; 580 } 581 582 ret = regmap_noinc_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, 583 buf, cnt); 584 if (ret) 585 return ret; 586 587 buf += cnt; 588 } 589 590 return 0; 591 } 592 593 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx) 594 { 595 int val; 596 597 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val)) 598 return false; 599 600 return val & IT66121_SYS_STATUS_HPDETECT; 601 } 602 603 static int it66121_bridge_attach(struct drm_bridge *bridge, 604 struct drm_encoder *encoder, 605 enum drm_bridge_attach_flags flags) 606 { 607 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 608 int ret; 609 610 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 611 return -EINVAL; 612 613 ret = drm_bridge_attach(encoder, ctx->bridge.next_bridge, bridge, flags); 614 if (ret) 615 return ret; 616 617 if (ctx->id == ID_IT66121 || ctx->id == ID_IT66122) { 618 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 619 IT66121_CLK_BANK_PWROFF_RCLK, 0); 620 if (ret) 621 return ret; 622 } 623 624 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG, 625 IT66121_INT_TX_CLK_OFF, 0); 626 if (ret) 627 return ret; 628 629 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 630 IT66121_AFE_DRV_PWD, 0); 631 if (ret) 632 return ret; 633 634 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 635 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0); 636 if (ret) 637 return ret; 638 639 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 640 IT66121_AFE_IP_PWDPLL, 0); 641 if (ret) 642 return ret; 643 644 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 645 IT66121_AFE_DRV_RST, 0); 646 if (ret) 647 return ret; 648 649 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 650 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB); 651 if (ret) 652 return ret; 653 654 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 655 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB); 656 if (ret) 657 return ret; 658 659 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 660 IT66121_SW_RST_REF, 661 IT66121_SW_RST_REF); 662 if (ret) 663 return ret; 664 665 /* Per programming manual, sleep here for bridge to settle */ 666 msleep(50); 667 668 return 0; 669 } 670 671 static void it66121_set_mode(struct it66121_ctx *ctx, 672 struct drm_connector *connector, 673 struct drm_atomic_commit *state) 674 { 675 const struct drm_connector_state *conn_state; 676 const struct drm_crtc_state *crtc_state; 677 const struct drm_display_mode *mode; 678 struct drm_crtc *crtc; 679 680 conn_state = drm_atomic_get_new_connector_state(state, connector); 681 if (WARN_ON(!conn_state)) 682 return; 683 684 crtc = conn_state->crtc; 685 if (WARN_ON(!crtc)) 686 return; 687 688 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 689 if (WARN_ON(!crtc_state)) 690 return; 691 692 mode = &crtc_state->adjusted_mode; 693 694 mutex_lock(&ctx->lock); 695 696 /* Set TX mode to HDMI or DVI */ 697 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, 698 connector->display_info.is_hdmi ? 699 IT66121_HDMI_MODE_HDMI : IT66121_HDMI_MODE_DVI)) 700 goto unlock; 701 702 if ((ctx->id == ID_IT66121 || ctx->id == ID_IT66122) && 703 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 704 IT66121_CLK_BANK_PWROFF_TXCLK, 705 IT66121_CLK_BANK_PWROFF_TXCLK)) { 706 goto unlock; 707 } 708 709 if (it66121_configure_input(ctx)) 710 goto unlock; 711 712 if (it66121_configure_afe(ctx, mode)) 713 goto unlock; 714 715 if ((ctx->id == ID_IT66121 || ctx->id == ID_IT66122) && 716 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 717 IT66121_CLK_BANK_PWROFF_TXCLK, 0)) { 718 goto unlock; 719 } 720 721 unlock: 722 mutex_unlock(&ctx->lock); 723 } 724 725 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute) 726 { 727 int ret; 728 unsigned int val = 0; 729 730 if (mute) 731 val = IT66121_AV_MUTE_ON; 732 733 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val); 734 if (ret) 735 return ret; 736 737 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG, 738 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT); 739 } 740 741 #define MAX_OUTPUT_SEL_FORMATS 1 742 743 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 744 struct drm_bridge_state *bridge_state, 745 struct drm_crtc_state *crtc_state, 746 struct drm_connector_state *conn_state, 747 unsigned int *num_output_fmts) 748 { 749 u32 *output_fmts; 750 751 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 752 GFP_KERNEL); 753 if (!output_fmts) 754 return NULL; 755 756 /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */ 757 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 758 *num_output_fmts = 1; 759 760 return output_fmts; 761 } 762 763 #define MAX_INPUT_SEL_FORMATS 1 764 765 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 766 struct drm_bridge_state *bridge_state, 767 struct drm_crtc_state *crtc_state, 768 struct drm_connector_state *conn_state, 769 u32 output_fmt, 770 unsigned int *num_input_fmts) 771 { 772 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 773 u32 *input_fmts; 774 775 *num_input_fmts = 0; 776 777 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 778 GFP_KERNEL); 779 if (!input_fmts) 780 return NULL; 781 782 if (ctx->bus_width == 12) 783 /* IT66121FN Datasheet specifies Little-Endian ordering */ 784 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; 785 else 786 /* TOFIX support more input bus formats in 24bit width */ 787 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 788 *num_input_fmts = 1; 789 790 return input_fmts; 791 } 792 793 static void it66121_bridge_enable(struct drm_bridge *bridge, 794 struct drm_atomic_commit *state) 795 { 796 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 797 struct drm_connector *connector; 798 799 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 800 if (WARN_ON(!connector)) 801 return; 802 803 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 804 805 it66121_set_mode(ctx, connector, state); 806 it66121_set_mute(ctx, false); 807 } 808 809 static void it66121_bridge_disable(struct drm_bridge *bridge, 810 struct drm_atomic_commit *state) 811 { 812 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 813 814 it66121_set_mute(ctx, true); 815 } 816 817 static int it66121_bridge_check(struct drm_bridge *bridge, 818 struct drm_bridge_state *bridge_state, 819 struct drm_crtc_state *crtc_state, 820 struct drm_connector_state *conn_state) 821 { 822 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 823 824 if (ctx->id == ID_IT6610) { 825 /* The IT6610 only supports these settings */ 826 bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH | 827 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE; 828 bridge_state->input_bus_cfg.flags &= 829 ~DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE; 830 } 831 832 return 0; 833 } 834 835 static enum drm_connector_status 836 it66121_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 837 { 838 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 839 840 return it66121_is_hpd_detect(ctx) ? connector_status_connected 841 : connector_status_disconnected; 842 } 843 844 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge) 845 { 846 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 847 int ret; 848 849 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0); 850 if (ret) 851 dev_err(ctx->dev, "failed to enable HPD IRQ\n"); 852 } 853 854 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge) 855 { 856 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 857 int ret; 858 859 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 860 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD); 861 if (ret) 862 dev_err(ctx->dev, "failed to disable HPD IRQ\n"); 863 } 864 865 static enum drm_mode_status 866 it66121_bridge_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, 867 const struct drm_display_mode *mode, 868 unsigned long long tmds_rate) 869 { 870 const struct it66121_ctx *ctx = 871 container_of(bridge, const struct it66121_ctx, bridge); 872 unsigned long long max_rate; 873 874 max_rate = (ctx->bus_width == 12) ? 74250000ULL : 148500000ULL; 875 876 if (tmds_rate > max_rate) 877 return MODE_CLOCK_HIGH; 878 879 if (tmds_rate < HDMI_TMDS_CHAR_RATE_MIN_HZ) 880 return MODE_CLOCK_LOW; 881 882 return MODE_OK; 883 } 884 885 static int it66121_bridge_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) 886 { 887 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 888 889 /* Clear both IT66121_AVI_INFO_PKT_ON and IT66121_AVI_INFO_PKT_RPT */ 890 return regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG, 0); 891 } 892 893 static int it66121_bridge_hdmi_write_avi_infoframe(struct drm_bridge *bridge, 894 const u8 *buffer, size_t len) 895 { 896 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 897 int ret; 898 899 mutex_lock(&ctx->lock); 900 901 /* Write new AVI infoframe packet */ 902 ret = regmap_bulk_write(ctx->regmap, IT66121_AVIINFO_DB1_REG, 903 &buffer[HDMI_INFOFRAME_HEADER_SIZE], 904 HDMI_AVI_INFOFRAME_SIZE); 905 if (ret) 906 goto unlock; 907 908 ret = regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buffer[3]); 909 if (ret) 910 goto unlock; 911 912 /* Enable AVI infoframe */ 913 ret = regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG, 914 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT); 915 916 unlock: 917 mutex_unlock(&ctx->lock); 918 return ret; 919 } 920 921 static int it66121_bridge_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) 922 { 923 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 924 925 /* Clear both IT66121_PKT_NULL_CTRL_ON and IT66121_PKT_NULL_CTRL_RPT */ 926 return regmap_write(ctx->regmap, IT66121_PKT_NULL_CTRL_REG, 0); 927 } 928 929 static int it66121_bridge_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, 930 const u8 *buffer, size_t len) 931 { 932 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 933 int ret; 934 935 mutex_lock(&ctx->lock); 936 937 /* Write new HDMI Vendor Specific Infoframe packet */ 938 ret = regmap_bulk_write(ctx->regmap, IT66121_PKT_NULL_HB(0), buffer, len); 939 if (ret) 940 goto unlock; 941 942 /* Enable HDMI Vendor Specific Infoframe */ 943 ret = regmap_write(ctx->regmap, IT66121_PKT_NULL_CTRL_REG, 944 IT66121_PKT_NULL_CTRL_ON | IT66121_PKT_NULL_CTRL_RPT); 945 946 unlock: 947 mutex_unlock(&ctx->lock); 948 return ret; 949 } 950 951 static int it66121_bridge_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) 952 { 953 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 954 955 /* Clear both IT66121_AUD_INFO_PKT_ON and IT66121_AUD_INFO_PKT_RPT */ 956 return regmap_write(ctx->regmap, IT66121_AUD_INFO_PKT_REG, 0); 957 } 958 959 static int it66121_bridge_hdmi_write_audio_infoframe(struct drm_bridge *bridge, 960 const u8 *buffer, size_t len) 961 { 962 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 963 int ret; 964 965 mutex_lock(&ctx->lock); 966 967 /* Write new Audio infoframe packet */ 968 ret = regmap_bulk_write(ctx->regmap, IT66121_AUD_INFO_DB1_REG, 969 &buffer[HDMI_INFOFRAME_HEADER_SIZE], 970 min_t(size_t, len - HDMI_INFOFRAME_HEADER_SIZE, 5)); 971 if (ret) 972 goto unlock; 973 974 ret = regmap_write(ctx->regmap, IT66121_AUD_INFO_CSUM_REG, buffer[3]); 975 if (ret) 976 goto unlock; 977 978 /* Enable Audio infoframe */ 979 ret = regmap_write(ctx->regmap, IT66121_AUD_INFO_PKT_REG, 980 IT66121_AUD_INFO_PKT_ON | IT66121_AUD_INFO_PKT_RPT); 981 982 unlock: 983 mutex_unlock(&ctx->lock); 984 return ret; 985 } 986 987 static const struct drm_edid *it66121_bridge_edid_read(struct drm_bridge *bridge, 988 struct drm_connector *connector) 989 { 990 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 991 const struct drm_edid *drm_edid; 992 int ret; 993 994 mutex_lock(&ctx->lock); 995 ret = it66121_preamble_ddc(ctx); 996 if (ret) { 997 drm_edid = NULL; 998 goto out_unlock; 999 } 1000 1001 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG, 1002 IT66121_DDC_HEADER_EDID); 1003 if (ret) { 1004 drm_edid = NULL; 1005 goto out_unlock; 1006 } 1007 1008 drm_edid = drm_edid_read_custom(connector, it66121_get_edid_block, ctx); 1009 1010 out_unlock: 1011 mutex_unlock(&ctx->lock); 1012 1013 return drm_edid; 1014 } 1015 1016 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id) 1017 { 1018 int ret; 1019 unsigned int val; 1020 struct it66121_ctx *ctx = dev_id; 1021 struct device *dev = ctx->dev; 1022 enum drm_connector_status status; 1023 bool event = false; 1024 1025 mutex_lock(&ctx->lock); 1026 1027 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val); 1028 if (ret) 1029 goto unlock; 1030 1031 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ)) 1032 goto unlock; 1033 1034 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 1035 if (ret) { 1036 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret); 1037 } else if (val & IT66121_INT_STATUS1_HPD_STATUS) { 1038 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG, 1039 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD); 1040 1041 status = it66121_is_hpd_detect(ctx) ? connector_status_connected 1042 : connector_status_disconnected; 1043 1044 event = true; 1045 } 1046 1047 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG, 1048 IT66121_SYS_STATUS_CLEAR_IRQ, 1049 IT66121_SYS_STATUS_CLEAR_IRQ); 1050 1051 unlock: 1052 mutex_unlock(&ctx->lock); 1053 1054 if (event) 1055 drm_bridge_hpd_notify(&ctx->bridge, status); 1056 1057 return IRQ_HANDLED; 1058 } 1059 1060 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[]) 1061 { 1062 int ret; 1063 1064 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C); 1065 if (ret) 1066 return ret; 1067 1068 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]); 1069 if (ret) 1070 return ret; 1071 1072 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F); 1073 if (ret) 1074 return ret; 1075 1076 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG, 1077 (iec60958_chstat[2] >> 4) & 0x0F); 1078 if (ret) 1079 return ret; 1080 1081 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]); 1082 if (ret) 1083 return ret; 1084 1085 return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]); 1086 } 1087 1088 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl) 1089 { 1090 int ret; 1091 unsigned int audio_enable = 0; 1092 unsigned int audio_format = 0; 1093 1094 switch (audio_swl) { 1095 case 16: 1096 audio_enable |= IT66121_AUD_16BIT; 1097 break; 1098 case 18: 1099 audio_enable |= IT66121_AUD_18BIT; 1100 break; 1101 case 20: 1102 audio_enable |= IT66121_AUD_20BIT; 1103 break; 1104 case 24: 1105 default: 1106 audio_enable |= IT66121_AUD_24BIT; 1107 break; 1108 } 1109 1110 audio_format |= 0x40; 1111 switch (audio_src_num) { 1112 case 4: 1113 audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1114 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1115 break; 1116 case 3: 1117 audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 | 1118 IT66121_AUD_EN_I2S0; 1119 break; 1120 case 2: 1121 audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1122 break; 1123 case 1: 1124 default: 1125 audio_format &= ~0x40; 1126 audio_enable |= IT66121_AUD_EN_I2S0; 1127 break; 1128 } 1129 1130 audio_format |= 0x01; 1131 ctx->audio.ch_enable = audio_enable; 1132 1133 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0); 1134 if (ret) 1135 return ret; 1136 1137 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format); 1138 if (ret) 1139 return ret; 1140 1141 ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4); 1142 if (ret) 1143 return ret; 1144 1145 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00); 1146 if (ret) 1147 return ret; 1148 1149 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00); 1150 if (ret) 1151 return ret; 1152 1153 return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00); 1154 } 1155 1156 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs) 1157 { 1158 int ret; 1159 unsigned int n; 1160 1161 switch (fs) { 1162 case IT66121_AUD_FS_32K: 1163 n = 4096; 1164 break; 1165 case IT66121_AUD_FS_44P1K: 1166 n = 6272; 1167 break; 1168 case IT66121_AUD_FS_48K: 1169 n = 6144; 1170 break; 1171 case IT66121_AUD_FS_88P2K: 1172 n = 12544; 1173 break; 1174 case IT66121_AUD_FS_96K: 1175 n = 12288; 1176 break; 1177 case IT66121_AUD_FS_176P4K: 1178 n = 25088; 1179 break; 1180 case IT66121_AUD_FS_192K: 1181 n = 24576; 1182 break; 1183 case IT66121_AUD_FS_768K: 1184 n = 24576; 1185 break; 1186 default: 1187 n = 6144; 1188 break; 1189 } 1190 1191 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF)); 1192 if (ret) 1193 return ret; 1194 1195 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF)); 1196 if (ret) 1197 return ret; 1198 1199 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF)); 1200 if (ret) 1201 return ret; 1202 1203 if (ctx->audio.auto_cts) { 1204 u8 loop_cnt = 255; 1205 u8 cts_stable_cnt = 0; 1206 unsigned int sum_cts = 0; 1207 unsigned int cts = 0; 1208 unsigned int last_cts = 0; 1209 unsigned int diff; 1210 unsigned int val; 1211 1212 while (loop_cnt--) { 1213 msleep(30); 1214 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val); 1215 cts = val << 12; 1216 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val); 1217 cts |= val << 4; 1218 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val); 1219 cts |= val >> 4; 1220 if (cts == 0) { 1221 continue; 1222 } else { 1223 if (last_cts > cts) 1224 diff = last_cts - cts; 1225 else 1226 diff = cts - last_cts; 1227 last_cts = cts; 1228 if (diff < 5) { 1229 cts_stable_cnt++; 1230 sum_cts += cts; 1231 } else { 1232 cts_stable_cnt = 0; 1233 sum_cts = 0; 1234 continue; 1235 } 1236 1237 if (cts_stable_cnt >= 32) { 1238 last_cts = (sum_cts >> 5); 1239 break; 1240 } 1241 } 1242 } 1243 1244 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF)); 1245 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF)); 1246 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F)); 1247 } 1248 1249 ret = regmap_write(ctx->regmap, 0xF8, 0xC3); 1250 if (ret) 1251 return ret; 1252 1253 ret = regmap_write(ctx->regmap, 0xF8, 0xA5); 1254 if (ret) 1255 return ret; 1256 1257 if (ctx->audio.auto_cts) { 1258 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1259 IT66121_PKT_CTS_CTRL_SEL, 1260 1); 1261 } else { 1262 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1263 IT66121_PKT_CTS_CTRL_SEL, 1264 0); 1265 } 1266 1267 if (ret) 1268 return ret; 1269 1270 return regmap_write(ctx->regmap, 0xF8, 0xFF); 1271 } 1272 1273 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable) 1274 { 1275 int ret; 1276 1277 if (enable) { 1278 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1279 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1280 0); 1281 if (ret) 1282 return ret; 1283 1284 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1285 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1286 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1287 ctx->audio.ch_enable); 1288 } else { 1289 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1290 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1291 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1292 ctx->audio.ch_enable & 0xF0); 1293 if (ret) 1294 return ret; 1295 1296 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1297 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1298 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF); 1299 } 1300 1301 return ret; 1302 } 1303 1304 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable) 1305 { 1306 int ret; 1307 1308 if (enable) { 1309 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0); 1310 if (ret) 1311 return ret; 1312 1313 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable); 1314 } else { 1315 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0); 1316 } 1317 1318 return ret; 1319 } 1320 1321 static int it66121_hdmi_audio_prepare(struct drm_bridge *bridge, 1322 struct drm_connector *connector, 1323 struct hdmi_codec_daifmt *daifmt, 1324 struct hdmi_codec_params *params) 1325 { 1326 u8 fs; 1327 u8 swl; 1328 int ret; 1329 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 1330 struct device *dev = ctx->dev; 1331 static u8 iec60958_chstat[5]; 1332 unsigned int channels = params->channels; 1333 unsigned int sample_rate = params->sample_rate; 1334 unsigned int sample_width = params->sample_width; 1335 1336 mutex_lock(&ctx->lock); 1337 dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__, 1338 daifmt->fmt, sample_rate, sample_width, channels); 1339 1340 switch (daifmt->fmt) { 1341 case HDMI_I2S: 1342 dev_dbg(dev, "Using HDMI I2S\n"); 1343 break; 1344 default: 1345 dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt); 1346 ret = -EINVAL; 1347 goto out; 1348 } 1349 1350 // Set audio clock recovery (N/CTS) 1351 ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG, 1352 IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING | 1353 IT66121_CLK_CTRL0_EXT_MCLK_256FS | 1354 IT66121_CLK_CTRL0_AUTO_IPCLK); 1355 if (ret) 1356 goto out; 1357 1358 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1359 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection 1360 if (ret) 1361 goto out; 1362 1363 switch (sample_rate) { 1364 case 44100L: 1365 fs = IT66121_AUD_FS_44P1K; 1366 break; 1367 case 88200L: 1368 fs = IT66121_AUD_FS_88P2K; 1369 break; 1370 case 176400L: 1371 fs = IT66121_AUD_FS_176P4K; 1372 break; 1373 case 32000L: 1374 fs = IT66121_AUD_FS_32K; 1375 break; 1376 case 48000L: 1377 fs = IT66121_AUD_FS_48K; 1378 break; 1379 case 96000L: 1380 fs = IT66121_AUD_FS_96K; 1381 break; 1382 case 192000L: 1383 fs = IT66121_AUD_FS_192K; 1384 break; 1385 case 768000L: 1386 fs = IT66121_AUD_FS_768K; 1387 break; 1388 default: 1389 fs = IT66121_AUD_FS_48K; 1390 break; 1391 } 1392 1393 ctx->audio.fs = fs; 1394 ret = it661221_set_ncts(ctx, fs); 1395 if (ret) { 1396 dev_err(dev, "Failed to set N/CTS: %d\n", ret); 1397 goto out; 1398 } 1399 1400 // Set audio format register (except audio channel enable) 1401 ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width); 1402 if (ret) { 1403 dev_err(dev, "Failed to set LPCM audio: %d\n", ret); 1404 goto out; 1405 } 1406 1407 // Set audio channel status 1408 iec60958_chstat[0] = 0; 1409 if ((channels + 1) / 2 == 1) 1410 iec60958_chstat[0] |= 0x1; 1411 iec60958_chstat[0] &= ~(1 << 1); 1412 iec60958_chstat[1] = 0; 1413 iec60958_chstat[2] = (channels + 1) / 2; 1414 iec60958_chstat[2] |= (channels << 4) & 0xF0; 1415 iec60958_chstat[3] = fs; 1416 1417 switch (sample_width) { 1418 case 21L: 1419 swl = IT66121_AUD_SWL_21BIT; 1420 break; 1421 case 24L: 1422 swl = IT66121_AUD_SWL_24BIT; 1423 break; 1424 case 23L: 1425 swl = IT66121_AUD_SWL_23BIT; 1426 break; 1427 case 22L: 1428 swl = IT66121_AUD_SWL_22BIT; 1429 break; 1430 case 20L: 1431 swl = IT66121_AUD_SWL_20BIT; 1432 break; 1433 case 17L: 1434 swl = IT66121_AUD_SWL_17BIT; 1435 break; 1436 case 19L: 1437 swl = IT66121_AUD_SWL_19BIT; 1438 break; 1439 case 18L: 1440 swl = IT66121_AUD_SWL_18BIT; 1441 break; 1442 case 16L: 1443 swl = IT66121_AUD_SWL_16BIT; 1444 break; 1445 default: 1446 swl = IT66121_AUD_SWL_NOT_INDICATED; 1447 break; 1448 } 1449 1450 iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl; 1451 ret = it661221_set_chstat(ctx, iec60958_chstat); 1452 if (ret) { 1453 dev_err(dev, "Failed to set channel status: %d\n", ret); 1454 goto out; 1455 } 1456 1457 // Enable audio channel enable while input clock stable (if SPDIF). 1458 ret = it661221_audio_ch_enable(ctx, true); 1459 if (ret) { 1460 dev_err(dev, "Failed to enable audio channel: %d\n", ret); 1461 goto out; 1462 } 1463 1464 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 1465 IT66121_INT_MASK1_AUD_OVF, 1466 0); 1467 if (ret) 1468 goto out; 1469 1470 dev_dbg(dev, "HDMI audio enabled.\n"); 1471 out: 1472 mutex_unlock(&ctx->lock); 1473 1474 if (!ret) 1475 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 1476 ¶ms->cea); 1477 1478 return ret; 1479 } 1480 1481 static int it66121_hdmi_audio_startup(struct drm_bridge *bridge, 1482 struct drm_connector *connector) 1483 { 1484 int ret; 1485 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 1486 1487 mutex_lock(&ctx->lock); 1488 ret = it661221_audio_output_enable(ctx, true); 1489 if (ret) 1490 dev_err(ctx->dev, "Failed to enable audio output: %d\n", ret); 1491 1492 mutex_unlock(&ctx->lock); 1493 1494 return ret; 1495 } 1496 1497 static void it66121_hdmi_audio_shutdown(struct drm_bridge *bridge, 1498 struct drm_connector *connector) 1499 { 1500 int ret; 1501 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 1502 1503 drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); 1504 1505 mutex_lock(&ctx->lock); 1506 ret = it661221_audio_output_enable(ctx, false); 1507 if (ret) 1508 dev_err(ctx->dev, "Failed to disable audio output: %d\n", ret); 1509 1510 mutex_unlock(&ctx->lock); 1511 } 1512 1513 static int it66121_hdmi_audio_mute_stream(struct drm_bridge *bridge, 1514 struct drm_connector *connector, 1515 bool enable, int direction) 1516 { 1517 int ret; 1518 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 1519 1520 dev_dbg(ctx->dev, "%s: enable=%s, direction=%d\n", 1521 __func__, enable ? "true" : "false", direction); 1522 1523 mutex_lock(&ctx->lock); 1524 1525 if (enable) { 1526 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1527 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1528 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1529 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1530 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3); 1531 } else { 1532 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1533 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1534 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1535 0); 1536 } 1537 1538 mutex_unlock(&ctx->lock); 1539 1540 return ret; 1541 } 1542 1543 static const struct drm_bridge_funcs it66121_bridge_funcs = { 1544 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1545 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1546 .atomic_reset = drm_atomic_helper_bridge_reset, 1547 .attach = it66121_bridge_attach, 1548 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts, 1549 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts, 1550 .atomic_enable = it66121_bridge_enable, 1551 .atomic_disable = it66121_bridge_disable, 1552 .atomic_check = it66121_bridge_check, 1553 .detect = it66121_bridge_detect, 1554 .edid_read = it66121_bridge_edid_read, 1555 .hpd_enable = it66121_bridge_hpd_enable, 1556 .hpd_disable = it66121_bridge_hpd_disable, 1557 .hdmi_tmds_char_rate_valid = it66121_bridge_hdmi_tmds_char_rate_valid, 1558 .hdmi_clear_avi_infoframe = it66121_bridge_hdmi_clear_avi_infoframe, 1559 .hdmi_write_avi_infoframe = it66121_bridge_hdmi_write_avi_infoframe, 1560 .hdmi_clear_hdmi_infoframe = it66121_bridge_hdmi_clear_hdmi_infoframe, 1561 .hdmi_write_hdmi_infoframe = it66121_bridge_hdmi_write_hdmi_infoframe, 1562 .hdmi_clear_audio_infoframe = it66121_bridge_hdmi_clear_audio_infoframe, 1563 .hdmi_write_audio_infoframe = it66121_bridge_hdmi_write_audio_infoframe, 1564 .hdmi_audio_startup = it66121_hdmi_audio_startup, 1565 .hdmi_audio_prepare = it66121_hdmi_audio_prepare, 1566 .hdmi_audio_shutdown = it66121_hdmi_audio_shutdown, 1567 .hdmi_audio_mute_stream = it66121_hdmi_audio_mute_stream, 1568 }; 1569 1570 static const char * const it66121_supplies[] = { 1571 "vcn33", "vcn18", "vrf12" 1572 }; 1573 1574 static const struct it66121_chip_info it66xx_chip_info[] = { 1575 {.id = ID_IT6610, .vid = 0xca00, .pid = 0x0611 }, 1576 {.id = ID_IT66121, .vid = 0x4954, .pid = 0x0612 }, 1577 {.id = ID_IT66122, .vid = 0x4954, .pid = 0x0622 }, 1578 }; 1579 1580 static int it66121_probe(struct i2c_client *client) 1581 { 1582 u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 }; 1583 struct device_node *ep; 1584 int ret, i; 1585 struct it66121_ctx *ctx; 1586 struct device *dev = &client->dev; 1587 const struct it66121_chip_info *chip_info; 1588 1589 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1590 dev_err(dev, "I2C check functionality failed.\n"); 1591 return -ENXIO; 1592 } 1593 1594 ctx = devm_drm_bridge_alloc(dev, struct it66121_ctx, bridge, 1595 &it66121_bridge_funcs); 1596 if (IS_ERR(ctx)) 1597 return PTR_ERR(ctx); 1598 1599 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 1600 if (!ep) 1601 return -EINVAL; 1602 1603 ctx->dev = dev; 1604 ctx->client = client; 1605 1606 of_property_read_u32(ep, "bus-width", &ctx->bus_width); 1607 of_node_put(ep); 1608 1609 if (ctx->bus_width != 12 && ctx->bus_width != 24) 1610 return -EINVAL; 1611 1612 ep = of_graph_get_remote_node(dev->of_node, 1, -1); 1613 if (!ep) { 1614 dev_err(ctx->dev, "The endpoint is unconnected\n"); 1615 return -EINVAL; 1616 } 1617 1618 ctx->bridge.next_bridge = of_drm_find_and_get_bridge(ep); 1619 of_node_put(ep); 1620 if (!ctx->bridge.next_bridge) { 1621 dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n"); 1622 return -EPROBE_DEFER; 1623 } 1624 1625 i2c_set_clientdata(client, ctx); 1626 mutex_init(&ctx->lock); 1627 1628 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it66121_supplies), 1629 it66121_supplies); 1630 if (ret) { 1631 dev_err(dev, "Failed to enable power supplies\n"); 1632 return ret; 1633 } 1634 1635 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1636 if (IS_ERR(ctx->gpio_reset)) 1637 return dev_err_probe(dev, PTR_ERR(ctx->gpio_reset), 1638 "Failed to get reset GPIO\n"); 1639 1640 it66121_hw_reset(ctx); 1641 1642 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config); 1643 if (IS_ERR(ctx->regmap)) 1644 return PTR_ERR(ctx->regmap); 1645 1646 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]); 1647 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]); 1648 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]); 1649 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]); 1650 1651 /* Revision is shared with DEVICE_ID1 */ 1652 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); 1653 device_ids[1] &= IT66121_DEVICE_ID1_MASK; 1654 1655 for (i = 0; i < ARRAY_SIZE(it66xx_chip_info); i++) { 1656 chip_info = &it66xx_chip_info[i]; 1657 if ((vendor_ids[1] << 8 | vendor_ids[0]) == chip_info->vid && 1658 (device_ids[1] << 8 | device_ids[0]) == chip_info->pid) { 1659 ctx->id = chip_info->id; 1660 break; 1661 } 1662 } 1663 1664 if (i == ARRAY_SIZE(it66xx_chip_info)) 1665 return -ENODEV; 1666 1667 ctx->bridge.of_node = dev->of_node; 1668 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1669 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | 1670 DRM_BRIDGE_OP_HDMI; 1671 ctx->bridge.vendor = "ITE"; 1672 ctx->bridge.product = "IT66121"; 1673 if (client->irq > 0) { 1674 ctx->bridge.ops |= DRM_BRIDGE_OP_HPD; 1675 1676 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1677 it66121_irq_threaded_handler, 1678 IRQF_ONESHOT, dev_name(dev), 1679 ctx); 1680 if (ret < 0) { 1681 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret); 1682 return ret; 1683 } 1684 } 1685 1686 if (of_property_present(dev->of_node, "#sound-dai-cells")) { 1687 ctx->bridge.ops |= DRM_BRIDGE_OP_HDMI_AUDIO; 1688 ctx->bridge.hdmi_audio_dev = dev; 1689 ctx->bridge.hdmi_audio_max_i2s_playback_channels = 8; 1690 /* of-graph not supported, phandle match only */ 1691 ctx->bridge.hdmi_audio_dai_port = -1; 1692 } else { 1693 dev_info(dev, "No \"#sound-dai-cells\", no audio\n"); 1694 } 1695 1696 drm_bridge_add(&ctx->bridge); 1697 1698 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id); 1699 1700 return 0; 1701 } 1702 1703 static void it66121_remove(struct i2c_client *client) 1704 { 1705 struct it66121_ctx *ctx = i2c_get_clientdata(client); 1706 1707 drm_bridge_remove(&ctx->bridge); 1708 mutex_destroy(&ctx->lock); 1709 } 1710 1711 static const struct of_device_id it66121_dt_match[] = { 1712 { .compatible = "ite,it6610" }, 1713 { .compatible = "ite,it66121" }, 1714 { .compatible = "ite,it66122" }, 1715 { } 1716 }; 1717 MODULE_DEVICE_TABLE(of, it66121_dt_match); 1718 1719 static const struct i2c_device_id it66121_id[] = { 1720 { .name = "it6610" }, 1721 { .name = "it66121" }, 1722 { .name = "it66122" }, 1723 { } 1724 }; 1725 MODULE_DEVICE_TABLE(i2c, it66121_id); 1726 1727 static struct i2c_driver it66121_driver = { 1728 .driver = { 1729 .name = "it66121", 1730 .of_match_table = it66121_dt_match, 1731 }, 1732 .probe = it66121_probe, 1733 .remove = it66121_remove, 1734 .id_table = it66121_id, 1735 }; 1736 1737 module_i2c_driver(it66121_driver); 1738 1739 MODULE_AUTHOR("Phong LE"); 1740 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver"); 1741 MODULE_LICENSE("GPL v2"); 1742