1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include "system_local.h" 17 18 /* ISP */ 19 const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { 20 0x0000000000020000ULL 21 }; 22 23 const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { 24 0x0000000000200000ULL 25 }; 26 27 const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { 28 0x0000000000100000ULL 29 }; 30 31 /* SP */ 32 const hrt_address SP_CTRL_BASE[N_SP_ID] = { 33 0x0000000000010000ULL 34 }; 35 36 const hrt_address SP_DMEM_BASE[N_SP_ID] = { 37 0x0000000000300000ULL 38 }; 39 40 /* MMU */ 41 /* 42 * MMU0_ID: The data MMU 43 * MMU1_ID: The icache MMU 44 */ 45 const hrt_address MMU_BASE[N_MMU_ID] = { 46 0x0000000000070000ULL, 47 0x00000000000A0000ULL 48 }; 49 50 /* DMA */ 51 const hrt_address DMA_BASE[N_DMA_ID] = { 52 0x0000000000040000ULL 53 }; 54 55 const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { 56 0x00000000000CA000ULL 57 }; 58 59 /* IRQ */ 60 const hrt_address IRQ_BASE[N_IRQ_ID] = { 61 0x0000000000000500ULL, 62 0x0000000000030A00ULL, 63 0x000000000008C000ULL, 64 0x0000000000090200ULL 65 }; 66 67 /* 68 0x0000000000000500ULL}; 69 */ 70 71 /* GDC */ 72 const hrt_address GDC_BASE[N_GDC_ID] = { 73 0x0000000000050000ULL, 74 0x0000000000060000ULL 75 }; 76 77 /* FIFO_MONITOR (not a subset of GP_DEVICE) */ 78 const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { 79 0x0000000000000000ULL 80 }; 81 82 /* 83 const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { 84 0x0000000000000000ULL}; 85 86 const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { 87 0x0000000000090000ULL}; 88 */ 89 90 /* GP_DEVICE (single base for all separate GP_REG instances) */ 91 const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { 92 0x0000000000000000ULL 93 }; 94 95 /*GP TIMER , all timer registers are inter-twined, 96 * so, having multiple base addresses for 97 * different timers does not help*/ 98 const hrt_address GP_TIMER_BASE = 99 (hrt_address)0x0000000000000600ULL; 100 101 /* GPIO */ 102 const hrt_address GPIO_BASE[N_GPIO_ID] = { 103 0x0000000000000400ULL 104 }; 105 106 /* TIMED_CTRL */ 107 const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { 108 0x0000000000000100ULL 109 }; 110 111 /* INPUT_FORMATTER */ 112 const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { 113 0x0000000000030000ULL, 114 0x0000000000030200ULL, 115 0x0000000000030400ULL, 116 0x0000000000030600ULL 117 }; /* memcpy() */ 118 119 /* INPUT_SYSTEM */ 120 const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { 121 0x0000000000080000ULL 122 }; 123 124 /* 0x0000000000081000ULL, */ /* capture A */ 125 /* 0x0000000000082000ULL, */ /* capture B */ 126 /* 0x0000000000083000ULL, */ /* capture C */ 127 /* 0x0000000000084000ULL, */ /* Acquisition */ 128 /* 0x0000000000085000ULL, */ /* DMA */ 129 /* 0x0000000000089000ULL, */ /* ctrl */ 130 /* 0x000000000008A000ULL, */ /* GP regs */ 131 /* 0x000000000008B000ULL, */ /* FIFO */ 132 /* 0x000000000008C000ULL, */ /* IRQ */ 133 134 /* RX, the MIPI lane control regs start at offset 0 */ 135 const hrt_address RX_BASE[N_RX_ID] = { 136 0x0000000000080100ULL 137 }; 138 139 /* IBUF_CTRL, part of the Input System 2401 */ 140 const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { 141 0x00000000000C1800ULL, /* ibuf controller A */ 142 0x00000000000C3800ULL, /* ibuf controller B */ 143 0x00000000000C5800ULL /* ibuf controller C */ 144 }; 145 146 /* ISYS IRQ Controllers, part of the Input System 2401 */ 147 const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { 148 0x00000000000C1400ULL, /* port a */ 149 0x00000000000C3400ULL, /* port b */ 150 0x00000000000C5400ULL /* port c */ 151 }; 152 153 /* CSI FE, part of the Input System 2401 */ 154 const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { 155 0x00000000000C0400ULL, /* csi fe controller A */ 156 0x00000000000C2400ULL, /* csi fe controller B */ 157 0x00000000000C4400ULL /* csi fe controller C */ 158 }; 159 160 /* CSI BE, part of the Input System 2401 */ 161 const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { 162 0x00000000000C0800ULL, /* csi be controller A */ 163 0x00000000000C2800ULL, /* csi be controller B */ 164 0x00000000000C4800ULL /* csi be controller C */ 165 }; 166 167 /* PIXEL Generator, part of the Input System 2401 */ 168 const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { 169 0x00000000000C1000ULL, /* pixel gen controller A */ 170 0x00000000000C3000ULL, /* pixel gen controller B */ 171 0x00000000000C5000ULL /* pixel gen controller C */ 172 }; 173 174 /* Stream2MMIO, part of the Input System 2401 */ 175 const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { 176 0x00000000000C0C00ULL, /* stream2mmio controller A */ 177 0x00000000000C2C00ULL, /* stream2mmio controller B */ 178 0x00000000000C4C00ULL /* stream2mmio controller C */ 179 }; 180