1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "gfx_v12_1.h" 83 #include "sdma_v5_0.h" 84 #include "sdma_v5_2.h" 85 #include "sdma_v6_0.h" 86 #include "sdma_v7_0.h" 87 #include "sdma_v7_1.h" 88 #include "lsdma_v6_0.h" 89 #include "lsdma_v7_0.h" 90 #include "vcn_v2_0.h" 91 #include "jpeg_v2_0.h" 92 #include "vcn_v3_0.h" 93 #include "jpeg_v3_0.h" 94 #include "vcn_v4_0.h" 95 #include "jpeg_v4_0.h" 96 #include "vcn_v4_0_3.h" 97 #include "jpeg_v4_0_3.h" 98 #include "vcn_v4_0_5.h" 99 #include "jpeg_v4_0_5.h" 100 #include "amdgpu_vkms.h" 101 #include "mes_v11_0.h" 102 #include "mes_v12_0.h" 103 #include "mes_v12_1.h" 104 #include "smuio_v11_0.h" 105 #include "smuio_v11_0_6.h" 106 #include "smuio_v13_0.h" 107 #include "smuio_v13_0_3.h" 108 #include "smuio_v13_0_6.h" 109 #include "smuio_v14_0_2.h" 110 #include "smuio_v15_0_0.h" 111 #include "smuio_v15_0_8.h" 112 #include "vcn_v5_0_0.h" 113 #include "vcn_v5_0_1.h" 114 #include "jpeg_v5_0_0.h" 115 #include "jpeg_v5_0_1.h" 116 #include "jpeg_v5_3_0.h" 117 118 #include "amdgpu_ras_mgr.h" 119 120 #include "amdgpu_vpe.h" 121 #if defined(CONFIG_DRM_AMD_ISP) 122 #include "amdgpu_isp.h" 123 #endif 124 125 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 126 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 127 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 128 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 134 135 #define mmIP_DISCOVERY_VERSION 0x16A00 136 #define mmRCC_CONFIG_MEMSIZE 0xde3 137 #define mmMP0_SMN_C2PMSG_33 0x16061 138 #define mmMM_INDEX 0x0 139 #define mmMM_INDEX_HI 0x6 140 #define mmMM_DATA 0x1 141 142 static const char *hw_id_names[HW_ID_MAX] = { 143 [MP1_HWID] = "MP1", 144 [MP2_HWID] = "MP2", 145 [THM_HWID] = "THM", 146 [SMUIO_HWID] = "SMUIO", 147 [FUSE_HWID] = "FUSE", 148 [CLKA_HWID] = "CLKA", 149 [PWR_HWID] = "PWR", 150 [GC_HWID] = "GC", 151 [UVD_HWID] = "UVD", 152 [AUDIO_AZ_HWID] = "AUDIO_AZ", 153 [ACP_HWID] = "ACP", 154 [DCI_HWID] = "DCI", 155 [DMU_HWID] = "DMU", 156 [DCO_HWID] = "DCO", 157 [DIO_HWID] = "DIO", 158 [XDMA_HWID] = "XDMA", 159 [DCEAZ_HWID] = "DCEAZ", 160 [DAZ_HWID] = "DAZ", 161 [SDPMUX_HWID] = "SDPMUX", 162 [NTB_HWID] = "NTB", 163 [IOHC_HWID] = "IOHC", 164 [L2IMU_HWID] = "L2IMU", 165 [VCE_HWID] = "VCE", 166 [MMHUB_HWID] = "MMHUB", 167 [ATHUB_HWID] = "ATHUB", 168 [DBGU_NBIO_HWID] = "DBGU_NBIO", 169 [DFX_HWID] = "DFX", 170 [DBGU0_HWID] = "DBGU0", 171 [DBGU1_HWID] = "DBGU1", 172 [OSSSYS_HWID] = "OSSSYS", 173 [HDP_HWID] = "HDP", 174 [SDMA0_HWID] = "SDMA0", 175 [SDMA1_HWID] = "SDMA1", 176 [SDMA2_HWID] = "SDMA2", 177 [SDMA3_HWID] = "SDMA3", 178 [LSDMA_HWID] = "LSDMA", 179 [ISP_HWID] = "ISP", 180 [DBGU_IO_HWID] = "DBGU_IO", 181 [DF_HWID] = "DF", 182 [CLKB_HWID] = "CLKB", 183 [FCH_HWID] = "FCH", 184 [DFX_DAP_HWID] = "DFX_DAP", 185 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 186 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 187 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 188 [L1IMU3_HWID] = "L1IMU3", 189 [L1IMU4_HWID] = "L1IMU4", 190 [L1IMU5_HWID] = "L1IMU5", 191 [L1IMU6_HWID] = "L1IMU6", 192 [L1IMU7_HWID] = "L1IMU7", 193 [L1IMU8_HWID] = "L1IMU8", 194 [L1IMU9_HWID] = "L1IMU9", 195 [L1IMU10_HWID] = "L1IMU10", 196 [L1IMU11_HWID] = "L1IMU11", 197 [L1IMU12_HWID] = "L1IMU12", 198 [L1IMU13_HWID] = "L1IMU13", 199 [L1IMU14_HWID] = "L1IMU14", 200 [L1IMU15_HWID] = "L1IMU15", 201 [WAFLC_HWID] = "WAFLC", 202 [FCH_USB_PD_HWID] = "FCH_USB_PD", 203 [PCIE_HWID] = "PCIE", 204 [PCS_HWID] = "PCS", 205 [DDCL_HWID] = "DDCL", 206 [SST_HWID] = "SST", 207 [IOAGR_HWID] = "IOAGR", 208 [NBIF_HWID] = "NBIF", 209 [IOAPIC_HWID] = "IOAPIC", 210 [SYSTEMHUB_HWID] = "SYSTEMHUB", 211 [NTBCCP_HWID] = "NTBCCP", 212 [UMC_HWID] = "UMC", 213 [SATA_HWID] = "SATA", 214 [USB_HWID] = "USB", 215 [CCXSEC_HWID] = "CCXSEC", 216 [XGMI_HWID] = "XGMI", 217 [XGBE_HWID] = "XGBE", 218 [MP0_HWID] = "MP0", 219 [VPE_HWID] = "VPE", 220 [ATU_HWID] = "ATU", 221 [AIGC_HWID] = "AIGC", 222 }; 223 224 static int hw_id_map[MAX_HWIP] = { 225 [GC_HWIP] = GC_HWID, 226 [HDP_HWIP] = HDP_HWID, 227 [SDMA0_HWIP] = SDMA0_HWID, 228 [SDMA1_HWIP] = SDMA1_HWID, 229 [SDMA2_HWIP] = SDMA2_HWID, 230 [SDMA3_HWIP] = SDMA3_HWID, 231 [LSDMA_HWIP] = LSDMA_HWID, 232 [MMHUB_HWIP] = MMHUB_HWID, 233 [ATHUB_HWIP] = ATHUB_HWID, 234 [NBIO_HWIP] = NBIF_HWID, 235 [MP0_HWIP] = MP0_HWID, 236 [MP1_HWIP] = MP1_HWID, 237 [UVD_HWIP] = UVD_HWID, 238 [VCE_HWIP] = VCE_HWID, 239 [DF_HWIP] = DF_HWID, 240 [DCE_HWIP] = DMU_HWID, 241 [OSSSYS_HWIP] = OSSSYS_HWID, 242 [SMUIO_HWIP] = SMUIO_HWID, 243 [PWR_HWIP] = PWR_HWID, 244 [NBIF_HWIP] = NBIF_HWID, 245 [THM_HWIP] = THM_HWID, 246 [CLK_HWIP] = CLKA_HWID, 247 [UMC_HWIP] = UMC_HWID, 248 [XGMI_HWIP] = XGMI_HWID, 249 [DCI_HWIP] = DCI_HWID, 250 [PCIE_HWIP] = PCIE_HWID, 251 [VPE_HWIP] = VPE_HWID, 252 [ISP_HWIP] = ISP_HWID, 253 [ATU_HWIP] = ATU_HWID, 254 }; 255 256 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 257 { 258 u64 tmr_offset, tmr_size, pos; 259 void *discv_regn; 260 int ret; 261 262 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 263 if (ret) 264 return ret; 265 266 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 267 268 /* This region is read-only and reserved from system use */ 269 discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); 270 if (discv_regn) { 271 memcpy(binary, discv_regn, adev->discovery.size); 272 memunmap(discv_regn); 273 return 0; 274 } 275 276 return -ENOENT; 277 } 278 279 #define IP_DISCOVERY_V2 2 280 #define IP_DISCOVERY_V4 4 281 282 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 283 uint8_t *binary) 284 { 285 bool sz_valid = true; 286 uint64_t vram_size; 287 int i, ret = 0; 288 u32 msg; 289 290 if (!amdgpu_sriov_vf(adev)) { 291 /* It can take up to two second for IFWI init to complete on some dGPUs, 292 * but generally it should be in the 60-100ms range. Normally this starts 293 * as soon as the device gets power so by the time the OS loads this has long 294 * completed. However, when a card is hotplugged via e.g., USB4, we need to 295 * wait for this to complete. Once the C2PMSG is updated, we can 296 * continue. 297 */ 298 299 for (i = 0; i < 2000; i++) { 300 msg = RREG32(mmMP0_SMN_C2PMSG_33); 301 if (msg & 0x80000000) 302 break; 303 msleep(1); 304 } 305 } 306 307 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 308 if (!vram_size || vram_size == U32_MAX) 309 sz_valid = false; 310 else 311 vram_size <<= 20; 312 313 /* 314 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, 315 * then it is not required to be reserved. 316 */ 317 if (sz_valid) { 318 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 319 /* For SRIOV VFs with dynamic critical region enabled, 320 * we will get the IPD binary via below call. 321 * If dynamic critical is disabled, fall through to normal seq. 322 */ 323 if (amdgpu_virt_get_dynamic_data_info(adev, 324 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 325 &adev->discovery.size)) { 326 dev_err(adev->dev, 327 "failed to read discovery info from dynamic critical region."); 328 ret = -EINVAL; 329 goto exit; 330 } 331 } else { 332 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 333 334 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 335 adev->discovery.size, false); 336 adev->discovery.reserve_tmr = true; 337 } 338 } else { 339 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 340 } 341 342 if (ret) 343 dev_err(adev->dev, 344 "failed to read discovery info from memory, vram size read: %llx", 345 vram_size); 346 exit: 347 return ret; 348 } 349 350 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 351 uint8_t *binary, 352 const char *fw_name) 353 { 354 const struct firmware *fw; 355 int r; 356 357 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 358 if (r) { 359 if (amdgpu_discovery == 2) 360 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 361 else 362 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 363 return r; 364 } 365 366 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 367 release_firmware(fw); 368 369 return 0; 370 } 371 372 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 373 { 374 uint16_t checksum = 0; 375 int i; 376 377 for (i = 0; i < size; i++) 378 checksum += data[i]; 379 380 return checksum; 381 } 382 383 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 384 uint8_t *data, uint32_t size, 385 uint16_t expected) 386 { 387 uint16_t calculated; 388 389 calculated = amdgpu_discovery_calculate_checksum(data, size); 390 391 if (calculated != expected) { 392 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 393 calculated, expected, size); 394 return false; 395 } 396 397 return true; 398 } 399 400 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 401 { 402 struct binary_header *bhdr; 403 bhdr = (struct binary_header *)binary; 404 405 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 406 } 407 408 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 409 { 410 /* 411 * So far, apply this quirk only on those Navy Flounder boards which 412 * have a bad harvest table of VCN config. 413 */ 414 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 415 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 416 switch (adev->pdev->revision) { 417 case 0xC1: 418 case 0xC2: 419 case 0xC3: 420 case 0xC5: 421 case 0xC7: 422 case 0xCF: 423 case 0xDF: 424 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 425 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 426 break; 427 default: 428 break; 429 } 430 } 431 } 432 433 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 434 struct binary_header *bhdr) 435 { 436 uint8_t *discovery_bin = adev->discovery.bin; 437 struct table_info *info; 438 uint16_t checksum; 439 uint16_t offset; 440 441 info = &bhdr->table_list[NPS_INFO]; 442 offset = le16_to_cpu(info->offset); 443 checksum = le16_to_cpu(info->checksum); 444 445 struct nps_info_header *nhdr = 446 (struct nps_info_header *)(discovery_bin + offset); 447 448 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 449 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 450 return -EINVAL; 451 } 452 453 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 454 le32_to_cpu(nhdr->size_bytes), 455 checksum)) { 456 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 464 { 465 if (amdgpu_discovery == 2) { 466 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 467 adev->discovery.reserve_tmr = true; 468 return "amdgpu/ip_discovery.bin"; 469 } 470 471 switch (adev->asic_type) { 472 case CHIP_VEGA10: 473 return "amdgpu/vega10_ip_discovery.bin"; 474 case CHIP_VEGA12: 475 return "amdgpu/vega12_ip_discovery.bin"; 476 case CHIP_RAVEN: 477 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 478 return "amdgpu/raven2_ip_discovery.bin"; 479 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 480 return "amdgpu/picasso_ip_discovery.bin"; 481 else 482 return "amdgpu/raven_ip_discovery.bin"; 483 case CHIP_VEGA20: 484 return "amdgpu/vega20_ip_discovery.bin"; 485 case CHIP_ARCTURUS: 486 return "amdgpu/arcturus_ip_discovery.bin"; 487 case CHIP_ALDEBARAN: 488 return "amdgpu/aldebaran_ip_discovery.bin"; 489 default: 490 return NULL; 491 } 492 } 493 494 static int amdgpu_discovery_init(struct amdgpu_device *adev) 495 { 496 struct table_info *info; 497 struct binary_header *bhdr; 498 uint8_t *discovery_bin; 499 const char *fw_name; 500 uint16_t offset; 501 uint16_t size; 502 uint16_t checksum; 503 int r; 504 505 adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 506 if (!adev->discovery.bin) 507 return -ENOMEM; 508 adev->discovery.size = DISCOVERY_TMR_SIZE; 509 adev->discovery.debugfs_blob.data = adev->discovery.bin; 510 adev->discovery.debugfs_blob.size = adev->discovery.size; 511 512 discovery_bin = adev->discovery.bin; 513 /* Read from file if it is the preferred option */ 514 fw_name = amdgpu_discovery_get_fw_name(adev); 515 if (fw_name != NULL) { 516 drm_dbg(&adev->ddev, "use ip discovery information from file"); 517 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 518 fw_name); 519 if (r) 520 goto out; 521 } else { 522 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 523 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); 524 if (r) 525 goto out; 526 } 527 528 /* check the ip discovery binary signature */ 529 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 530 dev_err(adev->dev, 531 "get invalid ip discovery binary signature\n"); 532 r = -EINVAL; 533 goto out; 534 } 535 536 bhdr = (struct binary_header *)discovery_bin; 537 538 offset = offsetof(struct binary_header, binary_checksum) + 539 sizeof(bhdr->binary_checksum); 540 size = le16_to_cpu(bhdr->binary_size) - offset; 541 checksum = le16_to_cpu(bhdr->binary_checksum); 542 543 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 544 checksum)) { 545 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 546 r = -EINVAL; 547 goto out; 548 } 549 550 info = &bhdr->table_list[IP_DISCOVERY]; 551 offset = le16_to_cpu(info->offset); 552 checksum = le16_to_cpu(info->checksum); 553 554 if (offset) { 555 struct ip_discovery_header *ihdr = 556 (struct ip_discovery_header *)(discovery_bin + offset); 557 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 558 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 559 r = -EINVAL; 560 goto out; 561 } 562 563 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 564 le16_to_cpu(ihdr->size), 565 checksum)) { 566 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 567 r = -EINVAL; 568 goto out; 569 } 570 } 571 572 info = &bhdr->table_list[GC]; 573 offset = le16_to_cpu(info->offset); 574 checksum = le16_to_cpu(info->checksum); 575 576 if (offset) { 577 struct gpu_info_header *ghdr = 578 (struct gpu_info_header *)(discovery_bin + offset); 579 580 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 581 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 582 r = -EINVAL; 583 goto out; 584 } 585 586 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 587 le32_to_cpu(ghdr->size), 588 checksum)) { 589 dev_err(adev->dev, "invalid gc data table checksum\n"); 590 r = -EINVAL; 591 goto out; 592 } 593 } 594 595 info = &bhdr->table_list[HARVEST_INFO]; 596 offset = le16_to_cpu(info->offset); 597 checksum = le16_to_cpu(info->checksum); 598 599 if (offset) { 600 struct harvest_info_header *hhdr = 601 (struct harvest_info_header *)(discovery_bin + offset); 602 603 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 604 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 605 r = -EINVAL; 606 goto out; 607 } 608 609 if (!amdgpu_discovery_verify_checksum(adev, 610 discovery_bin + offset, 611 sizeof(struct harvest_table), checksum)) { 612 dev_err(adev->dev, "invalid harvest data table checksum\n"); 613 r = -EINVAL; 614 goto out; 615 } 616 } 617 618 info = &bhdr->table_list[VCN_INFO]; 619 offset = le16_to_cpu(info->offset); 620 checksum = le16_to_cpu(info->checksum); 621 622 if (offset) { 623 struct vcn_info_header *vhdr = 624 (struct vcn_info_header *)(discovery_bin + offset); 625 626 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 627 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 628 r = -EINVAL; 629 goto out; 630 } 631 632 if (!amdgpu_discovery_verify_checksum(adev, 633 discovery_bin + offset, 634 le32_to_cpu(vhdr->size_bytes), checksum)) { 635 dev_err(adev->dev, "invalid vcn data table checksum\n"); 636 r = -EINVAL; 637 goto out; 638 } 639 } 640 641 info = &bhdr->table_list[MALL_INFO]; 642 offset = le16_to_cpu(info->offset); 643 checksum = le16_to_cpu(info->checksum); 644 645 if (0 && offset) { 646 struct mall_info_header *mhdr = 647 (struct mall_info_header *)(discovery_bin + offset); 648 649 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 650 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 651 r = -EINVAL; 652 goto out; 653 } 654 655 if (!amdgpu_discovery_verify_checksum(adev, 656 discovery_bin + offset, 657 le32_to_cpu(mhdr->size_bytes), checksum)) { 658 dev_err(adev->dev, "invalid mall data table checksum\n"); 659 r = -EINVAL; 660 goto out; 661 } 662 } 663 664 return 0; 665 666 out: 667 kfree(adev->discovery.bin); 668 adev->discovery.bin = NULL; 669 if ((amdgpu_discovery != 2) && 670 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 671 amdgpu_ras_query_boot_status(adev, 4); 672 return r; 673 } 674 675 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 676 677 void amdgpu_discovery_fini(struct amdgpu_device *adev) 678 { 679 amdgpu_discovery_sysfs_fini(adev); 680 kfree(adev->discovery.bin); 681 adev->discovery.bin = NULL; 682 } 683 684 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 685 uint8_t instance, uint16_t hw_id) 686 { 687 if (instance >= HWIP_MAX_INSTANCE) { 688 dev_err(adev->dev, 689 "Unexpected instance_number (%d) from ip discovery blob\n", 690 instance); 691 return -EINVAL; 692 } 693 if (hw_id >= HW_ID_MAX) { 694 dev_err(adev->dev, 695 "Unexpected hw_id (%d) from ip discovery blob\n", 696 hw_id); 697 return -EINVAL; 698 } 699 700 return 0; 701 } 702 703 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 704 uint32_t *vcn_harvest_count) 705 { 706 uint8_t *discovery_bin = adev->discovery.bin; 707 struct binary_header *bhdr; 708 struct ip_discovery_header *ihdr; 709 struct die_header *dhdr; 710 struct ip *ip; 711 uint16_t die_offset, ip_offset, num_dies, num_ips; 712 uint16_t hw_id; 713 uint8_t inst; 714 int i, j; 715 716 bhdr = (struct binary_header *)discovery_bin; 717 ihdr = (struct ip_discovery_header 718 *)(discovery_bin + 719 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 720 num_dies = le16_to_cpu(ihdr->num_dies); 721 722 /* scan harvest bit of all IP data structures */ 723 for (i = 0; i < num_dies; i++) { 724 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 725 dhdr = (struct die_header *)(discovery_bin + die_offset); 726 num_ips = le16_to_cpu(dhdr->num_ips); 727 ip_offset = die_offset + sizeof(*dhdr); 728 729 for (j = 0; j < num_ips; j++) { 730 ip = (struct ip *)(discovery_bin + ip_offset); 731 inst = ip->number_instance; 732 hw_id = le16_to_cpu(ip->hw_id); 733 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 734 goto next_ip; 735 736 if (ip->harvest == 1) { 737 switch (hw_id) { 738 case VCN_HWID: 739 (*vcn_harvest_count)++; 740 if (inst == 0) { 741 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 742 adev->vcn.inst_mask &= 743 ~AMDGPU_VCN_HARVEST_VCN0; 744 adev->jpeg.inst_mask &= 745 ~AMDGPU_VCN_HARVEST_VCN0; 746 } else { 747 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 748 adev->vcn.inst_mask &= 749 ~AMDGPU_VCN_HARVEST_VCN1; 750 adev->jpeg.inst_mask &= 751 ~AMDGPU_VCN_HARVEST_VCN1; 752 } 753 break; 754 case DMU_HWID: 755 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 756 break; 757 default: 758 break; 759 } 760 } 761 next_ip: 762 ip_offset += struct_size(ip, base_address, 763 ip->num_base_address); 764 } 765 } 766 } 767 768 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 769 uint32_t *vcn_harvest_count, 770 uint32_t *umc_harvest_count) 771 { 772 uint8_t *discovery_bin = adev->discovery.bin; 773 struct binary_header *bhdr; 774 struct harvest_table *harvest_info; 775 u16 offset; 776 int i; 777 uint32_t umc_harvest_config = 0; 778 779 bhdr = (struct binary_header *)discovery_bin; 780 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 781 782 if (!offset) { 783 dev_err(adev->dev, "invalid harvest table offset\n"); 784 return; 785 } 786 787 harvest_info = (struct harvest_table *)(discovery_bin + offset); 788 789 for (i = 0; i < 32; i++) { 790 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 791 break; 792 793 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 794 case VCN_HWID: 795 (*vcn_harvest_count)++; 796 adev->vcn.harvest_config |= 797 (1 << harvest_info->list[i].number_instance); 798 adev->jpeg.harvest_config |= 799 (1 << harvest_info->list[i].number_instance); 800 801 adev->vcn.inst_mask &= 802 ~(1U << harvest_info->list[i].number_instance); 803 adev->jpeg.inst_mask &= 804 ~(1U << harvest_info->list[i].number_instance); 805 break; 806 case DMU_HWID: 807 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 808 break; 809 case UMC_HWID: 810 umc_harvest_config |= 811 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 812 (*umc_harvest_count)++; 813 break; 814 case GC_HWID: 815 adev->gfx.xcc_mask &= 816 ~(1U << harvest_info->list[i].number_instance); 817 break; 818 case SDMA0_HWID: 819 adev->sdma.sdma_mask &= 820 ~(1U << harvest_info->list[i].number_instance); 821 break; 822 #if defined(CONFIG_DRM_AMD_ISP) 823 case ISP_HWID: 824 adev->isp.harvest_config |= 825 ~(1U << harvest_info->list[i].number_instance); 826 break; 827 #endif 828 default: 829 break; 830 } 831 } 832 833 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 834 ~umc_harvest_config; 835 } 836 837 /* ================================================== */ 838 839 struct ip_hw_instance { 840 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 841 842 int hw_id; 843 u8 num_instance; 844 u8 major, minor, revision; 845 u8 harvest; 846 847 int num_base_addresses; 848 u32 base_addr[] __counted_by(num_base_addresses); 849 }; 850 851 struct ip_hw_id { 852 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 853 int hw_id; 854 }; 855 856 struct ip_die_entry { 857 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 858 u16 num_ips; 859 }; 860 861 /* -------------------------------------------------- */ 862 863 struct ip_hw_instance_attr { 864 struct attribute attr; 865 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 866 }; 867 868 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 869 { 870 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 871 } 872 873 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 874 { 875 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 876 } 877 878 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 879 { 880 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 881 } 882 883 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 884 { 885 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 886 } 887 888 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 889 { 890 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 891 } 892 893 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 894 { 895 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 896 } 897 898 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 899 { 900 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 901 } 902 903 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 904 { 905 ssize_t at; 906 int ii; 907 908 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 909 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 910 */ 911 if (at + 12 > PAGE_SIZE) 912 break; 913 at += sysfs_emit_at(buf, at, "0x%08X\n", 914 ip_hw_instance->base_addr[ii]); 915 } 916 917 return at; 918 } 919 920 static struct ip_hw_instance_attr ip_hw_attr[] = { 921 __ATTR_RO(hw_id), 922 __ATTR_RO(num_instance), 923 __ATTR_RO(major), 924 __ATTR_RO(minor), 925 __ATTR_RO(revision), 926 __ATTR_RO(harvest), 927 __ATTR_RO(num_base_addresses), 928 __ATTR_RO(base_addr), 929 }; 930 931 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 932 ATTRIBUTE_GROUPS(ip_hw_instance); 933 934 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 935 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 936 937 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 938 struct attribute *attr, 939 char *buf) 940 { 941 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 942 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 943 944 if (!ip_hw_attr->show) 945 return -EIO; 946 947 return ip_hw_attr->show(ip_hw_instance, buf); 948 } 949 950 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 951 .show = ip_hw_instance_attr_show, 952 }; 953 954 static void ip_hw_instance_release(struct kobject *kobj) 955 { 956 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 957 958 kfree(ip_hw_instance); 959 } 960 961 static const struct kobj_type ip_hw_instance_ktype = { 962 .release = ip_hw_instance_release, 963 .sysfs_ops = &ip_hw_instance_sysfs_ops, 964 .default_groups = ip_hw_instance_groups, 965 }; 966 967 /* -------------------------------------------------- */ 968 969 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 970 971 static void ip_hw_id_release(struct kobject *kobj) 972 { 973 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 974 975 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 976 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 977 kfree(ip_hw_id); 978 } 979 980 static const struct kobj_type ip_hw_id_ktype = { 981 .release = ip_hw_id_release, 982 .sysfs_ops = &kobj_sysfs_ops, 983 }; 984 985 /* -------------------------------------------------- */ 986 987 static void die_kobj_release(struct kobject *kobj); 988 static void ip_disc_release(struct kobject *kobj); 989 990 struct ip_die_entry_attribute { 991 struct attribute attr; 992 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 993 }; 994 995 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 996 997 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 998 { 999 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1000 } 1001 1002 /* If there are more ip_die_entry attrs, other than the number of IPs, 1003 * we can make this intro an array of attrs, and then initialize 1004 * ip_die_entry_attrs in a loop. 1005 */ 1006 static struct ip_die_entry_attribute num_ips_attr = 1007 __ATTR_RO(num_ips); 1008 1009 static struct attribute *ip_die_entry_attrs[] = { 1010 &num_ips_attr.attr, 1011 NULL, 1012 }; 1013 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1014 1015 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1016 1017 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1018 struct attribute *attr, 1019 char *buf) 1020 { 1021 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1022 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1023 1024 if (!ip_die_entry_attr->show) 1025 return -EIO; 1026 1027 return ip_die_entry_attr->show(ip_die_entry, buf); 1028 } 1029 1030 static void ip_die_entry_release(struct kobject *kobj) 1031 { 1032 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1033 1034 if (!list_empty(&ip_die_entry->ip_kset.list)) 1035 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1036 kfree(ip_die_entry); 1037 } 1038 1039 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1040 .show = ip_die_entry_attr_show, 1041 }; 1042 1043 static const struct kobj_type ip_die_entry_ktype = { 1044 .release = ip_die_entry_release, 1045 .sysfs_ops = &ip_die_entry_sysfs_ops, 1046 .default_groups = ip_die_entry_groups, 1047 }; 1048 1049 static const struct kobj_type die_kobj_ktype = { 1050 .release = die_kobj_release, 1051 .sysfs_ops = &kobj_sysfs_ops, 1052 }; 1053 1054 static const struct kobj_type ip_discovery_ktype = { 1055 .release = ip_disc_release, 1056 .sysfs_ops = &kobj_sysfs_ops, 1057 }; 1058 1059 struct ip_discovery_top { 1060 struct kobject kobj; /* ip_discovery/ */ 1061 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1062 struct amdgpu_device *adev; 1063 }; 1064 1065 static void die_kobj_release(struct kobject *kobj) 1066 { 1067 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1068 struct ip_discovery_top, 1069 die_kset); 1070 if (!list_empty(&ip_top->die_kset.list)) 1071 DRM_ERROR("ip_top->die_kset is not empty"); 1072 } 1073 1074 static void ip_disc_release(struct kobject *kobj) 1075 { 1076 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1077 kobj); 1078 struct amdgpu_device *adev = ip_top->adev; 1079 1080 kfree(ip_top); 1081 adev->discovery.ip_top = NULL; 1082 } 1083 1084 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1085 uint16_t hw_id, uint8_t inst) 1086 { 1087 uint8_t harvest = 0; 1088 1089 /* Until a uniform way is figured, get mask based on hwid */ 1090 switch (hw_id) { 1091 case VCN_HWID: 1092 /* VCN vs UVD+VCE */ 1093 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1094 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1095 break; 1096 case DMU_HWID: 1097 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1098 harvest = 0x1; 1099 break; 1100 case UMC_HWID: 1101 /* TODO: It needs another parsing; for now, ignore.*/ 1102 break; 1103 case GC_HWID: 1104 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1105 break; 1106 case SDMA0_HWID: 1107 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 return harvest; 1114 } 1115 1116 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1117 struct ip_die_entry *ip_die_entry, 1118 const size_t _ip_offset, const int num_ips, 1119 bool reg_base_64) 1120 { 1121 uint8_t *discovery_bin = adev->discovery.bin; 1122 int ii, jj, kk, res; 1123 uint16_t hw_id; 1124 uint8_t inst; 1125 1126 DRM_DEBUG("num_ips:%d", num_ips); 1127 1128 /* Find all IPs of a given HW ID, and add their instance to 1129 * #die/#hw_id/#instance/<attributes> 1130 */ 1131 for (ii = 0; ii < HW_ID_MAX; ii++) { 1132 struct ip_hw_id *ip_hw_id = NULL; 1133 size_t ip_offset = _ip_offset; 1134 1135 for (jj = 0; jj < num_ips; jj++) { 1136 struct ip_v4 *ip; 1137 struct ip_hw_instance *ip_hw_instance; 1138 1139 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1140 inst = ip->instance_number; 1141 hw_id = le16_to_cpu(ip->hw_id); 1142 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1143 hw_id != ii) 1144 goto next_ip; 1145 1146 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1147 1148 /* We have a hw_id match; register the hw 1149 * block if not yet registered. 1150 */ 1151 if (!ip_hw_id) { 1152 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1153 if (!ip_hw_id) 1154 return -ENOMEM; 1155 ip_hw_id->hw_id = ii; 1156 1157 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1158 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1159 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1160 res = kset_register(&ip_hw_id->hw_id_kset); 1161 if (res) { 1162 DRM_ERROR("Couldn't register ip_hw_id kset"); 1163 kfree(ip_hw_id); 1164 return res; 1165 } 1166 if (hw_id_names[ii]) { 1167 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1168 &ip_hw_id->hw_id_kset.kobj, 1169 hw_id_names[ii]); 1170 if (res) { 1171 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1172 hw_id_names[ii], 1173 kobject_name(&ip_die_entry->ip_kset.kobj)); 1174 } 1175 } 1176 } 1177 1178 /* Now register its instance. 1179 */ 1180 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1181 base_addr, 1182 ip->num_base_address), 1183 GFP_KERNEL); 1184 if (!ip_hw_instance) { 1185 DRM_ERROR("no memory for ip_hw_instance"); 1186 return -ENOMEM; 1187 } 1188 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1189 ip_hw_instance->num_instance = ip->instance_number; 1190 ip_hw_instance->major = ip->major; 1191 ip_hw_instance->minor = ip->minor; 1192 ip_hw_instance->revision = ip->revision; 1193 ip_hw_instance->harvest = 1194 amdgpu_discovery_get_harvest_info( 1195 adev, ip_hw_instance->hw_id, 1196 ip_hw_instance->num_instance); 1197 ip_hw_instance->num_base_addresses = ip->num_base_address; 1198 1199 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1200 if (reg_base_64) 1201 ip_hw_instance->base_addr[kk] = 1202 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1203 else 1204 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1205 } 1206 1207 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1208 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1209 res = kobject_add(&ip_hw_instance->kobj, NULL, 1210 "%d", ip_hw_instance->num_instance); 1211 next_ip: 1212 if (reg_base_64) 1213 ip_offset += struct_size(ip, base_address_64, 1214 ip->num_base_address); 1215 else 1216 ip_offset += struct_size(ip, base_address, 1217 ip->num_base_address); 1218 } 1219 } 1220 1221 return 0; 1222 } 1223 1224 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1225 { 1226 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1227 uint8_t *discovery_bin = adev->discovery.bin; 1228 struct binary_header *bhdr; 1229 struct ip_discovery_header *ihdr; 1230 struct die_header *dhdr; 1231 struct kset *die_kset = &ip_top->die_kset; 1232 u16 num_dies, die_offset, num_ips; 1233 size_t ip_offset; 1234 int ii, res; 1235 1236 bhdr = (struct binary_header *)discovery_bin; 1237 ihdr = (struct ip_discovery_header 1238 *)(discovery_bin + 1239 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1240 num_dies = le16_to_cpu(ihdr->num_dies); 1241 1242 DRM_DEBUG("number of dies: %d\n", num_dies); 1243 1244 for (ii = 0; ii < num_dies; ii++) { 1245 struct ip_die_entry *ip_die_entry; 1246 1247 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1248 dhdr = (struct die_header *)(discovery_bin + die_offset); 1249 num_ips = le16_to_cpu(dhdr->num_ips); 1250 ip_offset = die_offset + sizeof(*dhdr); 1251 1252 /* Add the die to the kset. 1253 * 1254 * dhdr->die_id == ii, which was checked in 1255 * amdgpu_discovery_reg_base_init(). 1256 */ 1257 1258 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1259 if (!ip_die_entry) 1260 return -ENOMEM; 1261 1262 ip_die_entry->num_ips = num_ips; 1263 1264 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1265 ip_die_entry->ip_kset.kobj.kset = die_kset; 1266 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1267 res = kset_register(&ip_die_entry->ip_kset); 1268 if (res) { 1269 DRM_ERROR("Couldn't register ip_die_entry kset"); 1270 kfree(ip_die_entry); 1271 return res; 1272 } 1273 1274 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1281 { 1282 uint8_t *discovery_bin = adev->discovery.bin; 1283 struct ip_discovery_top *ip_top; 1284 struct kset *die_kset; 1285 int res, ii; 1286 1287 if (!discovery_bin) 1288 return -EINVAL; 1289 1290 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); 1291 if (!ip_top) 1292 return -ENOMEM; 1293 1294 ip_top->adev = adev; 1295 adev->discovery.ip_top = ip_top; 1296 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1297 &adev->dev->kobj, "ip_discovery"); 1298 if (res) { 1299 DRM_ERROR("Couldn't init and add ip_discovery/"); 1300 goto Err; 1301 } 1302 1303 die_kset = &ip_top->die_kset; 1304 kobject_set_name(&die_kset->kobj, "%s", "die"); 1305 die_kset->kobj.parent = &ip_top->kobj; 1306 die_kset->kobj.ktype = &die_kobj_ktype; 1307 res = kset_register(&ip_top->die_kset); 1308 if (res) { 1309 DRM_ERROR("Couldn't register die_kset"); 1310 goto Err; 1311 } 1312 1313 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1314 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1315 ip_hw_instance_attrs[ii] = NULL; 1316 1317 res = amdgpu_discovery_sysfs_recurse(adev); 1318 1319 return res; 1320 Err: 1321 kobject_put(&ip_top->kobj); 1322 return res; 1323 } 1324 1325 /* -------------------------------------------------- */ 1326 1327 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1328 1329 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1330 { 1331 struct list_head *el, *tmp; 1332 struct kset *hw_id_kset; 1333 1334 hw_id_kset = &ip_hw_id->hw_id_kset; 1335 spin_lock(&hw_id_kset->list_lock); 1336 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1337 list_del_init(el); 1338 spin_unlock(&hw_id_kset->list_lock); 1339 /* kobject is embedded in ip_hw_instance */ 1340 kobject_put(list_to_kobj(el)); 1341 spin_lock(&hw_id_kset->list_lock); 1342 } 1343 spin_unlock(&hw_id_kset->list_lock); 1344 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1345 } 1346 1347 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1348 { 1349 struct list_head *el, *tmp; 1350 struct kset *ip_kset; 1351 1352 ip_kset = &ip_die_entry->ip_kset; 1353 spin_lock(&ip_kset->list_lock); 1354 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1355 list_del_init(el); 1356 spin_unlock(&ip_kset->list_lock); 1357 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1358 spin_lock(&ip_kset->list_lock); 1359 } 1360 spin_unlock(&ip_kset->list_lock); 1361 kobject_put(&ip_die_entry->ip_kset.kobj); 1362 } 1363 1364 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1365 { 1366 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1367 struct list_head *el, *tmp; 1368 struct kset *die_kset; 1369 1370 die_kset = &ip_top->die_kset; 1371 spin_lock(&die_kset->list_lock); 1372 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1373 list_del_init(el); 1374 spin_unlock(&die_kset->list_lock); 1375 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1376 spin_lock(&die_kset->list_lock); 1377 } 1378 spin_unlock(&die_kset->list_lock); 1379 kobject_put(&ip_top->die_kset.kobj); 1380 kobject_put(&ip_top->kobj); 1381 } 1382 1383 /* ================================================== */ 1384 1385 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1386 { 1387 uint8_t num_base_address, subrev, variant; 1388 struct binary_header *bhdr; 1389 struct ip_discovery_header *ihdr; 1390 struct die_header *dhdr; 1391 uint8_t *discovery_bin; 1392 struct ip_v4 *ip; 1393 uint16_t die_offset; 1394 uint16_t ip_offset; 1395 uint16_t num_dies; 1396 uint32_t wafl_ver; 1397 uint16_t num_ips; 1398 uint16_t hw_id; 1399 uint8_t inst; 1400 int hw_ip; 1401 int i, j, k; 1402 int r; 1403 1404 r = amdgpu_discovery_init(adev); 1405 if (r) 1406 return r; 1407 discovery_bin = adev->discovery.bin; 1408 wafl_ver = 0; 1409 adev->gfx.xcc_mask = 0; 1410 adev->sdma.sdma_mask = 0; 1411 adev->vcn.inst_mask = 0; 1412 adev->jpeg.inst_mask = 0; 1413 bhdr = (struct binary_header *)discovery_bin; 1414 ihdr = (struct ip_discovery_header 1415 *)(discovery_bin + 1416 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1417 num_dies = le16_to_cpu(ihdr->num_dies); 1418 1419 DRM_DEBUG("number of dies: %d\n", num_dies); 1420 1421 for (i = 0; i < num_dies; i++) { 1422 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1423 dhdr = (struct die_header *)(discovery_bin + die_offset); 1424 num_ips = le16_to_cpu(dhdr->num_ips); 1425 ip_offset = die_offset + sizeof(*dhdr); 1426 1427 if (le16_to_cpu(dhdr->die_id) != i) { 1428 DRM_ERROR("invalid die id %d, expected %d\n", 1429 le16_to_cpu(dhdr->die_id), i); 1430 return -EINVAL; 1431 } 1432 1433 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1434 le16_to_cpu(dhdr->die_id), num_ips); 1435 1436 for (j = 0; j < num_ips; j++) { 1437 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1438 1439 inst = ip->instance_number; 1440 hw_id = le16_to_cpu(ip->hw_id); 1441 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1442 goto next_ip; 1443 1444 num_base_address = ip->num_base_address; 1445 1446 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1447 hw_id_names[le16_to_cpu(ip->hw_id)], 1448 le16_to_cpu(ip->hw_id), 1449 ip->instance_number, 1450 ip->major, ip->minor, 1451 ip->revision); 1452 1453 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1454 /* Bit [5:0]: original revision value 1455 * Bit [7:6]: en/decode capability: 1456 * 0b00 : VCN function normally 1457 * 0b10 : encode is disabled 1458 * 0b01 : decode is disabled 1459 */ 1460 if (adev->vcn.num_vcn_inst < 1461 AMDGPU_MAX_VCN_INSTANCES) { 1462 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1463 ip->revision & 0xc0; 1464 adev->vcn.num_vcn_inst++; 1465 adev->vcn.inst_mask |= 1466 (1U << ip->instance_number); 1467 adev->jpeg.inst_mask |= 1468 (1U << ip->instance_number); 1469 } else { 1470 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1471 adev->vcn.num_vcn_inst + 1, 1472 AMDGPU_MAX_VCN_INSTANCES); 1473 } 1474 ip->revision &= ~0xc0; 1475 } 1476 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1477 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1478 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1479 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1480 if (adev->sdma.num_instances < 1481 AMDGPU_MAX_SDMA_INSTANCES) { 1482 adev->sdma.num_instances++; 1483 adev->sdma.sdma_mask |= 1484 (1U << ip->instance_number); 1485 } else { 1486 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1487 adev->sdma.num_instances + 1, 1488 AMDGPU_MAX_SDMA_INSTANCES); 1489 } 1490 } 1491 1492 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1493 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1494 adev->vpe.num_instances++; 1495 else 1496 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1497 adev->vpe.num_instances + 1, 1498 AMDGPU_MAX_VPE_INSTANCES); 1499 } 1500 1501 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1502 adev->gmc.num_umc++; 1503 adev->umc.node_inst_num++; 1504 } 1505 1506 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1507 adev->gfx.xcc_mask |= 1508 (1U << ip->instance_number); 1509 1510 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1511 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1512 ip->revision, 0, 0); 1513 1514 for (k = 0; k < num_base_address; k++) { 1515 /* 1516 * convert the endianness of base addresses in place, 1517 * so that we don't need to convert them when accessing adev->reg_offset. 1518 */ 1519 if (ihdr->base_addr_64_bit) 1520 /* Truncate the 64bit base address from ip discovery 1521 * and only store lower 32bit ip base in reg_offset[]. 1522 * Bits > 32 follows ASIC specific format, thus just 1523 * discard them and handle it within specific ASIC. 1524 * By this way reg_offset[] and related helpers can 1525 * stay unchanged. 1526 * The base address is in dwords, thus clear the 1527 * highest 2 bits to store. 1528 */ 1529 ip->base_address[k] = 1530 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1531 else 1532 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1533 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1534 } 1535 1536 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1537 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1538 hw_id_map[hw_ip] != 0) { 1539 DRM_DEBUG("set register base offset for %s\n", 1540 hw_id_names[le16_to_cpu(ip->hw_id)]); 1541 adev->reg_offset[hw_ip][ip->instance_number] = 1542 ip->base_address; 1543 /* Instance support is somewhat inconsistent. 1544 * SDMA is a good example. Sienna cichlid has 4 total 1545 * SDMA instances, each enumerated separately (HWIDs 1546 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1547 * but they are enumerated as multiple instances of the 1548 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1549 * example. On most chips there are multiple instances 1550 * with the same HWID. 1551 */ 1552 1553 if (ihdr->version < 3) { 1554 subrev = 0; 1555 variant = 0; 1556 } else { 1557 subrev = ip->sub_revision; 1558 variant = ip->variant; 1559 } 1560 1561 adev->ip_versions[hw_ip] 1562 [ip->instance_number] = 1563 IP_VERSION_FULL(ip->major, 1564 ip->minor, 1565 ip->revision, 1566 variant, 1567 subrev); 1568 } 1569 } 1570 1571 next_ip: 1572 if (ihdr->base_addr_64_bit) 1573 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1574 else 1575 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1576 } 1577 } 1578 1579 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1580 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1581 1582 return 0; 1583 } 1584 1585 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1586 { 1587 uint8_t *discovery_bin = adev->discovery.bin; 1588 struct ip_discovery_header *ihdr; 1589 struct binary_header *bhdr; 1590 int vcn_harvest_count = 0; 1591 int umc_harvest_count = 0; 1592 uint16_t offset, ihdr_ver; 1593 1594 bhdr = (struct binary_header *)discovery_bin; 1595 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1596 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 1597 ihdr_ver = le16_to_cpu(ihdr->version); 1598 /* 1599 * Harvest table does not fit Navi1x and legacy GPUs, 1600 * so read harvest bit per IP data structure to set 1601 * harvest configuration. 1602 */ 1603 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1604 ihdr_ver <= 2) { 1605 if ((adev->pdev->device == 0x731E && 1606 (adev->pdev->revision == 0xC6 || 1607 adev->pdev->revision == 0xC7)) || 1608 (adev->pdev->device == 0x7340 && 1609 adev->pdev->revision == 0xC9) || 1610 (adev->pdev->device == 0x7360 && 1611 adev->pdev->revision == 0xC7)) 1612 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1613 &vcn_harvest_count); 1614 } else { 1615 amdgpu_discovery_read_from_harvest_table(adev, 1616 &vcn_harvest_count, 1617 &umc_harvest_count); 1618 } 1619 1620 amdgpu_discovery_harvest_config_quirk(adev); 1621 1622 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1623 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1624 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1625 } 1626 1627 if (umc_harvest_count < adev->gmc.num_umc) { 1628 adev->gmc.num_umc -= umc_harvest_count; 1629 } 1630 } 1631 1632 union gc_info { 1633 struct gc_info_v1_0 v1; 1634 struct gc_info_v1_1 v1_1; 1635 struct gc_info_v1_2 v1_2; 1636 struct gc_info_v1_3 v1_3; 1637 struct gc_info_v2_0 v2; 1638 struct gc_info_v2_1 v2_1; 1639 }; 1640 1641 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1642 { 1643 uint8_t *discovery_bin = adev->discovery.bin; 1644 struct binary_header *bhdr; 1645 union gc_info *gc_info; 1646 u16 offset; 1647 1648 if (!discovery_bin) { 1649 DRM_ERROR("ip discovery uninitialized\n"); 1650 return -EINVAL; 1651 } 1652 1653 bhdr = (struct binary_header *)discovery_bin; 1654 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1655 1656 if (!offset) 1657 return 0; 1658 1659 gc_info = (union gc_info *)(discovery_bin + offset); 1660 1661 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1662 case 1: 1663 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1664 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1665 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1666 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1667 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1668 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1669 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1670 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1671 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1672 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1673 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1674 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1675 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1676 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1677 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1678 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1679 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1680 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1681 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1682 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1683 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1684 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1685 } 1686 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1687 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1688 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1689 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1690 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1691 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1692 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1693 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1694 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1695 } 1696 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1697 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1698 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1699 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1700 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1701 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1702 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1703 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1704 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1705 } 1706 break; 1707 case 2: 1708 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1709 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1710 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1711 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1712 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1713 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1714 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1715 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1716 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1717 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1718 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1719 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1720 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1721 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1722 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1723 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1724 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1725 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1726 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1727 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1728 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1729 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1730 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1731 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1732 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1733 } 1734 break; 1735 default: 1736 dev_err(adev->dev, 1737 "Unhandled GC info table %d.%d\n", 1738 le16_to_cpu(gc_info->v1.header.version_major), 1739 le16_to_cpu(gc_info->v1.header.version_minor)); 1740 return -EINVAL; 1741 } 1742 return 0; 1743 } 1744 1745 union mall_info { 1746 struct mall_info_v1_0 v1; 1747 struct mall_info_v2_0 v2; 1748 }; 1749 1750 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1751 { 1752 uint8_t *discovery_bin = adev->discovery.bin; 1753 struct binary_header *bhdr; 1754 union mall_info *mall_info; 1755 u32 u, mall_size_per_umc, m_s_present, half_use; 1756 u64 mall_size; 1757 u16 offset; 1758 1759 if (!discovery_bin) { 1760 DRM_ERROR("ip discovery uninitialized\n"); 1761 return -EINVAL; 1762 } 1763 1764 bhdr = (struct binary_header *)discovery_bin; 1765 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1766 1767 if (!offset) 1768 return 0; 1769 1770 mall_info = (union mall_info *)(discovery_bin + offset); 1771 1772 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1773 case 1: 1774 mall_size = 0; 1775 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1776 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1777 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1778 for (u = 0; u < adev->gmc.num_umc; u++) { 1779 if (m_s_present & (1 << u)) 1780 mall_size += mall_size_per_umc * 2; 1781 else if (half_use & (1 << u)) 1782 mall_size += mall_size_per_umc / 2; 1783 else 1784 mall_size += mall_size_per_umc; 1785 } 1786 adev->gmc.mall_size = mall_size; 1787 adev->gmc.m_half_use = half_use; 1788 break; 1789 case 2: 1790 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1791 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1792 break; 1793 default: 1794 dev_err(adev->dev, 1795 "Unhandled MALL info table %d.%d\n", 1796 le16_to_cpu(mall_info->v1.header.version_major), 1797 le16_to_cpu(mall_info->v1.header.version_minor)); 1798 return -EINVAL; 1799 } 1800 return 0; 1801 } 1802 1803 union vcn_info { 1804 struct vcn_info_v1_0 v1; 1805 }; 1806 1807 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1808 { 1809 uint8_t *discovery_bin = adev->discovery.bin; 1810 struct binary_header *bhdr; 1811 union vcn_info *vcn_info; 1812 u16 offset; 1813 int v; 1814 1815 if (!discovery_bin) { 1816 DRM_ERROR("ip discovery uninitialized\n"); 1817 return -EINVAL; 1818 } 1819 1820 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1821 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1822 * but that may change in the future with new GPUs so keep this 1823 * check for defensive purposes. 1824 */ 1825 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1826 dev_err(adev->dev, "invalid vcn instances\n"); 1827 return -EINVAL; 1828 } 1829 1830 bhdr = (struct binary_header *)discovery_bin; 1831 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1832 1833 if (!offset) 1834 return 0; 1835 1836 vcn_info = (union vcn_info *)(discovery_bin + offset); 1837 1838 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1839 case 1: 1840 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1841 * so this won't overflow. 1842 */ 1843 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1844 adev->vcn.inst[v].vcn_codec_disable_mask = 1845 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1846 } 1847 break; 1848 default: 1849 dev_err(adev->dev, 1850 "Unhandled VCN info table %d.%d\n", 1851 le16_to_cpu(vcn_info->v1.header.version_major), 1852 le16_to_cpu(vcn_info->v1.header.version_minor)); 1853 return -EINVAL; 1854 } 1855 return 0; 1856 } 1857 1858 union nps_info { 1859 struct nps_info_v1_0 v1; 1860 }; 1861 1862 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1863 union nps_info *nps_data) 1864 { 1865 uint64_t vram_size, pos, offset; 1866 struct nps_info_header *nhdr; 1867 struct binary_header bhdr; 1868 uint16_t checksum; 1869 1870 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1871 pos = vram_size - DISCOVERY_TMR_OFFSET; 1872 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1873 1874 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1875 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1876 1877 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1878 sizeof(*nps_data), false); 1879 1880 nhdr = (struct nps_info_header *)(nps_data); 1881 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 1882 le32_to_cpu(nhdr->size_bytes), 1883 checksum)) { 1884 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1885 return -EINVAL; 1886 } 1887 1888 return 0; 1889 } 1890 1891 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1892 uint32_t *nps_type, 1893 struct amdgpu_gmc_memrange **ranges, 1894 int *range_cnt, bool refresh) 1895 { 1896 uint8_t *discovery_bin = adev->discovery.bin; 1897 struct amdgpu_gmc_memrange *mem_ranges; 1898 struct binary_header *bhdr; 1899 union nps_info *nps_info; 1900 union nps_info nps_data; 1901 u16 offset; 1902 int i, r; 1903 1904 if (!nps_type || !range_cnt || !ranges) 1905 return -EINVAL; 1906 1907 if (refresh) { 1908 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1909 if (r) 1910 return r; 1911 nps_info = &nps_data; 1912 } else { 1913 if (!discovery_bin) { 1914 dev_err(adev->dev, 1915 "fetch mem range failed, ip discovery uninitialized\n"); 1916 return -EINVAL; 1917 } 1918 1919 bhdr = (struct binary_header *)discovery_bin; 1920 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1921 1922 if (!offset) 1923 return -ENOENT; 1924 1925 /* If verification fails, return as if NPS table doesn't exist */ 1926 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1927 return -ENOENT; 1928 1929 nps_info = (union nps_info *)(discovery_bin + offset); 1930 } 1931 1932 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1933 case 1: 1934 mem_ranges = kvcalloc(nps_info->v1.count, 1935 sizeof(*mem_ranges), 1936 GFP_KERNEL); 1937 if (!mem_ranges) 1938 return -ENOMEM; 1939 *nps_type = nps_info->v1.nps_type; 1940 *range_cnt = nps_info->v1.count; 1941 for (i = 0; i < *range_cnt; i++) { 1942 mem_ranges[i].base_address = 1943 nps_info->v1.instance_info[i].base_address; 1944 mem_ranges[i].limit_address = 1945 nps_info->v1.instance_info[i].limit_address; 1946 mem_ranges[i].nid_mask = -1; 1947 mem_ranges[i].flags = 0; 1948 } 1949 *ranges = mem_ranges; 1950 break; 1951 default: 1952 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1953 le16_to_cpu(nps_info->v1.header.version_major), 1954 le16_to_cpu(nps_info->v1.header.version_minor)); 1955 return -EINVAL; 1956 } 1957 1958 return 0; 1959 } 1960 1961 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1962 { 1963 /* what IP to use for this? */ 1964 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1965 case IP_VERSION(9, 0, 1): 1966 case IP_VERSION(9, 1, 0): 1967 case IP_VERSION(9, 2, 1): 1968 case IP_VERSION(9, 2, 2): 1969 case IP_VERSION(9, 3, 0): 1970 case IP_VERSION(9, 4, 0): 1971 case IP_VERSION(9, 4, 1): 1972 case IP_VERSION(9, 4, 2): 1973 case IP_VERSION(9, 4, 3): 1974 case IP_VERSION(9, 4, 4): 1975 case IP_VERSION(9, 5, 0): 1976 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1977 break; 1978 case IP_VERSION(10, 1, 10): 1979 case IP_VERSION(10, 1, 1): 1980 case IP_VERSION(10, 1, 2): 1981 case IP_VERSION(10, 1, 3): 1982 case IP_VERSION(10, 1, 4): 1983 case IP_VERSION(10, 3, 0): 1984 case IP_VERSION(10, 3, 1): 1985 case IP_VERSION(10, 3, 2): 1986 case IP_VERSION(10, 3, 3): 1987 case IP_VERSION(10, 3, 4): 1988 case IP_VERSION(10, 3, 5): 1989 case IP_VERSION(10, 3, 6): 1990 case IP_VERSION(10, 3, 7): 1991 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1992 break; 1993 case IP_VERSION(11, 0, 0): 1994 case IP_VERSION(11, 0, 1): 1995 case IP_VERSION(11, 0, 2): 1996 case IP_VERSION(11, 0, 3): 1997 case IP_VERSION(11, 0, 4): 1998 case IP_VERSION(11, 5, 0): 1999 case IP_VERSION(11, 5, 1): 2000 case IP_VERSION(11, 5, 2): 2001 case IP_VERSION(11, 5, 3): 2002 case IP_VERSION(11, 5, 4): 2003 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2004 break; 2005 case IP_VERSION(12, 0, 0): 2006 case IP_VERSION(12, 0, 1): 2007 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2008 break; 2009 case IP_VERSION(12, 1, 0): 2010 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2011 break; 2012 default: 2013 dev_err(adev->dev, 2014 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2015 amdgpu_ip_version(adev, GC_HWIP, 0)); 2016 return -EINVAL; 2017 } 2018 return 0; 2019 } 2020 2021 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2022 { 2023 /* use GC or MMHUB IP version */ 2024 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2025 case IP_VERSION(9, 0, 1): 2026 case IP_VERSION(9, 1, 0): 2027 case IP_VERSION(9, 2, 1): 2028 case IP_VERSION(9, 2, 2): 2029 case IP_VERSION(9, 3, 0): 2030 case IP_VERSION(9, 4, 0): 2031 case IP_VERSION(9, 4, 1): 2032 case IP_VERSION(9, 4, 2): 2033 case IP_VERSION(9, 4, 3): 2034 case IP_VERSION(9, 4, 4): 2035 case IP_VERSION(9, 5, 0): 2036 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2037 break; 2038 case IP_VERSION(10, 1, 10): 2039 case IP_VERSION(10, 1, 1): 2040 case IP_VERSION(10, 1, 2): 2041 case IP_VERSION(10, 1, 3): 2042 case IP_VERSION(10, 1, 4): 2043 case IP_VERSION(10, 3, 0): 2044 case IP_VERSION(10, 3, 1): 2045 case IP_VERSION(10, 3, 2): 2046 case IP_VERSION(10, 3, 3): 2047 case IP_VERSION(10, 3, 4): 2048 case IP_VERSION(10, 3, 5): 2049 case IP_VERSION(10, 3, 6): 2050 case IP_VERSION(10, 3, 7): 2051 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2052 break; 2053 case IP_VERSION(11, 0, 0): 2054 case IP_VERSION(11, 0, 1): 2055 case IP_VERSION(11, 0, 2): 2056 case IP_VERSION(11, 0, 3): 2057 case IP_VERSION(11, 0, 4): 2058 case IP_VERSION(11, 5, 0): 2059 case IP_VERSION(11, 5, 1): 2060 case IP_VERSION(11, 5, 2): 2061 case IP_VERSION(11, 5, 3): 2062 case IP_VERSION(11, 5, 4): 2063 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2064 break; 2065 case IP_VERSION(12, 0, 0): 2066 case IP_VERSION(12, 0, 1): 2067 case IP_VERSION(12, 1, 0): 2068 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2069 break; 2070 default: 2071 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2072 amdgpu_ip_version(adev, GC_HWIP, 0)); 2073 return -EINVAL; 2074 } 2075 return 0; 2076 } 2077 2078 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2079 { 2080 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2081 case IP_VERSION(4, 0, 0): 2082 case IP_VERSION(4, 0, 1): 2083 case IP_VERSION(4, 1, 0): 2084 case IP_VERSION(4, 1, 1): 2085 case IP_VERSION(4, 3, 0): 2086 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2087 break; 2088 case IP_VERSION(4, 2, 0): 2089 case IP_VERSION(4, 2, 1): 2090 case IP_VERSION(4, 4, 0): 2091 case IP_VERSION(4, 4, 2): 2092 case IP_VERSION(4, 4, 5): 2093 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2094 break; 2095 case IP_VERSION(5, 0, 0): 2096 case IP_VERSION(5, 0, 1): 2097 case IP_VERSION(5, 0, 2): 2098 case IP_VERSION(5, 0, 3): 2099 case IP_VERSION(5, 2, 0): 2100 case IP_VERSION(5, 2, 1): 2101 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2102 break; 2103 case IP_VERSION(6, 0, 0): 2104 case IP_VERSION(6, 0, 1): 2105 case IP_VERSION(6, 0, 2): 2106 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2107 break; 2108 case IP_VERSION(6, 1, 0): 2109 case IP_VERSION(6, 1, 1): 2110 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2111 break; 2112 case IP_VERSION(7, 0, 0): 2113 case IP_VERSION(7, 1, 0): 2114 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2115 break; 2116 default: 2117 dev_err(adev->dev, 2118 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2119 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2120 return -EINVAL; 2121 } 2122 return 0; 2123 } 2124 2125 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2126 { 2127 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2128 case IP_VERSION(9, 0, 0): 2129 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2130 break; 2131 case IP_VERSION(10, 0, 0): 2132 case IP_VERSION(10, 0, 1): 2133 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2134 break; 2135 case IP_VERSION(11, 0, 0): 2136 case IP_VERSION(11, 0, 2): 2137 case IP_VERSION(11, 0, 4): 2138 case IP_VERSION(11, 0, 5): 2139 case IP_VERSION(11, 0, 9): 2140 case IP_VERSION(11, 0, 7): 2141 case IP_VERSION(11, 0, 11): 2142 case IP_VERSION(11, 0, 12): 2143 case IP_VERSION(11, 0, 13): 2144 case IP_VERSION(11, 5, 0): 2145 case IP_VERSION(11, 5, 2): 2146 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2147 break; 2148 case IP_VERSION(11, 0, 8): 2149 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2150 break; 2151 case IP_VERSION(11, 0, 3): 2152 case IP_VERSION(12, 0, 1): 2153 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2154 break; 2155 case IP_VERSION(13, 0, 0): 2156 case IP_VERSION(13, 0, 1): 2157 case IP_VERSION(13, 0, 2): 2158 case IP_VERSION(13, 0, 3): 2159 case IP_VERSION(13, 0, 5): 2160 case IP_VERSION(13, 0, 6): 2161 case IP_VERSION(13, 0, 7): 2162 case IP_VERSION(13, 0, 8): 2163 case IP_VERSION(13, 0, 10): 2164 case IP_VERSION(13, 0, 11): 2165 case IP_VERSION(13, 0, 12): 2166 case IP_VERSION(13, 0, 14): 2167 case IP_VERSION(14, 0, 0): 2168 case IP_VERSION(14, 0, 1): 2169 case IP_VERSION(14, 0, 4): 2170 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2171 break; 2172 case IP_VERSION(13, 0, 4): 2173 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2174 break; 2175 case IP_VERSION(14, 0, 2): 2176 case IP_VERSION(14, 0, 3): 2177 case IP_VERSION(14, 0, 5): 2178 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2179 break; 2180 case IP_VERSION(15, 0, 0): 2181 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2182 break; 2183 case IP_VERSION(15, 0, 8): 2184 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2185 break; 2186 default: 2187 dev_err(adev->dev, 2188 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2189 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2190 return -EINVAL; 2191 } 2192 return 0; 2193 } 2194 2195 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2196 { 2197 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2198 case IP_VERSION(9, 0, 0): 2199 case IP_VERSION(10, 0, 0): 2200 case IP_VERSION(10, 0, 1): 2201 case IP_VERSION(11, 0, 2): 2202 if (adev->asic_type == CHIP_ARCTURUS) 2203 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2204 else 2205 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2206 break; 2207 case IP_VERSION(11, 0, 0): 2208 case IP_VERSION(11, 0, 5): 2209 case IP_VERSION(11, 0, 9): 2210 case IP_VERSION(11, 0, 7): 2211 case IP_VERSION(11, 0, 11): 2212 case IP_VERSION(11, 0, 12): 2213 case IP_VERSION(11, 0, 13): 2214 case IP_VERSION(11, 5, 0): 2215 case IP_VERSION(11, 5, 2): 2216 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2217 break; 2218 case IP_VERSION(11, 0, 8): 2219 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2220 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2221 break; 2222 case IP_VERSION(12, 0, 0): 2223 case IP_VERSION(12, 0, 1): 2224 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2225 break; 2226 case IP_VERSION(13, 0, 0): 2227 case IP_VERSION(13, 0, 1): 2228 case IP_VERSION(13, 0, 2): 2229 case IP_VERSION(13, 0, 3): 2230 case IP_VERSION(13, 0, 4): 2231 case IP_VERSION(13, 0, 5): 2232 case IP_VERSION(13, 0, 6): 2233 case IP_VERSION(13, 0, 7): 2234 case IP_VERSION(13, 0, 8): 2235 case IP_VERSION(13, 0, 10): 2236 case IP_VERSION(13, 0, 11): 2237 case IP_VERSION(13, 0, 14): 2238 case IP_VERSION(13, 0, 12): 2239 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2240 break; 2241 case IP_VERSION(14, 0, 0): 2242 case IP_VERSION(14, 0, 1): 2243 case IP_VERSION(14, 0, 2): 2244 case IP_VERSION(14, 0, 3): 2245 case IP_VERSION(14, 0, 4): 2246 case IP_VERSION(14, 0, 5): 2247 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2248 break; 2249 case IP_VERSION(15, 0, 0): 2250 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2251 break; 2252 default: 2253 dev_err(adev->dev, 2254 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2255 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2256 return -EINVAL; 2257 } 2258 return 0; 2259 } 2260 2261 #if defined(CONFIG_DRM_AMD_DC) 2262 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2263 { 2264 amdgpu_device_set_sriov_virtual_display(adev); 2265 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2266 } 2267 #endif 2268 2269 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2270 { 2271 if (adev->enable_virtual_display) { 2272 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2273 return 0; 2274 } 2275 2276 if (!amdgpu_device_has_dc_support(adev)) 2277 return 0; 2278 2279 #if defined(CONFIG_DRM_AMD_DC) 2280 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2281 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2282 case IP_VERSION(1, 0, 0): 2283 case IP_VERSION(1, 0, 1): 2284 case IP_VERSION(2, 0, 2): 2285 case IP_VERSION(2, 0, 0): 2286 case IP_VERSION(2, 0, 3): 2287 case IP_VERSION(2, 1, 0): 2288 case IP_VERSION(3, 0, 0): 2289 case IP_VERSION(3, 0, 2): 2290 case IP_VERSION(3, 0, 3): 2291 case IP_VERSION(3, 0, 1): 2292 case IP_VERSION(3, 1, 2): 2293 case IP_VERSION(3, 1, 3): 2294 case IP_VERSION(3, 1, 4): 2295 case IP_VERSION(3, 1, 5): 2296 case IP_VERSION(3, 1, 6): 2297 case IP_VERSION(3, 2, 0): 2298 case IP_VERSION(3, 2, 1): 2299 case IP_VERSION(3, 5, 0): 2300 case IP_VERSION(3, 5, 1): 2301 case IP_VERSION(3, 6, 0): 2302 case IP_VERSION(4, 1, 0): 2303 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2304 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2305 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2306 2307 if (amdgpu_sriov_vf(adev)) 2308 amdgpu_discovery_set_sriov_display(adev); 2309 else 2310 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2311 break; 2312 default: 2313 dev_err(adev->dev, 2314 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2315 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2316 return -EINVAL; 2317 } 2318 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2319 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2320 case IP_VERSION(12, 0, 0): 2321 case IP_VERSION(12, 0, 1): 2322 case IP_VERSION(12, 1, 0): 2323 if (amdgpu_sriov_vf(adev)) 2324 amdgpu_discovery_set_sriov_display(adev); 2325 else 2326 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2327 break; 2328 default: 2329 dev_err(adev->dev, 2330 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2331 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2332 return -EINVAL; 2333 } 2334 } 2335 #endif 2336 return 0; 2337 } 2338 2339 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2340 { 2341 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2342 case IP_VERSION(9, 0, 1): 2343 case IP_VERSION(9, 1, 0): 2344 case IP_VERSION(9, 2, 1): 2345 case IP_VERSION(9, 2, 2): 2346 case IP_VERSION(9, 3, 0): 2347 case IP_VERSION(9, 4, 0): 2348 case IP_VERSION(9, 4, 1): 2349 case IP_VERSION(9, 4, 2): 2350 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2351 break; 2352 case IP_VERSION(9, 4, 3): 2353 case IP_VERSION(9, 4, 4): 2354 case IP_VERSION(9, 5, 0): 2355 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2356 break; 2357 case IP_VERSION(10, 1, 10): 2358 case IP_VERSION(10, 1, 2): 2359 case IP_VERSION(10, 1, 1): 2360 case IP_VERSION(10, 1, 3): 2361 case IP_VERSION(10, 1, 4): 2362 case IP_VERSION(10, 3, 0): 2363 case IP_VERSION(10, 3, 2): 2364 case IP_VERSION(10, 3, 1): 2365 case IP_VERSION(10, 3, 4): 2366 case IP_VERSION(10, 3, 5): 2367 case IP_VERSION(10, 3, 6): 2368 case IP_VERSION(10, 3, 3): 2369 case IP_VERSION(10, 3, 7): 2370 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2371 break; 2372 case IP_VERSION(11, 0, 0): 2373 case IP_VERSION(11, 0, 1): 2374 case IP_VERSION(11, 0, 2): 2375 case IP_VERSION(11, 0, 3): 2376 case IP_VERSION(11, 0, 4): 2377 case IP_VERSION(11, 5, 0): 2378 case IP_VERSION(11, 5, 1): 2379 case IP_VERSION(11, 5, 2): 2380 case IP_VERSION(11, 5, 3): 2381 case IP_VERSION(11, 5, 4): 2382 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2383 break; 2384 case IP_VERSION(12, 0, 0): 2385 case IP_VERSION(12, 0, 1): 2386 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2387 break; 2388 case IP_VERSION(12, 1, 0): 2389 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2390 break; 2391 default: 2392 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2393 amdgpu_ip_version(adev, GC_HWIP, 0)); 2394 return -EINVAL; 2395 } 2396 return 0; 2397 } 2398 2399 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2400 { 2401 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2402 case IP_VERSION(4, 0, 0): 2403 case IP_VERSION(4, 0, 1): 2404 case IP_VERSION(4, 1, 0): 2405 case IP_VERSION(4, 1, 1): 2406 case IP_VERSION(4, 1, 2): 2407 case IP_VERSION(4, 2, 0): 2408 case IP_VERSION(4, 2, 2): 2409 case IP_VERSION(4, 4, 0): 2410 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2411 break; 2412 case IP_VERSION(4, 4, 2): 2413 case IP_VERSION(4, 4, 5): 2414 case IP_VERSION(4, 4, 4): 2415 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2416 break; 2417 case IP_VERSION(5, 0, 0): 2418 case IP_VERSION(5, 0, 1): 2419 case IP_VERSION(5, 0, 2): 2420 case IP_VERSION(5, 0, 5): 2421 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2422 break; 2423 case IP_VERSION(5, 2, 0): 2424 case IP_VERSION(5, 2, 2): 2425 case IP_VERSION(5, 2, 4): 2426 case IP_VERSION(5, 2, 5): 2427 case IP_VERSION(5, 2, 6): 2428 case IP_VERSION(5, 2, 3): 2429 case IP_VERSION(5, 2, 1): 2430 case IP_VERSION(5, 2, 7): 2431 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2432 break; 2433 case IP_VERSION(6, 0, 0): 2434 case IP_VERSION(6, 0, 1): 2435 case IP_VERSION(6, 0, 2): 2436 case IP_VERSION(6, 0, 3): 2437 case IP_VERSION(6, 1, 0): 2438 case IP_VERSION(6, 1, 1): 2439 case IP_VERSION(6, 1, 2): 2440 case IP_VERSION(6, 1, 3): 2441 case IP_VERSION(6, 1, 4): 2442 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2443 break; 2444 case IP_VERSION(7, 0, 0): 2445 case IP_VERSION(7, 0, 1): 2446 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2447 break; 2448 case IP_VERSION(7, 1, 0): 2449 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2450 break; 2451 default: 2452 dev_err(adev->dev, 2453 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2454 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2455 return -EINVAL; 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2462 { 2463 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2464 case IP_VERSION(13, 0, 6): 2465 case IP_VERSION(13, 0, 12): 2466 case IP_VERSION(13, 0, 14): 2467 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2468 break; 2469 default: 2470 break; 2471 } 2472 return 0; 2473 } 2474 2475 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2476 { 2477 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2478 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2479 case IP_VERSION(7, 0, 0): 2480 case IP_VERSION(7, 2, 0): 2481 /* UVD is not supported on vega20 SR-IOV */ 2482 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2483 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2484 break; 2485 default: 2486 dev_err(adev->dev, 2487 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2488 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2489 return -EINVAL; 2490 } 2491 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2492 case IP_VERSION(4, 0, 0): 2493 case IP_VERSION(4, 1, 0): 2494 /* VCE is not supported on vega20 SR-IOV */ 2495 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2496 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2497 break; 2498 default: 2499 dev_err(adev->dev, 2500 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2501 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2502 return -EINVAL; 2503 } 2504 } else { 2505 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2506 case IP_VERSION(1, 0, 0): 2507 case IP_VERSION(1, 0, 1): 2508 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2509 break; 2510 case IP_VERSION(2, 0, 0): 2511 case IP_VERSION(2, 0, 2): 2512 case IP_VERSION(2, 2, 0): 2513 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2514 if (!amdgpu_sriov_vf(adev)) 2515 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2516 break; 2517 case IP_VERSION(2, 0, 3): 2518 break; 2519 case IP_VERSION(2, 5, 0): 2520 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2521 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2522 break; 2523 case IP_VERSION(2, 6, 0): 2524 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2525 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2526 break; 2527 case IP_VERSION(3, 0, 0): 2528 case IP_VERSION(3, 0, 16): 2529 case IP_VERSION(3, 1, 1): 2530 case IP_VERSION(3, 1, 2): 2531 case IP_VERSION(3, 0, 2): 2532 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2533 if (!amdgpu_sriov_vf(adev)) 2534 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2535 break; 2536 case IP_VERSION(3, 0, 33): 2537 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2538 break; 2539 case IP_VERSION(4, 0, 0): 2540 case IP_VERSION(4, 0, 2): 2541 case IP_VERSION(4, 0, 4): 2542 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2543 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2544 break; 2545 case IP_VERSION(4, 0, 3): 2546 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2547 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2548 break; 2549 case IP_VERSION(4, 0, 5): 2550 case IP_VERSION(4, 0, 6): 2551 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2552 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2553 break; 2554 case IP_VERSION(5, 0, 0): 2555 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2556 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2557 break; 2558 case IP_VERSION(5, 3, 0): 2559 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2560 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2561 break; 2562 case IP_VERSION(5, 0, 1): 2563 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2564 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2565 break; 2566 default: 2567 dev_err(adev->dev, 2568 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2569 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2570 return -EINVAL; 2571 } 2572 } 2573 return 0; 2574 } 2575 2576 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2577 { 2578 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2579 case IP_VERSION(11, 0, 0): 2580 case IP_VERSION(11, 0, 1): 2581 case IP_VERSION(11, 0, 2): 2582 case IP_VERSION(11, 0, 3): 2583 case IP_VERSION(11, 0, 4): 2584 case IP_VERSION(11, 5, 0): 2585 case IP_VERSION(11, 5, 1): 2586 case IP_VERSION(11, 5, 2): 2587 case IP_VERSION(11, 5, 3): 2588 case IP_VERSION(11, 5, 4): 2589 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2590 adev->enable_mes = true; 2591 adev->enable_mes_kiq = true; 2592 break; 2593 case IP_VERSION(12, 0, 0): 2594 case IP_VERSION(12, 0, 1): 2595 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2596 adev->enable_mes = true; 2597 adev->enable_mes_kiq = true; 2598 if (amdgpu_uni_mes) 2599 adev->enable_uni_mes = true; 2600 break; 2601 case IP_VERSION(12, 1, 0): 2602 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2603 adev->enable_mes = true; 2604 adev->enable_mes_kiq = true; 2605 if (amdgpu_uni_mes) 2606 adev->enable_uni_mes = true; 2607 break; 2608 default: 2609 break; 2610 } 2611 return 0; 2612 } 2613 2614 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2615 { 2616 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2617 case IP_VERSION(9, 4, 3): 2618 case IP_VERSION(9, 4, 4): 2619 case IP_VERSION(9, 5, 0): 2620 aqua_vanjaram_init_soc_config(adev); 2621 break; 2622 case IP_VERSION(12, 1, 0): 2623 soc_v1_0_init_soc_config(adev); 2624 break; 2625 default: 2626 break; 2627 } 2628 } 2629 2630 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2631 { 2632 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2633 case IP_VERSION(6, 1, 0): 2634 case IP_VERSION(6, 1, 1): 2635 case IP_VERSION(6, 1, 3): 2636 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2637 break; 2638 default: 2639 break; 2640 } 2641 2642 return 0; 2643 } 2644 2645 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2646 { 2647 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2648 case IP_VERSION(4, 0, 5): 2649 case IP_VERSION(4, 0, 6): 2650 if (amdgpu_umsch_mm & 0x1) { 2651 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2652 adev->enable_umsch_mm = true; 2653 } 2654 break; 2655 default: 2656 break; 2657 } 2658 2659 return 0; 2660 } 2661 2662 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2663 { 2664 #if defined(CONFIG_DRM_AMD_ISP) 2665 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2666 case IP_VERSION(4, 1, 0): 2667 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2668 break; 2669 case IP_VERSION(4, 1, 1): 2670 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2671 break; 2672 default: 2673 break; 2674 } 2675 #endif 2676 2677 return 0; 2678 } 2679 2680 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2681 { 2682 int r; 2683 2684 switch (adev->asic_type) { 2685 case CHIP_VEGA10: 2686 /* This is not fatal. We only need the discovery 2687 * binary for sysfs. We don't need it for a 2688 * functional system. 2689 */ 2690 amdgpu_discovery_init(adev); 2691 vega10_reg_base_init(adev); 2692 adev->sdma.num_instances = 2; 2693 adev->sdma.sdma_mask = 3; 2694 adev->gmc.num_umc = 4; 2695 adev->gfx.xcc_mask = 1; 2696 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2697 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2698 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2699 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2700 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2701 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2702 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2703 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2704 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2705 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2706 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2707 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2708 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2709 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2710 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2711 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2712 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2713 break; 2714 case CHIP_VEGA12: 2715 /* This is not fatal. We only need the discovery 2716 * binary for sysfs. We don't need it for a 2717 * functional system. 2718 */ 2719 amdgpu_discovery_init(adev); 2720 vega10_reg_base_init(adev); 2721 adev->sdma.num_instances = 2; 2722 adev->sdma.sdma_mask = 3; 2723 adev->gmc.num_umc = 4; 2724 adev->gfx.xcc_mask = 1; 2725 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2726 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2727 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2728 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2729 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2730 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2731 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2732 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2733 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2734 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2735 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2736 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2737 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2738 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2739 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2740 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2741 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2742 break; 2743 case CHIP_RAVEN: 2744 /* This is not fatal. We only need the discovery 2745 * binary for sysfs. We don't need it for a 2746 * functional system. 2747 */ 2748 amdgpu_discovery_init(adev); 2749 vega10_reg_base_init(adev); 2750 adev->sdma.num_instances = 1; 2751 adev->sdma.sdma_mask = 1; 2752 adev->vcn.num_vcn_inst = 1; 2753 adev->gmc.num_umc = 2; 2754 adev->gfx.xcc_mask = 1; 2755 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2756 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2757 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2758 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2759 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2760 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2761 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2762 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2763 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2764 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2765 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2766 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2767 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2768 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2769 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2770 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2771 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2772 } else { 2773 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2774 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2775 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2776 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2777 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2778 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2779 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2780 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2781 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2782 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2783 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2784 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2785 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2786 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2787 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2788 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2789 } 2790 break; 2791 case CHIP_VEGA20: 2792 /* This is not fatal. We only need the discovery 2793 * binary for sysfs. We don't need it for a 2794 * functional system. 2795 */ 2796 amdgpu_discovery_init(adev); 2797 vega20_reg_base_init(adev); 2798 adev->sdma.num_instances = 2; 2799 adev->sdma.sdma_mask = 3; 2800 adev->gmc.num_umc = 8; 2801 adev->gfx.xcc_mask = 1; 2802 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2803 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2804 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2805 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2806 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2807 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2808 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2809 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2810 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2811 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2812 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2813 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2814 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2815 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2816 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2817 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2818 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2819 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2820 break; 2821 case CHIP_ARCTURUS: 2822 /* This is not fatal. We only need the discovery 2823 * binary for sysfs. We don't need it for a 2824 * functional system. 2825 */ 2826 amdgpu_discovery_init(adev); 2827 arct_reg_base_init(adev); 2828 adev->sdma.num_instances = 8; 2829 adev->sdma.sdma_mask = 0xff; 2830 adev->vcn.num_vcn_inst = 2; 2831 adev->gmc.num_umc = 8; 2832 adev->gfx.xcc_mask = 1; 2833 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2834 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2835 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2836 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2837 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2838 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2839 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2840 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2841 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2842 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2843 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2844 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2845 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2846 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2847 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2848 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2849 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2850 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2851 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2852 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2853 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2854 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2855 break; 2856 case CHIP_ALDEBARAN: 2857 /* This is not fatal. We only need the discovery 2858 * binary for sysfs. We don't need it for a 2859 * functional system. 2860 */ 2861 amdgpu_discovery_init(adev); 2862 aldebaran_reg_base_init(adev); 2863 adev->sdma.num_instances = 5; 2864 adev->sdma.sdma_mask = 0x1f; 2865 adev->vcn.num_vcn_inst = 2; 2866 adev->gmc.num_umc = 4; 2867 adev->gfx.xcc_mask = 1; 2868 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2869 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2870 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2871 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2872 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2873 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2874 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2875 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2876 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2877 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2878 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2879 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2880 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2881 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2882 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2883 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2884 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2885 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2886 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2887 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2888 break; 2889 case CHIP_CYAN_SKILLFISH: 2890 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2891 r = amdgpu_discovery_reg_base_init(adev); 2892 if (r) 2893 return -EINVAL; 2894 2895 amdgpu_discovery_harvest_ip(adev); 2896 amdgpu_discovery_get_gfx_info(adev); 2897 amdgpu_discovery_get_mall_info(adev); 2898 amdgpu_discovery_get_vcn_info(adev); 2899 } else { 2900 cyan_skillfish_reg_base_init(adev); 2901 adev->sdma.num_instances = 2; 2902 adev->sdma.sdma_mask = 3; 2903 adev->gfx.xcc_mask = 1; 2904 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2905 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2906 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2907 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2908 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2909 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2910 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2911 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2912 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2913 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2914 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2915 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2916 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2917 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2918 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2919 } 2920 break; 2921 default: 2922 r = amdgpu_discovery_reg_base_init(adev); 2923 if (r) { 2924 drm_err(&adev->ddev, "discovery failed: %d\n", r); 2925 return r; 2926 } 2927 2928 amdgpu_discovery_harvest_ip(adev); 2929 amdgpu_discovery_get_gfx_info(adev); 2930 amdgpu_discovery_get_mall_info(adev); 2931 amdgpu_discovery_get_vcn_info(adev); 2932 break; 2933 } 2934 2935 amdgpu_discovery_init_soc_config(adev); 2936 amdgpu_discovery_sysfs_init(adev); 2937 2938 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2939 case IP_VERSION(9, 0, 1): 2940 case IP_VERSION(9, 2, 1): 2941 case IP_VERSION(9, 4, 0): 2942 case IP_VERSION(9, 4, 1): 2943 case IP_VERSION(9, 4, 2): 2944 case IP_VERSION(9, 4, 3): 2945 case IP_VERSION(9, 4, 4): 2946 case IP_VERSION(9, 5, 0): 2947 adev->family = AMDGPU_FAMILY_AI; 2948 break; 2949 case IP_VERSION(9, 1, 0): 2950 case IP_VERSION(9, 2, 2): 2951 case IP_VERSION(9, 3, 0): 2952 adev->family = AMDGPU_FAMILY_RV; 2953 break; 2954 case IP_VERSION(10, 1, 10): 2955 case IP_VERSION(10, 1, 1): 2956 case IP_VERSION(10, 1, 2): 2957 case IP_VERSION(10, 1, 3): 2958 case IP_VERSION(10, 1, 4): 2959 case IP_VERSION(10, 3, 0): 2960 case IP_VERSION(10, 3, 2): 2961 case IP_VERSION(10, 3, 4): 2962 case IP_VERSION(10, 3, 5): 2963 adev->family = AMDGPU_FAMILY_NV; 2964 break; 2965 case IP_VERSION(10, 3, 1): 2966 adev->family = AMDGPU_FAMILY_VGH; 2967 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2968 break; 2969 case IP_VERSION(10, 3, 3): 2970 adev->family = AMDGPU_FAMILY_YC; 2971 break; 2972 case IP_VERSION(10, 3, 6): 2973 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2974 break; 2975 case IP_VERSION(10, 3, 7): 2976 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2977 break; 2978 case IP_VERSION(11, 0, 0): 2979 case IP_VERSION(11, 0, 2): 2980 case IP_VERSION(11, 0, 3): 2981 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2982 break; 2983 case IP_VERSION(11, 0, 1): 2984 case IP_VERSION(11, 0, 4): 2985 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2986 break; 2987 case IP_VERSION(11, 5, 0): 2988 case IP_VERSION(11, 5, 1): 2989 case IP_VERSION(11, 5, 2): 2990 case IP_VERSION(11, 5, 3): 2991 case IP_VERSION(11, 5, 4): 2992 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2993 break; 2994 case IP_VERSION(12, 0, 0): 2995 case IP_VERSION(12, 0, 1): 2996 case IP_VERSION(12, 1, 0): 2997 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2998 break; 2999 default: 3000 return -EINVAL; 3001 } 3002 3003 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3004 case IP_VERSION(9, 1, 0): 3005 case IP_VERSION(9, 2, 2): 3006 case IP_VERSION(9, 3, 0): 3007 case IP_VERSION(10, 1, 3): 3008 case IP_VERSION(10, 1, 4): 3009 case IP_VERSION(10, 3, 1): 3010 case IP_VERSION(10, 3, 3): 3011 case IP_VERSION(10, 3, 6): 3012 case IP_VERSION(10, 3, 7): 3013 case IP_VERSION(11, 0, 1): 3014 case IP_VERSION(11, 0, 4): 3015 case IP_VERSION(11, 5, 0): 3016 case IP_VERSION(11, 5, 1): 3017 case IP_VERSION(11, 5, 2): 3018 case IP_VERSION(11, 5, 3): 3019 case IP_VERSION(11, 5, 4): 3020 adev->flags |= AMD_IS_APU; 3021 break; 3022 default: 3023 break; 3024 } 3025 3026 /* set NBIO version */ 3027 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3028 case IP_VERSION(6, 1, 0): 3029 case IP_VERSION(6, 2, 0): 3030 adev->nbio.funcs = &nbio_v6_1_funcs; 3031 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3032 break; 3033 case IP_VERSION(7, 0, 0): 3034 case IP_VERSION(7, 0, 1): 3035 case IP_VERSION(2, 5, 0): 3036 adev->nbio.funcs = &nbio_v7_0_funcs; 3037 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3038 break; 3039 case IP_VERSION(7, 4, 0): 3040 case IP_VERSION(7, 4, 1): 3041 case IP_VERSION(7, 4, 4): 3042 adev->nbio.funcs = &nbio_v7_4_funcs; 3043 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3044 break; 3045 case IP_VERSION(7, 9, 0): 3046 case IP_VERSION(7, 9, 1): 3047 adev->nbio.funcs = &nbio_v7_9_funcs; 3048 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3049 break; 3050 case IP_VERSION(7, 11, 0): 3051 case IP_VERSION(7, 11, 1): 3052 case IP_VERSION(7, 11, 2): 3053 case IP_VERSION(7, 11, 3): 3054 adev->nbio.funcs = &nbio_v7_11_funcs; 3055 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3056 break; 3057 case IP_VERSION(7, 2, 0): 3058 case IP_VERSION(7, 2, 1): 3059 case IP_VERSION(7, 3, 0): 3060 case IP_VERSION(7, 5, 0): 3061 case IP_VERSION(7, 5, 1): 3062 adev->nbio.funcs = &nbio_v7_2_funcs; 3063 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3064 break; 3065 case IP_VERSION(2, 1, 1): 3066 case IP_VERSION(2, 3, 0): 3067 case IP_VERSION(2, 3, 1): 3068 case IP_VERSION(2, 3, 2): 3069 case IP_VERSION(3, 3, 0): 3070 case IP_VERSION(3, 3, 1): 3071 case IP_VERSION(3, 3, 2): 3072 case IP_VERSION(3, 3, 3): 3073 adev->nbio.funcs = &nbio_v2_3_funcs; 3074 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3075 break; 3076 case IP_VERSION(4, 3, 0): 3077 case IP_VERSION(4, 3, 1): 3078 if (amdgpu_sriov_vf(adev)) 3079 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3080 else 3081 adev->nbio.funcs = &nbio_v4_3_funcs; 3082 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3083 break; 3084 case IP_VERSION(7, 7, 0): 3085 case IP_VERSION(7, 7, 1): 3086 adev->nbio.funcs = &nbio_v7_7_funcs; 3087 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3088 break; 3089 case IP_VERSION(6, 3, 1): 3090 case IP_VERSION(7, 11, 4): 3091 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3092 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3093 break; 3094 default: 3095 break; 3096 } 3097 3098 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3099 case IP_VERSION(4, 0, 0): 3100 case IP_VERSION(4, 0, 1): 3101 case IP_VERSION(4, 1, 0): 3102 case IP_VERSION(4, 1, 1): 3103 case IP_VERSION(4, 1, 2): 3104 case IP_VERSION(4, 2, 0): 3105 case IP_VERSION(4, 2, 1): 3106 case IP_VERSION(4, 4, 0): 3107 case IP_VERSION(4, 4, 2): 3108 case IP_VERSION(4, 4, 5): 3109 adev->hdp.funcs = &hdp_v4_0_funcs; 3110 break; 3111 case IP_VERSION(5, 0, 0): 3112 case IP_VERSION(5, 0, 1): 3113 case IP_VERSION(5, 0, 2): 3114 case IP_VERSION(5, 0, 3): 3115 case IP_VERSION(5, 0, 4): 3116 case IP_VERSION(5, 2, 0): 3117 adev->hdp.funcs = &hdp_v5_0_funcs; 3118 break; 3119 case IP_VERSION(5, 2, 1): 3120 adev->hdp.funcs = &hdp_v5_2_funcs; 3121 break; 3122 case IP_VERSION(6, 0, 0): 3123 case IP_VERSION(6, 0, 1): 3124 case IP_VERSION(6, 1, 0): 3125 case IP_VERSION(6, 1, 1): 3126 adev->hdp.funcs = &hdp_v6_0_funcs; 3127 break; 3128 case IP_VERSION(7, 0, 0): 3129 adev->hdp.funcs = &hdp_v7_0_funcs; 3130 break; 3131 default: 3132 break; 3133 } 3134 3135 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3136 case IP_VERSION(3, 6, 0): 3137 case IP_VERSION(3, 6, 1): 3138 case IP_VERSION(3, 6, 2): 3139 adev->df.funcs = &df_v3_6_funcs; 3140 break; 3141 case IP_VERSION(2, 1, 0): 3142 case IP_VERSION(2, 1, 1): 3143 case IP_VERSION(2, 5, 0): 3144 case IP_VERSION(3, 5, 1): 3145 case IP_VERSION(3, 5, 2): 3146 adev->df.funcs = &df_v1_7_funcs; 3147 break; 3148 case IP_VERSION(4, 3, 0): 3149 adev->df.funcs = &df_v4_3_funcs; 3150 break; 3151 case IP_VERSION(4, 6, 2): 3152 adev->df.funcs = &df_v4_6_2_funcs; 3153 break; 3154 case IP_VERSION(4, 15, 0): 3155 case IP_VERSION(4, 15, 1): 3156 adev->df.funcs = &df_v4_15_funcs; 3157 break; 3158 default: 3159 break; 3160 } 3161 3162 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3163 case IP_VERSION(9, 0, 0): 3164 case IP_VERSION(9, 0, 1): 3165 case IP_VERSION(10, 0, 0): 3166 case IP_VERSION(10, 0, 1): 3167 case IP_VERSION(10, 0, 2): 3168 adev->smuio.funcs = &smuio_v9_0_funcs; 3169 break; 3170 case IP_VERSION(11, 0, 0): 3171 case IP_VERSION(11, 0, 2): 3172 case IP_VERSION(11, 0, 3): 3173 case IP_VERSION(11, 0, 4): 3174 case IP_VERSION(11, 0, 7): 3175 case IP_VERSION(11, 0, 8): 3176 adev->smuio.funcs = &smuio_v11_0_funcs; 3177 break; 3178 case IP_VERSION(11, 0, 6): 3179 case IP_VERSION(11, 0, 10): 3180 case IP_VERSION(11, 0, 11): 3181 case IP_VERSION(11, 5, 0): 3182 case IP_VERSION(11, 5, 2): 3183 case IP_VERSION(13, 0, 1): 3184 case IP_VERSION(13, 0, 9): 3185 case IP_VERSION(13, 0, 10): 3186 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3187 break; 3188 case IP_VERSION(13, 0, 2): 3189 adev->smuio.funcs = &smuio_v13_0_funcs; 3190 break; 3191 case IP_VERSION(13, 0, 3): 3192 case IP_VERSION(13, 0, 11): 3193 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3194 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3195 adev->flags |= AMD_IS_APU; 3196 } 3197 break; 3198 case IP_VERSION(13, 0, 6): 3199 case IP_VERSION(13, 0, 8): 3200 case IP_VERSION(14, 0, 0): 3201 case IP_VERSION(14, 0, 1): 3202 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3203 break; 3204 case IP_VERSION(14, 0, 2): 3205 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3206 break; 3207 case IP_VERSION(15, 0, 0): 3208 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3209 break; 3210 case IP_VERSION(15, 0, 8): 3211 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3212 break; 3213 default: 3214 break; 3215 } 3216 3217 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3218 case IP_VERSION(6, 0, 0): 3219 case IP_VERSION(6, 0, 1): 3220 case IP_VERSION(6, 0, 2): 3221 case IP_VERSION(6, 0, 3): 3222 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3223 break; 3224 case IP_VERSION(7, 0, 0): 3225 case IP_VERSION(7, 0, 1): 3226 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3227 break; 3228 default: 3229 break; 3230 } 3231 3232 r = amdgpu_discovery_set_common_ip_blocks(adev); 3233 if (r) 3234 return r; 3235 3236 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3237 if (r) 3238 return r; 3239 3240 /* For SR-IOV, PSP needs to be initialized before IH */ 3241 if (amdgpu_sriov_vf(adev)) { 3242 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3243 if (r) 3244 return r; 3245 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3246 if (r) 3247 return r; 3248 } else { 3249 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3250 if (r) 3251 return r; 3252 3253 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3254 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3255 if (r) 3256 return r; 3257 } 3258 } 3259 3260 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3261 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3262 if (r) 3263 return r; 3264 } 3265 3266 r = amdgpu_discovery_set_display_ip_blocks(adev); 3267 if (r) 3268 return r; 3269 3270 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3271 if (r) 3272 return r; 3273 3274 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3275 if (r) 3276 return r; 3277 3278 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3279 if (r) 3280 return r; 3281 3282 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3283 !amdgpu_sriov_vf(adev) && 3284 amdgpu_dpm == 1) || 3285 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3286 amdgpu_dpm == 1)) { 3287 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3288 if (r) 3289 return r; 3290 } 3291 3292 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3293 if (r) 3294 return r; 3295 3296 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3297 if (r) 3298 return r; 3299 3300 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3301 if (r) 3302 return r; 3303 3304 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3305 if (r) 3306 return r; 3307 3308 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3309 if (r) 3310 return r; 3311 return 0; 3312 } 3313 3314