1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2018 - 2024 Intel Corporation */ 3 4 #ifndef IPU6_PLATFORM_REGS_H 5 #define IPU6_PLATFORM_REGS_H 6 7 #include <linux/bits.h> 8 9 /* 10 * IPU6 uses uniform address within IPU6, therefore all subsystem registers 11 * locates in one single space starts from 0 but in different sctions with 12 * different addresses, the subsystem offsets are defined to 0 as the 13 * register definition will have the address offset to 0. 14 */ 15 #define IPU6_UNIFIED_OFFSET 0 16 17 #define IPU6_ISYS_IOMMU0_OFFSET 0x2e0000 18 #define IPU6_ISYS_IOMMU1_OFFSET 0x2e0500 19 #define IPU6_ISYS_IOMMUI_OFFSET 0x2e0a00 20 21 #define IPU6_PSYS_IOMMU0_OFFSET 0x1b0000 22 #define IPU6_PSYS_IOMMU1_OFFSET 0x1b0700 23 #define IPU6_PSYS_IOMMU1R_OFFSET 0x1b0e00 24 #define IPU6_PSYS_IOMMUI_OFFSET 0x1b1500 25 26 /* the offset from IOMMU base register */ 27 #define IPU6_MMU_L1_STREAM_ID_REG_OFFSET 0x0c 28 #define IPU6_MMU_L2_STREAM_ID_REG_OFFSET 0x4c 29 #define IPU6_PSYS_MMU1W_L2_STREAM_ID_REG_OFFSET 0x8c 30 31 #define IPU6_MMU_INFO_OFFSET 0x8 32 33 #define IPU6_ISYS_SPC_OFFSET 0x210000 34 35 #define IPU6SE_PSYS_SPC_OFFSET 0x110000 36 #define IPU6_PSYS_SPC_OFFSET 0x118000 37 38 #define IPU6_ISYS_DMEM_OFFSET 0x200000 39 #define IPU6_PSYS_DMEM_OFFSET 0x100000 40 41 #define IPU6_REG_ISYS_UNISPART_IRQ_EDGE 0x27c000 42 #define IPU6_REG_ISYS_UNISPART_IRQ_MASK 0x27c004 43 #define IPU6_REG_ISYS_UNISPART_IRQ_STATUS 0x27c008 44 #define IPU6_REG_ISYS_UNISPART_IRQ_CLEAR 0x27c00c 45 #define IPU6_REG_ISYS_UNISPART_IRQ_ENABLE 0x27c010 46 #define IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE 0x27c014 47 #define IPU6_REG_ISYS_UNISPART_SW_IRQ_REG 0x27c414 48 #define IPU6_REG_ISYS_UNISPART_SW_IRQ_MUX_REG 0x27c418 49 #define IPU6_ISYS_UNISPART_IRQ_CSI0 BIT(2) 50 #define IPU6_ISYS_UNISPART_IRQ_CSI1 BIT(3) 51 #define IPU6_ISYS_UNISPART_IRQ_SW BIT(22) 52 53 #define IPU6_REG_ISYS_ISL_TOP_IRQ_EDGE 0x2b0200 54 #define IPU6_REG_ISYS_ISL_TOP_IRQ_MASK 0x2b0204 55 #define IPU6_REG_ISYS_ISL_TOP_IRQ_STATUS 0x2b0208 56 #define IPU6_REG_ISYS_ISL_TOP_IRQ_CLEAR 0x2b020c 57 #define IPU6_REG_ISYS_ISL_TOP_IRQ_ENABLE 0x2b0210 58 #define IPU6_REG_ISYS_ISL_TOP_IRQ_LEVEL_NOT_PULSE 0x2b0214 59 60 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_EDGE 0x2d2100 61 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK 0x2d2104 62 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_STATUS 0x2d2108 63 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_CLEAR 0x2d210c 64 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_ENABLE 0x2d2110 65 #define IPU6_REG_ISYS_CMPR_TOP_IRQ_LEVEL_NOT_PULSE 0x2d2114 66 67 /* CDC Burst collector thresholds for isys - 3 FIFOs i = 0..2 */ 68 #define IPU6_REG_ISYS_CDC_THRESHOLD(i) (0x27c400 + ((i) * 4)) 69 70 #define IPU6_CSI_IRQ_NUM_PER_PIPE 4 71 #define IPU6SE_ISYS_CSI_PORT_NUM 4 72 #define IPU6_ISYS_CSI_PORT_NUM 8 73 74 #define IPU6_ISYS_CSI_PORT_IRQ(irq_num) BIT(irq_num) 75 76 /* PKG DIR OFFSET in IMR in secure mode */ 77 #define IPU6_PKG_DIR_IMR_OFFSET 0x40 78 79 #define IPU6_ISYS_REG_SPC_STATUS_CTRL 0x0 80 81 #define IPU6_ISYS_SPC_STATUS_START BIT(1) 82 #define IPU6_ISYS_SPC_STATUS_RUN BIT(3) 83 #define IPU6_ISYS_SPC_STATUS_READY BIT(5) 84 #define IPU6_ISYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE BIT(12) 85 #define IPU6_ISYS_SPC_STATUS_ICACHE_PREFETCH BIT(13) 86 87 #define IPU6_PSYS_REG_SPC_STATUS_CTRL 0x0 88 #define IPU6_PSYS_REG_SPC_START_PC 0x4 89 #define IPU6_PSYS_REG_SPC_ICACHE_BASE 0x10 90 #define IPU6_REG_PSYS_INFO_SEG_0_CONFIG_ICACHE_MASTER 0x14 91 92 #define IPU6_PSYS_SPC_STATUS_START BIT(1) 93 #define IPU6_PSYS_SPC_STATUS_RUN BIT(3) 94 #define IPU6_PSYS_SPC_STATUS_READY BIT(5) 95 #define IPU6_PSYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE BIT(12) 96 #define IPU6_PSYS_SPC_STATUS_ICACHE_PREFETCH BIT(13) 97 98 #define IPU6_PSYS_REG_SPP0_STATUS_CTRL 0x20000 99 100 #define IPU6_INFO_ENABLE_SNOOP BIT(0) 101 #define IPU6_INFO_DEC_FORCE_FLUSH BIT(1) 102 #define IPU6_INFO_DEC_PASS_THROUGH BIT(2) 103 #define IPU6_INFO_ZLW BIT(3) 104 #define IPU6_INFO_REQUEST_DESTINATION_IOSF BIT(9) 105 #define IPU6_INFO_IMR_BASE BIT(10) 106 #define IPU6_INFO_IMR_DESTINED BIT(11) 107 108 #define IPU6_INFO_REQUEST_DESTINATION_PRIMARY IPU6_INFO_REQUEST_DESTINATION_IOSF 109 110 /* 111 * s2m_pixel_soc_pixel_remapping is dedicated for the enabling of the 112 * pixel s2m remp ability.Remap here means that s2m rearange the order 113 * of the pixels in each 4 pixels group. 114 * For examle, mirroring remping means that if input's 4 first pixels 115 * are 1 2 3 4 then in output we should see 4 3 2 1 in this 4 first pixels. 116 * 0xE4 is from s2m MAS document. It means no remapping. 117 */ 118 #define S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING 0xe4 119 /* 120 * csi_be_soc_pixel_remapping is for the enabling of the pixel remapping. 121 * This remapping is exactly like the stream2mmio remapping. 122 */ 123 #define CSI_BE_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING 0xe4 124 125 #define IPU6_REG_DMA_TOP_AB_GROUP1_BASE_ADDR 0x1ae000 126 #define IPU6_REG_DMA_TOP_AB_GROUP2_BASE_ADDR 0x1af000 127 #define IPU6_REG_DMA_TOP_AB_RING_MIN_OFFSET(n) (0x4 + (n) * 0xc) 128 #define IPU6_REG_DMA_TOP_AB_RING_MAX_OFFSET(n) (0x8 + (n) * 0xc) 129 #define IPU6_REG_DMA_TOP_AB_RING_ACCESS_OFFSET(n) (0xc + (n) * 0xc) 130 131 enum ipu6_device_ab_group1_target_id { 132 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R0_SPC_DMEM, 133 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R1_SPC_DMEM, 134 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R2_SPC_DMEM, 135 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R3_SPC_STATUS_REG, 136 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R4_SPC_MASTER_BASE_ADDR, 137 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R5_SPC_PC_STALL, 138 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R6_SPC_EQ, 139 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R7_SPC_RESERVED, 140 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R8_SPC_RESERVED, 141 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R9_SPP0, 142 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R10_SPP1, 143 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R11_CENTRAL_R1, 144 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R12_IRQ, 145 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R13_CENTRAL_R2, 146 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R14_DMA, 147 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R15_DMA, 148 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R16_GP, 149 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R17_ZLW_INSERTER, 150 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R18_AB, 151 }; 152 153 enum nci_ab_access_mode { 154 NCI_AB_ACCESS_MODE_RW, /* read & write */ 155 NCI_AB_ACCESS_MODE_RO, /* read only */ 156 NCI_AB_ACCESS_MODE_WO, /* write only */ 157 NCI_AB_ACCESS_MODE_NA, /* No access at all */ 158 }; 159 160 /* IRQ-related registers in PSYS */ 161 #define IPU6_REG_PSYS_GPDEV_IRQ_EDGE 0x1aa200 162 #define IPU6_REG_PSYS_GPDEV_IRQ_MASK 0x1aa204 163 #define IPU6_REG_PSYS_GPDEV_IRQ_STATUS 0x1aa208 164 #define IPU6_REG_PSYS_GPDEV_IRQ_CLEAR 0x1aa20c 165 #define IPU6_REG_PSYS_GPDEV_IRQ_ENABLE 0x1aa210 166 #define IPU6_REG_PSYS_GPDEV_IRQ_LEVEL_NOT_PULSE 0x1aa214 167 /* There are 8 FW interrupts, n = 0..7 */ 168 #define IPU6_PSYS_GPDEV_FWIRQ0 5 169 #define IPU6_PSYS_GPDEV_FWIRQ1 6 170 #define IPU6_PSYS_GPDEV_FWIRQ2 7 171 #define IPU6_PSYS_GPDEV_FWIRQ3 8 172 #define IPU6_PSYS_GPDEV_FWIRQ4 9 173 #define IPU6_PSYS_GPDEV_FWIRQ5 10 174 #define IPU6_PSYS_GPDEV_FWIRQ6 11 175 #define IPU6_PSYS_GPDEV_FWIRQ7 12 176 #define IPU6_PSYS_GPDEV_IRQ_FWIRQ(n) BIT(n) 177 #define IPU6_REG_PSYS_GPDEV_FWIRQ(n) (4 * (n) + 0x1aa100) 178 179 #endif /* IPU6_PLATFORM_REGS_H */ 180