1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2024 Rockchip Electronics Co., Ltd.
4 * Author:
5 * Guochun Huang <hero.huang@rock-chips.com>
6 * Heiko Stuebner <heiko.stuebner@cherry.de>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/phy/phy.h>
21
22 #include <drm/bridge/dw_mipi_dsi2.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25
26 #include <uapi/linux/videodev2.h>
27
28 #include "rockchip_drm_drv.h"
29
30 #define PSEC_PER_SEC 1000000000000LL
31
32 struct dsigrf_reg {
33 u16 offset;
34 u16 lsb;
35 u16 msb;
36 };
37
38 enum grf_reg_fields {
39 TXREQCLKHS_EN,
40 GATING_EN,
41 IPI_SHUTDN,
42 IPI_COLORM,
43 IPI_COLOR_DEPTH,
44 IPI_FORMAT,
45 MAX_FIELDS,
46 };
47
48 #define IPI_DEPTH_5_6_5_BITS 0x02
49 #define IPI_DEPTH_6_BITS 0x03
50 #define IPI_DEPTH_8_BITS 0x05
51 #define IPI_DEPTH_10_BITS 0x06
52
53 struct rockchip_dw_dsi2_chip_data {
54 u32 reg;
55 const struct dsigrf_reg *grf_regs;
56 unsigned long long max_bit_rate_per_lane;
57 };
58
59 struct dw_mipi_dsi2_rockchip {
60 struct device *dev;
61 struct rockchip_encoder encoder;
62 struct regmap *regmap;
63
64 unsigned int lane_mbps; /* per lane */
65 u32 format;
66
67 struct regmap *grf_regmap;
68 struct phy *phy;
69 union phy_configure_opts phy_opts;
70
71 struct dw_mipi_dsi2 *dmd;
72 struct dw_mipi_dsi2_plat_data pdata;
73 const struct rockchip_dw_dsi2_chip_data *cdata;
74 };
75
to_dsi2(struct drm_encoder * encoder)76 static inline struct dw_mipi_dsi2_rockchip *to_dsi2(struct drm_encoder *encoder)
77 {
78 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
79
80 return container_of(rkencoder, struct dw_mipi_dsi2_rockchip, encoder);
81 }
82
grf_field_write(struct dw_mipi_dsi2_rockchip * dsi2,enum grf_reg_fields index,unsigned int val)83 static void grf_field_write(struct dw_mipi_dsi2_rockchip *dsi2, enum grf_reg_fields index,
84 unsigned int val)
85 {
86 const struct dsigrf_reg *field = &dsi2->cdata->grf_regs[index];
87
88 if (!field)
89 return;
90
91 regmap_write(dsi2->grf_regmap, field->offset,
92 (val << field->lsb) | (GENMASK(field->msb, field->lsb) << 16));
93 }
94
dw_mipi_dsi2_phy_init(void * priv_data)95 static int dw_mipi_dsi2_phy_init(void *priv_data)
96 {
97 return 0;
98 }
99
dw_mipi_dsi2_phy_power_on(void * priv_data)100 static void dw_mipi_dsi2_phy_power_on(void *priv_data)
101 {
102 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data;
103 int ret;
104
105 ret = phy_set_mode(dsi2->phy, PHY_MODE_MIPI_DPHY);
106 if (ret) {
107 dev_err(dsi2->dev, "Failed to set phy mode: %d\n", ret);
108 return;
109 }
110
111 phy_configure(dsi2->phy, &dsi2->phy_opts);
112 phy_power_on(dsi2->phy);
113 }
114
dw_mipi_dsi2_phy_power_off(void * priv_data)115 static void dw_mipi_dsi2_phy_power_off(void *priv_data)
116 {
117 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data;
118
119 phy_power_off(dsi2->phy);
120 }
121
122 static int
dw_mipi_dsi2_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)123 dw_mipi_dsi2_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
124 unsigned long mode_flags, u32 lanes, u32 format,
125 unsigned int *lane_mbps)
126 {
127 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data;
128 u64 max_lane_rate, target_phyclk;
129 unsigned int lane_rate_kbps;
130 int bpp;
131
132 max_lane_rate = dsi2->cdata->max_bit_rate_per_lane;
133
134 dsi2->format = format;
135 bpp = mipi_dsi_pixel_format_to_bpp(format);
136 if (bpp < 0) {
137 dev_err(dsi2->dev, "failed to get bpp for pixel format %d\n", format);
138 return bpp;
139 }
140
141 lane_rate_kbps = mode->clock * bpp / lanes;
142
143 /*
144 * Set BW a little larger only in video burst mode in
145 * consideration of the protocol overhead and HS mode
146 * switching to BLLP mode, take 1 / 0.9, since Mbps must
147 * big than bandwidth of RGB
148 */
149 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
150 lane_rate_kbps = (lane_rate_kbps * 10) / 9;
151
152 if (lane_rate_kbps > max_lane_rate) {
153 dev_err(dsi2->dev, "DPHY clock frequency is out of range\n");
154 return -ERANGE;
155 }
156
157 dsi2->lane_mbps = lane_rate_kbps / 1000;
158 *lane_mbps = dsi2->lane_mbps;
159
160 if (dsi2->phy) {
161 target_phyclk = DIV_ROUND_CLOSEST_ULL(lane_rate_kbps * lanes * 1000, bpp);
162 phy_mipi_dphy_get_default_config(target_phyclk, bpp, lanes,
163 &dsi2->phy_opts.mipi_dphy);
164 }
165
166 return 0;
167 }
168
dw_mipi_dsi2_phy_get_iface(void * priv_data,struct dw_mipi_dsi2_phy_iface * iface)169 static void dw_mipi_dsi2_phy_get_iface(void *priv_data, struct dw_mipi_dsi2_phy_iface *iface)
170 {
171 /* PPI width is fixed to 16 bits in DCPHY */
172 iface->ppi_width = 16;
173 iface->phy_type = DW_MIPI_DSI2_DPHY;
174 }
175
176 static int
dw_mipi_dsi2_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi2_phy_timing * timing)177 dw_mipi_dsi2_phy_get_timing(void *priv_data, unsigned int lane_mbps,
178 struct dw_mipi_dsi2_phy_timing *timing)
179 {
180 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data;
181 struct phy_configure_opts_mipi_dphy *cfg = &dsi2->phy_opts.mipi_dphy;
182 unsigned long long tmp, ui;
183 unsigned long long hstx_clk;
184
185 hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_mbps * USEC_PER_SEC, 16);
186
187 ui = ALIGN(PSEC_PER_SEC, hstx_clk);
188 do_div(ui, hstx_clk);
189
190 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */
191 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero;
192 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
193 timing->data_lp2hs = tmp;
194
195 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */
196 tmp = cfg->hs_trail + cfg->hs_exit;
197 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
198 timing->data_hs2lp = tmp;
199
200 return 0;
201 }
202
203 static const struct dw_mipi_dsi2_phy_ops dw_mipi_dsi2_rockchip_phy_ops = {
204 .init = dw_mipi_dsi2_phy_init,
205 .power_on = dw_mipi_dsi2_phy_power_on,
206 .power_off = dw_mipi_dsi2_phy_power_off,
207 .get_interface = dw_mipi_dsi2_phy_get_iface,
208 .get_lane_mbps = dw_mipi_dsi2_get_lane_mbps,
209 .get_timing = dw_mipi_dsi2_phy_get_timing,
210 };
211
dw_mipi_dsi2_encoder_atomic_enable(struct drm_encoder * encoder,struct drm_atomic_commit * state)212 static void dw_mipi_dsi2_encoder_atomic_enable(struct drm_encoder *encoder,
213 struct drm_atomic_commit *state)
214 {
215 struct dw_mipi_dsi2_rockchip *dsi2 = to_dsi2(encoder);
216 u32 color_depth;
217
218 switch (dsi2->format) {
219 case MIPI_DSI_FMT_RGB666:
220 case MIPI_DSI_FMT_RGB666_PACKED:
221 color_depth = IPI_DEPTH_6_BITS;
222 break;
223 case MIPI_DSI_FMT_RGB565:
224 color_depth = IPI_DEPTH_5_6_5_BITS;
225 break;
226 case MIPI_DSI_FMT_RGB888:
227 color_depth = IPI_DEPTH_8_BITS;
228 break;
229 default:
230 /* Should've been caught by atomic_check */
231 WARN_ON(1);
232 return;
233 }
234
235 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth);
236 }
237
238 static int
dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)239 dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder *encoder,
240 struct drm_crtc_state *crtc_state,
241 struct drm_connector_state *conn_state)
242 {
243 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
244 struct dw_mipi_dsi2_rockchip *dsi2 = to_dsi2(encoder);
245 struct drm_connector *connector = conn_state->connector;
246 struct drm_display_info *info = &connector->display_info;
247
248 switch (dsi2->format) {
249 case MIPI_DSI_FMT_RGB666:
250 case MIPI_DSI_FMT_RGB666_PACKED:
251 s->output_mode = ROCKCHIP_OUT_MODE_P666;
252 break;
253 case MIPI_DSI_FMT_RGB565:
254 s->output_mode = ROCKCHIP_OUT_MODE_P565;
255 break;
256 case MIPI_DSI_FMT_RGB888:
257 s->output_mode = ROCKCHIP_OUT_MODE_P888;
258 break;
259 default:
260 WARN_ON(1);
261 return -EINVAL;
262 }
263
264 if (info->num_bus_formats)
265 s->bus_format = info->bus_formats[0];
266 else
267 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
268
269 s->output_type = DRM_MODE_CONNECTOR_DSI;
270 s->bus_flags = info->bus_flags;
271 s->color_space = V4L2_COLORSPACE_DEFAULT;
272
273 return 0;
274 }
275
276 static const struct drm_encoder_funcs dw_mipi_dsi2_encoder_funcs = {
277 .destroy = drm_encoder_cleanup,
278 };
279
280 static const struct drm_encoder_helper_funcs
281 dw_mipi_dsi2_encoder_helper_funcs = {
282 .atomic_enable = dw_mipi_dsi2_encoder_atomic_enable,
283 .atomic_check = dw_mipi_dsi2_encoder_atomic_check,
284 };
285
rockchip_dsi2_drm_create_encoder(struct dw_mipi_dsi2_rockchip * dsi2,struct drm_device * drm_dev)286 static int rockchip_dsi2_drm_create_encoder(struct dw_mipi_dsi2_rockchip *dsi2,
287 struct drm_device *drm_dev)
288 {
289 struct drm_encoder *encoder = &dsi2->encoder.encoder;
290 int ret;
291
292 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
293 dsi2->dev->of_node);
294
295 ret = drm_encoder_init(drm_dev, encoder, &dw_mipi_dsi2_encoder_funcs,
296 DRM_MODE_ENCODER_DSI, NULL);
297 if (ret) {
298 dev_err(dsi2->dev, "Failed to initialize encoder with drm\n");
299 return ret;
300 }
301
302 drm_encoder_helper_add(encoder, &dw_mipi_dsi2_encoder_helper_funcs);
303
304 return 0;
305 }
306
dw_mipi_dsi2_rockchip_bind(struct device * dev,struct device * master,void * data)307 static int dw_mipi_dsi2_rockchip_bind(struct device *dev, struct device *master,
308 void *data)
309 {
310 struct dw_mipi_dsi2_rockchip *dsi2 = dev_get_drvdata(dev);
311 struct drm_device *drm_dev = data;
312 int ret;
313
314 ret = rockchip_dsi2_drm_create_encoder(dsi2, drm_dev);
315 if (ret)
316 return dev_err_probe(dev, ret, "Failed to create drm encoder\n");
317
318 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi2->encoder,
319 dev->of_node, 0, 0);
320
321 ret = dw_mipi_dsi2_bind(dsi2->dmd, &dsi2->encoder.encoder);
322 if (ret)
323 return dev_err_probe(dev, ret, "Failed to bind\n");
324
325 return 0;
326 }
327
dw_mipi_dsi2_rockchip_unbind(struct device * dev,struct device * master,void * data)328 static void dw_mipi_dsi2_rockchip_unbind(struct device *dev, struct device *master,
329 void *data)
330 {
331 struct dw_mipi_dsi2_rockchip *dsi2 = dev_get_drvdata(dev);
332
333 dw_mipi_dsi2_unbind(dsi2->dmd);
334 }
335
336 static const struct component_ops dw_mipi_dsi2_rockchip_ops = {
337 .bind = dw_mipi_dsi2_rockchip_bind,
338 .unbind = dw_mipi_dsi2_rockchip_unbind,
339 };
340
dw_mipi_dsi2_rockchip_host_attach(void * priv_data,struct mipi_dsi_device * device)341 static int dw_mipi_dsi2_rockchip_host_attach(void *priv_data,
342 struct mipi_dsi_device *device)
343 {
344 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data;
345 int ret;
346
347 ret = component_add(dsi2->dev, &dw_mipi_dsi2_rockchip_ops);
348 if (ret)
349 return dev_err_probe(dsi2->dev, ret, "Failed to register component\n");
350
351 return 0;
352 }
353
dw_mipi_dsi2_rockchip_host_detach(void * priv_data,struct mipi_dsi_device * device)354 static int dw_mipi_dsi2_rockchip_host_detach(void *priv_data,
355 struct mipi_dsi_device *device)
356 {
357 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data;
358
359 component_del(dsi2->dev, &dw_mipi_dsi2_rockchip_ops);
360
361 return 0;
362 }
363
364 static const struct dw_mipi_dsi2_host_ops dw_mipi_dsi2_rockchip_host_ops = {
365 .attach = dw_mipi_dsi2_rockchip_host_attach,
366 .detach = dw_mipi_dsi2_rockchip_host_detach,
367 };
368
369 static const struct regmap_config dw_mipi_dsi2_rockchip_regmap_config = {
370 .name = "dsi2-host",
371 .reg_bits = 32,
372 .val_bits = 32,
373 .reg_stride = 4,
374 .fast_io = true,
375 };
376
dw_mipi_dsi2_rockchip_probe(struct platform_device * pdev)377 static int dw_mipi_dsi2_rockchip_probe(struct platform_device *pdev)
378 {
379 struct device *dev = &pdev->dev;
380 struct device_node *np = dev->of_node;
381 const struct rockchip_dw_dsi2_chip_data *cdata =
382 of_device_get_match_data(dev);
383 struct dw_mipi_dsi2_rockchip *dsi2;
384 struct resource *res;
385 void __iomem *base;
386 int i;
387
388 dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
389 if (!dsi2)
390 return -ENOMEM;
391
392 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
393 if (IS_ERR(base))
394 return dev_err_probe(dev, PTR_ERR(base), "Unable to get dsi registers\n");
395
396 dsi2->regmap = devm_regmap_init_mmio(dev, base, &dw_mipi_dsi2_rockchip_regmap_config);
397 if (IS_ERR(dsi2->regmap))
398 return dev_err_probe(dev, PTR_ERR(dsi2->regmap), "failed to init register map\n");
399
400 i = 0;
401 while (cdata[i].reg) {
402 if (cdata[i].reg == res->start) {
403 dsi2->cdata = &cdata[i];
404 break;
405 }
406
407 i++;
408 }
409
410 if (!dsi2->cdata)
411 return dev_err_probe(dev, -EINVAL, "No dsi-config for %s node\n", np->name);
412
413 dsi2->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
414 if (IS_ERR(dsi2->grf_regmap))
415 return dev_err_probe(dsi2->dev, PTR_ERR(dsi2->grf_regmap), "Unable to get grf\n");
416
417 dsi2->phy = devm_phy_optional_get(dev, "dcphy");
418 if (IS_ERR(dsi2->phy))
419 return dev_err_probe(dev, PTR_ERR(dsi2->phy), "failed to get mipi phy\n");
420
421 dsi2->dev = dev;
422 dsi2->pdata.regmap = dsi2->regmap;
423 dsi2->pdata.max_data_lanes = 4;
424 dsi2->pdata.phy_ops = &dw_mipi_dsi2_rockchip_phy_ops;
425 dsi2->pdata.host_ops = &dw_mipi_dsi2_rockchip_host_ops;
426 dsi2->pdata.priv_data = dsi2;
427 platform_set_drvdata(pdev, dsi2);
428
429 dsi2->dmd = dw_mipi_dsi2_probe(pdev, &dsi2->pdata);
430 if (IS_ERR(dsi2->dmd))
431 return dev_err_probe(dev, PTR_ERR(dsi2->dmd), "Failed to probe dw_mipi_dsi2\n");
432
433 return 0;
434 }
435
dw_mipi_dsi2_rockchip_remove(struct platform_device * pdev)436 static void dw_mipi_dsi2_rockchip_remove(struct platform_device *pdev)
437 {
438 struct dw_mipi_dsi2_rockchip *dsi2 = platform_get_drvdata(pdev);
439
440 dw_mipi_dsi2_remove(dsi2->dmd);
441 }
442
443 static const struct dsigrf_reg rk3576_dsi_grf_reg_fields[MAX_FIELDS] = {
444 [TXREQCLKHS_EN] = { 0x0028, 1, 1 },
445 [GATING_EN] = { 0x0028, 0, 0 },
446 [IPI_SHUTDN] = { 0x0028, 3, 3 },
447 [IPI_COLORM] = { 0x0028, 2, 2 },
448 [IPI_COLOR_DEPTH] = { 0x0028, 8, 11 },
449 [IPI_FORMAT] = { 0x0028, 4, 7 },
450 };
451
452 static const struct dsigrf_reg rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = {
453 [TXREQCLKHS_EN] = { 0x0000, 11, 11 },
454 [GATING_EN] = { 0x0000, 10, 10 },
455 [IPI_SHUTDN] = { 0x0000, 9, 9 },
456 [IPI_COLORM] = { 0x0000, 8, 8 },
457 [IPI_COLOR_DEPTH] = { 0x0000, 4, 7 },
458 [IPI_FORMAT] = { 0x0000, 0, 3 },
459 };
460
461 static const struct dsigrf_reg rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = {
462 [TXREQCLKHS_EN] = { 0x0004, 11, 11 },
463 [GATING_EN] = { 0x0004, 10, 10 },
464 [IPI_SHUTDN] = { 0x0004, 9, 9 },
465 [IPI_COLORM] = { 0x0004, 8, 8 },
466 [IPI_COLOR_DEPTH] = { 0x0004, 4, 7 },
467 [IPI_FORMAT] = { 0x0004, 0, 3 },
468 };
469
470 static const struct rockchip_dw_dsi2_chip_data rk3576_chip_data[] = {
471 {
472 .reg = 0x27d80000,
473 .grf_regs = rk3576_dsi_grf_reg_fields,
474 .max_bit_rate_per_lane = 2500000ULL,
475 },
476 { /* sentinel */ }
477 };
478
479 static const struct rockchip_dw_dsi2_chip_data rk3588_chip_data[] = {
480 {
481 .reg = 0xfde20000,
482 .grf_regs = rk3588_dsi0_grf_reg_fields,
483 .max_bit_rate_per_lane = 4500000ULL,
484 },
485 {
486 .reg = 0xfde30000,
487 .grf_regs = rk3588_dsi1_grf_reg_fields,
488 .max_bit_rate_per_lane = 4500000ULL,
489 }
490 };
491
492 static const struct of_device_id dw_mipi_dsi2_rockchip_dt_ids[] = {
493 {
494 .compatible = "rockchip,rk3576-mipi-dsi2",
495 .data = &rk3576_chip_data,
496 }, {
497 .compatible = "rockchip,rk3588-mipi-dsi2",
498 .data = &rk3588_chip_data,
499 },
500 {}
501 };
502 MODULE_DEVICE_TABLE(of, dw_mipi_dsi2_rockchip_dt_ids);
503
504 struct platform_driver dw_mipi_dsi2_rockchip_driver = {
505 .probe = dw_mipi_dsi2_rockchip_probe,
506 .remove = dw_mipi_dsi2_rockchip_remove,
507 .driver = {
508 .of_match_table = dw_mipi_dsi2_rockchip_dt_ids,
509 .name = "dw-mipi-dsi2",
510 },
511 };
512