1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel MID platform setup code 4 * 5 * (C) Copyright 2008, 2012, 2021 Intel Corporation 6 * Author: Jacob Pan (jacob.jun.pan@intel.com) 7 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 8 */ 9 10 #define pr_fmt(fmt) "intel_mid: " fmt 11 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/regulator/machine.h> 16 #include <linux/scatterlist.h> 17 #include <linux/irq.h> 18 #include <linux/export.h> 19 #include <linux/notifier.h> 20 21 #include <asm/setup.h> 22 #include <asm/mpspec_def.h> 23 #include <asm/hw_irq.h> 24 #include <asm/apic.h> 25 #include <asm/cpu_device_id.h> 26 #include <asm/io_apic.h> 27 #include <asm/intel-mid.h> 28 #include <asm/io.h> 29 #include <asm/i8259.h> 30 #include <asm/reboot.h> 31 32 #include <linux/platform_data/x86/intel_scu_ipc.h> 33 34 #define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */ 35 #define IPCMSG_COLD_RESET 0xF1 36 intel_mid_power_off(void)37static void intel_mid_power_off(void) 38 { 39 /* Shut down South Complex via PWRMU */ 40 intel_mid_pwr_power_off(); 41 42 /* Only for Tangier, the rest will ignore this command */ 43 intel_scu_ipc_dev_simple_command(NULL, IPCMSG_COLD_OFF, 1); 44 }; 45 intel_mid_reboot(void)46static void intel_mid_reboot(void) 47 { 48 intel_scu_ipc_dev_simple_command(NULL, IPCMSG_COLD_RESET, 0); 49 } 50 intel_mid_time_init(void)51static void __init intel_mid_time_init(void) 52 { 53 /* Lapic only, no apbt */ 54 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 55 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 56 } 57 intel_mid_arch_setup(void)58static void intel_mid_arch_setup(void) 59 { 60 switch (boot_cpu_data.x86_vfm) { 61 case INTEL_ATOM_SILVERMONT_MID: 62 x86_platform.legacy.rtc = 1; 63 break; 64 default: 65 break; 66 } 67 68 /* 69 * Intel MID platforms are using explicitly defined regulators. 70 * 71 * Let the regulator core know that we do not have any additional 72 * regulators left. This lets it substitute unprovided regulators with 73 * dummy ones: 74 */ 75 regulator_has_full_constraints(); 76 } 77 78 /* 79 * Moorestown does not have external NMI source nor port 0x61 to report 80 * NMI status. The possible NMI sources are from pmu as a result of NMI 81 * watchdog or lock debug. Reading io port 0x61 results in 0xff which 82 * misled NMI handler. 83 */ intel_mid_get_nmi_reason(void)84static unsigned char intel_mid_get_nmi_reason(void) 85 { 86 return 0; 87 } 88 89 /* 90 * Moorestown specific x86_init function overrides and early setup 91 * calls. 92 */ x86_intel_mid_early_setup(void)93void __init x86_intel_mid_early_setup(void) 94 { 95 x86_init.resources.probe_roms = x86_init_noop; 96 x86_init.resources.reserve_resources = x86_init_noop; 97 98 x86_init.timers.timer_init = intel_mid_time_init; 99 x86_init.timers.setup_percpu_clockev = x86_init_noop; 100 101 x86_init.irqs.pre_vector_init = x86_init_noop; 102 103 x86_init.oem.arch_setup = intel_mid_arch_setup; 104 105 x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; 106 107 x86_init.pci.arch_init = intel_mid_pci_init; 108 x86_init.pci.fixup_irqs = x86_init_noop; 109 110 legacy_pic = &null_legacy_pic; 111 112 /* 113 * Do nothing for now as everything needed done in 114 * x86_intel_mid_early_setup() below. 115 */ 116 x86_init.acpi.reduced_hw_early_init = x86_init_noop; 117 118 pm_power_off = intel_mid_power_off; 119 machine_ops.emergency_restart = intel_mid_reboot; 120 121 /* Avoid searching for BIOS MP tables */ 122 x86_init.mpparse.find_mptable = x86_init_noop; 123 x86_init.mpparse.early_parse_smp_cfg = x86_init_noop; 124 x86_init.mpparse.parse_smp_cfg = x86_init_noop; 125 set_bit(MP_BUS_ISA, mp_bus_not_pci); 126 } 127