xref: /linux/drivers/net/ipa/data/ipa_data-v5.0.c (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
4 
5 #include <linux/array_size.h>
6 #include <linux/log2.h>
7 
8 #include "../ipa_data.h"
9 #include "../ipa_endpoint.h"
10 #include "../ipa_mem.h"
11 #include "../ipa_version.h"
12 
13 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */
14 enum ipa_resource_type {
15 	/* Source resource types; first must have value 0 */
16 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
17 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
18 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
19 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
20 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
21 
22 	/* Destination resource types; first must have value 0 */
23 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
24 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
25 	IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
26 };
27 
28 /* Resource groups used for an SoC having IPA v5.0 */
29 enum ipa_rsrc_group_id {
30 	/* Source resource group identifiers */
31 	IPA_RSRC_GROUP_SRC_UL				= 0,
32 	IPA_RSRC_GROUP_SRC_DL,
33 	IPA_RSRC_GROUP_SRC_UNUSED_2,
34 	IPA_RSRC_GROUP_SRC_UNUSED_3,
35 	IPA_RSRC_GROUP_SRC_URLLC,
36 	IPA_RSRC_GROUP_SRC_U_RX_QC,
37 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
38 
39 	/* Destination resource group identifiers */
40 	IPA_RSRC_GROUP_DST_UL				= 0,
41 	IPA_RSRC_GROUP_DST_DL,
42 	IPA_RSRC_GROUP_DST_DMA,
43 	IPA_RSRC_GROUP_DST_QDSS,
44 	IPA_RSRC_GROUP_DST_CV2X,
45 	IPA_RSRC_GROUP_DST_UC,
46 	IPA_RSRC_GROUP_DST_DRB_IP,
47 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
48 };
49 
50 /* QSB configuration data for an SoC having IPA v5.0 */
51 static const struct ipa_qsb_data ipa_qsb_data[] = {
52 	[IPA_QSB_MASTER_DDR] = {
53 		.max_writes		= 0,
54 		.max_reads		= 0,	/* no limit (hardware max) */
55 		.max_reads_beats	= 0,
56 	},
57 	[IPA_QSB_MASTER_PCIE] = {
58 		.max_writes		= 0,
59 		.max_reads		= 0,	/* no limit (hardware max) */
60 		.max_reads_beats	= 0,
61 	},
62 };
63 
64 /* Endpoint configuration data for an SoC having IPA v5.0 */
65 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
66 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
67 		.ee_id		= GSI_EE_AP,
68 		.channel_id	= 12,
69 		.endpoint_id	= 14,
70 		.toward_ipa	= true,
71 		.channel = {
72 			.tre_count	= 256,
73 			.event_count	= 256,
74 			.tlv_count	= 20,
75 		},
76 		.endpoint = {
77 			.config = {
78 				.resource_group	= IPA_RSRC_GROUP_SRC_UL,
79 				.dma_mode	= true,
80 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
81 				.tx = {
82 					.seq_type = IPA_SEQ_DMA,
83 				},
84 			},
85 		},
86 	},
87 	[IPA_ENDPOINT_AP_LAN_RX] = {
88 		.ee_id		= GSI_EE_AP,
89 		.channel_id	= 13,
90 		.endpoint_id	= 16,
91 		.toward_ipa	= false,
92 		.channel = {
93 			.tre_count	= 256,
94 			.event_count	= 256,
95 			.tlv_count	= 9,
96 		},
97 		.endpoint = {
98 			.config = {
99 				.resource_group	= IPA_RSRC_GROUP_DST_UL,
100 				.aggregation	= true,
101 				.status_enable	= true,
102 				.rx = {
103 					.buffer_size	= 8192,
104 					.pad_align	= ilog2(sizeof(u32)),
105 					.aggr_time_limit = 500,
106 				},
107 			},
108 		},
109 	},
110 	[IPA_ENDPOINT_AP_MODEM_TX] = {
111 		.ee_id		= GSI_EE_AP,
112 		.channel_id	= 11,
113 		.endpoint_id	= 2,
114 		.toward_ipa	= true,
115 		.channel = {
116 			.tre_count	= 512,
117 			.event_count	= 512,
118 			.tlv_count	= 25,
119 		},
120 		.endpoint = {
121 			.filter_support	= true,
122 			.config = {
123 				.resource_group	= IPA_RSRC_GROUP_SRC_UL,
124 				.checksum       = true,
125 				.qmap		= true,
126 				.status_enable	= true,
127 				.tx = {
128 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
129 					.status_endpoint =
130 						IPA_ENDPOINT_MODEM_AP_RX,
131 				},
132 			},
133 		},
134 	},
135 	[IPA_ENDPOINT_AP_MODEM_RX] = {
136 		.ee_id		= GSI_EE_AP,
137 		.channel_id	= 1,
138 		.endpoint_id	= 23,
139 		.toward_ipa	= false,
140 		.channel = {
141 			.tre_count	= 256,
142 			.event_count	= 256,
143 			.tlv_count	= 9,
144 		},
145 		.endpoint = {
146 			.config = {
147 				.resource_group	= IPA_RSRC_GROUP_DST_DL,
148 				.checksum       = true,
149 				.qmap		= true,
150 				.aggregation	= true,
151 				.rx = {
152 					.buffer_size	= 8192,
153 					.aggr_time_limit = 500,
154 					.aggr_close_eof	= true,
155 				},
156 			},
157 		},
158 	},
159 	[IPA_ENDPOINT_MODEM_AP_TX] = {
160 		.ee_id		= GSI_EE_MODEM,
161 		.channel_id	= 0,
162 		.endpoint_id	= 12,
163 		.toward_ipa	= true,
164 		.endpoint = {
165 			.filter_support	= true,
166 		},
167 	},
168 	[IPA_ENDPOINT_MODEM_AP_RX] = {
169 		.ee_id		= GSI_EE_MODEM,
170 		.channel_id	= 7,
171 		.endpoint_id	= 21,
172 		.toward_ipa	= false,
173 	},
174 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
175 		.ee_id		= GSI_EE_MODEM,
176 		.channel_id	= 2,
177 		.endpoint_id	= 15,
178 		.toward_ipa	= true,
179 		.endpoint = {
180 			.filter_support	= true,
181 		},
182 	},
183 };
184 
185 /* Source resource configuration data for an SoC having IPA v5.0 */
186 static const struct ipa_resource ipa_resource_src[] = {
187 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
188 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
189 			.min = 3,	.max = 9,
190 		},
191 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
192 			.min = 4,	.max = 10,
193 		},
194 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
195 			.min = 1,	.max = 63,
196 		},
197 		.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
198 			.min = 0,	.max = 63,
199 		},
200 	},
201 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
202 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
203 			.min = 9,	.max = 9,
204 		},
205 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
206 			.min = 12,	.max = 12,
207 		},
208 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
209 			.min = 10,	.max = 10,
210 		},
211 	},
212 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
213 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
214 			.min = 9,	.max = 9,
215 		},
216 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
217 			.min = 24,	.max = 24,
218 		},
219 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
220 			.min = 20,	.max = 20,
221 		},
222 	},
223 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
224 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
225 			.min = 0,	.max = 63,
226 		},
227 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
228 			.min = 0,	.max = 63,
229 		},
230 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
231 			.min = 1,	.max = 63,
232 		},
233 		.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
234 			.min = 0,	.max = 63,
235 		},
236 	},
237 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
238 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
239 			.min = 22,	.max = 22,
240 		},
241 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
242 			.min = 16,	.max = 16,
243 		},
244 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
245 			.min = 16,	.max = 16,
246 		},
247 	},
248 };
249 
250 /* Destination resource configuration data for an SoC having IPA v5.0 */
251 static const struct ipa_resource ipa_resource_dst[] = {
252 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
253 		.limits[IPA_RSRC_GROUP_DST_UL] = {
254 			.min = 6,	.max = 6,
255 		},
256 		.limits[IPA_RSRC_GROUP_DST_DL] = {
257 			.min = 5,	.max = 5,
258 		},
259 		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
260 			.min = 39,	.max = 39,
261 		},
262 	},
263 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
264 		.limits[IPA_RSRC_GROUP_DST_UL] = {
265 			.min = 0,	.max = 3,
266 		},
267 		.limits[IPA_RSRC_GROUP_DST_DL] = {
268 			.min = 0,	.max = 3,
269 		},
270 	},
271 	[IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
272 		.limits[IPA_RSRC_GROUP_DST_UL] = {
273 			.min = 0,	.max = 63,
274 		},
275 		.limits[IPA_RSRC_GROUP_DST_DL] = {
276 			.min = 0,	.max = 63,
277 		},
278 	},
279 };
280 
281 /* Resource configuration data for an SoC having IPA v5.0 */
282 static const struct ipa_resource_data ipa_resource_data = {
283 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
284 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
285 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
286 	.resource_src		= ipa_resource_src,
287 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
288 	.resource_dst		= ipa_resource_dst,
289 };
290 
291 /* IPA-resident memory region data for an SoC having IPA v5.0 */
292 static const struct ipa_mem ipa_mem_local_data[] = {
293 	{
294 		.id		= IPA_MEM_UC_EVENT_RING,
295 		.offset		= 0x0000,
296 		.size		= 0x1000,
297 		.canary_count	= 0,
298 	},
299 	{
300 		.id		= IPA_MEM_UC_SHARED,
301 		.offset		= 0x1000,
302 		.size		= 0x0080,
303 		.canary_count	= 0,
304 	},
305 	{
306 		.id		= IPA_MEM_UC_INFO,
307 		.offset		= 0x1080,
308 		.size		= 0x0200,
309 		.canary_count	= 0,
310 	},
311 	{
312 		.id		= IPA_MEM_V4_FILTER_HASHED,
313 		.offset		= 0x1288,
314 		.size		= 0x0078,
315 		.canary_count	= 2,
316 	},
317 	{
318 		.id		= IPA_MEM_V4_FILTER,
319 		.offset		= 0x1308,
320 		.size		= 0x0078,
321 		.canary_count	= 2,
322 	},
323 	{
324 		.id		= IPA_MEM_V6_FILTER_HASHED,
325 		.offset		= 0x1388,
326 		.size		= 0x0078,
327 		.canary_count	= 2,
328 	},
329 	{
330 		.id		= IPA_MEM_V6_FILTER,
331 		.offset		= 0x1408,
332 		.size		= 0x0078,
333 		.canary_count	= 2,
334 	},
335 	{
336 		.id		= IPA_MEM_V4_ROUTE_HASHED,
337 		.offset		= 0x1488,
338 		.size		= 0x0098,
339 		.canary_count	= 2,
340 	},
341 	{
342 		.id		= IPA_MEM_V4_ROUTE,
343 		.offset		= 0x1528,
344 		.size		= 0x0098,
345 		.canary_count	= 2,
346 	},
347 	{
348 		.id		= IPA_MEM_V6_ROUTE_HASHED,
349 		.offset		= 0x15c8,
350 		.size		= 0x0098,
351 		.canary_count	= 2,
352 	},
353 	{
354 		.id		= IPA_MEM_V6_ROUTE,
355 		.offset		= 0x1668,
356 		.size		= 0x0098,
357 		.canary_count	= 2,
358 	},
359 	{
360 		.id		= IPA_MEM_MODEM_HEADER,
361 		.offset		= 0x1708,
362 		.size		= 0x0240,
363 		.canary_count	= 2,
364 	},
365 	{
366 		.id		= IPA_MEM_AP_HEADER,
367 		.offset		= 0x1948,
368 		.size		= 0x01e0,
369 		.canary_count	= 0,
370 	},
371 	{
372 		.id		= IPA_MEM_MODEM_PROC_CTX,
373 		.offset		= 0x1b40,
374 		.size		= 0x0b20,
375 		.canary_count	= 2,
376 	},
377 	{
378 		.id		= IPA_MEM_AP_PROC_CTX,
379 		.offset		= 0x2660,
380 		.size		= 0x0200,
381 		.canary_count	= 0,
382 	},
383 	{
384 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
385 		.offset		= 0x2868,
386 		.size		= 0x0060,
387 		.canary_count	= 2,
388 	},
389 	{
390 		.id		= IPA_MEM_STATS_QUOTA_AP,
391 		.offset		= 0x28c8,
392 		.size		= 0x0048,
393 		.canary_count	= 0,
394 	},
395 	{
396 		.id		= IPA_MEM_AP_V4_FILTER,
397 		.offset		= 0x2918,
398 		.size		= 0x0118,
399 		.canary_count	= 2,
400 	},
401 	{
402 		.id		= IPA_MEM_AP_V6_FILTER,
403 		.offset		= 0x2aa0,
404 		.size		= 0x0228,
405 		.canary_count	= 0,
406 	},
407 	{
408 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
409 		.offset		= 0x2cd0,
410 		.size		= 0x0ba0,
411 		.canary_count	= 2,
412 	},
413 	{
414 		.id		= IPA_MEM_STATS_DROP,
415 		.offset		= 0x3870,
416 		.size		= 0x0020,
417 		.canary_count	= 0,
418 	},
419 	{
420 		.id		= IPA_MEM_MODEM,
421 		.offset		= 0x3898,
422 		.size		= 0x0d48,
423 		.canary_count	= 2,
424 	},
425 	{
426 		.id		= IPA_MEM_NAT_TABLE,
427 		.offset		= 0x45e0,
428 		.size		= 0x0900,
429 		.canary_count	= 0,
430 	},
431 	{
432 		.id		= IPA_MEM_PDN_CONFIG,
433 		.offset		= 0x4ee8,
434 		.size		= 0x0100,
435 		.canary_count	= 2,
436 	},
437 };
438 
439 /* Memory configuration data for an SoC having IPA v5.0 */
440 static const struct ipa_mem_data ipa_mem_data = {
441 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
442 	.local		= ipa_mem_local_data,
443 	.imem_addr	= 0x14688000,
444 	.imem_size	= 0x00003000,
445 	.smem_id	= 497,
446 	.smem_size	= 0x00009000,
447 };
448 
449 /* Interconnect rates are in 1000 byte/second units */
450 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
451 	{
452 		.name			= "memory",
453 		.peak_bandwidth		= 1900000,	/* 1.9 GBps */
454 		.average_bandwidth	= 600000,	/* 600 MBps */
455 	},
456 	/* Average rate is unused for the next interconnect */
457 	{
458 		.name			= "config",
459 		.peak_bandwidth		= 76800,	/* 76.8 MBps */
460 		.average_bandwidth	= 0,		/* unused */
461 	},
462 };
463 
464 /* Clock and interconnect configuration data for an SoC having IPA v5.0 */
465 static const struct ipa_power_data ipa_power_data = {
466 	.core_clock_rate	= 120 * 1000 * 1000,	/* Hz */
467 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
468 	.interconnect_data	= ipa_interconnect_data,
469 };
470 
471 /* Configuration data for an SoC having IPA v5.0. */
472 const struct ipa_data ipa_data_v5_0 = {
473 	.version		= IPA_VERSION_5_0,
474 	.qsb_count		= ARRAY_SIZE(ipa_qsb_data),
475 	.qsb_data		= ipa_qsb_data,
476 	.modem_route_count	= 11,
477 	.endpoint_count		= ARRAY_SIZE(ipa_gsi_endpoint_data),
478 	.endpoint_data		= ipa_gsi_endpoint_data,
479 	.resource_data		= &ipa_resource_data,
480 	.mem_data		= &ipa_mem_data,
481 	.power_data		= &ipa_power_data,
482 };
483