1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2025 Invensense, Inc. */ 3 4 #ifndef INV_ICM45600_H_ 5 #define INV_ICM45600_H_ 6 7 #include <linux/bits.h> 8 #include <linux/limits.h> 9 #include <linux/mutex.h> 10 #include <linux/regmap.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/sizes.h> 13 #include <linux/types.h> 14 15 #include <linux/iio/common/inv_sensors_timestamp.h> 16 #include <linux/iio/iio.h> 17 18 #include "inv_icm45600_buffer.h" 19 20 #define INV_ICM45600_REG_BANK_MASK GENMASK(15, 8) 21 #define INV_ICM45600_REG_ADDR_MASK GENMASK(7, 0) 22 23 enum inv_icm45600_sensor_mode { 24 INV_ICM45600_SENSOR_MODE_OFF, 25 INV_ICM45600_SENSOR_MODE_STANDBY, 26 INV_ICM45600_SENSOR_MODE_LOW_POWER, 27 INV_ICM45600_SENSOR_MODE_LOW_NOISE, 28 INV_ICM45600_SENSOR_MODE_MAX 29 }; 30 31 /* gyroscope fullscale values */ 32 enum inv_icm45600_gyro_fs { 33 INV_ICM45600_GYRO_FS_2000DPS, 34 INV_ICM45600_GYRO_FS_1000DPS, 35 INV_ICM45600_GYRO_FS_500DPS, 36 INV_ICM45600_GYRO_FS_250DPS, 37 INV_ICM45600_GYRO_FS_125DPS, 38 INV_ICM45600_GYRO_FS_62_5DPS, 39 INV_ICM45600_GYRO_FS_31_25DPS, 40 INV_ICM45600_GYRO_FS_15_625DPS, 41 INV_ICM45600_GYRO_FS_MAX 42 }; 43 44 enum inv_icm45686_gyro_fs { 45 INV_ICM45686_GYRO_FS_4000DPS, 46 INV_ICM45686_GYRO_FS_2000DPS, 47 INV_ICM45686_GYRO_FS_1000DPS, 48 INV_ICM45686_GYRO_FS_500DPS, 49 INV_ICM45686_GYRO_FS_250DPS, 50 INV_ICM45686_GYRO_FS_125DPS, 51 INV_ICM45686_GYRO_FS_62_5DPS, 52 INV_ICM45686_GYRO_FS_31_25DPS, 53 INV_ICM45686_GYRO_FS_15_625DPS, 54 INV_ICM45686_GYRO_FS_MAX 55 }; 56 57 /* accelerometer fullscale values */ 58 enum inv_icm45600_accel_fs { 59 INV_ICM45600_ACCEL_FS_16G, 60 INV_ICM45600_ACCEL_FS_8G, 61 INV_ICM45600_ACCEL_FS_4G, 62 INV_ICM45600_ACCEL_FS_2G, 63 INV_ICM45600_ACCEL_FS_MAX 64 }; 65 66 enum inv_icm45686_accel_fs { 67 INV_ICM45686_ACCEL_FS_32G, 68 INV_ICM45686_ACCEL_FS_16G, 69 INV_ICM45686_ACCEL_FS_8G, 70 INV_ICM45686_ACCEL_FS_4G, 71 INV_ICM45686_ACCEL_FS_2G, 72 INV_ICM45686_ACCEL_FS_MAX 73 }; 74 75 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ 76 enum inv_icm45600_odr { 77 INV_ICM45600_ODR_6400HZ_LN = 0x03, 78 INV_ICM45600_ODR_3200HZ_LN, 79 INV_ICM45600_ODR_1600HZ_LN, 80 INV_ICM45600_ODR_800HZ_LN, 81 INV_ICM45600_ODR_400HZ, 82 INV_ICM45600_ODR_200HZ, 83 INV_ICM45600_ODR_100HZ, 84 INV_ICM45600_ODR_50HZ, 85 INV_ICM45600_ODR_25HZ, 86 INV_ICM45600_ODR_12_5HZ, 87 INV_ICM45600_ODR_6_25HZ_LP, 88 INV_ICM45600_ODR_3_125HZ_LP, 89 INV_ICM45600_ODR_1_5625HZ_LP, 90 INV_ICM45600_ODR_MAX 91 }; 92 93 struct inv_icm45600_sensor_conf { 94 u8 mode; 95 u8 fs; 96 u8 odr; 97 u8 filter; 98 }; 99 100 #define INV_ICM45600_SENSOR_CONF_KEEP_VALUES { U8_MAX, U8_MAX, U8_MAX, U8_MAX } 101 102 struct inv_icm45600_conf { 103 struct inv_icm45600_sensor_conf gyro; 104 struct inv_icm45600_sensor_conf accel; 105 }; 106 107 struct inv_icm45600_suspended { 108 enum inv_icm45600_sensor_mode gyro; 109 enum inv_icm45600_sensor_mode accel; 110 }; 111 112 struct inv_icm45600_chip_info { 113 u8 whoami; 114 const char *name; 115 const struct inv_icm45600_conf *conf; 116 const int *accel_scales; 117 const int accel_scales_len; 118 const int *gyro_scales; 119 const int gyro_scales_len; 120 }; 121 122 extern const struct inv_icm45600_chip_info inv_icm45605_chip_info; 123 extern const struct inv_icm45600_chip_info inv_icm45606_chip_info; 124 extern const struct inv_icm45600_chip_info inv_icm45608_chip_info; 125 extern const struct inv_icm45600_chip_info inv_icm45634_chip_info; 126 extern const struct inv_icm45600_chip_info inv_icm45686_chip_info; 127 extern const struct inv_icm45600_chip_info inv_icm45687_chip_info; 128 extern const struct inv_icm45600_chip_info inv_icm45688p_chip_info; 129 extern const struct inv_icm45600_chip_info inv_icm45689_chip_info; 130 131 extern const int inv_icm45600_accel_scale[][2]; 132 extern const int inv_icm45686_accel_scale[][2]; 133 extern const int inv_icm45600_gyro_scale[][2]; 134 extern const int inv_icm45686_gyro_scale[][2]; 135 136 /** 137 * struct inv_icm45600_state - driver state variables 138 * @lock: lock for serializing multiple registers access. 139 * @map: regmap pointer. 140 * @vddio_supply: I/O voltage regulator for the chip. 141 * @orientation: sensor chip orientation relative to main hardware. 142 * @conf: chip sensors configurations. 143 * @suspended: suspended sensors configuration. 144 * @indio_gyro: gyroscope IIO device. 145 * @indio_accel: accelerometer IIO device. 146 * @chip_info: chip driver data. 147 * @timestamp: interrupt timestamps. 148 * @fifo: FIFO management structure. 149 * @buffer: data transfer buffer aligned for DMA. 150 */ 151 struct inv_icm45600_state { 152 struct mutex lock; 153 struct regmap *map; 154 struct regulator *vddio_supply; 155 struct iio_mount_matrix orientation; 156 struct inv_icm45600_conf conf; 157 struct inv_icm45600_suspended suspended; 158 struct iio_dev *indio_gyro; 159 struct iio_dev *indio_accel; 160 const struct inv_icm45600_chip_info *chip_info; 161 struct { 162 s64 gyro; 163 s64 accel; 164 } timestamp; 165 struct inv_icm45600_fifo fifo; 166 union { 167 u8 buff[2]; 168 __le16 u16; 169 u8 ireg[3]; 170 } buffer __aligned(IIO_DMA_MINALIGN); 171 }; 172 173 /** 174 * struct inv_icm45600_sensor_state - sensor state variables 175 * @scales: table of scales. 176 * @scales_len: length (nb of items) of the scales table. 177 * @power_mode: sensor requested power mode (for common frequencies) 178 * @ts: timestamp module states. 179 */ 180 struct inv_icm45600_sensor_state { 181 const int *scales; 182 size_t scales_len; 183 enum inv_icm45600_sensor_mode power_mode; 184 struct inv_sensors_timestamp ts; 185 }; 186 187 /* Virtual register addresses: @bank on MSB (16 bits), @address on LSB */ 188 189 /* Indirect register access */ 190 #define INV_ICM45600_REG_IREG_ADDR 0x7C 191 #define INV_ICM45600_REG_IREG_DATA 0x7E 192 193 /* Direct acces registers */ 194 #define INV_ICM45600_REG_MISC2 0x007F 195 #define INV_ICM45600_MISC2_SOFT_RESET BIT(1) 196 197 #define INV_ICM45600_REG_DRIVE_CONFIG0 0x0032 198 #define INV_ICM45600_DRIVE_CONFIG0_SPI_MASK GENMASK(3, 1) 199 #define INV_ICM45600_SPI_SLEW_RATE_0_5NS 6 200 #define INV_ICM45600_SPI_SLEW_RATE_4NS 5 201 #define INV_ICM45600_SPI_SLEW_RATE_5NS 4 202 #define INV_ICM45600_SPI_SLEW_RATE_7NS 3 203 #define INV_ICM45600_SPI_SLEW_RATE_10NS 2 204 #define INV_ICM45600_SPI_SLEW_RATE_14NS 1 205 #define INV_ICM45600_SPI_SLEW_RATE_38NS 0 206 207 #define INV_ICM45600_REG_INT1_CONFIG2 0x0018 208 #define INV_ICM45600_INT1_CONFIG2_PUSH_PULL BIT(2) 209 #define INV_ICM45600_INT1_CONFIG2_LATCHED BIT(1) 210 #define INV_ICM45600_INT1_CONFIG2_ACTIVE_HIGH BIT(0) 211 #define INV_ICM45600_INT1_CONFIG2_ACTIVE_LOW 0x00 212 213 #define INV_ICM45600_REG_FIFO_CONFIG0 0x001D 214 #define INV_ICM45600_FIFO_CONFIG0_MODE_MASK GENMASK(7, 6) 215 #define INV_ICM45600_FIFO_CONFIG0_MODE_BYPASS 0 216 #define INV_ICM45600_FIFO_CONFIG0_MODE_STREAM 1 217 #define INV_ICM45600_FIFO_CONFIG0_MODE_STOP_ON_FULL 2 218 #define INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MASK GENMASK(5, 0) 219 #define INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MAX 0x1F 220 221 #define INV_ICM45600_REG_FIFO_CONFIG2 0x0020 222 #define INV_ICM45600_REG_FIFO_CONFIG2_FIFO_FLUSH BIT(7) 223 #define INV_ICM45600_REG_FIFO_CONFIG2_WM_GT_TH BIT(3) 224 225 #define INV_ICM45600_REG_FIFO_CONFIG3 0x0021 226 #define INV_ICM45600_FIFO_CONFIG3_ES1_EN BIT(5) 227 #define INV_ICM45600_FIFO_CONFIG3_ES0_EN BIT(4) 228 #define INV_ICM45600_FIFO_CONFIG3_HIRES_EN BIT(3) 229 #define INV_ICM45600_FIFO_CONFIG3_GYRO_EN BIT(2) 230 #define INV_ICM45600_FIFO_CONFIG3_ACCEL_EN BIT(1) 231 #define INV_ICM45600_FIFO_CONFIG3_IF_EN BIT(0) 232 233 #define INV_ICM45600_REG_FIFO_CONFIG4 0x0022 234 #define INV_ICM45600_FIFO_CONFIG4_COMP_EN BIT(2) 235 #define INV_ICM45600_FIFO_CONFIG4_TMST_FSYNC_EN BIT(1) 236 #define INV_ICM45600_FIFO_CONFIG4_ES0_9B BIT(0) 237 238 /* all sensor data are 16 bits (2 registers wide) in big-endian */ 239 #define INV_ICM45600_REG_TEMP_DATA 0x000C 240 #define INV_ICM45600_REG_ACCEL_DATA_X 0x0000 241 #define INV_ICM45600_REG_ACCEL_DATA_Y 0x0002 242 #define INV_ICM45600_REG_ACCEL_DATA_Z 0x0004 243 #define INV_ICM45600_REG_GYRO_DATA_X 0x0006 244 #define INV_ICM45600_REG_GYRO_DATA_Y 0x0008 245 #define INV_ICM45600_REG_GYRO_DATA_Z 0x000A 246 247 #define INV_ICM45600_REG_INT_STATUS 0x0019 248 #define INV_ICM45600_INT_STATUS_RESET_DONE BIT(7) 249 #define INV_ICM45600_INT_STATUS_AUX1_AGC_RDY BIT(6) 250 #define INV_ICM45600_INT_STATUS_AP_AGC_RDY BIT(5) 251 #define INV_ICM45600_INT_STATUS_AP_FSYNC BIT(4) 252 #define INV_ICM45600_INT_STATUS_AUX1_DRDY BIT(3) 253 #define INV_ICM45600_INT_STATUS_DATA_RDY BIT(2) 254 #define INV_ICM45600_INT_STATUS_FIFO_THS BIT(1) 255 #define INV_ICM45600_INT_STATUS_FIFO_FULL BIT(0) 256 257 /* 258 * FIFO access registers 259 * FIFO count is 16 bits (2 registers) 260 * FIFO data is a continuous read register to read FIFO content 261 */ 262 #define INV_ICM45600_REG_FIFO_COUNT 0x0012 263 #define INV_ICM45600_REG_FIFO_DATA 0x0014 264 265 #define INV_ICM45600_REG_PWR_MGMT0 0x0010 266 #define INV_ICM45600_PWR_MGMT0_GYRO_MODE_MASK GENMASK(3, 2) 267 #define INV_ICM45600_PWR_MGMT0_ACCEL_MODE_MASK GENMASK(1, 0) 268 269 #define INV_ICM45600_REG_ACCEL_CONFIG0 0x001B 270 #define INV_ICM45600_ACCEL_CONFIG0_FS_MASK GENMASK(6, 4) 271 #define INV_ICM45600_ACCEL_CONFIG0_ODR_MASK GENMASK(3, 0) 272 #define INV_ICM45600_REG_GYRO_CONFIG0 0x001C 273 #define INV_ICM45600_GYRO_CONFIG0_FS_MASK GENMASK(7, 4) 274 #define INV_ICM45600_GYRO_CONFIG0_ODR_MASK GENMASK(3, 0) 275 276 #define INV_ICM45600_REG_SMC_CONTROL_0 0xA258 277 #define INV_ICM45600_SMC_CONTROL_0_ACCEL_LP_CLK_SEL BIT(4) 278 #define INV_ICM45600_SMC_CONTROL_0_TMST_EN BIT(0) 279 280 /* FIFO watermark is 16 bits (2 registers wide) in little-endian */ 281 #define INV_ICM45600_REG_FIFO_WATERMARK 0x001E 282 283 /* FIFO is configured for 8kb */ 284 #define INV_ICM45600_FIFO_SIZE_MAX SZ_8K 285 286 #define INV_ICM45600_REG_INT1_CONFIG0 0x0016 287 #define INV_ICM45600_INT1_CONFIG0_RESET_DONE_EN BIT(7) 288 #define INV_ICM45600_INT1_CONFIG0_AUX1_AGC_RDY_EN BIT(6) 289 #define INV_ICM45600_INT1_CONFIG0_AP_AGC_RDY_EN BIT(5) 290 #define INV_ICM45600_INT1_CONFIG0_AP_FSYNC_EN BIT(4) 291 #define INV_ICM45600_INT1_CONFIG0_AUX1_DRDY_EN BIT(3) 292 #define INV_ICM45600_INT1_CONFIG0_DRDY_EN BIT(2) 293 #define INV_ICM45600_INT1_CONFIG0_FIFO_THS_EN BIT(1) 294 #define INV_ICM45600_INT1_CONFIG0_FIFO_FULL_EN BIT(0) 295 296 #define INV_ICM45600_REG_WHOAMI 0x0072 297 #define INV_ICM45600_WHOAMI_ICM45605 0xE5 298 #define INV_ICM45600_WHOAMI_ICM45686 0xE9 299 #define INV_ICM45600_WHOAMI_ICM45688P 0xE7 300 #define INV_ICM45600_WHOAMI_ICM45608 0x81 301 #define INV_ICM45600_WHOAMI_ICM45634 0x82 302 #define INV_ICM45600_WHOAMI_ICM45689 0x83 303 #define INV_ICM45600_WHOAMI_ICM45606 0x84 304 #define INV_ICM45600_WHOAMI_ICM45687 0x85 305 306 /* Gyro USER offset */ 307 #define INV_ICM45600_IPREG_SYS1_REG_42 0xA42A 308 #define INV_ICM45600_IPREG_SYS1_REG_56 0xA438 309 #define INV_ICM45600_IPREG_SYS1_REG_70 0xA446 310 #define INV_ICM45600_GYRO_OFFUSER_MASK GENMASK(13, 0) 311 /* Gyro Averaging filter */ 312 #define INV_ICM45600_IPREG_SYS1_REG_170 0xA4AA 313 #define INV_ICM45600_IPREG_SYS1_170_GYRO_LP_AVG_MASK GENMASK(4, 1) 314 #define INV_ICM45600_GYRO_LP_AVG_SEL_8X 5 315 #define INV_ICM45600_GYRO_LP_AVG_SEL_2X 1 316 /* Accel USER offset */ 317 #define INV_ICM45600_IPREG_SYS2_REG_24 0xA518 318 #define INV_ICM45600_IPREG_SYS2_REG_32 0xA520 319 #define INV_ICM45600_IPREG_SYS2_REG_40 0xA528 320 #define INV_ICM45600_ACCEL_OFFUSER_MASK GENMASK(13, 0) 321 /* Accel averaging filter */ 322 #define INV_ICM45600_IPREG_SYS2_REG_129 0xA581 323 #define INV_ICM45600_ACCEL_LP_AVG_SEL_1X 0x0000 324 #define INV_ICM45600_ACCEL_LP_AVG_SEL_4X 0x0002 325 326 /* Sleep times required by the driver */ 327 #define INV_ICM45600_ACCEL_STARTUP_TIME_MS 60 328 #define INV_ICM45600_GYRO_STARTUP_TIME_MS 60 329 #define INV_ICM45600_GYRO_STOP_TIME_MS 150 330 #define INV_ICM45600_IREG_DELAY_US 4 331 332 typedef int (*inv_icm45600_bus_setup)(struct inv_icm45600_state *); 333 334 extern const struct dev_pm_ops inv_icm45600_pm_ops; 335 336 const struct iio_mount_matrix * 337 inv_icm45600_get_mount_matrix(const struct iio_dev *indio_dev, 338 const struct iio_chan_spec *chan); 339 340 #define INV_ICM45600_TEMP_CHAN(_index) \ 341 { \ 342 .type = IIO_TEMP, \ 343 .info_mask_separate = \ 344 BIT(IIO_CHAN_INFO_RAW) | \ 345 BIT(IIO_CHAN_INFO_OFFSET) | \ 346 BIT(IIO_CHAN_INFO_SCALE), \ 347 .scan_index = _index, \ 348 .scan_type = { \ 349 .sign = 's', \ 350 .realbits = 16, \ 351 .storagebits = 16, \ 352 .endianness = IIO_LE, \ 353 }, \ 354 } 355 356 int inv_icm45600_temp_read_raw(struct iio_dev *indio_dev, 357 struct iio_chan_spec const *chan, 358 int *val, int *val2, long mask); 359 360 u32 inv_icm45600_odr_to_period(enum inv_icm45600_odr odr); 361 362 int inv_icm45600_set_accel_conf(struct inv_icm45600_state *st, 363 struct inv_icm45600_sensor_conf *conf, 364 unsigned int *sleep_ms); 365 366 int inv_icm45600_set_gyro_conf(struct inv_icm45600_state *st, 367 struct inv_icm45600_sensor_conf *conf, 368 unsigned int *sleep_ms); 369 370 int inv_icm45600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, 371 unsigned int writeval, unsigned int *readval); 372 373 int inv_icm45600_core_probe(struct regmap *regmap, 374 const struct inv_icm45600_chip_info *chip_info, 375 bool reset, inv_icm45600_bus_setup bus_setup); 376 377 struct iio_dev *inv_icm45600_gyro_init(struct inv_icm45600_state *st); 378 379 int inv_icm45600_gyro_parse_fifo(struct iio_dev *indio_dev); 380 381 struct iio_dev *inv_icm45600_accel_init(struct inv_icm45600_state *st); 382 383 int inv_icm45600_accel_parse_fifo(struct iio_dev *indio_dev); 384 385 #endif 386