1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_step.h" 31 32 #include "gt/intel_engine_types.h" 33 #include "gt/intel_context_types.h" 34 #include "gt/intel_sseu.h" 35 36 #include "gem/i915_gem_object_types.h" 37 38 struct drm_printer; 39 struct drm_i915_private; 40 struct intel_gt_definition; 41 42 /* Keep in gen based order, and chronological order within a gen */ 43 enum intel_platform { 44 INTEL_PLATFORM_UNINITIALIZED = 0, 45 /* gen2 */ 46 INTEL_I830, 47 INTEL_I845G, 48 INTEL_I85X, 49 INTEL_I865G, 50 /* gen3 */ 51 INTEL_I915G, 52 INTEL_I915GM, 53 INTEL_I945G, 54 INTEL_I945GM, 55 INTEL_G33, 56 INTEL_PINEVIEW, 57 /* gen4 */ 58 INTEL_I965G, 59 INTEL_I965GM, 60 INTEL_G45, 61 INTEL_GM45, 62 /* gen5 */ 63 INTEL_IRONLAKE, 64 /* gen6 */ 65 INTEL_SANDYBRIDGE, 66 /* gen7 */ 67 INTEL_IVYBRIDGE, 68 INTEL_VALLEYVIEW, 69 INTEL_HASWELL, 70 /* gen8 */ 71 INTEL_BROADWELL, 72 INTEL_CHERRYVIEW, 73 /* gen9 */ 74 INTEL_SKYLAKE, 75 INTEL_BROXTON, 76 INTEL_KABYLAKE, 77 INTEL_GEMINILAKE, 78 INTEL_COFFEELAKE, 79 INTEL_COMETLAKE, 80 /* gen11 */ 81 INTEL_ICELAKE, 82 INTEL_ELKHARTLAKE, 83 INTEL_JASPERLAKE, 84 /* gen12 */ 85 INTEL_TIGERLAKE, 86 INTEL_ROCKETLAKE, 87 INTEL_DG1, 88 INTEL_ALDERLAKE_S, 89 INTEL_ALDERLAKE_P, 90 INTEL_DG2, 91 INTEL_METEORLAKE, 92 INTEL_MAX_PLATFORMS 93 }; 94 95 /* 96 * Subplatform bits share the same namespace per parent platform. In other words 97 * it is fine for the same bit to be used on multiple parent platforms. 98 * Devices can belong to multiple subplatforms if needed, so it's possible to set 99 * multiple bits for same device. 100 */ 101 102 #define INTEL_SUBPLATFORM_BITS (4) 103 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) 104 105 /* HSW/BDW/SKL/KBL/CFL */ 106 #define INTEL_SUBPLATFORM_ULT (0) 107 #define INTEL_SUBPLATFORM_ULX (1) 108 109 /* ICL */ 110 #define INTEL_SUBPLATFORM_PORTF (0) 111 112 /* TGL */ 113 #define INTEL_SUBPLATFORM_UY (0) 114 115 /* DG2 */ 116 #define INTEL_SUBPLATFORM_G10 0 117 #define INTEL_SUBPLATFORM_G11 1 118 #define INTEL_SUBPLATFORM_G12 2 119 #define INTEL_SUBPLATFORM_D 3 120 121 /* ADL */ 122 #define INTEL_SUBPLATFORM_RPL 0 123 124 /* ADL-P */ 125 /* 126 * As #define INTEL_SUBPLATFORM_RPL 0 will apply 127 * here too, SUBPLATFORM_N will have different 128 * bit set 129 */ 130 #define INTEL_SUBPLATFORM_N 1 131 #define INTEL_SUBPLATFORM_RPLU 2 132 133 /* MTL */ 134 #define INTEL_SUBPLATFORM_ARL_H 0 135 #define INTEL_SUBPLATFORM_ARL_U 1 136 #define INTEL_SUBPLATFORM_ARL_S 2 137 138 enum intel_ppgtt_type { 139 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 140 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 141 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 142 }; 143 144 #define DEV_INFO_FOR_EACH_FLAG(func) \ 145 func(is_mobile); \ 146 func(require_force_probe); \ 147 func(is_dgfx); \ 148 /* Keep has_* in alphabetical order */ \ 149 func(has_64bit_reloc); \ 150 func(has_64k_pages); \ 151 func(gpu_reset_clobbers_display); \ 152 func(has_reset_engine); \ 153 func(has_3d_pipeline); \ 154 func(has_flat_ccs); \ 155 func(has_global_mocs); \ 156 func(has_gmd_id); \ 157 func(has_gt_uc); \ 158 func(has_heci_pxp); \ 159 func(has_heci_gscfi); \ 160 func(has_guc_deprivilege); \ 161 func(has_guc_tlb_invalidation); \ 162 func(has_l3_ccs_read); \ 163 func(has_l3_dpf); \ 164 func(has_llc); \ 165 func(has_logical_ring_contexts); \ 166 func(has_logical_ring_elsq); \ 167 func(has_media_ratio_mode); \ 168 func(has_mslice_steering); \ 169 func(has_oa_bpc_reporting); \ 170 func(has_oa_slice_contrib_limits); \ 171 func(has_oam); \ 172 func(has_one_eu_per_fuse_bit); \ 173 func(has_pxp); \ 174 func(has_rc6); \ 175 func(has_rc6p); \ 176 func(has_rps); \ 177 func(has_runtime_pm); \ 178 func(has_snoop); \ 179 func(has_coherent_ggtt); \ 180 func(tuning_thread_rr_after_dep); \ 181 func(unfenced_needs_alignment); \ 182 func(hws_needs_physical); 183 184 struct intel_ip_version { 185 u8 ver; 186 u8 rel; 187 u8 step; 188 }; 189 190 struct intel_runtime_info { 191 /* 192 * Single "graphics" IP version that represents 193 * render, compute and copy behavior. 194 */ 195 struct { 196 struct intel_ip_version ip; 197 } graphics; 198 struct { 199 struct intel_ip_version ip; 200 } media; 201 202 /* 203 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 204 * single runtime conditionals, and also to provide groundwork for 205 * future per platform, or per SKU build optimizations. 206 * 207 * Array can be extended when necessary if the corresponding 208 * BUILD_BUG_ON is hit. 209 */ 210 u32 platform_mask[2]; 211 212 u16 device_id; 213 214 struct intel_step_info step; 215 216 unsigned int page_sizes; /* page sizes supported by the HW */ 217 218 enum intel_ppgtt_type ppgtt_type; 219 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 220 221 bool has_pooled_eu; 222 }; 223 224 struct intel_device_info { 225 enum intel_platform platform; 226 227 unsigned int dma_mask_size; /* available DMA address bits */ 228 229 const struct intel_gt_definition *extra_gt_list; 230 231 u8 gt; /* GT number, 0 if undefined */ 232 233 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ 234 u32 memory_regions; /* regions supported by the HW */ 235 236 #define DEFINE_FLAG(name) u8 name:1 237 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 238 #undef DEFINE_FLAG 239 240 /* 241 * Initial runtime info. Do not access outside of i915_driver_create(). 242 */ 243 const struct intel_runtime_info __runtime; 244 245 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL]; 246 u32 max_pat_index; 247 }; 248 249 struct intel_driver_caps { 250 unsigned int scheduler; 251 bool has_logical_contexts:1; 252 }; 253 254 const char *intel_platform_name(enum intel_platform platform); 255 256 void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id, 257 const struct intel_device_info *match_info); 258 void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv); 259 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 260 261 void intel_device_info_print(const struct intel_device_info *info, 262 const struct intel_runtime_info *runtime, 263 struct drm_printer *p); 264 265 void intel_driver_caps_print(const struct intel_driver_caps *caps, 266 struct drm_printer *p); 267 268 #endif 269