1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved 4 */ 5 6 #ifndef _DPU_HW_CWB_H 7 #define _DPU_HW_CWB_H 8 9 #include "dpu_hw_util.h" 10 11 struct dpu_hw_cwb; 12 13 enum cwb_mode_input { 14 INPUT_MODE_LM_OUT, 15 INPUT_MODE_DSPP_OUT, 16 INPUT_MODE_MAX 17 }; 18 19 /** 20 * struct dpu_hw_cwb_setup_cfg : Describes configuration for CWB mux 21 * @pp_idx: Index of the real-time pinpong that the CWB mux will 22 * feed the CWB mux 23 * @input: Input tap point 24 */ 25 struct dpu_hw_cwb_setup_cfg { 26 enum dpu_pingpong pp_idx; 27 enum cwb_mode_input input; 28 }; 29 30 /** 31 * struct dpu_hw_cwb_ops : Interface to the cwb hw driver functions 32 * @config_cwb: configure CWB mux 33 */ 34 struct dpu_hw_cwb_ops { 35 void (*config_cwb)(struct dpu_hw_cwb *ctx, 36 struct dpu_hw_cwb_setup_cfg *cwb_cfg); 37 }; 38 39 /** 40 * struct dpu_hw_cwb : CWB mux driver object 41 * @base: Hardware block base structure 42 * @hw: Block hardware details 43 * @idx: CWB index 44 * @ops: handle to operations possible for this CWB 45 */ 46 struct dpu_hw_cwb { 47 struct dpu_hw_blk base; 48 struct dpu_hw_blk_reg_map hw; 49 50 enum dpu_cwb idx; 51 52 struct dpu_hw_cwb_ops ops; 53 }; 54 55 /** 56 * to_dpu_hw_cwb - convert base object dpu_hw_base to container 57 * @hw: Pointer to base hardware block 58 * return: Pointer to hardware block container 59 */ to_dpu_hw_cwb(struct dpu_hw_blk * hw)60static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw) 61 { 62 return container_of(hw, struct dpu_hw_cwb, base); 63 } 64 65 struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev, 66 const struct dpu_cwb_cfg *cfg, 67 void __iomem *addr); 68 69 #endif /*_DPU_HW_CWB_H */ 70