1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017 Impinj, Inc 4 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 5 * 6 * Based on the code of analogus driver: 7 * 8 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 #include <linux/sizes.h> 20 #include <dt-bindings/power/imx7-power.h> 21 #include <dt-bindings/power/imx8mq-power.h> 22 #include <dt-bindings/power/imx8mm-power.h> 23 #include <dt-bindings/power/imx8mn-power.h> 24 #include <dt-bindings/power/imx8mp-power.h> 25 26 #define GPC_LPCR_A_CORE_BSC 0x000 27 28 #define GPC_PGC_CPU_MAPPING 0x0ec 29 #define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc 30 31 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6) 32 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5) 33 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4) 34 #define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3) 35 #define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2) 36 37 #define IMX8M_PCIE2_A53_DOMAIN BIT(15) 38 #define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14) 39 #define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13) 40 #define IMX8M_DISP_A53_DOMAIN BIT(12) 41 #define IMX8M_HDMI_A53_DOMAIN BIT(11) 42 #define IMX8M_VPU_A53_DOMAIN BIT(10) 43 #define IMX8M_GPU_A53_DOMAIN BIT(9) 44 #define IMX8M_DDR2_A53_DOMAIN BIT(8) 45 #define IMX8M_DDR1_A53_DOMAIN BIT(7) 46 #define IMX8M_OTG2_A53_DOMAIN BIT(5) 47 #define IMX8M_OTG1_A53_DOMAIN BIT(4) 48 #define IMX8M_PCIE1_A53_DOMAIN BIT(3) 49 #define IMX8M_MIPI_A53_DOMAIN BIT(2) 50 51 #define IMX8MM_VPUH1_A53_DOMAIN BIT(15) 52 #define IMX8MM_VPUG2_A53_DOMAIN BIT(14) 53 #define IMX8MM_VPUG1_A53_DOMAIN BIT(13) 54 #define IMX8MM_DISPMIX_A53_DOMAIN BIT(12) 55 #define IMX8MM_VPUMIX_A53_DOMAIN BIT(10) 56 #define IMX8MM_GPUMIX_A53_DOMAIN BIT(9) 57 #define IMX8MM_GPU_A53_DOMAIN (BIT(8) | BIT(11)) 58 #define IMX8MM_DDR1_A53_DOMAIN BIT(7) 59 #define IMX8MM_OTG2_A53_DOMAIN BIT(5) 60 #define IMX8MM_OTG1_A53_DOMAIN BIT(4) 61 #define IMX8MM_PCIE_A53_DOMAIN BIT(3) 62 #define IMX8MM_MIPI_A53_DOMAIN BIT(2) 63 64 #define IMX8MN_DISPMIX_A53_DOMAIN BIT(12) 65 #define IMX8MN_GPUMIX_A53_DOMAIN BIT(9) 66 #define IMX8MN_DDR1_A53_DOMAIN BIT(7) 67 #define IMX8MN_OTG1_A53_DOMAIN BIT(4) 68 #define IMX8MN_MIPI_A53_DOMAIN BIT(2) 69 70 #define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20) 71 #define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19) 72 #define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18) 73 #define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17) 74 #define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16) 75 #define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15) 76 #define IMX8MP_VPU_G2_A53_DOMAIN BIT(14) 77 #define IMX8MP_VPU_G1_A53_DOMAIN BIT(13) 78 #define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12) 79 #define IMX8MP_GPU3D_A53_DOMAIN BIT(11) 80 #define IMX8MP_VPUMIX_A53_DOMAIN BIT(10) 81 #define IMX8MP_GPUMIX_A53_DOMAIN BIT(9) 82 #define IMX8MP_GPU2D_A53_DOMAIN BIT(8) 83 #define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7) 84 #define IMX8MP_MLMIX_A53_DOMAIN BIT(6) 85 #define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5) 86 #define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4) 87 #define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3) 88 #define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2) 89 90 #define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8 91 #define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4 92 93 #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 94 #define GPC_PU_PGC_SW_PDN_REQ 0x104 95 96 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4) 97 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3) 98 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2) 99 #define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1) 100 #define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0) 101 102 #define IMX8M_PCIE2_SW_Pxx_REQ BIT(13) 103 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12) 104 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11) 105 #define IMX8M_DISP_SW_Pxx_REQ BIT(10) 106 #define IMX8M_HDMI_SW_Pxx_REQ BIT(9) 107 #define IMX8M_VPU_SW_Pxx_REQ BIT(8) 108 #define IMX8M_GPU_SW_Pxx_REQ BIT(7) 109 #define IMX8M_DDR2_SW_Pxx_REQ BIT(6) 110 #define IMX8M_DDR1_SW_Pxx_REQ BIT(5) 111 #define IMX8M_OTG2_SW_Pxx_REQ BIT(3) 112 #define IMX8M_OTG1_SW_Pxx_REQ BIT(2) 113 #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) 114 #define IMX8M_MIPI_SW_Pxx_REQ BIT(0) 115 116 #define IMX8MM_VPUH1_SW_Pxx_REQ BIT(13) 117 #define IMX8MM_VPUG2_SW_Pxx_REQ BIT(12) 118 #define IMX8MM_VPUG1_SW_Pxx_REQ BIT(11) 119 #define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10) 120 #define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8) 121 #define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7) 122 #define IMX8MM_GPU_SW_Pxx_REQ (BIT(6) | BIT(9)) 123 #define IMX8MM_DDR1_SW_Pxx_REQ BIT(5) 124 #define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) 125 #define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) 126 #define IMX8MM_PCIE_SW_Pxx_REQ BIT(1) 127 #define IMX8MM_MIPI_SW_Pxx_REQ BIT(0) 128 129 #define IMX8MN_DISPMIX_SW_Pxx_REQ BIT(10) 130 #define IMX8MN_GPUMIX_SW_Pxx_REQ BIT(7) 131 #define IMX8MN_DDR1_SW_Pxx_REQ BIT(5) 132 #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) 133 #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) 134 135 #define IMX8MP_DDRMIX_Pxx_REQ BIT(19) 136 #define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18) 137 #define IMX8MP_HSIOMIX_Pxx_REQ BIT(17) 138 #define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16) 139 #define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15) 140 #define IMX8MP_HDMIMIX_Pxx_REQ BIT(14) 141 #define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13) 142 #define IMX8MP_VPU_G2_Pxx_REQ BIT(12) 143 #define IMX8MP_VPU_G1_Pxx_REQ BIT(11) 144 #define IMX8MP_MEDIMIX_Pxx_REQ BIT(10) 145 #define IMX8MP_GPU_3D_Pxx_REQ BIT(9) 146 #define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8) 147 #define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7) 148 #define IMX8MP_GPU_2D_Pxx_REQ BIT(6) 149 #define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5) 150 #define IMX8MP_MLMIX_Pxx_REQ BIT(4) 151 #define IMX8MP_USB2_PHY_Pxx_REQ BIT(3) 152 #define IMX8MP_USB1_PHY_Pxx_REQ BIT(2) 153 #define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1) 154 #define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0) 155 156 #define GPC_M4_PU_PDN_FLG 0x1bc 157 158 #define IMX8MP_GPC_PU_PWRHSK 0x190 159 #define GPC_PU_PWRHSK 0x1fc 160 161 #define IMX8M_GPU_HSK_PWRDNACKN BIT(26) 162 #define IMX8M_VPU_HSK_PWRDNACKN BIT(25) 163 #define IMX8M_DISP_HSK_PWRDNACKN BIT(24) 164 #define IMX8M_GPU_HSK_PWRDNREQN BIT(6) 165 #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) 166 #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) 167 168 #define IMX8MM_GPU_HSK_PWRDNACKN GENMASK(29, 27) 169 #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26) 170 #define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25) 171 #define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24)) 172 #define IMX8MM_GPU_HSK_PWRDNREQN GENMASK(11, 9) 173 #define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8) 174 #define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7) 175 #define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6)) 176 177 #define IMX8MN_GPUMIX_HSK_PWRDNACKN (BIT(29) | BIT(27)) 178 #define IMX8MN_DISPMIX_HSK_PWRDNACKN BIT(25) 179 #define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23) 180 #define IMX8MN_GPUMIX_HSK_PWRDNREQN (BIT(11) | BIT(9)) 181 #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7) 182 #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) 183 184 #define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30) 185 #define IMX8MP_HDMIMIX_PWRDNACKN BIT(29) 186 #define IMX8MP_HSIOMIX_PWRDNACKN BIT(28) 187 #define IMX8MP_VPUMIX_PWRDNACKN BIT(26) 188 #define IMX8MP_GPUMIX_PWRDNACKN BIT(25) 189 #define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24)) 190 #define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31)) 191 #define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14) 192 #define IMX8MP_HDMIMIX_PWRDNREQN BIT(13) 193 #define IMX8MP_HSIOMIX_PWRDNREQN BIT(12) 194 #define IMX8MP_VPUMIX_PWRDNREQN BIT(10) 195 #define IMX8MP_GPUMIX_PWRDNREQN BIT(9) 196 #define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8)) 197 #define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15)) 198 199 /* 200 * The PGC offset values in Reference Manual 201 * (Rev. 1, 01/2018 and the older ones) GPC chapter's 202 * GPC_PGC memory map are incorrect, below offset 203 * values are from design RTL. 204 */ 205 #define IMX7_PGC_MIPI 16 206 #define IMX7_PGC_PCIE 17 207 #define IMX7_PGC_USB_HSIC 20 208 209 #define IMX8M_PGC_MIPI 16 210 #define IMX8M_PGC_PCIE1 17 211 #define IMX8M_PGC_OTG1 18 212 #define IMX8M_PGC_OTG2 19 213 #define IMX8M_PGC_DDR1 21 214 #define IMX8M_PGC_GPU 23 215 #define IMX8M_PGC_VPU 24 216 #define IMX8M_PGC_DISP 26 217 #define IMX8M_PGC_MIPI_CSI1 27 218 #define IMX8M_PGC_MIPI_CSI2 28 219 #define IMX8M_PGC_PCIE2 29 220 221 #define IMX8MM_PGC_MIPI 16 222 #define IMX8MM_PGC_PCIE 17 223 #define IMX8MM_PGC_OTG1 18 224 #define IMX8MM_PGC_OTG2 19 225 #define IMX8MM_PGC_DDR1 21 226 #define IMX8MM_PGC_GPU2D 22 227 #define IMX8MM_PGC_GPUMIX 23 228 #define IMX8MM_PGC_VPUMIX 24 229 #define IMX8MM_PGC_GPU3D 25 230 #define IMX8MM_PGC_DISPMIX 26 231 #define IMX8MM_PGC_VPUG1 27 232 #define IMX8MM_PGC_VPUG2 28 233 #define IMX8MM_PGC_VPUH1 29 234 235 #define IMX8MN_PGC_MIPI 16 236 #define IMX8MN_PGC_OTG1 18 237 #define IMX8MN_PGC_DDR1 21 238 #define IMX8MN_PGC_GPUMIX 23 239 #define IMX8MN_PGC_DISPMIX 26 240 241 #define IMX8MP_PGC_NOC 9 242 #define IMX8MP_PGC_MIPI1 12 243 #define IMX8MP_PGC_PCIE 13 244 #define IMX8MP_PGC_USB1 14 245 #define IMX8MP_PGC_USB2 15 246 #define IMX8MP_PGC_MLMIX 16 247 #define IMX8MP_PGC_AUDIOMIX 17 248 #define IMX8MP_PGC_GPU2D 18 249 #define IMX8MP_PGC_GPUMIX 19 250 #define IMX8MP_PGC_VPUMIX 20 251 #define IMX8MP_PGC_GPU3D 21 252 #define IMX8MP_PGC_MEDIAMIX 22 253 #define IMX8MP_PGC_VPU_G1 23 254 #define IMX8MP_PGC_VPU_G2 24 255 #define IMX8MP_PGC_VPU_VC8000E 25 256 #define IMX8MP_PGC_HDMIMIX 26 257 #define IMX8MP_PGC_HDMI 27 258 #define IMX8MP_PGC_MIPI2 28 259 #define IMX8MP_PGC_HSIOMIX 29 260 #define IMX8MP_PGC_MEDIA_ISP_DWP 30 261 #define IMX8MP_PGC_DDRMIX 31 262 263 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) 264 #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) 265 266 #define GPC_PGC_CTRL_PCR BIT(0) 267 268 struct imx_pgc_regs { 269 u16 map; 270 u16 pup; 271 u16 pdn; 272 u16 hsk; 273 }; 274 275 struct imx_pgc_domain { 276 struct generic_pm_domain genpd; 277 struct regmap *regmap; 278 const struct imx_pgc_regs *regs; 279 struct regulator *regulator; 280 struct reset_control *reset; 281 struct clk_bulk_data *clks; 282 int num_clks; 283 284 unsigned long pgc; 285 286 const struct { 287 u32 pxx; 288 u32 map; 289 u32 hskreq; 290 u32 hskack; 291 } bits; 292 293 const int voltage; 294 const bool keep_clocks; 295 struct device *dev; 296 297 unsigned int pgc_sw_pup_reg; 298 unsigned int pgc_sw_pdn_reg; 299 }; 300 301 struct imx_pgc_domain_data { 302 const struct imx_pgc_domain *domains; 303 size_t domains_num; 304 const struct regmap_access_table *reg_access_table; 305 const struct imx_pgc_regs *pgc_regs; 306 }; 307 308 static inline struct imx_pgc_domain * 309 to_imx_pgc_domain(struct generic_pm_domain *genpd) 310 { 311 return container_of(genpd, struct imx_pgc_domain, genpd); 312 } 313 314 static int imx_pgc_power_up(struct generic_pm_domain *genpd) 315 { 316 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); 317 u32 reg_val, pgc; 318 int ret; 319 320 ret = pm_runtime_resume_and_get(domain->dev); 321 if (ret < 0) 322 return ret; 323 324 if (!IS_ERR(domain->regulator)) { 325 ret = regulator_enable(domain->regulator); 326 if (ret) { 327 dev_err(domain->dev, 328 "failed to enable regulator: %pe\n", 329 ERR_PTR(ret)); 330 goto out_put_pm; 331 } 332 } 333 334 reset_control_assert(domain->reset); 335 336 /* Enable reset clocks for all devices in the domain */ 337 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); 338 if (ret) { 339 dev_err(domain->dev, "failed to enable reset clocks\n"); 340 goto out_regulator_disable; 341 } 342 343 /* delays for reset to propagate */ 344 udelay(5); 345 346 if (domain->bits.pxx) { 347 /* request the domain to power up */ 348 regmap_update_bits(domain->regmap, domain->regs->pup, 349 domain->bits.pxx, domain->bits.pxx); 350 /* 351 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait 352 * for PUP_REQ/PDN_REQ bit to be cleared 353 */ 354 ret = regmap_read_poll_timeout(domain->regmap, 355 domain->regs->pup, reg_val, 356 !(reg_val & domain->bits.pxx), 357 0, USEC_PER_MSEC); 358 if (ret) { 359 dev_err(domain->dev, "failed to command PGC\n"); 360 goto out_clk_disable; 361 } 362 363 /* disable power control */ 364 for_each_set_bit(pgc, &domain->pgc, 32) { 365 regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), 366 GPC_PGC_CTRL_PCR); 367 } 368 } 369 370 /* delay for reset to propagate */ 371 udelay(5); 372 373 reset_control_deassert(domain->reset); 374 375 /* request the ADB400 to power up */ 376 if (domain->bits.hskreq) { 377 regmap_update_bits(domain->regmap, domain->regs->hsk, 378 domain->bits.hskreq, domain->bits.hskreq); 379 380 /* 381 * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val, 382 * (reg_val & domain->bits.hskack), 0, 383 * USEC_PER_MSEC); 384 * Technically we need the commented code to wait handshake. But that needs 385 * the BLK-CTL module BUS clk-en bit being set. 386 * 387 * There is a separate BLK-CTL module and we will have such a driver for it, 388 * that driver will set the BUS clk-en bit and handshake will be triggered 389 * automatically there. Just add a delay and suppose the handshake finish 390 * after that. 391 */ 392 393 /* 394 * For some BLK-CTL module (eg. AudioMix on i.MX8MP) doesn't have BUS 395 * clk-en bit, it is better to add delay here, as the BLK-CTL module 396 * doesn't need to care about how it is powered up. 397 * 398 * regmap_read_bypassed() is to make sure the above write IO transaction 399 * already reaches target before udelay() 400 */ 401 regmap_read_bypassed(domain->regmap, domain->regs->hsk, ®_val); 402 udelay(10); 403 } 404 405 /* Disable reset clocks for all devices in the domain */ 406 if (!domain->keep_clocks) 407 clk_bulk_disable_unprepare(domain->num_clks, domain->clks); 408 409 return 0; 410 411 out_clk_disable: 412 clk_bulk_disable_unprepare(domain->num_clks, domain->clks); 413 out_regulator_disable: 414 if (!IS_ERR(domain->regulator)) 415 regulator_disable(domain->regulator); 416 out_put_pm: 417 pm_runtime_put(domain->dev); 418 419 return ret; 420 } 421 422 static int imx_pgc_power_down(struct generic_pm_domain *genpd) 423 { 424 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); 425 u32 reg_val, pgc; 426 int ret; 427 428 /* Enable reset clocks for all devices in the domain */ 429 if (!domain->keep_clocks) { 430 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); 431 if (ret) { 432 dev_err(domain->dev, "failed to enable reset clocks\n"); 433 return ret; 434 } 435 } 436 437 /* request the ADB400 to power down */ 438 if (domain->bits.hskreq) { 439 regmap_clear_bits(domain->regmap, domain->regs->hsk, 440 domain->bits.hskreq); 441 442 ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, 443 reg_val, 444 !(reg_val & domain->bits.hskack), 445 0, USEC_PER_MSEC); 446 if (ret) { 447 dev_err(domain->dev, "failed to power down ADB400\n"); 448 goto out_clk_disable; 449 } 450 } 451 452 if (domain->bits.pxx) { 453 /* enable power control */ 454 for_each_set_bit(pgc, &domain->pgc, 32) { 455 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), 456 GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); 457 } 458 459 /* request the domain to power down */ 460 regmap_update_bits(domain->regmap, domain->regs->pdn, 461 domain->bits.pxx, domain->bits.pxx); 462 /* 463 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait 464 * for PUP_REQ/PDN_REQ bit to be cleared 465 */ 466 ret = regmap_read_poll_timeout(domain->regmap, 467 domain->regs->pdn, reg_val, 468 !(reg_val & domain->bits.pxx), 469 0, USEC_PER_MSEC); 470 if (ret) { 471 dev_err(domain->dev, "failed to command PGC\n"); 472 goto out_clk_disable; 473 } 474 } 475 476 /* Disable reset clocks for all devices in the domain */ 477 clk_bulk_disable_unprepare(domain->num_clks, domain->clks); 478 479 if (!IS_ERR(domain->regulator)) { 480 ret = regulator_disable(domain->regulator); 481 if (ret) { 482 dev_err(domain->dev, 483 "failed to disable regulator: %pe\n", 484 ERR_PTR(ret)); 485 return ret; 486 } 487 } 488 489 pm_runtime_put_sync_suspend(domain->dev); 490 491 return 0; 492 493 out_clk_disable: 494 if (!domain->keep_clocks) 495 clk_bulk_disable_unprepare(domain->num_clks, domain->clks); 496 497 return ret; 498 } 499 500 static const struct imx_pgc_domain imx7_pgc_domains[] = { 501 [IMX7_POWER_DOMAIN_MIPI_PHY] = { 502 .genpd = { 503 .name = "mipi-phy", 504 }, 505 .bits = { 506 .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ, 507 .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, 508 }, 509 .voltage = 1000000, 510 .pgc = BIT(IMX7_PGC_MIPI), 511 }, 512 513 [IMX7_POWER_DOMAIN_PCIE_PHY] = { 514 .genpd = { 515 .name = "pcie-phy", 516 }, 517 .bits = { 518 .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ, 519 .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, 520 }, 521 .voltage = 1000000, 522 .pgc = BIT(IMX7_PGC_PCIE), 523 }, 524 525 [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { 526 .genpd = { 527 .name = "usb-hsic-phy", 528 }, 529 .bits = { 530 .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ, 531 .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, 532 }, 533 .voltage = 1200000, 534 .pgc = BIT(IMX7_PGC_USB_HSIC), 535 }, 536 }; 537 538 static const struct regmap_range imx7_yes_ranges[] = { 539 regmap_reg_range(GPC_LPCR_A_CORE_BSC, 540 GPC_M4_PU_PDN_FLG), 541 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI), 542 GPC_PGC_SR(IMX7_PGC_MIPI)), 543 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE), 544 GPC_PGC_SR(IMX7_PGC_PCIE)), 545 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC), 546 GPC_PGC_SR(IMX7_PGC_USB_HSIC)), 547 }; 548 549 static const struct regmap_access_table imx7_access_table = { 550 .yes_ranges = imx7_yes_ranges, 551 .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges), 552 }; 553 554 static const struct imx_pgc_regs imx7_pgc_regs = { 555 .map = GPC_PGC_CPU_MAPPING, 556 .pup = GPC_PU_PGC_SW_PUP_REQ, 557 .pdn = GPC_PU_PGC_SW_PDN_REQ, 558 .hsk = GPC_PU_PWRHSK, 559 }; 560 561 static const struct imx_pgc_domain_data imx7_pgc_domain_data = { 562 .domains = imx7_pgc_domains, 563 .domains_num = ARRAY_SIZE(imx7_pgc_domains), 564 .reg_access_table = &imx7_access_table, 565 .pgc_regs = &imx7_pgc_regs, 566 }; 567 568 static const struct imx_pgc_domain imx8m_pgc_domains[] = { 569 [IMX8M_POWER_DOMAIN_MIPI] = { 570 .genpd = { 571 .name = "mipi", 572 }, 573 .bits = { 574 .pxx = IMX8M_MIPI_SW_Pxx_REQ, 575 .map = IMX8M_MIPI_A53_DOMAIN, 576 }, 577 .pgc = BIT(IMX8M_PGC_MIPI), 578 }, 579 580 [IMX8M_POWER_DOMAIN_PCIE1] = { 581 .genpd = { 582 .name = "pcie1", 583 }, 584 .bits = { 585 .pxx = IMX8M_PCIE1_SW_Pxx_REQ, 586 .map = IMX8M_PCIE1_A53_DOMAIN, 587 }, 588 .pgc = BIT(IMX8M_PGC_PCIE1), 589 }, 590 591 [IMX8M_POWER_DOMAIN_USB_OTG1] = { 592 .genpd = { 593 .name = "usb-otg1", 594 }, 595 .bits = { 596 .pxx = IMX8M_OTG1_SW_Pxx_REQ, 597 .map = IMX8M_OTG1_A53_DOMAIN, 598 }, 599 .pgc = BIT(IMX8M_PGC_OTG1), 600 }, 601 602 [IMX8M_POWER_DOMAIN_USB_OTG2] = { 603 .genpd = { 604 .name = "usb-otg2", 605 }, 606 .bits = { 607 .pxx = IMX8M_OTG2_SW_Pxx_REQ, 608 .map = IMX8M_OTG2_A53_DOMAIN, 609 }, 610 .pgc = BIT(IMX8M_PGC_OTG2), 611 }, 612 613 [IMX8M_POWER_DOMAIN_DDR1] = { 614 .genpd = { 615 .name = "ddr1", 616 }, 617 .bits = { 618 .pxx = IMX8M_DDR1_SW_Pxx_REQ, 619 .map = IMX8M_DDR2_A53_DOMAIN, 620 }, 621 .pgc = BIT(IMX8M_PGC_DDR1), 622 }, 623 624 [IMX8M_POWER_DOMAIN_GPU] = { 625 .genpd = { 626 .name = "gpu", 627 }, 628 .bits = { 629 .pxx = IMX8M_GPU_SW_Pxx_REQ, 630 .map = IMX8M_GPU_A53_DOMAIN, 631 .hskreq = IMX8M_GPU_HSK_PWRDNREQN, 632 .hskack = IMX8M_GPU_HSK_PWRDNACKN, 633 }, 634 .pgc = BIT(IMX8M_PGC_GPU), 635 }, 636 637 [IMX8M_POWER_DOMAIN_VPU] = { 638 .genpd = { 639 .name = "vpu", 640 }, 641 .bits = { 642 .pxx = IMX8M_VPU_SW_Pxx_REQ, 643 .map = IMX8M_VPU_A53_DOMAIN, 644 .hskreq = IMX8M_VPU_HSK_PWRDNREQN, 645 .hskack = IMX8M_VPU_HSK_PWRDNACKN, 646 }, 647 .pgc = BIT(IMX8M_PGC_VPU), 648 .keep_clocks = true, 649 }, 650 651 [IMX8M_POWER_DOMAIN_DISP] = { 652 .genpd = { 653 .name = "disp", 654 }, 655 .bits = { 656 .pxx = IMX8M_DISP_SW_Pxx_REQ, 657 .map = IMX8M_DISP_A53_DOMAIN, 658 .hskreq = IMX8M_DISP_HSK_PWRDNREQN, 659 .hskack = IMX8M_DISP_HSK_PWRDNACKN, 660 }, 661 .pgc = BIT(IMX8M_PGC_DISP), 662 }, 663 664 [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { 665 .genpd = { 666 .name = "mipi-csi1", 667 }, 668 .bits = { 669 .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, 670 .map = IMX8M_MIPI_CSI1_A53_DOMAIN, 671 }, 672 .pgc = BIT(IMX8M_PGC_MIPI_CSI1), 673 }, 674 675 [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { 676 .genpd = { 677 .name = "mipi-csi2", 678 }, 679 .bits = { 680 .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, 681 .map = IMX8M_MIPI_CSI2_A53_DOMAIN, 682 }, 683 .pgc = BIT(IMX8M_PGC_MIPI_CSI2), 684 }, 685 686 [IMX8M_POWER_DOMAIN_PCIE2] = { 687 .genpd = { 688 .name = "pcie2", 689 }, 690 .bits = { 691 .pxx = IMX8M_PCIE2_SW_Pxx_REQ, 692 .map = IMX8M_PCIE2_A53_DOMAIN, 693 }, 694 .pgc = BIT(IMX8M_PGC_PCIE2), 695 }, 696 }; 697 698 static const struct regmap_range imx8m_yes_ranges[] = { 699 regmap_reg_range(GPC_LPCR_A_CORE_BSC, 700 GPC_PU_PWRHSK), 701 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI), 702 GPC_PGC_SR(IMX8M_PGC_MIPI)), 703 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1), 704 GPC_PGC_SR(IMX8M_PGC_PCIE1)), 705 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1), 706 GPC_PGC_SR(IMX8M_PGC_OTG1)), 707 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2), 708 GPC_PGC_SR(IMX8M_PGC_OTG2)), 709 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1), 710 GPC_PGC_SR(IMX8M_PGC_DDR1)), 711 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU), 712 GPC_PGC_SR(IMX8M_PGC_GPU)), 713 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU), 714 GPC_PGC_SR(IMX8M_PGC_VPU)), 715 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP), 716 GPC_PGC_SR(IMX8M_PGC_DISP)), 717 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1), 718 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)), 719 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2), 720 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)), 721 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2), 722 GPC_PGC_SR(IMX8M_PGC_PCIE2)), 723 }; 724 725 static const struct regmap_access_table imx8m_access_table = { 726 .yes_ranges = imx8m_yes_ranges, 727 .n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges), 728 }; 729 730 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { 731 .domains = imx8m_pgc_domains, 732 .domains_num = ARRAY_SIZE(imx8m_pgc_domains), 733 .reg_access_table = &imx8m_access_table, 734 .pgc_regs = &imx7_pgc_regs, 735 }; 736 737 static const struct imx_pgc_domain imx8mm_pgc_domains[] = { 738 [IMX8MM_POWER_DOMAIN_HSIOMIX] = { 739 .genpd = { 740 .name = "hsiomix", 741 }, 742 .bits = { 743 .pxx = 0, /* no power sequence control */ 744 .map = 0, /* no power sequence control */ 745 .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN, 746 .hskack = IMX8MM_HSIO_HSK_PWRDNACKN, 747 }, 748 .keep_clocks = true, 749 }, 750 751 [IMX8MM_POWER_DOMAIN_PCIE] = { 752 .genpd = { 753 .name = "pcie", 754 }, 755 .bits = { 756 .pxx = IMX8MM_PCIE_SW_Pxx_REQ, 757 .map = IMX8MM_PCIE_A53_DOMAIN, 758 }, 759 .pgc = BIT(IMX8MM_PGC_PCIE), 760 }, 761 762 [IMX8MM_POWER_DOMAIN_OTG1] = { 763 .genpd = { 764 .name = "usb-otg1", 765 .flags = GENPD_FLAG_ACTIVE_WAKEUP, 766 }, 767 .bits = { 768 .pxx = IMX8MM_OTG1_SW_Pxx_REQ, 769 .map = IMX8MM_OTG1_A53_DOMAIN, 770 }, 771 .pgc = BIT(IMX8MM_PGC_OTG1), 772 }, 773 774 [IMX8MM_POWER_DOMAIN_OTG2] = { 775 .genpd = { 776 .name = "usb-otg2", 777 .flags = GENPD_FLAG_ACTIVE_WAKEUP, 778 }, 779 .bits = { 780 .pxx = IMX8MM_OTG2_SW_Pxx_REQ, 781 .map = IMX8MM_OTG2_A53_DOMAIN, 782 }, 783 .pgc = BIT(IMX8MM_PGC_OTG2), 784 }, 785 786 [IMX8MM_POWER_DOMAIN_GPUMIX] = { 787 .genpd = { 788 .name = "gpumix", 789 }, 790 .bits = { 791 .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ, 792 .map = IMX8MM_GPUMIX_A53_DOMAIN, 793 }, 794 .pgc = BIT(IMX8MM_PGC_GPUMIX), 795 .keep_clocks = true, 796 }, 797 798 [IMX8MM_POWER_DOMAIN_GPU] = { 799 .genpd = { 800 .name = "gpu", 801 }, 802 .bits = { 803 .pxx = IMX8MM_GPU_SW_Pxx_REQ, 804 .map = IMX8MM_GPU_A53_DOMAIN, 805 .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, 806 .hskack = IMX8MM_GPU_HSK_PWRDNACKN, 807 }, 808 .pgc = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D), 809 }, 810 811 [IMX8MM_POWER_DOMAIN_VPUMIX] = { 812 .genpd = { 813 .name = "vpumix", 814 }, 815 .bits = { 816 .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ, 817 .map = IMX8MM_VPUMIX_A53_DOMAIN, 818 .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, 819 .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, 820 }, 821 .pgc = BIT(IMX8MM_PGC_VPUMIX), 822 .keep_clocks = true, 823 }, 824 825 [IMX8MM_POWER_DOMAIN_VPUG1] = { 826 .genpd = { 827 .name = "vpu-g1", 828 }, 829 .bits = { 830 .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, 831 .map = IMX8MM_VPUG1_A53_DOMAIN, 832 }, 833 .pgc = BIT(IMX8MM_PGC_VPUG1), 834 }, 835 836 [IMX8MM_POWER_DOMAIN_VPUG2] = { 837 .genpd = { 838 .name = "vpu-g2", 839 }, 840 .bits = { 841 .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, 842 .map = IMX8MM_VPUG2_A53_DOMAIN, 843 }, 844 .pgc = BIT(IMX8MM_PGC_VPUG2), 845 }, 846 847 [IMX8MM_POWER_DOMAIN_VPUH1] = { 848 .genpd = { 849 .name = "vpu-h1", 850 }, 851 .bits = { 852 .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, 853 .map = IMX8MM_VPUH1_A53_DOMAIN, 854 }, 855 .pgc = BIT(IMX8MM_PGC_VPUH1), 856 .keep_clocks = true, 857 }, 858 859 [IMX8MM_POWER_DOMAIN_DISPMIX] = { 860 .genpd = { 861 .name = "dispmix", 862 }, 863 .bits = { 864 .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ, 865 .map = IMX8MM_DISPMIX_A53_DOMAIN, 866 .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, 867 .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, 868 }, 869 .pgc = BIT(IMX8MM_PGC_DISPMIX), 870 .keep_clocks = true, 871 }, 872 873 [IMX8MM_POWER_DOMAIN_MIPI] = { 874 .genpd = { 875 .name = "mipi", 876 }, 877 .bits = { 878 .pxx = IMX8MM_MIPI_SW_Pxx_REQ, 879 .map = IMX8MM_MIPI_A53_DOMAIN, 880 }, 881 .pgc = BIT(IMX8MM_PGC_MIPI), 882 }, 883 }; 884 885 static const struct regmap_range imx8mm_yes_ranges[] = { 886 regmap_reg_range(GPC_LPCR_A_CORE_BSC, 887 GPC_PU_PWRHSK), 888 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI), 889 GPC_PGC_SR(IMX8MM_PGC_MIPI)), 890 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE), 891 GPC_PGC_SR(IMX8MM_PGC_PCIE)), 892 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1), 893 GPC_PGC_SR(IMX8MM_PGC_OTG1)), 894 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2), 895 GPC_PGC_SR(IMX8MM_PGC_OTG2)), 896 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1), 897 GPC_PGC_SR(IMX8MM_PGC_DDR1)), 898 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D), 899 GPC_PGC_SR(IMX8MM_PGC_GPU2D)), 900 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX), 901 GPC_PGC_SR(IMX8MM_PGC_GPUMIX)), 902 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX), 903 GPC_PGC_SR(IMX8MM_PGC_VPUMIX)), 904 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D), 905 GPC_PGC_SR(IMX8MM_PGC_GPU3D)), 906 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX), 907 GPC_PGC_SR(IMX8MM_PGC_DISPMIX)), 908 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1), 909 GPC_PGC_SR(IMX8MM_PGC_VPUG1)), 910 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2), 911 GPC_PGC_SR(IMX8MM_PGC_VPUG2)), 912 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1), 913 GPC_PGC_SR(IMX8MM_PGC_VPUH1)), 914 }; 915 916 static const struct regmap_access_table imx8mm_access_table = { 917 .yes_ranges = imx8mm_yes_ranges, 918 .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges), 919 }; 920 921 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { 922 .domains = imx8mm_pgc_domains, 923 .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), 924 .reg_access_table = &imx8mm_access_table, 925 .pgc_regs = &imx7_pgc_regs, 926 }; 927 928 static const struct imx_pgc_domain imx8mp_pgc_domains[] = { 929 [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = { 930 .genpd = { 931 .name = "mipi-phy1", 932 }, 933 .bits = { 934 .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ, 935 .map = IMX8MP_MIPI_PHY1_A53_DOMAIN, 936 }, 937 .pgc = BIT(IMX8MP_PGC_MIPI1), 938 }, 939 940 [IMX8MP_POWER_DOMAIN_PCIE_PHY] = { 941 .genpd = { 942 .name = "pcie-phy1", 943 }, 944 .bits = { 945 .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ, 946 .map = IMX8MP_PCIE_PHY_A53_DOMAIN, 947 }, 948 .pgc = BIT(IMX8MP_PGC_PCIE), 949 }, 950 951 [IMX8MP_POWER_DOMAIN_USB1_PHY] = { 952 .genpd = { 953 .name = "usb-otg1", 954 }, 955 .bits = { 956 .pxx = IMX8MP_USB1_PHY_Pxx_REQ, 957 .map = IMX8MP_USB1_PHY_A53_DOMAIN, 958 }, 959 .pgc = BIT(IMX8MP_PGC_USB1), 960 }, 961 962 [IMX8MP_POWER_DOMAIN_USB2_PHY] = { 963 .genpd = { 964 .name = "usb-otg2", 965 }, 966 .bits = { 967 .pxx = IMX8MP_USB2_PHY_Pxx_REQ, 968 .map = IMX8MP_USB2_PHY_A53_DOMAIN, 969 }, 970 .pgc = BIT(IMX8MP_PGC_USB2), 971 }, 972 973 [IMX8MP_POWER_DOMAIN_MLMIX] = { 974 .genpd = { 975 .name = "mlmix", 976 }, 977 .bits = { 978 .pxx = IMX8MP_MLMIX_Pxx_REQ, 979 .map = IMX8MP_MLMIX_A53_DOMAIN, 980 .hskreq = IMX8MP_MLMIX_PWRDNREQN, 981 .hskack = IMX8MP_MLMIX_PWRDNACKN, 982 }, 983 .pgc = BIT(IMX8MP_PGC_MLMIX), 984 .keep_clocks = true, 985 }, 986 987 [IMX8MP_POWER_DOMAIN_AUDIOMIX] = { 988 .genpd = { 989 .name = "audiomix", 990 }, 991 .bits = { 992 .pxx = IMX8MP_AUDIOMIX_Pxx_REQ, 993 .map = IMX8MP_AUDIOMIX_A53_DOMAIN, 994 .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN, 995 .hskack = IMX8MP_AUDIOMIX_PWRDNACKN, 996 }, 997 .pgc = BIT(IMX8MP_PGC_AUDIOMIX), 998 .keep_clocks = true, 999 }, 1000 1001 [IMX8MP_POWER_DOMAIN_GPU2D] = { 1002 .genpd = { 1003 .name = "gpu2d", 1004 }, 1005 .bits = { 1006 .pxx = IMX8MP_GPU_2D_Pxx_REQ, 1007 .map = IMX8MP_GPU2D_A53_DOMAIN, 1008 }, 1009 .pgc = BIT(IMX8MP_PGC_GPU2D), 1010 }, 1011 1012 [IMX8MP_POWER_DOMAIN_GPUMIX] = { 1013 .genpd = { 1014 .name = "gpumix", 1015 }, 1016 .bits = { 1017 .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ, 1018 .map = IMX8MP_GPUMIX_A53_DOMAIN, 1019 .hskreq = IMX8MP_GPUMIX_PWRDNREQN, 1020 .hskack = IMX8MP_GPUMIX_PWRDNACKN, 1021 }, 1022 .pgc = BIT(IMX8MP_PGC_GPUMIX), 1023 .keep_clocks = true, 1024 }, 1025 1026 [IMX8MP_POWER_DOMAIN_VPUMIX] = { 1027 .genpd = { 1028 .name = "vpumix", 1029 }, 1030 .bits = { 1031 .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ, 1032 .map = IMX8MP_VPUMIX_A53_DOMAIN, 1033 .hskreq = IMX8MP_VPUMIX_PWRDNREQN, 1034 .hskack = IMX8MP_VPUMIX_PWRDNACKN, 1035 }, 1036 .pgc = BIT(IMX8MP_PGC_VPUMIX), 1037 .keep_clocks = true, 1038 }, 1039 1040 [IMX8MP_POWER_DOMAIN_GPU3D] = { 1041 .genpd = { 1042 .name = "gpu3d", 1043 }, 1044 .bits = { 1045 .pxx = IMX8MP_GPU_3D_Pxx_REQ, 1046 .map = IMX8MP_GPU3D_A53_DOMAIN, 1047 }, 1048 .pgc = BIT(IMX8MP_PGC_GPU3D), 1049 }, 1050 1051 [IMX8MP_POWER_DOMAIN_MEDIAMIX] = { 1052 .genpd = { 1053 .name = "mediamix", 1054 }, 1055 .bits = { 1056 .pxx = IMX8MP_MEDIMIX_Pxx_REQ, 1057 .map = IMX8MP_MEDIAMIX_A53_DOMAIN, 1058 .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN, 1059 .hskack = IMX8MP_MEDIAMIX_PWRDNACKN, 1060 }, 1061 .pgc = BIT(IMX8MP_PGC_MEDIAMIX), 1062 .keep_clocks = true, 1063 }, 1064 1065 [IMX8MP_POWER_DOMAIN_VPU_G1] = { 1066 .genpd = { 1067 .name = "vpu-g1", 1068 }, 1069 .bits = { 1070 .pxx = IMX8MP_VPU_G1_Pxx_REQ, 1071 .map = IMX8MP_VPU_G1_A53_DOMAIN, 1072 }, 1073 .pgc = BIT(IMX8MP_PGC_VPU_G1), 1074 }, 1075 1076 [IMX8MP_POWER_DOMAIN_VPU_G2] = { 1077 .genpd = { 1078 .name = "vpu-g2", 1079 }, 1080 .bits = { 1081 .pxx = IMX8MP_VPU_G2_Pxx_REQ, 1082 .map = IMX8MP_VPU_G2_A53_DOMAIN 1083 }, 1084 .pgc = BIT(IMX8MP_PGC_VPU_G2), 1085 }, 1086 1087 [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = { 1088 .genpd = { 1089 .name = "vpu-h1", 1090 }, 1091 .bits = { 1092 .pxx = IMX8MP_VPU_VC8K_Pxx_REQ, 1093 .map = IMX8MP_VPU_VC8000E_A53_DOMAIN, 1094 }, 1095 .pgc = BIT(IMX8MP_PGC_VPU_VC8000E), 1096 }, 1097 1098 [IMX8MP_POWER_DOMAIN_HDMIMIX] = { 1099 .genpd = { 1100 .name = "hdmimix", 1101 }, 1102 .bits = { 1103 .pxx = IMX8MP_HDMIMIX_Pxx_REQ, 1104 .map = IMX8MP_HDMIMIX_A53_DOMAIN, 1105 .hskreq = IMX8MP_HDMIMIX_PWRDNREQN, 1106 .hskack = IMX8MP_HDMIMIX_PWRDNACKN, 1107 }, 1108 .pgc = BIT(IMX8MP_PGC_HDMIMIX), 1109 .keep_clocks = true, 1110 }, 1111 1112 [IMX8MP_POWER_DOMAIN_HDMI_PHY] = { 1113 .genpd = { 1114 .name = "hdmi-phy", 1115 }, 1116 .bits = { 1117 .pxx = IMX8MP_HDMI_PHY_Pxx_REQ, 1118 .map = IMX8MP_HDMI_PHY_A53_DOMAIN, 1119 }, 1120 .pgc = BIT(IMX8MP_PGC_HDMI), 1121 }, 1122 1123 [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = { 1124 .genpd = { 1125 .name = "mipi-phy2", 1126 }, 1127 .bits = { 1128 .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ, 1129 .map = IMX8MP_MIPI_PHY2_A53_DOMAIN, 1130 }, 1131 .pgc = BIT(IMX8MP_PGC_MIPI2), 1132 }, 1133 1134 [IMX8MP_POWER_DOMAIN_HSIOMIX] = { 1135 .genpd = { 1136 .name = "hsiomix", 1137 }, 1138 .bits = { 1139 .pxx = IMX8MP_HSIOMIX_Pxx_REQ, 1140 .map = IMX8MP_HSIOMIX_A53_DOMAIN, 1141 .hskreq = IMX8MP_HSIOMIX_PWRDNREQN, 1142 .hskack = IMX8MP_HSIOMIX_PWRDNACKN, 1143 }, 1144 .pgc = BIT(IMX8MP_PGC_HSIOMIX), 1145 .keep_clocks = true, 1146 }, 1147 1148 [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = { 1149 .genpd = { 1150 .name = "mediamix-isp-dwp", 1151 }, 1152 .bits = { 1153 .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ, 1154 .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN, 1155 }, 1156 .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP), 1157 }, 1158 }; 1159 1160 static const struct regmap_range imx8mp_yes_ranges[] = { 1161 regmap_reg_range(GPC_LPCR_A_CORE_BSC, 1162 IMX8MP_GPC_PGC_CPU_MAPPING), 1163 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC), 1164 GPC_PGC_SR(IMX8MP_PGC_NOC)), 1165 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1), 1166 GPC_PGC_SR(IMX8MP_PGC_MIPI1)), 1167 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE), 1168 GPC_PGC_SR(IMX8MP_PGC_PCIE)), 1169 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1), 1170 GPC_PGC_SR(IMX8MP_PGC_USB1)), 1171 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2), 1172 GPC_PGC_SR(IMX8MP_PGC_USB2)), 1173 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX), 1174 GPC_PGC_SR(IMX8MP_PGC_MLMIX)), 1175 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX), 1176 GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)), 1177 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D), 1178 GPC_PGC_SR(IMX8MP_PGC_GPU2D)), 1179 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX), 1180 GPC_PGC_SR(IMX8MP_PGC_GPUMIX)), 1181 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX), 1182 GPC_PGC_SR(IMX8MP_PGC_VPUMIX)), 1183 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D), 1184 GPC_PGC_SR(IMX8MP_PGC_GPU3D)), 1185 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX), 1186 GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)), 1187 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1), 1188 GPC_PGC_SR(IMX8MP_PGC_VPU_G1)), 1189 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2), 1190 GPC_PGC_SR(IMX8MP_PGC_VPU_G2)), 1191 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E), 1192 GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)), 1193 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX), 1194 GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)), 1195 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI), 1196 GPC_PGC_SR(IMX8MP_PGC_HDMI)), 1197 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2), 1198 GPC_PGC_SR(IMX8MP_PGC_MIPI2)), 1199 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX), 1200 GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)), 1201 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP), 1202 GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)), 1203 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX), 1204 GPC_PGC_SR(IMX8MP_PGC_DDRMIX)), 1205 }; 1206 1207 static const struct regmap_access_table imx8mp_access_table = { 1208 .yes_ranges = imx8mp_yes_ranges, 1209 .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges), 1210 }; 1211 1212 static const struct imx_pgc_regs imx8mp_pgc_regs = { 1213 .map = IMX8MP_GPC_PGC_CPU_MAPPING, 1214 .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ, 1215 .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ, 1216 .hsk = IMX8MP_GPC_PU_PWRHSK, 1217 }; 1218 static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = { 1219 .domains = imx8mp_pgc_domains, 1220 .domains_num = ARRAY_SIZE(imx8mp_pgc_domains), 1221 .reg_access_table = &imx8mp_access_table, 1222 .pgc_regs = &imx8mp_pgc_regs, 1223 }; 1224 1225 static const struct imx_pgc_domain imx8mn_pgc_domains[] = { 1226 [IMX8MN_POWER_DOMAIN_HSIOMIX] = { 1227 .genpd = { 1228 .name = "hsiomix", 1229 }, 1230 .bits = { 1231 .pxx = 0, /* no power sequence control */ 1232 .map = 0, /* no power sequence control */ 1233 .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN, 1234 .hskack = IMX8MN_HSIO_HSK_PWRDNACKN, 1235 }, 1236 .keep_clocks = true, 1237 }, 1238 1239 [IMX8MN_POWER_DOMAIN_OTG1] = { 1240 .genpd = { 1241 .name = "usb-otg1", 1242 .flags = GENPD_FLAG_ACTIVE_WAKEUP, 1243 }, 1244 .bits = { 1245 .pxx = IMX8MN_OTG1_SW_Pxx_REQ, 1246 .map = IMX8MN_OTG1_A53_DOMAIN, 1247 }, 1248 .pgc = BIT(IMX8MN_PGC_OTG1), 1249 }, 1250 1251 [IMX8MN_POWER_DOMAIN_GPUMIX] = { 1252 .genpd = { 1253 .name = "gpumix", 1254 }, 1255 .bits = { 1256 .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ, 1257 .map = IMX8MN_GPUMIX_A53_DOMAIN, 1258 .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN, 1259 .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN, 1260 }, 1261 .pgc = BIT(IMX8MN_PGC_GPUMIX), 1262 .keep_clocks = true, 1263 }, 1264 1265 [IMX8MN_POWER_DOMAIN_DISPMIX] = { 1266 .genpd = { 1267 .name = "dispmix", 1268 }, 1269 .bits = { 1270 .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ, 1271 .map = IMX8MN_DISPMIX_A53_DOMAIN, 1272 .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN, 1273 .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN, 1274 }, 1275 .pgc = BIT(IMX8MN_PGC_DISPMIX), 1276 .keep_clocks = true, 1277 }, 1278 1279 [IMX8MN_POWER_DOMAIN_MIPI] = { 1280 .genpd = { 1281 .name = "mipi", 1282 }, 1283 .bits = { 1284 .pxx = IMX8MN_MIPI_SW_Pxx_REQ, 1285 .map = IMX8MN_MIPI_A53_DOMAIN, 1286 }, 1287 .pgc = BIT(IMX8MN_PGC_MIPI), 1288 }, 1289 }; 1290 1291 static const struct regmap_range imx8mn_yes_ranges[] = { 1292 regmap_reg_range(GPC_LPCR_A_CORE_BSC, 1293 GPC_PU_PWRHSK), 1294 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI), 1295 GPC_PGC_SR(IMX8MN_PGC_MIPI)), 1296 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1), 1297 GPC_PGC_SR(IMX8MN_PGC_OTG1)), 1298 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1), 1299 GPC_PGC_SR(IMX8MN_PGC_DDR1)), 1300 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX), 1301 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)), 1302 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX), 1303 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)), 1304 }; 1305 1306 static const struct regmap_access_table imx8mn_access_table = { 1307 .yes_ranges = imx8mn_yes_ranges, 1308 .n_yes_ranges = ARRAY_SIZE(imx8mn_yes_ranges), 1309 }; 1310 1311 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { 1312 .domains = imx8mn_pgc_domains, 1313 .domains_num = ARRAY_SIZE(imx8mn_pgc_domains), 1314 .reg_access_table = &imx8mn_access_table, 1315 .pgc_regs = &imx7_pgc_regs, 1316 }; 1317 1318 static int imx_pgc_domain_probe(struct platform_device *pdev) 1319 { 1320 struct imx_pgc_domain *domain = pdev->dev.platform_data; 1321 int ret; 1322 1323 domain->dev = &pdev->dev; 1324 1325 domain->regulator = devm_regulator_get_optional(domain->dev, "power"); 1326 if (IS_ERR(domain->regulator)) { 1327 if (PTR_ERR(domain->regulator) != -ENODEV) 1328 return dev_err_probe(domain->dev, PTR_ERR(domain->regulator), 1329 "Failed to get domain's regulator\n"); 1330 } else if (domain->voltage) { 1331 regulator_set_voltage(domain->regulator, 1332 domain->voltage, domain->voltage); 1333 } 1334 1335 domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks); 1336 if (domain->num_clks < 0) 1337 return dev_err_probe(domain->dev, domain->num_clks, 1338 "Failed to get domain's clocks\n"); 1339 1340 domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev); 1341 if (IS_ERR(domain->reset)) 1342 return dev_err_probe(domain->dev, PTR_ERR(domain->reset), 1343 "Failed to get domain's resets\n"); 1344 1345 pm_runtime_enable(domain->dev); 1346 1347 if (domain->bits.map) 1348 regmap_update_bits(domain->regmap, domain->regs->map, 1349 domain->bits.map, domain->bits.map); 1350 1351 ret = pm_genpd_init(&domain->genpd, NULL, true); 1352 if (ret) { 1353 dev_err_probe(domain->dev, ret, "Failed to init power domain\n"); 1354 goto out_domain_unmap; 1355 } 1356 1357 if (IS_ENABLED(CONFIG_LOCKDEP) && 1358 of_property_present(domain->dev->of_node, "power-domains")) 1359 lockdep_set_subclass(&domain->genpd.mlock, 1); 1360 1361 ret = of_genpd_add_provider_simple(domain->dev->of_node, 1362 &domain->genpd); 1363 if (ret) { 1364 dev_err_probe(domain->dev, ret, "Failed to add genpd provider\n"); 1365 goto out_genpd_remove; 1366 } 1367 1368 return 0; 1369 1370 out_genpd_remove: 1371 pm_genpd_remove(&domain->genpd); 1372 out_domain_unmap: 1373 if (domain->bits.map) 1374 regmap_update_bits(domain->regmap, domain->regs->map, 1375 domain->bits.map, 0); 1376 pm_runtime_disable(domain->dev); 1377 1378 return ret; 1379 } 1380 1381 static void imx_pgc_domain_remove(struct platform_device *pdev) 1382 { 1383 struct imx_pgc_domain *domain = pdev->dev.platform_data; 1384 1385 of_genpd_del_provider(domain->dev->of_node); 1386 pm_genpd_remove(&domain->genpd); 1387 1388 if (domain->bits.map) 1389 regmap_update_bits(domain->regmap, domain->regs->map, 1390 domain->bits.map, 0); 1391 1392 pm_runtime_disable(domain->dev); 1393 } 1394 1395 #ifdef CONFIG_PM_SLEEP 1396 static int imx_pgc_domain_suspend(struct device *dev) 1397 { 1398 /* 1399 * This may look strange, but is done so the generic PM_SLEEP code 1400 * can power down our domain and more importantly power it up again 1401 * after resume, without tripping over our usage of runtime PM to 1402 * power up/down the nested domains. 1403 */ 1404 return pm_runtime_resume_and_get(dev); 1405 } 1406 1407 static int imx_pgc_domain_resume(struct device *dev) 1408 { 1409 pm_runtime_put(dev); 1410 1411 return 0; 1412 } 1413 #endif 1414 1415 static const struct dev_pm_ops imx_pgc_domain_pm_ops = { 1416 SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume) 1417 }; 1418 1419 static const struct platform_device_id imx_pgc_domain_id[] = { 1420 { "imx-pgc-domain", }, 1421 { }, 1422 }; 1423 1424 static struct platform_driver imx_pgc_domain_driver = { 1425 .driver = { 1426 .name = "imx-pgc", 1427 .pm = &imx_pgc_domain_pm_ops, 1428 .suppress_bind_attrs = true, 1429 }, 1430 .probe = imx_pgc_domain_probe, 1431 .remove = imx_pgc_domain_remove, 1432 .id_table = imx_pgc_domain_id, 1433 }; 1434 builtin_platform_driver(imx_pgc_domain_driver) 1435 1436 static int imx_gpcv2_probe(struct platform_device *pdev) 1437 { 1438 const struct imx_pgc_domain_data *domain_data = 1439 of_device_get_match_data(&pdev->dev); 1440 1441 struct regmap_config regmap_config = { 1442 .reg_bits = 32, 1443 .val_bits = 32, 1444 .reg_stride = 4, 1445 .rd_table = domain_data->reg_access_table, 1446 .wr_table = domain_data->reg_access_table, 1447 .max_register = SZ_4K, 1448 }; 1449 struct device *dev = &pdev->dev; 1450 struct device_node *pgc_np __free(device_node) = 1451 of_get_child_by_name(dev->of_node, "pgc"); 1452 struct regmap *regmap; 1453 void __iomem *base; 1454 int ret; 1455 1456 if (!pgc_np) { 1457 dev_err(dev, "No power domains specified in DT\n"); 1458 return -EINVAL; 1459 } 1460 1461 base = devm_platform_ioremap_resource(pdev, 0); 1462 if (IS_ERR(base)) 1463 return PTR_ERR(base); 1464 1465 regmap = devm_regmap_init_mmio(dev, base, ®map_config); 1466 if (IS_ERR(regmap)) { 1467 ret = PTR_ERR(regmap); 1468 dev_err(dev, "failed to init regmap (%d)\n", ret); 1469 return ret; 1470 } 1471 1472 for_each_child_of_node_scoped(pgc_np, np) { 1473 struct platform_device *pd_pdev; 1474 struct imx_pgc_domain *domain; 1475 u32 domain_index; 1476 1477 if (!of_device_is_available(np)) 1478 continue; 1479 1480 ret = of_property_read_u32(np, "reg", &domain_index); 1481 if (ret) { 1482 dev_err(dev, "Failed to read 'reg' property\n"); 1483 return ret; 1484 } 1485 1486 if (domain_index >= domain_data->domains_num) { 1487 dev_warn(dev, 1488 "Domain index %d is out of bounds\n", 1489 domain_index); 1490 continue; 1491 } 1492 1493 pd_pdev = platform_device_alloc("imx-pgc-domain", 1494 domain_index); 1495 if (!pd_pdev) { 1496 dev_err(dev, "Failed to allocate platform device\n"); 1497 return -ENOMEM; 1498 } 1499 1500 ret = platform_device_add_data(pd_pdev, 1501 &domain_data->domains[domain_index], 1502 sizeof(domain_data->domains[domain_index])); 1503 if (ret) { 1504 platform_device_put(pd_pdev); 1505 return ret; 1506 } 1507 1508 domain = pd_pdev->dev.platform_data; 1509 domain->regmap = regmap; 1510 domain->regs = domain_data->pgc_regs; 1511 1512 domain->genpd.power_on = imx_pgc_power_up; 1513 domain->genpd.power_off = imx_pgc_power_down; 1514 1515 pd_pdev->dev.parent = dev; 1516 device_set_node(&pd_pdev->dev, of_fwnode_handle(np)); 1517 1518 ret = platform_device_add(pd_pdev); 1519 if (ret) { 1520 platform_device_put(pd_pdev); 1521 return ret; 1522 } 1523 } 1524 1525 return 0; 1526 } 1527 1528 static const struct of_device_id imx_gpcv2_dt_ids[] = { 1529 { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, 1530 { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, 1531 { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, }, 1532 { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, }, 1533 { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, 1534 { } 1535 }; 1536 1537 static struct platform_driver imx_gpc_driver = { 1538 .driver = { 1539 .name = "imx-gpcv2", 1540 .of_match_table = imx_gpcv2_dt_ids, 1541 .suppress_bind_attrs = true, 1542 }, 1543 .probe = imx_gpcv2_probe, 1544 }; 1545 builtin_platform_driver(imx_gpc_driver) 1546