xref: /linux/include/dt-bindings/clock/imx7d-clock.h (revision ead5d1f4d877e92c051e1a1ade623d0d30e71619)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __DT_BINDINGS_CLOCK_IMX7D_H
7 #define __DT_BINDINGS_CLOCK_IMX7D_H
8 
9 #define IMX7D_OSC_24M_CLK		0
10 #define IMX7D_PLL_ARM_MAIN		1
11 #define IMX7D_PLL_ARM_MAIN_CLK		2
12 #define IMX7D_PLL_ARM_MAIN_SRC		3
13 #define IMX7D_PLL_ARM_MAIN_BYPASS	4
14 #define IMX7D_PLL_SYS_MAIN		5
15 #define IMX7D_PLL_SYS_MAIN_CLK		6
16 #define IMX7D_PLL_SYS_MAIN_SRC		7
17 #define IMX7D_PLL_SYS_MAIN_BYPASS	8
18 #define IMX7D_PLL_SYS_MAIN_480M		9
19 #define IMX7D_PLL_SYS_MAIN_240M		10
20 #define IMX7D_PLL_SYS_MAIN_120M		11
21 #define IMX7D_PLL_SYS_MAIN_480M_CLK	12
22 #define IMX7D_PLL_SYS_MAIN_240M_CLK	13
23 #define IMX7D_PLL_SYS_MAIN_120M_CLK	14
24 #define IMX7D_PLL_SYS_PFD0_392M_CLK	15
25 #define IMX7D_PLL_SYS_PFD0_196M		16
26 #define IMX7D_PLL_SYS_PFD0_196M_CLK	17
27 #define IMX7D_PLL_SYS_PFD1_332M_CLK	18
28 #define IMX7D_PLL_SYS_PFD1_166M		19
29 #define IMX7D_PLL_SYS_PFD1_166M_CLK	20
30 #define IMX7D_PLL_SYS_PFD2_270M_CLK	21
31 #define IMX7D_PLL_SYS_PFD2_135M		22
32 #define IMX7D_PLL_SYS_PFD2_135M_CLK	23
33 #define IMX7D_PLL_SYS_PFD3_CLK		24
34 #define IMX7D_PLL_SYS_PFD4_CLK		25
35 #define IMX7D_PLL_SYS_PFD5_CLK		26
36 #define IMX7D_PLL_SYS_PFD6_CLK		27
37 #define IMX7D_PLL_SYS_PFD7_CLK		28
38 #define IMX7D_PLL_ENET_MAIN		29
39 #define IMX7D_PLL_ENET_MAIN_CLK		30
40 #define IMX7D_PLL_ENET_MAIN_SRC		31
41 #define IMX7D_PLL_ENET_MAIN_BYPASS	32
42 #define IMX7D_PLL_ENET_MAIN_500M	33
43 #define IMX7D_PLL_ENET_MAIN_250M	34
44 #define IMX7D_PLL_ENET_MAIN_125M	35
45 #define IMX7D_PLL_ENET_MAIN_100M	36
46 #define IMX7D_PLL_ENET_MAIN_50M		37
47 #define IMX7D_PLL_ENET_MAIN_40M		38
48 #define IMX7D_PLL_ENET_MAIN_25M		39
49 #define IMX7D_PLL_ENET_MAIN_500M_CLK	40
50 #define IMX7D_PLL_ENET_MAIN_250M_CLK	41
51 #define IMX7D_PLL_ENET_MAIN_125M_CLK	42
52 #define IMX7D_PLL_ENET_MAIN_100M_CLK	43
53 #define IMX7D_PLL_ENET_MAIN_50M_CLK	44
54 #define IMX7D_PLL_ENET_MAIN_40M_CLK	45
55 #define IMX7D_PLL_ENET_MAIN_25M_CLK	46
56 #define IMX7D_PLL_DRAM_MAIN		47
57 #define IMX7D_PLL_DRAM_MAIN_CLK		48
58 #define IMX7D_PLL_DRAM_MAIN_SRC		49
59 #define IMX7D_PLL_DRAM_MAIN_BYPASS	50
60 #define IMX7D_PLL_DRAM_MAIN_533M	51
61 #define IMX7D_PLL_DRAM_MAIN_533M_CLK	52
62 #define IMX7D_PLL_AUDIO_MAIN		53
63 #define IMX7D_PLL_AUDIO_MAIN_CLK	54
64 #define IMX7D_PLL_AUDIO_MAIN_SRC	55
65 #define IMX7D_PLL_AUDIO_MAIN_BYPASS	56
66 #define IMX7D_PLL_VIDEO_MAIN_CLK	57
67 #define IMX7D_PLL_VIDEO_MAIN		58
68 #define IMX7D_PLL_VIDEO_MAIN_SRC	59
69 #define IMX7D_PLL_VIDEO_MAIN_BYPASS	60
70 #define IMX7D_USB_MAIN_480M_CLK		61
71 #define IMX7D_ARM_A7_ROOT_CLK		62
72 #define IMX7D_ARM_A7_ROOT_SRC		63
73 #define IMX7D_ARM_A7_ROOT_CG		64
74 #define IMX7D_ARM_A7_ROOT_DIV		65
75 #define IMX7D_ARM_M4_ROOT_CLK		66
76 #define IMX7D_ARM_M4_ROOT_SRC		67
77 #define IMX7D_ARM_M4_ROOT_CG		68
78 #define IMX7D_ARM_M4_ROOT_DIV		69
79 #define IMX7D_ARM_M0_ROOT_CLK		70	/* unused */
80 #define IMX7D_ARM_M0_ROOT_SRC		71	/* unused */
81 #define IMX7D_ARM_M0_ROOT_CG		72	/* unused */
82 #define IMX7D_ARM_M0_ROOT_DIV		73	/* unused */
83 #define IMX7D_MAIN_AXI_ROOT_CLK		74
84 #define IMX7D_MAIN_AXI_ROOT_SRC		75
85 #define IMX7D_MAIN_AXI_ROOT_CG		76
86 #define IMX7D_MAIN_AXI_ROOT_DIV		77
87 #define IMX7D_DISP_AXI_ROOT_CLK		78
88 #define IMX7D_DISP_AXI_ROOT_SRC		79
89 #define IMX7D_DISP_AXI_ROOT_CG		80
90 #define IMX7D_DISP_AXI_ROOT_DIV		81
91 #define IMX7D_ENET_AXI_ROOT_CLK		82
92 #define IMX7D_ENET_AXI_ROOT_SRC		83
93 #define IMX7D_ENET_AXI_ROOT_CG		84
94 #define IMX7D_ENET_AXI_ROOT_DIV		85
95 #define IMX7D_NAND_USDHC_BUS_ROOT_CLK	86
96 #define IMX7D_NAND_USDHC_BUS_ROOT_SRC	87
97 #define IMX7D_NAND_USDHC_BUS_ROOT_CG	88
98 #define IMX7D_NAND_USDHC_BUS_ROOT_DIV	89
99 #define IMX7D_AHB_CHANNEL_ROOT_CLK	90
100 #define IMX7D_AHB_CHANNEL_ROOT_SRC	91
101 #define IMX7D_AHB_CHANNEL_ROOT_CG	92
102 #define IMX7D_AHB_CHANNEL_ROOT_DIV	93
103 #define IMX7D_DRAM_PHYM_ROOT_CLK	94
104 #define IMX7D_DRAM_PHYM_ROOT_SRC	95
105 #define IMX7D_DRAM_PHYM_ROOT_CG		96
106 #define IMX7D_DRAM_PHYM_ROOT_DIV	97
107 #define IMX7D_DRAM_ROOT_CLK		98
108 #define IMX7D_DRAM_ROOT_SRC		99
109 #define IMX7D_DRAM_ROOT_CG		100
110 #define IMX7D_DRAM_ROOT_DIV		101
111 #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK	102
112 #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC	103
113 #define IMX7D_DRAM_PHYM_ALT_ROOT_CG	104
114 #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV	105
115 #define IMX7D_DRAM_ALT_ROOT_CLK		106
116 #define IMX7D_DRAM_ALT_ROOT_SRC		107
117 #define IMX7D_DRAM_ALT_ROOT_CG		108
118 #define IMX7D_DRAM_ALT_ROOT_DIV		109
119 #define IMX7D_USB_HSIC_ROOT_CLK		110
120 #define IMX7D_USB_HSIC_ROOT_SRC		111
121 #define IMX7D_USB_HSIC_ROOT_CG		112
122 #define IMX7D_USB_HSIC_ROOT_DIV		113
123 #define IMX7D_PCIE_CTRL_ROOT_CLK	114
124 #define IMX7D_PCIE_CTRL_ROOT_SRC	115
125 #define IMX7D_PCIE_CTRL_ROOT_CG		116
126 #define IMX7D_PCIE_CTRL_ROOT_DIV	117
127 #define IMX7D_PCIE_PHY_ROOT_CLK		118
128 #define IMX7D_PCIE_PHY_ROOT_SRC		119
129 #define IMX7D_PCIE_PHY_ROOT_CG		120
130 #define IMX7D_PCIE_PHY_ROOT_DIV		121
131 #define IMX7D_EPDC_PIXEL_ROOT_CLK	122
132 #define IMX7D_EPDC_PIXEL_ROOT_SRC	123
133 #define IMX7D_EPDC_PIXEL_ROOT_CG	124
134 #define IMX7D_EPDC_PIXEL_ROOT_DIV	125
135 #define IMX7D_LCDIF_PIXEL_ROOT_CLK	126
136 #define IMX7D_LCDIF_PIXEL_ROOT_SRC	127
137 #define IMX7D_LCDIF_PIXEL_ROOT_CG	128
138 #define IMX7D_LCDIF_PIXEL_ROOT_DIV	129
139 #define IMX7D_MIPI_DSI_ROOT_CLK		130
140 #define IMX7D_MIPI_DSI_ROOT_SRC		131
141 #define IMX7D_MIPI_DSI_ROOT_CG		132
142 #define IMX7D_MIPI_DSI_ROOT_DIV		133
143 #define IMX7D_MIPI_CSI_ROOT_CLK		134
144 #define IMX7D_MIPI_CSI_ROOT_SRC		135
145 #define IMX7D_MIPI_CSI_ROOT_CG		136
146 #define IMX7D_MIPI_CSI_ROOT_DIV		137
147 #define IMX7D_MIPI_DPHY_ROOT_CLK	138
148 #define IMX7D_MIPI_DPHY_ROOT_SRC	139
149 #define IMX7D_MIPI_DPHY_ROOT_CG		140
150 #define IMX7D_MIPI_DPHY_ROOT_DIV	141
151 #define IMX7D_SAI1_ROOT_CLK		142
152 #define IMX7D_SAI1_ROOT_SRC		143
153 #define IMX7D_SAI1_ROOT_CG		144
154 #define IMX7D_SAI1_ROOT_DIV		145
155 #define IMX7D_SAI2_ROOT_CLK		146
156 #define IMX7D_SAI2_ROOT_SRC		147
157 #define IMX7D_SAI2_ROOT_CG		148
158 #define IMX7D_SAI2_ROOT_DIV		149
159 #define IMX7D_SAI3_ROOT_CLK		150
160 #define IMX7D_SAI3_ROOT_SRC		151
161 #define IMX7D_SAI3_ROOT_CG		152
162 #define IMX7D_SAI3_ROOT_DIV		153
163 #define IMX7D_SPDIF_ROOT_CLK		154
164 #define IMX7D_SPDIF_ROOT_SRC		155
165 #define IMX7D_SPDIF_ROOT_CG		156
166 #define IMX7D_SPDIF_ROOT_DIV		157
167 #define IMX7D_ENET1_IPG_ROOT_CLK        158
168 #define IMX7D_ENET1_REF_ROOT_SRC	159
169 #define IMX7D_ENET1_REF_ROOT_CG		160
170 #define IMX7D_ENET1_REF_ROOT_DIV	161
171 #define IMX7D_ENET1_TIME_ROOT_CLK	162
172 #define IMX7D_ENET1_TIME_ROOT_SRC	163
173 #define IMX7D_ENET1_TIME_ROOT_CG	164
174 #define IMX7D_ENET1_TIME_ROOT_DIV	165
175 #define IMX7D_ENET2_IPG_ROOT_CLK        166
176 #define IMX7D_ENET2_REF_ROOT_SRC	167
177 #define IMX7D_ENET2_REF_ROOT_CG		168
178 #define IMX7D_ENET2_REF_ROOT_DIV	169
179 #define IMX7D_ENET2_TIME_ROOT_CLK	170
180 #define IMX7D_ENET2_TIME_ROOT_SRC	171
181 #define IMX7D_ENET2_TIME_ROOT_CG	172
182 #define IMX7D_ENET2_TIME_ROOT_DIV	173
183 #define IMX7D_ENET_PHY_REF_ROOT_CLK	174
184 #define IMX7D_ENET_PHY_REF_ROOT_SRC	175
185 #define IMX7D_ENET_PHY_REF_ROOT_CG	176
186 #define IMX7D_ENET_PHY_REF_ROOT_DIV	177
187 #define IMX7D_EIM_ROOT_CLK		178
188 #define IMX7D_EIM_ROOT_SRC		179
189 #define IMX7D_EIM_ROOT_CG		180
190 #define IMX7D_EIM_ROOT_DIV		181
191 #define IMX7D_NAND_ROOT_CLK		182
192 #define IMX7D_NAND_ROOT_SRC		183
193 #define IMX7D_NAND_ROOT_CG		184
194 #define IMX7D_NAND_ROOT_DIV		185
195 #define IMX7D_QSPI_ROOT_CLK		186
196 #define IMX7D_QSPI_ROOT_SRC		187
197 #define IMX7D_QSPI_ROOT_CG		188
198 #define IMX7D_QSPI_ROOT_DIV		189
199 #define IMX7D_USDHC1_ROOT_CLK		190
200 #define IMX7D_USDHC1_ROOT_SRC		191
201 #define IMX7D_USDHC1_ROOT_CG		192
202 #define IMX7D_USDHC1_ROOT_DIV		193
203 #define IMX7D_USDHC2_ROOT_CLK		194
204 #define IMX7D_USDHC2_ROOT_SRC		195
205 #define IMX7D_USDHC2_ROOT_CG		196
206 #define IMX7D_USDHC2_ROOT_DIV		197
207 #define IMX7D_USDHC3_ROOT_CLK		198
208 #define IMX7D_USDHC3_ROOT_SRC		199
209 #define IMX7D_USDHC3_ROOT_CG		200
210 #define IMX7D_USDHC3_ROOT_DIV		201
211 #define IMX7D_CAN1_ROOT_CLK		202
212 #define IMX7D_CAN1_ROOT_SRC		203
213 #define IMX7D_CAN1_ROOT_CG		204
214 #define IMX7D_CAN1_ROOT_DIV		205
215 #define IMX7D_CAN2_ROOT_CLK		206
216 #define IMX7D_CAN2_ROOT_SRC		207
217 #define IMX7D_CAN2_ROOT_CG		208
218 #define IMX7D_CAN2_ROOT_DIV		209
219 #define IMX7D_I2C1_ROOT_CLK		210
220 #define IMX7D_I2C1_ROOT_SRC		211
221 #define IMX7D_I2C1_ROOT_CG		212
222 #define IMX7D_I2C1_ROOT_DIV		213
223 #define IMX7D_I2C2_ROOT_CLK		214
224 #define IMX7D_I2C2_ROOT_SRC		215
225 #define IMX7D_I2C2_ROOT_CG		216
226 #define IMX7D_I2C2_ROOT_DIV		217
227 #define IMX7D_I2C3_ROOT_CLK		218
228 #define IMX7D_I2C3_ROOT_SRC		219
229 #define IMX7D_I2C3_ROOT_CG		220
230 #define IMX7D_I2C3_ROOT_DIV		221
231 #define IMX7D_I2C4_ROOT_CLK		222
232 #define IMX7D_I2C4_ROOT_SRC		223
233 #define IMX7D_I2C4_ROOT_CG		224
234 #define IMX7D_I2C4_ROOT_DIV		225
235 #define IMX7D_UART1_ROOT_CLK		226
236 #define IMX7D_UART1_ROOT_SRC		227
237 #define IMX7D_UART1_ROOT_CG		228
238 #define IMX7D_UART1_ROOT_DIV		229
239 #define IMX7D_UART2_ROOT_CLK		230
240 #define IMX7D_UART2_ROOT_SRC		231
241 #define IMX7D_UART2_ROOT_CG		232
242 #define IMX7D_UART2_ROOT_DIV		233
243 #define IMX7D_UART3_ROOT_CLK		234
244 #define IMX7D_UART3_ROOT_SRC		235
245 #define IMX7D_UART3_ROOT_CG		236
246 #define IMX7D_UART3_ROOT_DIV		237
247 #define IMX7D_UART4_ROOT_CLK		238
248 #define IMX7D_UART4_ROOT_SRC		239
249 #define IMX7D_UART4_ROOT_CG		240
250 #define IMX7D_UART4_ROOT_DIV		241
251 #define IMX7D_UART5_ROOT_CLK		242
252 #define IMX7D_UART5_ROOT_SRC		243
253 #define IMX7D_UART5_ROOT_CG		244
254 #define IMX7D_UART5_ROOT_DIV		245
255 #define IMX7D_UART6_ROOT_CLK		246
256 #define IMX7D_UART6_ROOT_SRC		247
257 #define IMX7D_UART6_ROOT_CG		248
258 #define IMX7D_UART6_ROOT_DIV		249
259 #define IMX7D_UART7_ROOT_CLK		250
260 #define IMX7D_UART7_ROOT_SRC		251
261 #define IMX7D_UART7_ROOT_CG		252
262 #define IMX7D_UART7_ROOT_DIV		253
263 #define IMX7D_ECSPI1_ROOT_CLK		254
264 #define IMX7D_ECSPI1_ROOT_SRC		255
265 #define IMX7D_ECSPI1_ROOT_CG		256
266 #define IMX7D_ECSPI1_ROOT_DIV		257
267 #define IMX7D_ECSPI2_ROOT_CLK		258
268 #define IMX7D_ECSPI2_ROOT_SRC		259
269 #define IMX7D_ECSPI2_ROOT_CG		260
270 #define IMX7D_ECSPI2_ROOT_DIV		261
271 #define IMX7D_ECSPI3_ROOT_CLK		262
272 #define IMX7D_ECSPI3_ROOT_SRC		263
273 #define IMX7D_ECSPI3_ROOT_CG		264
274 #define IMX7D_ECSPI3_ROOT_DIV		265
275 #define IMX7D_ECSPI4_ROOT_CLK		266
276 #define IMX7D_ECSPI4_ROOT_SRC		267
277 #define IMX7D_ECSPI4_ROOT_CG		268
278 #define IMX7D_ECSPI4_ROOT_DIV		269
279 #define IMX7D_PWM1_ROOT_CLK		270
280 #define IMX7D_PWM1_ROOT_SRC		271
281 #define IMX7D_PWM1_ROOT_CG		272
282 #define IMX7D_PWM1_ROOT_DIV		273
283 #define IMX7D_PWM2_ROOT_CLK		274
284 #define IMX7D_PWM2_ROOT_SRC		275
285 #define IMX7D_PWM2_ROOT_CG		276
286 #define IMX7D_PWM2_ROOT_DIV		277
287 #define IMX7D_PWM3_ROOT_CLK		278
288 #define IMX7D_PWM3_ROOT_SRC		279
289 #define IMX7D_PWM3_ROOT_CG		280
290 #define IMX7D_PWM3_ROOT_DIV		281
291 #define IMX7D_PWM4_ROOT_CLK		282
292 #define IMX7D_PWM4_ROOT_SRC		283
293 #define IMX7D_PWM4_ROOT_CG		284
294 #define IMX7D_PWM4_ROOT_DIV		285
295 #define IMX7D_FLEXTIMER1_ROOT_CLK	286
296 #define IMX7D_FLEXTIMER1_ROOT_SRC	287
297 #define IMX7D_FLEXTIMER1_ROOT_CG	288
298 #define IMX7D_FLEXTIMER1_ROOT_DIV	289
299 #define IMX7D_FLEXTIMER2_ROOT_CLK	290
300 #define IMX7D_FLEXTIMER2_ROOT_SRC	291
301 #define IMX7D_FLEXTIMER2_ROOT_CG	292
302 #define IMX7D_FLEXTIMER2_ROOT_DIV	293
303 #define IMX7D_SIM1_ROOT_CLK		294
304 #define IMX7D_SIM1_ROOT_SRC		295
305 #define IMX7D_SIM1_ROOT_CG		296
306 #define IMX7D_SIM1_ROOT_DIV		297
307 #define IMX7D_SIM2_ROOT_CLK		298
308 #define IMX7D_SIM2_ROOT_SRC		299
309 #define IMX7D_SIM2_ROOT_CG		300
310 #define IMX7D_SIM2_ROOT_DIV		301
311 #define IMX7D_GPT1_ROOT_CLK		302
312 #define IMX7D_GPT1_ROOT_SRC		303
313 #define IMX7D_GPT1_ROOT_CG		304
314 #define IMX7D_GPT1_ROOT_DIV		305
315 #define IMX7D_GPT2_ROOT_CLK		306
316 #define IMX7D_GPT2_ROOT_SRC		307
317 #define IMX7D_GPT2_ROOT_CG		308
318 #define IMX7D_GPT2_ROOT_DIV		309
319 #define IMX7D_GPT3_ROOT_CLK		310
320 #define IMX7D_GPT3_ROOT_SRC		311
321 #define IMX7D_GPT3_ROOT_CG		312
322 #define IMX7D_GPT3_ROOT_DIV		313
323 #define IMX7D_GPT4_ROOT_CLK		314
324 #define IMX7D_GPT4_ROOT_SRC		315
325 #define IMX7D_GPT4_ROOT_CG		316
326 #define IMX7D_GPT4_ROOT_DIV		317
327 #define IMX7D_TRACE_ROOT_CLK		318
328 #define IMX7D_TRACE_ROOT_SRC		319
329 #define IMX7D_TRACE_ROOT_CG		320
330 #define IMX7D_TRACE_ROOT_DIV		321
331 #define IMX7D_WDOG1_ROOT_CLK		322
332 #define IMX7D_WDOG_ROOT_SRC		323
333 #define IMX7D_WDOG_ROOT_CG		324
334 #define IMX7D_WDOG_ROOT_DIV		325
335 #define IMX7D_CSI_MCLK_ROOT_CLK		326
336 #define IMX7D_CSI_MCLK_ROOT_SRC		327
337 #define IMX7D_CSI_MCLK_ROOT_CG		328
338 #define IMX7D_CSI_MCLK_ROOT_DIV		329
339 #define IMX7D_AUDIO_MCLK_ROOT_CLK	330
340 #define IMX7D_AUDIO_MCLK_ROOT_SRC	331
341 #define IMX7D_AUDIO_MCLK_ROOT_CG	332
342 #define IMX7D_AUDIO_MCLK_ROOT_DIV	333
343 #define IMX7D_WRCLK_ROOT_CLK		334
344 #define IMX7D_WRCLK_ROOT_SRC		335
345 #define IMX7D_WRCLK_ROOT_CG		336
346 #define IMX7D_WRCLK_ROOT_DIV		337
347 #define IMX7D_CLKO1_ROOT_SRC		338
348 #define IMX7D_CLKO1_ROOT_CG		339
349 #define IMX7D_CLKO1_ROOT_DIV		340
350 #define IMX7D_CLKO2_ROOT_SRC		341
351 #define IMX7D_CLKO2_ROOT_CG		342
352 #define IMX7D_CLKO2_ROOT_DIV		343
353 #define IMX7D_MAIN_AXI_ROOT_PRE_DIV	344
354 #define IMX7D_DISP_AXI_ROOT_PRE_DIV	345
355 #define IMX7D_ENET_AXI_ROOT_PRE_DIV	346
356 #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
357 #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV	348
358 #define IMX7D_USB_HSIC_ROOT_PRE_DIV	349
359 #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV	350
360 #define IMX7D_PCIE_PHY_ROOT_PRE_DIV	351
361 #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV	352
362 #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV	353
363 #define IMX7D_MIPI_DSI_ROOT_PRE_DIV	354
364 #define IMX7D_MIPI_CSI_ROOT_PRE_DIV	355
365 #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV	356
366 #define IMX7D_SAI1_ROOT_PRE_DIV		357
367 #define IMX7D_SAI2_ROOT_PRE_DIV		358
368 #define IMX7D_SAI3_ROOT_PRE_DIV		359
369 #define IMX7D_SPDIF_ROOT_PRE_DIV	360
370 #define IMX7D_ENET1_REF_ROOT_PRE_DIV	361
371 #define IMX7D_ENET1_TIME_ROOT_PRE_DIV	362
372 #define IMX7D_ENET2_REF_ROOT_PRE_DIV	363
373 #define IMX7D_ENET2_TIME_ROOT_PRE_DIV	364
374 #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
375 #define IMX7D_EIM_ROOT_PRE_DIV		366
376 #define IMX7D_NAND_ROOT_PRE_DIV		367
377 #define IMX7D_QSPI_ROOT_PRE_DIV		368
378 #define IMX7D_USDHC1_ROOT_PRE_DIV	369
379 #define IMX7D_USDHC2_ROOT_PRE_DIV	370
380 #define IMX7D_USDHC3_ROOT_PRE_DIV	371
381 #define IMX7D_CAN1_ROOT_PRE_DIV		372
382 #define IMX7D_CAN2_ROOT_PRE_DIV		373
383 #define IMX7D_I2C1_ROOT_PRE_DIV		374
384 #define IMX7D_I2C2_ROOT_PRE_DIV		375
385 #define IMX7D_I2C3_ROOT_PRE_DIV		376
386 #define IMX7D_I2C4_ROOT_PRE_DIV		377
387 #define IMX7D_UART1_ROOT_PRE_DIV	378
388 #define IMX7D_UART2_ROOT_PRE_DIV	379
389 #define IMX7D_UART3_ROOT_PRE_DIV	380
390 #define IMX7D_UART4_ROOT_PRE_DIV	381
391 #define IMX7D_UART5_ROOT_PRE_DIV	382
392 #define IMX7D_UART6_ROOT_PRE_DIV	383
393 #define IMX7D_UART7_ROOT_PRE_DIV	384
394 #define IMX7D_ECSPI1_ROOT_PRE_DIV	385
395 #define IMX7D_ECSPI2_ROOT_PRE_DIV	386
396 #define IMX7D_ECSPI3_ROOT_PRE_DIV	387
397 #define IMX7D_ECSPI4_ROOT_PRE_DIV	388
398 #define IMX7D_PWM1_ROOT_PRE_DIV		389
399 #define IMX7D_PWM2_ROOT_PRE_DIV		390
400 #define IMX7D_PWM3_ROOT_PRE_DIV		391
401 #define IMX7D_PWM4_ROOT_PRE_DIV		392
402 #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV	393
403 #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV	394
404 #define IMX7D_SIM1_ROOT_PRE_DIV		395
405 #define IMX7D_SIM2_ROOT_PRE_DIV		396
406 #define IMX7D_GPT1_ROOT_PRE_DIV		397
407 #define IMX7D_GPT2_ROOT_PRE_DIV		398
408 #define IMX7D_GPT3_ROOT_PRE_DIV		399
409 #define IMX7D_GPT4_ROOT_PRE_DIV		400
410 #define IMX7D_TRACE_ROOT_PRE_DIV	401
411 #define IMX7D_WDOG_ROOT_PRE_DIV		402
412 #define IMX7D_CSI_MCLK_ROOT_PRE_DIV	403
413 #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV	404
414 #define IMX7D_WRCLK_ROOT_PRE_DIV	405
415 #define IMX7D_CLKO1_ROOT_PRE_DIV	406
416 #define IMX7D_CLKO2_ROOT_PRE_DIV	407
417 #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
418 #define IMX7D_DRAM_ALT_ROOT_PRE_DIV	409
419 #define IMX7D_LVDS1_IN_CLK		410
420 #define IMX7D_LVDS1_OUT_SEL		411
421 #define IMX7D_LVDS1_OUT_CLK		412
422 #define IMX7D_CLK_DUMMY			413
423 #define IMX7D_GPT_3M_CLK		414
424 #define IMX7D_OCRAM_CLK			415
425 #define IMX7D_OCRAM_S_CLK		416
426 #define IMX7D_WDOG2_ROOT_CLK		417
427 #define IMX7D_WDOG3_ROOT_CLK		418
428 #define IMX7D_WDOG4_ROOT_CLK		419
429 #define IMX7D_SDMA_CORE_CLK		420
430 #define IMX7D_USB1_MAIN_480M_CLK	421
431 #define IMX7D_USB_CTRL_CLK		422
432 #define IMX7D_USB_PHY1_CLK		423
433 #define IMX7D_USB_PHY2_CLK		424
434 #define IMX7D_IPG_ROOT_CLK		425
435 #define IMX7D_SAI1_IPG_CLK		426
436 #define IMX7D_SAI2_IPG_CLK		427
437 #define IMX7D_SAI3_IPG_CLK		428
438 #define IMX7D_PLL_AUDIO_TEST_DIV	429
439 #define IMX7D_PLL_AUDIO_POST_DIV	430
440 #define IMX7D_PLL_VIDEO_TEST_DIV	431
441 #define IMX7D_PLL_VIDEO_POST_DIV	432
442 #define IMX7D_MU_ROOT_CLK		433
443 #define IMX7D_SEMA4_HS_ROOT_CLK		434
444 #define IMX7D_PLL_DRAM_TEST_DIV		435
445 #define IMX7D_ADC_ROOT_CLK		436
446 #define IMX7D_CLK_ARM			437
447 #define IMX7D_CKIL			438
448 #define IMX7D_OCOTP_CLK			439
449 #define IMX7D_NAND_RAWNAND_CLK		440
450 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
451 #define IMX7D_SNVS_CLK			442
452 #define IMX7D_CAAM_CLK			443
453 #define IMX7D_KPP_ROOT_CLK		444
454 #define IMX7D_PXP_CLK			445
455 #define IMX7D_CLK_END			446
456 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
457