1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD5766, AD5767
4 * Digital to Analog Converters driver
5 * Copyright 2019-2020 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/iio/iio.h>
13 #include <linux/iio/triggered_buffer.h>
14 #include <linux/iio/trigger_consumer.h>
15 #include <linux/module.h>
16 #include <linux/spi/spi.h>
17 #include <linux/unaligned.h>
18
19 #define AD5766_UPPER_WORD_SPI_MASK GENMASK(31, 16)
20 #define AD5766_LOWER_WORD_SPI_MASK GENMASK(15, 0)
21 #define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))
22 #define AD5766_DITHER_SOURCE(ch, source) BIT((ch * 2) + source)
23 #define AD5766_DITHER_SCALE_MASK(x) AD5766_DITHER_SOURCE_MASK(x)
24 #define AD5766_DITHER_SCALE(ch, scale) (scale << (ch * 2))
25 #define AD5766_DITHER_ENABLE_MASK(ch) BIT(ch)
26 #define AD5766_DITHER_ENABLE(ch, state) ((!state) << ch)
27 #define AD5766_DITHER_INVERT_MASK(ch) BIT(ch)
28 #define AD5766_DITHER_INVERT(ch, state) (state << ch)
29
30 #define AD5766_CMD_NOP_MUX_OUT 0x00
31 #define AD5766_CMD_SDO_CNTRL 0x01
32 #define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))
33 #define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))
34 #define AD5766_CMD_SW_LDAC 0x30
35 #define AD5766_CMD_SPAN_REG 0x40
36 #define AD5766_CMD_WR_PWR_DITHER 0x51
37 #define AD5766_CMD_WR_DAC_REG_ALL 0x60
38 #define AD5766_CMD_SW_FULL_RESET 0x70
39 #define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))
40 #define AD5766_CMD_DITHER_SIG_1 0x90
41 #define AD5766_CMD_DITHER_SIG_2 0xA0
42 #define AD5766_CMD_INV_DITHER 0xB0
43 #define AD5766_CMD_DITHER_SCALE_1 0xC0
44 #define AD5766_CMD_DITHER_SCALE_2 0xD0
45
46 #define AD5766_FULL_RESET_CODE 0x1234
47
48 enum ad5766_type {
49 ID_AD5766,
50 ID_AD5767,
51 };
52
53 enum ad5766_voltage_range {
54 AD5766_VOLTAGE_RANGE_M20V_0V,
55 AD5766_VOLTAGE_RANGE_M16V_to_0V,
56 AD5766_VOLTAGE_RANGE_M10V_to_0V,
57 AD5766_VOLTAGE_RANGE_M12V_to_14V,
58 AD5766_VOLTAGE_RANGE_M16V_to_10V,
59 AD5766_VOLTAGE_RANGE_M10V_to_6V,
60 AD5766_VOLTAGE_RANGE_M5V_to_5V,
61 AD5766_VOLTAGE_RANGE_M10V_to_10V,
62 };
63
64 /**
65 * struct ad5766_chip_info - chip specific information
66 * @num_channels: number of channels
67 * @channels: channel specification
68 */
69 struct ad5766_chip_info {
70 unsigned int num_channels;
71 const struct iio_chan_spec *channels;
72 };
73
74 enum {
75 AD5766_DITHER_ENABLE,
76 AD5766_DITHER_INVERT,
77 AD5766_DITHER_SOURCE,
78 };
79
80 /*
81 * Dither signal can also be scaled.
82 * Available dither scale strings corresponding to "dither_scale" field in
83 * "struct ad5766_state".
84 */
85 static const char * const ad5766_dither_scales[] = {
86 "1",
87 "0.75",
88 "0.5",
89 "0.25",
90 };
91
92 /**
93 * struct ad5766_state - driver instance specific data
94 * @spi: SPI device
95 * @lock: Lock used to restrict concurrent access to SPI device
96 * @chip_info: Chip model specific constants
97 * @gpio_reset: Reset GPIO, used to reset the device
98 * @crt_range: Current selected output range
99 * @dither_enable: Power enable bit for each channel dither block (for
100 * example, D15 = DAC 15,D8 = DAC 8, and D0 = DAC 0)
101 * 0 - Normal operation, 1 - Power down
102 * @dither_invert: Inverts the dither signal applied to the selected DAC
103 * outputs
104 * @dither_source: Selects between 2 possible sources:
105 * 1: N0, 2: N1
106 * Two bits are used for each channel
107 * @dither_scale: Two bits are used for each of the 16 channels:
108 * 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
109 * 3: 0.25 SCALING.
110 * @data: SPI transfer buffers
111 */
112 struct ad5766_state {
113 struct spi_device *spi;
114 struct mutex lock;
115 const struct ad5766_chip_info *chip_info;
116 struct gpio_desc *gpio_reset;
117 enum ad5766_voltage_range crt_range;
118 u16 dither_enable;
119 u16 dither_invert;
120 u32 dither_source;
121 u32 dither_scale;
122 union {
123 u32 d32;
124 u16 w16[2];
125 u8 b8[4];
126 } data[3] __aligned(IIO_DMA_MINALIGN);
127 };
128
129 struct ad5766_span_tbl {
130 int min;
131 int max;
132 };
133
134 static const struct ad5766_span_tbl ad5766_span_tbl[] = {
135 [AD5766_VOLTAGE_RANGE_M20V_0V] = {-20, 0},
136 [AD5766_VOLTAGE_RANGE_M16V_to_0V] = {-16, 0},
137 [AD5766_VOLTAGE_RANGE_M10V_to_0V] = {-10, 0},
138 [AD5766_VOLTAGE_RANGE_M12V_to_14V] = {-12, 14},
139 [AD5766_VOLTAGE_RANGE_M16V_to_10V] = {-16, 10},
140 [AD5766_VOLTAGE_RANGE_M10V_to_6V] = {-10, 6},
141 [AD5766_VOLTAGE_RANGE_M5V_to_5V] = {-5, 5},
142 [AD5766_VOLTAGE_RANGE_M10V_to_10V] = {-10, 10},
143 };
144
__ad5766_spi_read(struct ad5766_state * st,u8 dac,int * val)145 static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val)
146 {
147 int ret;
148 struct spi_transfer xfers[] = {
149 {
150 .tx_buf = &st->data[0].d32,
151 .len = 3,
152 .cs_change = 1,
153 }, {
154 .tx_buf = &st->data[1].d32,
155 .rx_buf = &st->data[2].d32,
156 .len = 3,
157 },
158 };
159
160 st->data[0].d32 = AD5766_CMD_READBACK_REG(dac);
161 st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT;
162
163 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
164 if (ret)
165 return ret;
166
167 *val = st->data[2].w16[1];
168
169 return ret;
170 }
171
__ad5766_spi_write(struct ad5766_state * st,u8 command,u16 data)172 static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data)
173 {
174 st->data[0].b8[0] = command;
175 put_unaligned_be16(data, &st->data[0].b8[1]);
176
177 return spi_write(st->spi, &st->data[0].b8[0], 3);
178 }
179
ad5766_read(struct iio_dev * indio_dev,u8 dac,int * val)180 static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val)
181 {
182 struct ad5766_state *st = iio_priv(indio_dev);
183 int ret;
184
185 mutex_lock(&st->lock);
186 ret = __ad5766_spi_read(st, dac, val);
187 mutex_unlock(&st->lock);
188
189 return ret;
190 }
191
ad5766_write(struct iio_dev * indio_dev,u8 dac,u16 data)192 static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data)
193 {
194 struct ad5766_state *st = iio_priv(indio_dev);
195 int ret;
196
197 mutex_lock(&st->lock);
198 ret = __ad5766_spi_write(st, AD5766_CMD_WR_DAC_REG(dac), data);
199 mutex_unlock(&st->lock);
200
201 return ret;
202 }
203
ad5766_reset(struct ad5766_state * st)204 static int ad5766_reset(struct ad5766_state *st)
205 {
206 int ret;
207
208 if (st->gpio_reset) {
209 gpiod_set_value_cansleep(st->gpio_reset, 1);
210 ndelay(100); /* t_reset >= 100ns */
211 gpiod_set_value_cansleep(st->gpio_reset, 0);
212 } else {
213 ret = __ad5766_spi_write(st, AD5766_CMD_SW_FULL_RESET,
214 AD5766_FULL_RESET_CODE);
215 if (ret < 0)
216 return ret;
217 }
218
219 /*
220 * Minimum time between a reset and the subsequent successful write is
221 * typically 25 ns
222 */
223 ndelay(25);
224
225 return 0;
226 }
227
ad5766_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)228 static int ad5766_read_raw(struct iio_dev *indio_dev,
229 struct iio_chan_spec const *chan,
230 int *val,
231 int *val2,
232 long m)
233 {
234 struct ad5766_state *st = iio_priv(indio_dev);
235 int ret;
236
237 switch (m) {
238 case IIO_CHAN_INFO_RAW:
239 ret = ad5766_read(indio_dev, chan->address, val);
240 if (ret)
241 return ret;
242
243 return IIO_VAL_INT;
244 case IIO_CHAN_INFO_OFFSET:
245 *val = ad5766_span_tbl[st->crt_range].min;
246
247 return IIO_VAL_INT;
248 case IIO_CHAN_INFO_SCALE:
249 *val = ad5766_span_tbl[st->crt_range].max -
250 ad5766_span_tbl[st->crt_range].min;
251 *val2 = st->chip_info->channels[0].scan_type.realbits;
252
253 return IIO_VAL_FRACTIONAL_LOG2;
254 default:
255 return -EINVAL;
256 }
257 }
258
ad5766_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)259 static int ad5766_write_raw(struct iio_dev *indio_dev,
260 struct iio_chan_spec const *chan,
261 int val,
262 int val2,
263 long info)
264 {
265 switch (info) {
266 case IIO_CHAN_INFO_RAW:
267 {
268 const int max_val = GENMASK(chan->scan_type.realbits - 1, 0);
269
270 if (val > max_val || val < 0)
271 return -EINVAL;
272 val <<= chan->scan_type.shift;
273 return ad5766_write(indio_dev, chan->address, val);
274 }
275 default:
276 return -EINVAL;
277 }
278 }
279
280 static const struct iio_info ad5766_info = {
281 .read_raw = ad5766_read_raw,
282 .write_raw = ad5766_write_raw,
283 };
284
ad5766_get_dither_source(struct iio_dev * dev,const struct iio_chan_spec * chan)285 static int ad5766_get_dither_source(struct iio_dev *dev,
286 const struct iio_chan_spec *chan)
287 {
288 struct ad5766_state *st = iio_priv(dev);
289 u32 source;
290
291 source = st->dither_source & AD5766_DITHER_SOURCE_MASK(chan->channel);
292 source = source >> (chan->channel * 2);
293 source -= 1;
294
295 return source;
296 }
297
ad5766_set_dither_source(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int source)298 static int ad5766_set_dither_source(struct iio_dev *dev,
299 const struct iio_chan_spec *chan,
300 unsigned int source)
301 {
302 struct ad5766_state *st = iio_priv(dev);
303 uint16_t val;
304 int ret;
305
306 st->dither_source &= ~AD5766_DITHER_SOURCE_MASK(chan->channel);
307 st->dither_source |= AD5766_DITHER_SOURCE(chan->channel, source);
308
309 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
310 ret = ad5766_write(dev, AD5766_CMD_DITHER_SIG_1, val);
311 if (ret)
312 return ret;
313
314 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
315
316 return ad5766_write(dev, AD5766_CMD_DITHER_SIG_2, val);
317 }
318
ad5766_get_dither_scale(struct iio_dev * dev,const struct iio_chan_spec * chan)319 static int ad5766_get_dither_scale(struct iio_dev *dev,
320 const struct iio_chan_spec *chan)
321 {
322 struct ad5766_state *st = iio_priv(dev);
323 u32 scale;
324
325 scale = st->dither_scale & AD5766_DITHER_SCALE_MASK(chan->channel);
326
327 return (scale >> (chan->channel * 2));
328 }
329
ad5766_set_dither_scale(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int scale)330 static int ad5766_set_dither_scale(struct iio_dev *dev,
331 const struct iio_chan_spec *chan,
332 unsigned int scale)
333 {
334 int ret;
335 struct ad5766_state *st = iio_priv(dev);
336 uint16_t val;
337
338 st->dither_scale &= ~AD5766_DITHER_SCALE_MASK(chan->channel);
339 st->dither_scale |= AD5766_DITHER_SCALE(chan->channel, scale);
340
341 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
342 ret = ad5766_write(dev, AD5766_CMD_DITHER_SCALE_1, val);
343 if (ret)
344 return ret;
345 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
346
347 return ad5766_write(dev, AD5766_CMD_DITHER_SCALE_2, val);
348 }
349
350 static const struct iio_enum ad5766_dither_scale_enum = {
351 .items = ad5766_dither_scales,
352 .num_items = ARRAY_SIZE(ad5766_dither_scales),
353 .set = ad5766_set_dither_scale,
354 .get = ad5766_get_dither_scale,
355 };
356
ad5766_read_ext(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)357 static ssize_t ad5766_read_ext(struct iio_dev *indio_dev,
358 uintptr_t private,
359 const struct iio_chan_spec *chan,
360 char *buf)
361 {
362 struct ad5766_state *st = iio_priv(indio_dev);
363
364 switch (private) {
365 case AD5766_DITHER_ENABLE:
366 return sprintf(buf, "%u\n",
367 !(st->dither_enable & BIT(chan->channel)));
368 break;
369 case AD5766_DITHER_INVERT:
370 return sprintf(buf, "%u\n",
371 !!(st->dither_invert & BIT(chan->channel)));
372 break;
373 case AD5766_DITHER_SOURCE:
374 return sprintf(buf, "%d\n",
375 ad5766_get_dither_source(indio_dev, chan));
376 default:
377 return -EINVAL;
378 }
379 }
380
ad5766_write_ext(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)381 static ssize_t ad5766_write_ext(struct iio_dev *indio_dev,
382 uintptr_t private,
383 const struct iio_chan_spec *chan,
384 const char *buf, size_t len)
385 {
386 struct ad5766_state *st = iio_priv(indio_dev);
387 bool readin;
388 int ret;
389
390 ret = kstrtobool(buf, &readin);
391 if (ret)
392 return ret;
393
394 switch (private) {
395 case AD5766_DITHER_ENABLE:
396 st->dither_enable &= ~AD5766_DITHER_ENABLE_MASK(chan->channel);
397 st->dither_enable |= AD5766_DITHER_ENABLE(chan->channel,
398 readin);
399 ret = ad5766_write(indio_dev, AD5766_CMD_WR_PWR_DITHER,
400 st->dither_enable);
401 break;
402 case AD5766_DITHER_INVERT:
403 st->dither_invert &= ~AD5766_DITHER_INVERT_MASK(chan->channel);
404 st->dither_invert |= AD5766_DITHER_INVERT(chan->channel,
405 readin);
406 ret = ad5766_write(indio_dev, AD5766_CMD_INV_DITHER,
407 st->dither_invert);
408 break;
409 case AD5766_DITHER_SOURCE:
410 ret = ad5766_set_dither_source(indio_dev, chan, readin);
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 return ret ? ret : len;
417 }
418
419 #define _AD5766_CHAN_EXT_INFO(_name, _what, _shared) { \
420 .name = _name, \
421 .read = ad5766_read_ext, \
422 .write = ad5766_write_ext, \
423 .private = _what, \
424 .shared = _shared, \
425 }
426
427 static const struct iio_chan_spec_ext_info ad5766_ext_info[] = {
428
429 _AD5766_CHAN_EXT_INFO("dither_enable", AD5766_DITHER_ENABLE,
430 IIO_SEPARATE),
431 _AD5766_CHAN_EXT_INFO("dither_invert", AD5766_DITHER_INVERT,
432 IIO_SEPARATE),
433 _AD5766_CHAN_EXT_INFO("dither_source", AD5766_DITHER_SOURCE,
434 IIO_SEPARATE),
435 IIO_ENUM("dither_scale", IIO_SEPARATE, &ad5766_dither_scale_enum),
436 IIO_ENUM_AVAILABLE("dither_scale", IIO_SEPARATE,
437 &ad5766_dither_scale_enum),
438 { }
439 };
440
441 #define AD576x_CHANNEL(_chan, _bits) { \
442 .type = IIO_VOLTAGE, \
443 .indexed = 1, \
444 .output = 1, \
445 .channel = (_chan), \
446 .address = (_chan), \
447 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
448 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
449 BIT(IIO_CHAN_INFO_SCALE), \
450 .scan_index = (_chan), \
451 .scan_type = { \
452 .sign = 'u', \
453 .realbits = (_bits), \
454 .storagebits = 16, \
455 .shift = 16 - (_bits), \
456 }, \
457 .ext_info = ad5766_ext_info, \
458 }
459
460 #define DECLARE_AD576x_CHANNELS(_name, _bits) \
461 const struct iio_chan_spec _name[] = { \
462 AD576x_CHANNEL(0, (_bits)), \
463 AD576x_CHANNEL(1, (_bits)), \
464 AD576x_CHANNEL(2, (_bits)), \
465 AD576x_CHANNEL(3, (_bits)), \
466 AD576x_CHANNEL(4, (_bits)), \
467 AD576x_CHANNEL(5, (_bits)), \
468 AD576x_CHANNEL(6, (_bits)), \
469 AD576x_CHANNEL(7, (_bits)), \
470 AD576x_CHANNEL(8, (_bits)), \
471 AD576x_CHANNEL(9, (_bits)), \
472 AD576x_CHANNEL(10, (_bits)), \
473 AD576x_CHANNEL(11, (_bits)), \
474 AD576x_CHANNEL(12, (_bits)), \
475 AD576x_CHANNEL(13, (_bits)), \
476 AD576x_CHANNEL(14, (_bits)), \
477 AD576x_CHANNEL(15, (_bits)), \
478 }
479
480 static DECLARE_AD576x_CHANNELS(ad5766_channels, 16);
481 static DECLARE_AD576x_CHANNELS(ad5767_channels, 12);
482
483 static const struct ad5766_chip_info ad5766_chip_infos[] = {
484 [ID_AD5766] = {
485 .num_channels = ARRAY_SIZE(ad5766_channels),
486 .channels = ad5766_channels,
487 },
488 [ID_AD5767] = {
489 .num_channels = ARRAY_SIZE(ad5767_channels),
490 .channels = ad5767_channels,
491 },
492 };
493
ad5766_get_output_range(struct ad5766_state * st)494 static int ad5766_get_output_range(struct ad5766_state *st)
495 {
496 int i, ret, min, max, tmp[2];
497
498 ret = device_property_read_u32_array(&st->spi->dev,
499 "output-range-microvolts",
500 tmp, 2);
501 if (ret)
502 return ret;
503
504 min = tmp[0] / 1000000;
505 max = tmp[1] / 1000000;
506 for (i = 0; i < ARRAY_SIZE(ad5766_span_tbl); i++) {
507 if (ad5766_span_tbl[i].min != min ||
508 ad5766_span_tbl[i].max != max)
509 continue;
510
511 st->crt_range = i;
512
513 return 0;
514 }
515
516 return -EINVAL;
517 }
518
ad5766_default_setup(struct ad5766_state * st)519 static int ad5766_default_setup(struct ad5766_state *st)
520 {
521 uint16_t val;
522 int ret, i;
523
524 /* Always issue a reset before writing to the span register. */
525 ret = ad5766_reset(st);
526 if (ret)
527 return ret;
528
529 ret = ad5766_get_output_range(st);
530 if (ret)
531 return ret;
532
533 /* Dither power down */
534 st->dither_enable = GENMASK(15, 0);
535 ret = __ad5766_spi_write(st, AD5766_CMD_WR_PWR_DITHER,
536 st->dither_enable);
537 if (ret)
538 return ret;
539
540 st->dither_source = 0;
541 for (i = 0; i < ARRAY_SIZE(ad5766_channels); i++)
542 st->dither_source |= AD5766_DITHER_SOURCE(i, 0);
543 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
544 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_1, val);
545 if (ret)
546 return ret;
547
548 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
549 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_2, val);
550 if (ret)
551 return ret;
552
553 st->dither_scale = 0;
554 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
555 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_1, val);
556 if (ret)
557 return ret;
558
559 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
560 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_2, val);
561 if (ret)
562 return ret;
563
564 st->dither_invert = 0;
565 ret = __ad5766_spi_write(st, AD5766_CMD_INV_DITHER, st->dither_invert);
566 if (ret)
567 return ret;
568
569 return __ad5766_spi_write(st, AD5766_CMD_SPAN_REG, st->crt_range);
570 }
571
ad5766_trigger_handler(int irq,void * p)572 static irqreturn_t ad5766_trigger_handler(int irq, void *p)
573 {
574 struct iio_poll_func *pf = p;
575 struct iio_dev *indio_dev = pf->indio_dev;
576 struct iio_buffer *buffer = indio_dev->buffer;
577 struct ad5766_state *st = iio_priv(indio_dev);
578 int ret, ch, i;
579 u16 data[ARRAY_SIZE(ad5766_channels)];
580
581 ret = iio_pop_from_buffer(buffer, data);
582 if (ret)
583 goto done;
584
585 i = 0;
586 mutex_lock(&st->lock);
587 for_each_set_bit(ch, indio_dev->active_scan_mask,
588 st->chip_info->num_channels - 1)
589 __ad5766_spi_write(st, AD5766_CMD_WR_IN_REG(ch), data[i++]);
590
591 __ad5766_spi_write(st, AD5766_CMD_SW_LDAC,
592 *indio_dev->active_scan_mask);
593 mutex_unlock(&st->lock);
594
595 done:
596 iio_trigger_notify_done(indio_dev->trig);
597
598 return IRQ_HANDLED;
599 }
600
ad5766_probe(struct spi_device * spi)601 static int ad5766_probe(struct spi_device *spi)
602 {
603 enum ad5766_type type;
604 struct iio_dev *indio_dev;
605 struct ad5766_state *st;
606 int ret;
607
608 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
609 if (!indio_dev)
610 return -ENOMEM;
611
612 st = iio_priv(indio_dev);
613 mutex_init(&st->lock);
614
615 st->spi = spi;
616 type = spi_get_device_id(spi)->driver_data;
617 st->chip_info = &ad5766_chip_infos[type];
618
619 indio_dev->channels = st->chip_info->channels;
620 indio_dev->num_channels = st->chip_info->num_channels;
621 indio_dev->info = &ad5766_info;
622 indio_dev->name = spi_get_device_id(spi)->name;
623 indio_dev->modes = INDIO_DIRECT_MODE;
624
625 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
626 GPIOD_OUT_LOW);
627 if (IS_ERR(st->gpio_reset))
628 return PTR_ERR(st->gpio_reset);
629
630 ret = ad5766_default_setup(st);
631 if (ret)
632 return ret;
633
634 /* Configure trigger buffer */
635 ret = devm_iio_triggered_buffer_setup_ext(&spi->dev, indio_dev, NULL,
636 ad5766_trigger_handler,
637 IIO_BUFFER_DIRECTION_OUT,
638 NULL,
639 NULL);
640 if (ret)
641 return ret;
642
643 return devm_iio_device_register(&spi->dev, indio_dev);
644 }
645
646 static const struct of_device_id ad5766_dt_match[] = {
647 { .compatible = "adi,ad5766" },
648 { .compatible = "adi,ad5767" },
649 { }
650 };
651 MODULE_DEVICE_TABLE(of, ad5766_dt_match);
652
653 static const struct spi_device_id ad5766_spi_ids[] = {
654 { "ad5766", ID_AD5766 },
655 { "ad5767", ID_AD5767 },
656 { }
657 };
658 MODULE_DEVICE_TABLE(spi, ad5766_spi_ids);
659
660 static struct spi_driver ad5766_driver = {
661 .driver = {
662 .name = "ad5766",
663 .of_match_table = ad5766_dt_match,
664 },
665 .probe = ad5766_probe,
666 .id_table = ad5766_spi_ids,
667 };
668 module_spi_driver(ad5766_driver);
669
670 MODULE_AUTHOR("Denis-Gabriel Gheorghescu <denis.gheorghescu@analog.com>");
671 MODULE_DESCRIPTION("Analog Devices AD5766/AD5767 DACs");
672 MODULE_LICENSE("GPL v2");
673