1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_CONFIG_H 9 #define __NET_TI_ICSSG_CONFIG_H 10 11 struct icssg_buffer_pool_cfg { 12 __le32 addr; 13 __le32 len; 14 } __packed; 15 16 struct icssg_flow_cfg { 17 __le16 rx_base_flow; 18 __le16 mgm_base_flow; 19 } __packed; 20 21 #define PRUETH_PKT_TYPE_CMD 0x10 22 #define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ 23 #define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ 24 #define PRUETH_MAX_TX_DESC 512 25 #define PRUETH_MAX_RX_DESC 512 26 #define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ 27 #define PRUETH_RX_FLOW_DATA 0 28 29 /* Defines for forwarding path buffer pools: 30 * - used by firmware to store packets to be forwarded to other port 31 * - 8 total pools per slice 32 * - only used in switch mode (as no forwarding in mac mode) 33 */ 34 #define PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE 8 35 #define PRUETH_SW_FWD_BUF_POOL_SIZE (SZ_8K) 36 37 /* Defines for local injection path buffer pools: 38 * - used by firmware to store packets received from host core 39 * - 16 total pools per slice 40 * - 8 pools per port per slice and each slice handles both ports 41 * - only 4 out of 8 pools used per port (as only 4 real QoS levels in ICSSG) 42 * - switch mode: 8 total pools used 43 * - mac mode: 4 total pools used 44 */ 45 #define PRUETH_NUM_LI_BUF_POOLS_PER_SLICE 16 46 #define PRUETH_NUM_LI_BUF_POOLS_PER_PORT_PER_SLICE 8 47 #define PRUETH_SW_LI_BUF_POOL_SIZE SZ_4K 48 #define PRUETH_SW_USED_LI_BUF_POOLS_PER_SLICE 8 49 #define PRUETH_SW_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE 4 50 #define PRUETH_EMAC_LI_BUF_POOL_SIZE SZ_8K 51 #define PRUETH_EMAC_USED_LI_BUF_POOLS_PER_SLICE 4 52 #define PRUETH_EMAC_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE 4 53 54 /* Defines for host egress path - express and preemptible buffers 55 * - used by firmware to store express and preemptible packets 56 * to be transmitted to host core 57 * - used by both mac/switch modes 58 */ 59 #define PRUETH_SW_HOST_EXP_BUF_POOL_SIZE SZ_16K 60 #define PRUETH_SW_HOST_PRE_BUF_POOL_SIZE (SZ_16K - SZ_2K) 61 #define PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE PRUETH_SW_HOST_EXP_BUF_POOL_SIZE 62 #define PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE PRUETH_SW_HOST_PRE_BUF_POOL_SIZE 63 64 /* Buffer used by firmware to temporarily store packet to be dropped */ 65 #define PRUETH_SW_DROP_PKT_BUF_SIZE SZ_2K 66 #define PRUETH_EMAC_DROP_PKT_BUF_SIZE PRUETH_SW_DROP_PKT_BUF_SIZE 67 68 /* Total switch mode memory usage for buffers per slice */ 69 #define PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE \ 70 (PRUETH_SW_FWD_BUF_POOL_SIZE * PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE + \ 71 PRUETH_SW_LI_BUF_POOL_SIZE * PRUETH_SW_USED_LI_BUF_POOLS_PER_SLICE + \ 72 PRUETH_SW_HOST_EXP_BUF_POOL_SIZE + \ 73 PRUETH_SW_HOST_PRE_BUF_POOL_SIZE + \ 74 PRUETH_SW_DROP_PKT_BUF_SIZE) 75 76 /* Total switch mode memory usage for all buffers */ 77 #define PRUETH_SW_TOTAL_BUF_SIZE \ 78 (2 * PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE) 79 80 /* Total mac mode memory usage for buffers per slice */ 81 #define PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE \ 82 (PRUETH_EMAC_LI_BUF_POOL_SIZE * \ 83 PRUETH_EMAC_USED_LI_BUF_POOLS_PER_SLICE + \ 84 PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE + \ 85 PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE + \ 86 PRUETH_EMAC_DROP_PKT_BUF_SIZE) 87 88 /* Total mac mode memory usage for all buffers */ 89 #define PRUETH_EMAC_TOTAL_BUF_SIZE \ 90 (2 * PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE) 91 92 /* Size of 1 bank of MSMC/OC_SRAM memory */ 93 #define MSMC_RAM_BANK_SIZE SZ_256K 94 95 #define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1) 96 97 struct icssg_rxq_ctx { 98 __le32 start[3]; 99 __le32 end; 100 } __packed; 101 102 /* Load time Fiwmware Configuration */ 103 104 #define ICSSG_FW_MGMT_CMD_HEADER 0x81 105 #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 106 #define ICSSG_FW_MGMT_CMD_TYPE 0x04 107 #define ICSSG_FW_MGMT_PKT 0x80000000 108 #define ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW 0x05 109 110 struct icssg_r30_cmd { 111 u32 cmd[4]; 112 } __packed; 113 114 enum icssg_port_state_cmd { 115 ICSSG_EMAC_PORT_DISABLE = 0, 116 ICSSG_EMAC_PORT_BLOCK, 117 ICSSG_EMAC_PORT_FORWARD, 118 ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, 119 ICSSG_EMAC_PORT_ACCEPT_ALL, 120 ICSSG_EMAC_PORT_ACCEPT_TAGGED, 121 ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, 122 ICSSG_EMAC_PORT_TAS_TRIGGER, 123 ICSSG_EMAC_PORT_TAS_ENABLE, 124 ICSSG_EMAC_PORT_TAS_RESET, 125 ICSSG_EMAC_PORT_TAS_DISABLE, 126 ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, 127 ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, 128 ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, 129 ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, 130 ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, 131 ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, 132 ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE, 133 ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE, 134 ICSSG_EMAC_HSR_RX_OFFLOAD_ENABLE, 135 ICSSG_EMAC_HSR_RX_OFFLOAD_DISABLE, 136 ICSSG_EMAC_PORT_MAX_COMMANDS 137 }; 138 139 #define EMAC_NONE 0xffff0000 140 #define EMAC_PRU0_P_DI 0xffff0004 141 #define EMAC_PRU1_P_DI 0xffff0040 142 #define EMAC_TX_P_DI 0xffff0100 143 144 #define EMAC_PRU0_P_EN 0xfffb0000 145 #define EMAC_PRU1_P_EN 0xffbf0000 146 #define EMAC_TX_P_EN 0xfeff0000 147 148 #define EMAC_P_BLOCK 0xffff0040 149 #define EMAC_TX_P_BLOCK 0xffff0200 150 #define EMAC_P_UNBLOCK 0xffbf0000 151 #define EMAC_TX_P_UNBLOCK 0xfdff0000 152 #define EMAC_LEAN_EN 0xfff70000 153 #define EMAC_LEAN_DI 0xffff0008 154 155 #define EMAC_ACCEPT_ALL 0xffff0001 156 #define EMAC_ACCEPT_TAG 0xfffe0002 157 #define EMAC_ACCEPT_PRIOR 0xfffc0000 158 159 /* Config area lies in DRAM */ 160 #define ICSSG_CONFIG_OFFSET 0x0 161 162 /* Config area lies in shared RAM */ 163 #define ICSSG_CONFIG_OFFSET_SLICE0 0 164 #define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 165 166 #define ICSSG_NUM_NORMAL_PDS 64 167 #define ICSSG_NUM_SPECIAL_PDS 16 168 169 #define ICSSG_NORMAL_PD_SIZE 8 170 #define ICSSG_SPECIAL_PD_SIZE 20 171 172 #define ICSSG_FLAG_MASK 0xff00ffff 173 174 /* SR1.0-specific bits */ 175 #define PRUETH_MAX_RX_FLOWS_SR1 4 /* excluding default flow */ 176 #define PRUETH_RX_FLOW_DATA_SR1 3 /* highest priority flow */ 177 #define PRUETH_MAX_RX_MGM_DESC_SR1 8 178 #define PRUETH_MAX_RX_MGM_FLOWS_SR1 2 /* excluding default flow */ 179 #define PRUETH_RX_MGM_FLOW_RESPONSE_SR1 0 180 #define PRUETH_RX_MGM_FLOW_TIMESTAMP_SR1 1 181 182 #define PRUETH_NUM_BUF_POOLS_SR1 16 183 #define PRUETH_EMAC_BUF_POOL_START_SR1 8 184 #define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1 128 185 #define PRUETH_EMAC_BUF_SIZE_SR1 1536 186 #define PRUETH_EMAC_NUM_BUF_SR1 4 187 #define PRUETH_EMAC_BUF_POOL_SIZE_SR1 (PRUETH_EMAC_NUM_BUF_SR1 * \ 188 PRUETH_EMAC_BUF_SIZE_SR1) 189 #define MSMC_RAM_SIZE_SR1 (SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */ 190 191 struct icssg_sr1_config { 192 __le32 status; /* Firmware status */ 193 __le32 addr_lo; /* MSMC Buffer pool base address low. */ 194 __le32 addr_hi; /* MSMC Buffer pool base address high. Must be 0 */ 195 __le32 tx_buf_sz[16]; /* Array of buffer pool sizes */ 196 __le32 num_tx_threads; /* Number of active egress threads, 1 to 4 */ 197 __le32 tx_rate_lim_en; /* Bitmask: Egress rate limit en per thread */ 198 __le32 rx_flow_id; /* RX flow id for first rx ring */ 199 __le32 rx_mgr_flow_id; /* RX flow id for the first management ring */ 200 __le32 flags; /* TBD */ 201 __le32 n_burst; /* for debug */ 202 __le32 rtu_status; /* RTU status */ 203 __le32 info; /* reserved */ 204 __le32 reserve; 205 __le32 rand_seed; /* Used for the random number generation at fw */ 206 } __packed; 207 208 /* SR1.0 shutdown command to stop processing at firmware. 209 * Command format: 0x8101ss00, where 210 * - ss: sequence number. Currently not used by driver. 211 */ 212 #define ICSSG_SHUTDOWN_CMD_SR1 0x81010000 213 214 /* SR1.0 pstate speed/duplex command to set speed and duplex settings 215 * in firmware. 216 * Command format: 0x8102ssPN, where 217 * - ss: sequence number. Currently not used by driver. 218 * - P: port number (for switch mode). 219 * - N: Speed/Duplex state: 220 * 0x0 - 10Mbps/Half duplex; 221 * 0x8 - 10Mbps/Full duplex; 222 * 0x2 - 100Mbps/Half duplex; 223 * 0xa - 100Mbps/Full duplex; 224 * 0xc - 1Gbps/Full duplex; 225 * NOTE: The above are the same value as bits [3..1](slice 0) 226 * or bits [7..5](slice 1) of RGMII CFG register. 227 */ 228 #define ICSSG_PSTATE_SPEED_DUPLEX_CMD_SR1 0x81020000 229 230 struct icssg_setclock_desc { 231 u8 request; 232 u8 restore; 233 u8 acknowledgment; 234 u8 cmp_status; 235 u32 margin; 236 u32 cyclecounter0_set; 237 u32 cyclecounter1_set; 238 u32 iepcount_set; 239 u32 rsvd1; 240 u32 rsvd2; 241 u32 CMP0_current; 242 u32 iepcount_current; 243 u32 difference; 244 u32 cyclecounter0_new; 245 u32 cyclecounter1_new; 246 u32 CMP0_new; 247 } __packed; 248 249 #define ICSSG_CMD_POP_SLICE0 56 250 #define ICSSG_CMD_POP_SLICE1 60 251 252 #define ICSSG_CMD_PUSH_SLICE0 57 253 #define ICSSG_CMD_PUSH_SLICE1 61 254 255 #define ICSSG_RSP_POP_SLICE0 58 256 #define ICSSG_RSP_POP_SLICE1 62 257 258 #define ICSSG_RSP_PUSH_SLICE0 56 259 #define ICSSG_RSP_PUSH_SLICE1 60 260 261 #define ICSSG_TS_POP_SLICE0 59 262 #define ICSSG_TS_POP_SLICE1 63 263 264 #define ICSSG_TS_PUSH_SLICE0 40 265 #define ICSSG_TS_PUSH_SLICE1 41 266 267 struct mgmt_cmd { 268 u8 param; 269 u8 seqnum; 270 u8 type; 271 u8 header; 272 u32 cmd_args[3]; 273 }; 274 275 struct mgmt_cmd_rsp { 276 u32 reserved; 277 u8 status; 278 u8 seqnum; 279 u8 type; 280 u8 header; 281 u32 cmd_args[3]; 282 }; 283 284 /* FDB FID_C2 flag definitions */ 285 /* Indicates host port membership.*/ 286 #define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0) 287 /* Indicates that MAC ID is connected to physical port 1 */ 288 #define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1) 289 /* Indicates that MAC ID is connected to physical port 2 */ 290 #define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2) 291 /* Ageable bit is set for learned entries and cleared for static entries */ 292 #define ICSSG_FDB_ENTRY_AGEABLE BIT(3) 293 /* If set for DA then packet is determined to be a special packet */ 294 #define ICSSG_FDB_ENTRY_BLOCK BIT(4) 295 /* If set for DA then the SA from the packet is not learned */ 296 #define ICSSG_FDB_ENTRY_SECURE BIT(5) 297 /* If set, it means packet has been seen recently with source address + FID 298 * matching MAC address/FID of entry 299 */ 300 #define ICSSG_FDB_ENTRY_TOUCHED BIT(6) 301 /* Set if entry is valid */ 302 #define ICSSG_FDB_ENTRY_VALID BIT(7) 303 304 /** 305 * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM 306 * @fid_c1: membership and forwarding rules flag to this table. See 307 * above to defines for bit definitions 308 * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID) 309 */ 310 struct prueth_vlan_tbl { 311 u8 fid_c1; 312 u8 fid; 313 } __packed; 314 315 /** 316 * struct prueth_fdb_slot - Result of FDB slot lookup 317 * @mac: MAC address 318 * @fid: fid to be associated with MAC 319 * @fid_c2: FID_C2 entry for this MAC 320 */ 321 struct prueth_fdb_slot { 322 u8 mac[ETH_ALEN]; 323 u8 fid; 324 u8 fid_c2; 325 } __packed; 326 327 enum icssg_ietfpe_verify_states { 328 ICSSG_IETFPE_STATE_UNKNOWN = 0, 329 ICSSG_IETFPE_STATE_INITIAL, 330 ICSSG_IETFPE_STATE_VERIFYING, 331 ICSSG_IETFPE_STATE_SUCCEEDED, 332 ICSSG_IETFPE_STATE_FAILED, 333 ICSSG_IETFPE_STATE_DISABLED 334 }; 335 #endif /* __NET_TI_ICSSG_CONFIG_H */ 336