1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/arm/mach-vt8500/irq.c
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
7 */
8
9 /*
10 * This file is copied and modified from the original irq.c provided by
11 * Alexey Charkov. Minor changes have been made for Device Tree Support.
12 */
13
14 #include <linux/slab.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/irqchip.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/interrupt.h>
21 #include <linux/bitops.h>
22
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26
27 #include <asm/irq.h>
28 #include <asm/exception.h>
29 #include <asm/mach/irq.h>
30
31 #define VT8500_ICPC_IRQ 0x20
32 #define VT8500_ICPC_FIQ 0x24
33 #define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
34 #define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
35
36 /* ICPC */
37 #define ICPC_MASK 0x3F
38 #define ICPC_ROTATE BIT(6)
39
40 /* IC_DCTR */
41 #define ICDC_IRQ 0x00
42 #define ICDC_FIQ 0x01
43 #define ICDC_DSS0 0x02
44 #define ICDC_DSS1 0x03
45 #define ICDC_DSS2 0x04
46 #define ICDC_DSS3 0x05
47 #define ICDC_DSS4 0x06
48 #define ICDC_DSS5 0x07
49
50 #define VT8500_INT_DISABLE 0
51 #define VT8500_INT_ENABLE BIT(3)
52
53 #define VT8500_TRIGGER_HIGH 0
54 #define VT8500_TRIGGER_RISING BIT(5)
55 #define VT8500_TRIGGER_FALLING BIT(6)
56 #define VT8500_EDGE ( VT8500_TRIGGER_RISING \
57 | VT8500_TRIGGER_FALLING)
58
59 /* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
60 #define VT8500_INTC_MAX 2
61
62 struct vt8500_irq_data {
63 void __iomem *base; /* IO Memory base address */
64 struct irq_domain *domain; /* Domain for this controller */
65 };
66
67 /* Primary interrupt controller data */
68 static struct vt8500_irq_data *primary_intc;
69
vt8500_irq_ack(struct irq_data * d)70 static void vt8500_irq_ack(struct irq_data *d)
71 {
72 struct vt8500_irq_data *priv = d->domain->host_data;
73 void __iomem *base = priv->base;
74 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
75 u32 status = (1 << (d->hwirq & 0x1f));
76
77 writel(status, stat_reg);
78 }
79
vt8500_irq_mask(struct irq_data * d)80 static void vt8500_irq_mask(struct irq_data *d)
81 {
82 struct vt8500_irq_data *priv = d->domain->host_data;
83 void __iomem *base = priv->base;
84 u8 dctr;
85
86 dctr = readb(base + VT8500_ICDC + d->hwirq);
87 dctr &= ~VT8500_INT_ENABLE;
88 writeb(dctr, base + VT8500_ICDC + d->hwirq);
89 }
90
vt8500_irq_unmask(struct irq_data * d)91 static void vt8500_irq_unmask(struct irq_data *d)
92 {
93 struct vt8500_irq_data *priv = d->domain->host_data;
94 void __iomem *base = priv->base;
95 u8 dctr;
96
97 dctr = readb(base + VT8500_ICDC + d->hwirq);
98 dctr |= VT8500_INT_ENABLE;
99 writeb(dctr, base + VT8500_ICDC + d->hwirq);
100 }
101
vt8500_irq_set_type(struct irq_data * d,unsigned int flow_type)102 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
103 {
104 struct vt8500_irq_data *priv = d->domain->host_data;
105 void __iomem *base = priv->base;
106 u8 dctr;
107
108 dctr = readb(base + VT8500_ICDC + d->hwirq);
109 dctr &= ~VT8500_EDGE;
110
111 switch (flow_type) {
112 case IRQF_TRIGGER_LOW:
113 return -EINVAL;
114 case IRQF_TRIGGER_HIGH:
115 dctr |= VT8500_TRIGGER_HIGH;
116 irq_set_handler_locked(d, handle_level_irq);
117 break;
118 case IRQF_TRIGGER_FALLING:
119 dctr |= VT8500_TRIGGER_FALLING;
120 irq_set_handler_locked(d, handle_edge_irq);
121 break;
122 case IRQF_TRIGGER_RISING:
123 dctr |= VT8500_TRIGGER_RISING;
124 irq_set_handler_locked(d, handle_edge_irq);
125 break;
126 }
127 writeb(dctr, base + VT8500_ICDC + d->hwirq);
128
129 return 0;
130 }
131
132 static struct irq_chip vt8500_irq_chip = {
133 .name = "vt8500",
134 .irq_ack = vt8500_irq_ack,
135 .irq_mask = vt8500_irq_mask,
136 .irq_unmask = vt8500_irq_unmask,
137 .irq_set_type = vt8500_irq_set_type,
138 };
139
vt8500_init_irq_hw(void __iomem * base)140 static void __init vt8500_init_irq_hw(void __iomem *base)
141 {
142 u32 i;
143
144 /* Enable rotating priority for IRQ */
145 writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
146 writel(0x00, base + VT8500_ICPC_FIQ);
147
148 /* Disable all interrupts and route them to IRQ */
149 for (i = 0; i < 64; i++)
150 writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
151 }
152
vt8500_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)153 static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
154 irq_hw_number_t hw)
155 {
156 irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
157
158 return 0;
159 }
160
161 static const struct irq_domain_ops vt8500_irq_domain_ops = {
162 .map = vt8500_irq_map,
163 .xlate = irq_domain_xlate_onecell,
164 };
165
vt8500_handle_irq_common(struct vt8500_irq_data * intc)166 static inline void vt8500_handle_irq_common(struct vt8500_irq_data *intc)
167 {
168 unsigned long irqnr = readl_relaxed(intc->base) & 0x3F;
169 unsigned long stat;
170
171 /*
172 * Highest Priority register default = 63, so check that this
173 * is a real interrupt by checking the status register
174 */
175 if (irqnr == 63) {
176 stat = readl_relaxed(intc->base + VT8500_ICIS + 4);
177 if (!(stat & BIT(31)))
178 return;
179 }
180
181 generic_handle_domain_irq(intc->domain, irqnr);
182 }
183
vt8500_handle_irq(struct pt_regs * regs)184 static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
185 {
186 vt8500_handle_irq_common(primary_intc);
187 }
188
vt8500_handle_irq_chained(struct irq_desc * desc)189 static void vt8500_handle_irq_chained(struct irq_desc *desc)
190 {
191 struct irq_domain *d = irq_desc_get_handler_data(desc);
192 struct irq_chip *chip = irq_desc_get_chip(desc);
193 struct vt8500_irq_data *intc = d->host_data;
194
195 chained_irq_enter(chip, desc);
196 vt8500_handle_irq_common(intc);
197 chained_irq_exit(chip, desc);
198 }
199
vt8500_irq_init(struct device_node * node,struct device_node * parent)200 static int __init vt8500_irq_init(struct device_node *node,
201 struct device_node *parent)
202 {
203 struct vt8500_irq_data *intc;
204 int irq, i, ret = 0;
205
206 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
207 if (!intc)
208 return -ENOMEM;
209
210 intc->base = of_iomap(node, 0);
211 if (!intc->base) {
212 pr_err("%s: Unable to map IO memory\n", __func__);
213 ret = -ENOMEM;
214 goto err_free;
215 }
216
217 intc->domain = irq_domain_create_linear(of_fwnode_handle(node), 64,
218 &vt8500_irq_domain_ops, intc);
219 if (!intc->domain) {
220 pr_err("%s: Unable to add irq domain!\n", __func__);
221 ret = -ENOMEM;
222 goto err_unmap;
223 }
224
225 vt8500_init_irq_hw(intc->base);
226
227 pr_info("vt8500-irq: Added interrupt controller\n");
228
229 /* check if this is a chained controller */
230 if (of_irq_count(node) != 0) {
231 for (i = 0; i < of_irq_count(node); i++) {
232 irq = irq_of_parse_and_map(node, i);
233 irq_set_chained_handler_and_data(irq, vt8500_handle_irq_chained,
234 intc);
235 }
236
237 pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
238 } else {
239 primary_intc = intc;
240 set_handle_irq(vt8500_handle_irq);
241 }
242 return 0;
243
244 err_unmap:
245 iounmap(intc->base);
246 err_free:
247 kfree(intc);
248 return ret;
249 }
250
251 IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
252