1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RIIC driver
4 *
5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 */
8
9 /*
10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as
11 * some kind of state machine.
12 *
13 * 1) The main xfer routine kicks off a transmission by putting the start bit
14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
15 * since we need to send the target address + RW bit in every case.
16 *
17 * 2) TIE sends target address + RW bit and selects how to continue.
18 *
19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
20 * are done, we switch over to the transmission done interrupt (TEIE) and mark
21 * the message as completed (includes sending STOP) there.
22 *
23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
24 * needed to start clocking, then we keep receiving until we are done. Note
25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
27 * message to create the final NACK as sketched in the datasheet. This caused
28 * some subtle races (when byte n was processed and byte n+1 was already
29 * waiting), though, and I started with the safe approach.
30 *
31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission
32 * via NAKIE.
33 *
34 * Also check the comments in the interrupt routines for some gory details.
35 */
36
37 #include <linux/bits.h>
38 #include <linux/clk.h>
39 #include <linux/completion.h>
40 #include <linux/err.h>
41 #include <linux/i2c.h>
42 #include <linux/interrupt.h>
43 #include <linux/io.h>
44 #include <linux/iopoll.h>
45 #include <linux/module.h>
46 #include <linux/of.h>
47 #include <linux/platform_device.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/reset.h>
50 #include <linux/time.h>
51
52 #define ICCR1_ICE BIT(7)
53 #define ICCR1_IICRST BIT(6)
54 #define ICCR1_SOWP BIT(4)
55 #define ICCR1_SCLI BIT(1)
56 #define ICCR1_SDAI BIT(0)
57
58 #define ICCR2_BBSY BIT(7)
59 #define ICCR2_SP BIT(3)
60 #define ICCR2_RS BIT(2)
61 #define ICCR2_ST BIT(1)
62
63 #define ICMR1_CKS_MASK GENMASK(6, 4)
64 #define ICMR1_BCWP BIT(3)
65 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
66
67 #define ICMR3_RDRFS BIT(5)
68 #define ICMR3_ACKWP BIT(4)
69 #define ICMR3_ACKBT BIT(3)
70
71 #define ICFER_FMPE BIT(7)
72
73 #define ICIER_TIE BIT(7)
74 #define ICIER_TEIE BIT(6)
75 #define ICIER_RIE BIT(5)
76 #define ICIER_NAKIE BIT(4)
77 #define ICIER_SPIE BIT(3)
78
79 #define ICSR2_NACKF BIT(4)
80
81 #define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */
82
83 #define RIIC_INIT_MSG -1
84
85 enum riic_reg_list {
86 RIIC_ICCR1 = 0,
87 RIIC_ICCR2,
88 RIIC_ICMR1,
89 RIIC_ICMR3,
90 RIIC_ICFER,
91 RIIC_ICSER,
92 RIIC_ICIER,
93 RIIC_ICSR2,
94 RIIC_ICBRL,
95 RIIC_ICBRH,
96 RIIC_ICDRT,
97 RIIC_ICDRR,
98 RIIC_REG_END,
99 };
100
101 struct riic_of_data {
102 const u8 *regs;
103 bool fast_mode_plus;
104 };
105
106 struct riic_dev {
107 void __iomem *base;
108 u8 *buf;
109 struct i2c_msg *msg;
110 int bytes_left;
111 int err;
112 int is_last;
113 const struct riic_of_data *info;
114 struct completion msg_done;
115 struct i2c_adapter adapter;
116 struct clk *clk;
117 struct reset_control *rstc;
118 struct i2c_timings i2c_t;
119 };
120
121 struct riic_irq_desc {
122 int res_num;
123 irq_handler_t isr;
124 char *name;
125 };
126
riic_writeb(struct riic_dev * riic,u8 val,u8 offset)127 static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)
128 {
129 writeb(val, riic->base + riic->info->regs[offset]);
130 }
131
riic_readb(struct riic_dev * riic,u8 offset)132 static inline u8 riic_readb(struct riic_dev *riic, u8 offset)
133 {
134 return readb(riic->base + riic->info->regs[offset]);
135 }
136
riic_clear_set_bit(struct riic_dev * riic,u8 clear,u8 set,u8 reg)137 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
138 {
139 riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg);
140 }
141
riic_bus_barrier(struct riic_dev * riic)142 static int riic_bus_barrier(struct riic_dev *riic)
143 {
144 int ret;
145 u8 val;
146
147 /*
148 * The SDA line can still be low even when BBSY = 0. Therefore, after checking
149 * the BBSY flag, also verify that the SDA and SCL lines are not being held low.
150 */
151 ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val,
152 !(val & ICCR2_BBSY), 10, riic->adapter.timeout);
153 if (ret)
154 return ret;
155
156 if ((riic_readb(riic, RIIC_ICCR1) & (ICCR1_SDAI | ICCR1_SCLI)) !=
157 (ICCR1_SDAI | ICCR1_SCLI))
158 return -EBUSY;
159
160 return 0;
161 }
162
riic_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)163 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
164 {
165 struct riic_dev *riic = i2c_get_adapdata(adap);
166 struct device *dev = adap->dev.parent;
167 unsigned long time_left;
168 int i, ret;
169 u8 start_bit;
170
171 ret = pm_runtime_resume_and_get(dev);
172 if (ret)
173 return ret;
174
175 riic->err = riic_bus_barrier(riic);
176 if (riic->err)
177 goto out;
178
179 reinit_completion(&riic->msg_done);
180
181 riic_writeb(riic, 0, RIIC_ICSR2);
182
183 for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
184 riic->bytes_left = RIIC_INIT_MSG;
185 riic->buf = msgs[i].buf;
186 riic->msg = &msgs[i];
187 riic->is_last = (i == num - 1);
188
189 riic_writeb(riic, ICIER_NAKIE | ICIER_TIE, RIIC_ICIER);
190
191 riic_writeb(riic, start_bit, RIIC_ICCR2);
192
193 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
194 if (time_left == 0)
195 riic->err = -ETIMEDOUT;
196
197 if (riic->err)
198 break;
199
200 start_bit = ICCR2_RS;
201 }
202
203 out:
204 pm_runtime_mark_last_busy(dev);
205 pm_runtime_put_autosuspend(dev);
206
207 return riic->err ?: num;
208 }
209
riic_tdre_isr(int irq,void * data)210 static irqreturn_t riic_tdre_isr(int irq, void *data)
211 {
212 struct riic_dev *riic = data;
213 u8 val;
214
215 if (!riic->bytes_left)
216 return IRQ_NONE;
217
218 if (riic->bytes_left == RIIC_INIT_MSG) {
219 if (riic->msg->flags & I2C_M_RD)
220 /* On read, switch over to receive interrupt */
221 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
222 else
223 /* On write, initialize length */
224 riic->bytes_left = riic->msg->len;
225
226 val = i2c_8bit_addr_from_msg(riic->msg);
227 } else {
228 val = *riic->buf;
229 riic->buf++;
230 riic->bytes_left--;
231 }
232
233 /*
234 * Switch to transmission ended interrupt when done. Do check here
235 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
236 * 0 length then)
237 */
238 if (riic->bytes_left == 0)
239 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
240
241 /*
242 * This acks the TIE interrupt. We get another TIE immediately if our
243 * value could be moved to the shadow shift register right away. So
244 * this must be after updates to ICIER (where we want to disable TIE)!
245 */
246 riic_writeb(riic, val, RIIC_ICDRT);
247
248 return IRQ_HANDLED;
249 }
250
riic_tend_isr(int irq,void * data)251 static irqreturn_t riic_tend_isr(int irq, void *data)
252 {
253 struct riic_dev *riic = data;
254
255 if (riic_readb(riic, RIIC_ICSR2) & ICSR2_NACKF) {
256 /* We got a NACKIE */
257 riic_readb(riic, RIIC_ICDRR); /* dummy read */
258 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
259 riic->err = -ENXIO;
260 } else if (riic->bytes_left) {
261 return IRQ_NONE;
262 }
263
264 if (riic->is_last || riic->err) {
265 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
266 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);
267 } else {
268 /* Transfer is complete, but do not send STOP */
269 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
270 complete(&riic->msg_done);
271 }
272
273 return IRQ_HANDLED;
274 }
275
riic_rdrf_isr(int irq,void * data)276 static irqreturn_t riic_rdrf_isr(int irq, void *data)
277 {
278 struct riic_dev *riic = data;
279
280 if (!riic->bytes_left)
281 return IRQ_NONE;
282
283 if (riic->bytes_left == RIIC_INIT_MSG) {
284 riic->bytes_left = riic->msg->len;
285 riic_readb(riic, RIIC_ICDRR); /* dummy read */
286 return IRQ_HANDLED;
287 }
288
289 if (riic->bytes_left == 1) {
290 /* STOP must come before we set ACKBT! */
291 if (riic->is_last) {
292 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
293 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);
294 }
295
296 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
297
298 } else {
299 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
300 }
301
302 /* Reading acks the RIE interrupt */
303 *riic->buf = riic_readb(riic, RIIC_ICDRR);
304 riic->buf++;
305 riic->bytes_left--;
306
307 return IRQ_HANDLED;
308 }
309
riic_stop_isr(int irq,void * data)310 static irqreturn_t riic_stop_isr(int irq, void *data)
311 {
312 struct riic_dev *riic = data;
313
314 /* read back registers to confirm writes have fully propagated */
315 riic_writeb(riic, 0, RIIC_ICSR2);
316 riic_readb(riic, RIIC_ICSR2);
317 riic_writeb(riic, 0, RIIC_ICIER);
318 riic_readb(riic, RIIC_ICIER);
319
320 complete(&riic->msg_done);
321
322 return IRQ_HANDLED;
323 }
324
riic_func(struct i2c_adapter * adap)325 static u32 riic_func(struct i2c_adapter *adap)
326 {
327 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
328 }
329
330 static const struct i2c_algorithm riic_algo = {
331 .xfer = riic_xfer,
332 .functionality = riic_func,
333 };
334
riic_init_hw(struct riic_dev * riic)335 static int riic_init_hw(struct riic_dev *riic)
336 {
337 int ret;
338 unsigned long rate;
339 unsigned long ns_per_tick;
340 int total_ticks, cks, brl, brh;
341 struct i2c_timings *t = &riic->i2c_t;
342 struct device *dev = riic->adapter.dev.parent;
343 bool fast_mode_plus = riic->info->fast_mode_plus;
344 u32 max_freq = fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ
345 : I2C_MAX_FAST_MODE_FREQ;
346
347 if (t->bus_freq_hz > max_freq)
348 return dev_err_probe(dev, -EINVAL,
349 "unsupported bus speed %uHz (%u max)\n",
350 t->bus_freq_hz, max_freq);
351
352 rate = clk_get_rate(riic->clk);
353
354 /*
355 * Assume the default register settings:
356 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
357 * FER.NFE = 1 (noise circuit enabled)
358 * MR3.NF = 0 (1 cycle of noise filtered out)
359 *
360 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
361 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
362 */
363
364 /*
365 * Determine reference clock rate. We must be able to get the desired
366 * frequency with only 62 clock ticks max (31 high, 31 low).
367 * Aim for a duty of 60% LOW, 40% HIGH.
368 */
369 total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz ?: 1);
370
371 for (cks = 0; cks < 7; cks++) {
372 /*
373 * 60% low time must be less than BRL + 2 + 1
374 * BRL max register value is 0x1F.
375 */
376 brl = ((total_ticks * 6) / 10);
377 if (brl <= (0x1F + 3))
378 break;
379
380 total_ticks = DIV_ROUND_UP(total_ticks, 2);
381 rate /= 2;
382 }
383
384 if (brl > (0x1F + 3))
385 return dev_err_probe(dev, -EINVAL, "invalid speed (%uHz). Too slow.\n",
386 t->bus_freq_hz);
387
388 brh = total_ticks - brl;
389
390 /* Remove automatic clock ticks for sync circuit and NF */
391 if (cks == 0) {
392 brl -= 4;
393 brh -= 4;
394 } else {
395 brl -= 3;
396 brh -= 3;
397 }
398
399 /*
400 * Remove clock ticks for rise and fall times. Convert ns to clock
401 * ticks.
402 */
403 ns_per_tick = NSEC_PER_SEC / rate;
404 brl -= t->scl_fall_ns / ns_per_tick;
405 brh -= t->scl_rise_ns / ns_per_tick;
406
407 /* Adjust for min register values for when SCLE=1 and NFE=1 */
408 if (brl < 1)
409 brl = 1;
410 if (brh < 1)
411 brh = 1;
412
413 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
414 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
415 t->scl_fall_ns / ns_per_tick, t->scl_rise_ns / ns_per_tick, cks, brl, brh);
416
417 ret = pm_runtime_resume_and_get(dev);
418 if (ret)
419 return ret;
420
421 /* Changing the order of accessing IICRST and ICE may break things! */
422 riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1);
423 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
424
425 riic_writeb(riic, ICMR1_CKS(cks), RIIC_ICMR1);
426 riic_writeb(riic, brh | ICBR_RESERVED, RIIC_ICBRH);
427 riic_writeb(riic, brl | ICBR_RESERVED, RIIC_ICBRL);
428
429 riic_writeb(riic, 0, RIIC_ICSER);
430 riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);
431
432 if (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
433 riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER);
434
435 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
436
437 pm_runtime_mark_last_busy(dev);
438 pm_runtime_put_autosuspend(dev);
439 return 0;
440 }
441
442 static const struct riic_irq_desc riic_irqs[] = {
443 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
444 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
445 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
446 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
447 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
448 };
449
riic_i2c_probe(struct platform_device * pdev)450 static int riic_i2c_probe(struct platform_device *pdev)
451 {
452 struct device *dev = &pdev->dev;
453 struct riic_dev *riic;
454 struct i2c_adapter *adap;
455 int i, ret;
456
457 riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL);
458 if (!riic)
459 return -ENOMEM;
460
461 riic->base = devm_platform_ioremap_resource(pdev, 0);
462 if (IS_ERR(riic->base))
463 return PTR_ERR(riic->base);
464
465 riic->clk = devm_clk_get(dev, NULL);
466 if (IS_ERR(riic->clk))
467 return dev_err_probe(dev, PTR_ERR(riic->clk),
468 "missing controller clock");
469
470 riic->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
471 if (IS_ERR(riic->rstc))
472 return dev_err_probe(dev, PTR_ERR(riic->rstc),
473 "failed to acquire deasserted reset\n");
474
475 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
476 int irq;
477
478 irq = platform_get_irq(pdev, riic_irqs[i].res_num);
479 if (irq < 0)
480 return irq;
481
482 ret = devm_request_irq(dev, irq, riic_irqs[i].isr,
483 0, riic_irqs[i].name, riic);
484 if (ret)
485 return dev_err_probe(dev, ret, "failed to request irq %s\n",
486 riic_irqs[i].name);
487 }
488
489 riic->info = of_device_get_match_data(dev);
490
491 adap = &riic->adapter;
492 i2c_set_adapdata(adap, riic);
493 strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
494 adap->owner = THIS_MODULE;
495 adap->algo = &riic_algo;
496 adap->dev.parent = dev;
497 adap->dev.of_node = dev->of_node;
498
499 init_completion(&riic->msg_done);
500
501 i2c_parse_fw_timings(dev, &riic->i2c_t, true);
502
503 /* Default 0 to save power. Can be overridden via sysfs for lower latency. */
504 pm_runtime_set_autosuspend_delay(dev, 0);
505 pm_runtime_use_autosuspend(dev);
506 pm_runtime_enable(dev);
507
508 ret = riic_init_hw(riic);
509 if (ret)
510 goto out;
511
512 ret = i2c_add_adapter(adap);
513 if (ret)
514 goto out;
515
516 platform_set_drvdata(pdev, riic);
517
518 dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz);
519 return 0;
520
521 out:
522 pm_runtime_disable(dev);
523 pm_runtime_dont_use_autosuspend(dev);
524 return ret;
525 }
526
riic_i2c_remove(struct platform_device * pdev)527 static void riic_i2c_remove(struct platform_device *pdev)
528 {
529 struct riic_dev *riic = platform_get_drvdata(pdev);
530 struct device *dev = &pdev->dev;
531 int ret;
532
533 ret = pm_runtime_resume_and_get(dev);
534 if (!ret) {
535 riic_writeb(riic, 0, RIIC_ICIER);
536 pm_runtime_put(dev);
537 }
538 i2c_del_adapter(&riic->adapter);
539 pm_runtime_disable(dev);
540 pm_runtime_dont_use_autosuspend(dev);
541 }
542
543 static const u8 riic_rz_a_regs[RIIC_REG_END] = {
544 [RIIC_ICCR1] = 0x00,
545 [RIIC_ICCR2] = 0x04,
546 [RIIC_ICMR1] = 0x08,
547 [RIIC_ICMR3] = 0x10,
548 [RIIC_ICFER] = 0x14,
549 [RIIC_ICSER] = 0x18,
550 [RIIC_ICIER] = 0x1c,
551 [RIIC_ICSR2] = 0x24,
552 [RIIC_ICBRL] = 0x34,
553 [RIIC_ICBRH] = 0x38,
554 [RIIC_ICDRT] = 0x3c,
555 [RIIC_ICDRR] = 0x40,
556 };
557
558 static const struct riic_of_data riic_rz_a_info = {
559 .regs = riic_rz_a_regs,
560 .fast_mode_plus = true,
561 };
562
563 static const struct riic_of_data riic_rz_a1h_info = {
564 .regs = riic_rz_a_regs,
565 };
566
567 static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
568 [RIIC_ICCR1] = 0x00,
569 [RIIC_ICCR2] = 0x01,
570 [RIIC_ICMR1] = 0x02,
571 [RIIC_ICMR3] = 0x04,
572 [RIIC_ICFER] = 0x05,
573 [RIIC_ICSER] = 0x06,
574 [RIIC_ICIER] = 0x07,
575 [RIIC_ICSR2] = 0x09,
576 [RIIC_ICBRL] = 0x10,
577 [RIIC_ICBRH] = 0x11,
578 [RIIC_ICDRT] = 0x12,
579 [RIIC_ICDRR] = 0x13,
580 };
581
582 static const struct riic_of_data riic_rz_v2h_info = {
583 .regs = riic_rz_v2h_regs,
584 .fast_mode_plus = true,
585 };
586
riic_i2c_suspend(struct device * dev)587 static int riic_i2c_suspend(struct device *dev)
588 {
589 struct riic_dev *riic = dev_get_drvdata(dev);
590 int ret;
591
592 ret = pm_runtime_resume_and_get(dev);
593 if (ret)
594 return ret;
595
596 i2c_mark_adapter_suspended(&riic->adapter);
597
598 /* Disable output on SDA, SCL pins. */
599 riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1);
600
601 pm_runtime_mark_last_busy(dev);
602 pm_runtime_put_sync(dev);
603
604 return reset_control_assert(riic->rstc);
605 }
606
riic_i2c_resume(struct device * dev)607 static int riic_i2c_resume(struct device *dev)
608 {
609 struct riic_dev *riic = dev_get_drvdata(dev);
610 int ret;
611
612 ret = reset_control_deassert(riic->rstc);
613 if (ret)
614 return ret;
615
616 ret = riic_init_hw(riic);
617 if (ret) {
618 /*
619 * In case this happens there is no way to recover from this
620 * state. The driver will remain loaded. We want to avoid
621 * keeping the reset line de-asserted for no reason.
622 */
623 reset_control_assert(riic->rstc);
624 return ret;
625 }
626
627 i2c_mark_adapter_resumed(&riic->adapter);
628
629 return 0;
630 }
631
632 static const struct dev_pm_ops riic_i2c_pm_ops = {
633 SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume)
634 };
635
636 static const struct of_device_id riic_i2c_dt_ids[] = {
637 { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
638 { .compatible = "renesas,riic-r7s72100", .data = &riic_rz_a1h_info, },
639 { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
640 { /* Sentinel */ },
641 };
642
643 static struct platform_driver riic_i2c_driver = {
644 .probe = riic_i2c_probe,
645 .remove = riic_i2c_remove,
646 .driver = {
647 .name = "i2c-riic",
648 .of_match_table = riic_i2c_dt_ids,
649 .pm = pm_ptr(&riic_i2c_pm_ops),
650 },
651 };
652
653 module_platform_driver(riic_i2c_driver);
654
655 MODULE_DESCRIPTION("Renesas RIIC adapter");
656 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
657 MODULE_LICENSE("GPL v2");
658 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
659