1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 #define ICE_CHNL_MAX_TC 16 10 11 #include "ice_hw_autogen.h" 12 #include "ice_devids.h" 13 #include "ice_osdep.h" 14 #include "ice_controlq.h" 15 #include "ice_lan_tx_rx.h" 16 #include "ice_flex_type.h" 17 #include "ice_protocol_type.h" 18 #include "ice_sbq_cmd.h" 19 #include "ice_vlan_mode.h" 20 #include <linux/net/intel/libie/fwlog.h> 21 #include <linux/wait.h> 22 #include <net/dscp.h> 23 24 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 25 { 26 return test_bit(tc, &bitmap); 27 } 28 29 static inline u64 round_up_64bit(u64 a, u32 b) 30 { 31 return div64_long(((a) + (b) / 2), (b)); 32 } 33 34 static inline u32 ice_round_to_num(u32 N, u32 R) 35 { 36 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 37 ((((N) + (R) - 1) / (R)) * (R))); 38 } 39 40 /* Driver always calls main vsi_handle first */ 41 #define ICE_MAIN_VSI_HANDLE 0 42 43 /* debug masks - set these bits in hw->debug_mask to control output */ 44 #define ICE_DBG_INIT BIT_ULL(1) 45 #define ICE_DBG_FW_LOG BIT_ULL(3) 46 #define ICE_DBG_LINK BIT_ULL(4) 47 #define ICE_DBG_PHY BIT_ULL(5) 48 #define ICE_DBG_QCTX BIT_ULL(6) 49 #define ICE_DBG_NVM BIT_ULL(7) 50 #define ICE_DBG_LAN BIT_ULL(8) 51 #define ICE_DBG_FLOW BIT_ULL(9) 52 #define ICE_DBG_SW BIT_ULL(13) 53 #define ICE_DBG_SCHED BIT_ULL(14) 54 #define ICE_DBG_RDMA BIT_ULL(15) 55 #define ICE_DBG_PKG BIT_ULL(16) 56 #define ICE_DBG_RES BIT_ULL(17) 57 #define ICE_DBG_PTP BIT_ULL(19) 58 #define ICE_DBG_AQ_MSG BIT_ULL(24) 59 #define ICE_DBG_AQ_DESC BIT_ULL(25) 60 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 61 #define ICE_DBG_AQ_CMD BIT_ULL(27) 62 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 63 ICE_DBG_AQ_DESC | \ 64 ICE_DBG_AQ_DESC_BUF | \ 65 ICE_DBG_AQ_CMD) 66 #define ICE_DBG_PARSER BIT_ULL(28) 67 68 #define ICE_DBG_USER BIT_ULL(31) 69 70 enum ice_aq_res_ids { 71 ICE_NVM_RES_ID = 1, 72 ICE_SPD_RES_ID, 73 ICE_CHANGE_LOCK_RES_ID, 74 ICE_GLOBAL_CFG_LOCK_RES_ID 75 }; 76 77 enum ice_fec_stats_types { 78 ICE_FEC_CORR_LOW, 79 ICE_FEC_CORR_HIGH, 80 ICE_FEC_UNCORR_LOW, 81 ICE_FEC_UNCORR_HIGH, 82 ICE_FEC_MAX 83 }; 84 85 /* FW update timeout definitions are in milliseconds */ 86 #define ICE_NVM_TIMEOUT 180000 87 #define ICE_CHANGE_LOCK_TIMEOUT 1000 88 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000 89 90 enum ice_aq_res_access_type { 91 ICE_RES_READ = 1, 92 ICE_RES_WRITE 93 }; 94 95 struct ice_driver_ver { 96 u8 major_ver; 97 u8 minor_ver; 98 u8 build_ver; 99 u8 subbuild_ver; 100 u8 driver_string[32]; 101 }; 102 103 enum ice_fc_mode { 104 ICE_FC_NONE = 0, 105 ICE_FC_RX_PAUSE, 106 ICE_FC_TX_PAUSE, 107 ICE_FC_FULL, 108 ICE_FC_PFC, 109 ICE_FC_DFLT 110 }; 111 112 enum ice_phy_cache_mode { 113 ICE_FC_MODE = 0, 114 ICE_SPEED_MODE, 115 ICE_FEC_MODE 116 }; 117 118 enum ice_fec_mode { 119 ICE_FEC_NONE = 0, 120 ICE_FEC_RS, 121 ICE_FEC_BASER, 122 ICE_FEC_AUTO 123 }; 124 125 struct ice_phy_cache_mode_data { 126 union { 127 enum ice_fec_mode curr_user_fec_req; 128 enum ice_fc_mode curr_user_fc_req; 129 u16 curr_user_speed_req; 130 } data; 131 }; 132 133 enum ice_set_fc_aq_failures { 134 ICE_SET_FC_AQ_FAIL_NONE = 0, 135 ICE_SET_FC_AQ_FAIL_GET, 136 ICE_SET_FC_AQ_FAIL_SET, 137 ICE_SET_FC_AQ_FAIL_UPDATE 138 }; 139 140 /* Various MAC types */ 141 enum ice_mac_type { 142 ICE_MAC_UNKNOWN = 0, 143 ICE_MAC_E810, 144 ICE_MAC_E830, 145 ICE_MAC_GENERIC, 146 ICE_MAC_GENERIC_3K_E825, 147 }; 148 149 /* Media Types */ 150 enum ice_media_type { 151 ICE_MEDIA_UNKNOWN = 0, 152 ICE_MEDIA_FIBER, 153 ICE_MEDIA_BASET, 154 ICE_MEDIA_BACKPLANE, 155 ICE_MEDIA_DA, 156 }; 157 158 enum ice_vsi_type { 159 ICE_VSI_PF = 0, 160 ICE_VSI_VF = 1, 161 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 162 ICE_VSI_CHNL = 4, 163 ICE_VSI_LB = 6, 164 ICE_VSI_SF = 9, 165 }; 166 167 struct ice_link_status { 168 /* Refer to ice_aq_phy_type for bits definition */ 169 u64 phy_type_low; 170 u64 phy_type_high; 171 u8 topo_media_conflict; 172 u16 max_frame_size; 173 u16 link_speed; 174 u16 req_speeds; 175 u8 link_cfg_err; 176 u8 lse_ena; /* Link Status Event notification */ 177 u8 link_info; 178 u8 an_info; 179 u8 ext_info; 180 u8 fec_info; 181 u8 pacing; 182 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 183 * ice_aqc_get_phy_caps structure 184 */ 185 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 186 }; 187 188 /* Different reset sources for which a disable queue AQ call has to be made in 189 * order to clean the Tx scheduler as a part of the reset 190 */ 191 enum ice_disq_rst_src { 192 ICE_NO_RESET = 0, 193 ICE_VM_RESET, 194 ICE_VF_RESET, 195 }; 196 197 /* PHY info such as phy_type, etc... */ 198 struct ice_phy_info { 199 struct ice_link_status link_info; 200 struct ice_link_status link_info_old; 201 u64 phy_type_low; 202 u64 phy_type_high; 203 enum ice_media_type media_type; 204 u8 get_link_info; 205 /* Please refer to struct ice_aqc_get_link_status_data to get 206 * detail of enable bit in curr_user_speed_req 207 */ 208 u16 curr_user_speed_req; 209 enum ice_fec_mode curr_user_fec_req; 210 enum ice_fc_mode curr_user_fc_req; 211 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 212 }; 213 214 /* protocol enumeration for filters */ 215 enum ice_fltr_ptype { 216 /* NONE - used for undef/error */ 217 ICE_FLTR_PTYPE_NONF_NONE = 0, 218 ICE_FLTR_PTYPE_NONF_ETH, 219 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 220 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 221 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 222 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 223 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 224 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 225 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 226 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 227 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 228 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 229 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 230 ICE_FLTR_PTYPE_NONF_IPV4_ESP, 231 ICE_FLTR_PTYPE_NONF_IPV6_ESP, 232 ICE_FLTR_PTYPE_NONF_IPV4_AH, 233 ICE_FLTR_PTYPE_NONF_IPV6_AH, 234 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 235 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 236 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 237 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 238 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 239 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 240 ICE_FLTR_PTYPE_NON_IP_L2, 241 ICE_FLTR_PTYPE_FRAG_IPV4, 242 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 243 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 244 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 245 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 246 ICE_FLTR_PTYPE_MAX, 247 }; 248 249 enum ice_fd_hw_seg { 250 ICE_FD_HW_SEG_NON_TUN = 0, 251 ICE_FD_HW_SEG_TUN, 252 ICE_FD_HW_SEG_MAX, 253 }; 254 255 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */ 256 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC) 257 258 struct ice_fd_hw_prof { 259 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 260 int cnt; 261 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 262 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 263 u64 prof_id[ICE_FD_HW_SEG_MAX]; 264 }; 265 266 /* Common HW capabilities for SW use */ 267 struct ice_hw_common_caps { 268 u32 valid_functions; 269 /* DCB capabilities */ 270 u32 active_tc_bitmap; 271 u32 maxtc; 272 273 /* Tx/Rx queues */ 274 u16 num_rxq; /* Number/Total Rx queues */ 275 u16 rxq_first_id; /* First queue ID for Rx queues */ 276 u16 num_txq; /* Number/Total Tx queues */ 277 u16 txq_first_id; /* First queue ID for Tx queues */ 278 279 /* MSI-X vectors */ 280 u16 num_msix_vectors; 281 u16 msix_vector_first_id; 282 283 /* Max MTU for function or device */ 284 u16 max_mtu; 285 286 /* Virtualization support */ 287 u8 sr_iov_1_1; /* SR-IOV enabled */ 288 289 /* RSS related capabilities */ 290 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 291 u8 rss_table_entry_width; /* RSS Entry width in bits */ 292 293 u8 dcb; 294 u8 ieee_1588; 295 u8 rdma; 296 297 bool roce_lag; 298 bool sriov_lag; 299 bool sriov_aa_lag; 300 301 bool nvm_update_pending_nvm; 302 bool nvm_update_pending_orom; 303 bool nvm_update_pending_netlist; 304 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 305 #define ICE_NVM_PENDING_OROM BIT(1) 306 #define ICE_NVM_PENDING_NETLIST BIT(2) 307 bool nvm_unified_update; 308 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 309 /* PCIe reset avoidance */ 310 bool pcie_reset_avoidance; 311 /* Post update reset restriction */ 312 bool reset_restrict_support; 313 bool tx_sched_topo_comp_mode_en; 314 }; 315 316 /* IEEE 1588 TIME_SYNC specific info */ 317 /* Function specific definitions */ 318 #define ICE_TS_FUNC_ENA_M BIT(0) 319 #define ICE_TS_SRC_TMR_OWND_M BIT(1) 320 #define ICE_TS_TMR_ENA_M BIT(2) 321 #define ICE_TS_TMR_IDX_OWND_S 4 322 #define ICE_TS_TMR_IDX_OWND_M BIT(4) 323 #define ICE_TS_CLK_FREQ_S 16 324 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S) 325 #define ICE_TS_CLK_SRC_S 20 326 #define ICE_TS_CLK_SRC_M BIT(20) 327 #define ICE_TS_TMR_IDX_ASSOC_S 24 328 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24) 329 330 /* TIME_REF clock rate specification */ 331 enum ice_tspll_freq { 332 ICE_TSPLL_FREQ_25_000 = 0, 333 ICE_TSPLL_FREQ_122_880 = 1, 334 ICE_TSPLL_FREQ_125_000 = 2, 335 ICE_TSPLL_FREQ_153_600 = 3, 336 ICE_TSPLL_FREQ_156_250 = 4, 337 ICE_TSPLL_FREQ_245_760 = 5, 338 339 NUM_ICE_TSPLL_FREQ, 340 341 ICE_TSPLL_FREQ_INVALID = -1, 342 }; 343 344 /* Clock source specification */ 345 enum ice_clk_src { 346 ICE_CLK_SRC_TCXO = 0, /* Temperature compensated oscillator */ 347 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */ 348 349 NUM_ICE_CLK_SRC 350 }; 351 352 enum ice_synce_clk { 353 ICE_SYNCE_CLK0, 354 ICE_SYNCE_CLK1, 355 ICE_SYNCE_CLK_NUM 356 }; 357 358 struct ice_ts_func_info { 359 /* Function specific info */ 360 enum ice_tspll_freq time_ref; 361 u8 clk_freq; 362 u8 clk_src; 363 u8 tmr_index_assoc; 364 u8 ena; 365 u8 tmr_index_owned; 366 u8 src_tmr_owned; 367 u8 tmr_ena; 368 }; 369 370 /* Device specific definitions */ 371 #define ICE_TS_TMR0_OWNR_M 0x7 372 #define ICE_TS_TMR0_OWND_M BIT(3) 373 #define ICE_TS_TMR1_OWNR_S 4 374 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S) 375 #define ICE_TS_TMR1_OWND_M BIT(7) 376 #define ICE_TS_DEV_ENA_M BIT(24) 377 #define ICE_TS_TMR0_ENA_M BIT(25) 378 #define ICE_TS_TMR1_ENA_M BIT(26) 379 #define ICE_TS_LL_TX_TS_READ_M BIT(28) 380 #define ICE_TS_LL_TX_TS_INT_READ_M BIT(29) 381 #define ICE_TS_LL_PHY_TMR_UPDATE_M BIT(30) 382 383 struct ice_ts_dev_info { 384 /* Device specific info */ 385 u32 ena_ports; 386 u32 tmr_own_map; 387 u32 tmr0_owner; 388 u32 tmr1_owner; 389 u8 tmr0_owned; 390 u8 tmr1_owned; 391 u8 ena; 392 u8 tmr0_ena; 393 u8 tmr1_ena; 394 u8 ts_ll_read; 395 u8 ts_ll_int_read; 396 u8 ll_phy_tmr_update; 397 }; 398 399 #define ICE_NAC_TOPO_PRIMARY_M BIT(0) 400 #define ICE_NAC_TOPO_DUAL_M BIT(1) 401 #define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0) 402 403 struct ice_nac_topology { 404 u32 mode; 405 u8 id; 406 }; 407 408 /* Function specific capabilities */ 409 struct ice_hw_func_caps { 410 struct ice_hw_common_caps common_cap; 411 u32 num_allocd_vfs; /* Number of allocated VFs */ 412 u32 vf_base_id; /* Logical ID of the first VF */ 413 u32 guar_num_vsi; 414 u32 fd_fltr_guar; /* Number of filters guaranteed */ 415 u32 fd_fltr_best_effort; /* Number of best effort filters */ 416 struct ice_ts_func_info ts_func_info; 417 }; 418 419 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0 420 421 /* Device wide capabilities */ 422 struct ice_hw_dev_caps { 423 struct ice_hw_common_caps common_cap; 424 u32 num_vfs_exposed; /* Total number of VFs exposed */ 425 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 426 u32 num_flow_director_fltr; /* Number of FD filters available */ 427 struct ice_ts_dev_info ts_dev_info; 428 u32 num_funcs; 429 struct ice_nac_topology nac_topo; 430 /* bitmap of supported sensors 431 * bit 0 - internal temperature sensor 432 * bit 31:1 - Reserved 433 */ 434 u32 supported_sensors; 435 }; 436 437 /* MAC info */ 438 struct ice_mac_info { 439 u8 lan_addr[ETH_ALEN]; 440 u8 perm_addr[ETH_ALEN]; 441 }; 442 443 /* Reset types used to determine which kind of reset was requested. These 444 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 445 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 446 * because its reset source is different than the other types listed. 447 */ 448 enum ice_reset_req { 449 ICE_RESET_POR = 0, 450 ICE_RESET_INVAL = 0, 451 ICE_RESET_CORER = 1, 452 ICE_RESET_GLOBR = 2, 453 ICE_RESET_EMPR = 3, 454 ICE_RESET_PFR = 4, 455 }; 456 457 /* Bus parameters */ 458 struct ice_bus_info { 459 u16 device; 460 u8 func; 461 }; 462 463 /* Flow control (FC) parameters */ 464 struct ice_fc_info { 465 enum ice_fc_mode current_mode; /* FC mode in effect */ 466 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 467 }; 468 469 /* Option ROM version information */ 470 struct ice_orom_info { 471 u8 major; /* Major version of OROM */ 472 u8 patch; /* Patch version of OROM */ 473 u16 build; /* Build version of OROM */ 474 }; 475 476 /* NVM version information */ 477 struct ice_nvm_info { 478 u32 eetrack; 479 u8 major; 480 u8 minor; 481 }; 482 483 /* netlist version information */ 484 struct ice_netlist_info { 485 u32 major; /* major high/low */ 486 u32 minor; /* minor high/low */ 487 u32 type; /* type high/low */ 488 u32 rev; /* revision high/low */ 489 u32 hash; /* SHA-1 hash word */ 490 u16 cust_ver; /* customer version */ 491 }; 492 493 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 494 * of the flash image. 495 */ 496 enum ice_flash_bank { 497 ICE_INVALID_FLASH_BANK, 498 ICE_1ST_FLASH_BANK, 499 ICE_2ND_FLASH_BANK, 500 }; 501 502 /* Enumeration of which flash bank is desired to read from, either the active 503 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 504 * code which just wants to read the active or inactive flash bank. 505 */ 506 enum ice_bank_select { 507 ICE_ACTIVE_FLASH_BANK, 508 ICE_INACTIVE_FLASH_BANK, 509 }; 510 511 /* information for accessing NVM, OROM, and Netlist flash banks */ 512 struct ice_bank_info { 513 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 514 u32 nvm_size; /* Size of NVM bank */ 515 u32 orom_ptr; /* Pointer to 1st OROM bank */ 516 u32 orom_size; /* Size of OROM bank */ 517 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 518 u32 netlist_size; /* Size of Netlist bank */ 519 u32 active_css_hdr_len; /* Active CSS header length */ 520 u32 inactive_css_hdr_len; /* Inactive CSS header length */ 521 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 522 enum ice_flash_bank orom_bank; /* Active OROM bank */ 523 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 524 }; 525 526 /* Flash Chip Information */ 527 struct ice_flash_info { 528 struct ice_orom_info orom; /* Option ROM version info */ 529 struct ice_nvm_info nvm; /* NVM version information */ 530 struct ice_netlist_info netlist;/* Netlist version info */ 531 struct ice_bank_info banks; /* Flash Bank information */ 532 u32 flash_size; /* Size of available flash in bytes */ 533 u16 sr_words; /* Shadow RAM size in words */ 534 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 535 }; 536 537 struct ice_link_default_override_tlv { 538 u8 options; 539 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 540 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 541 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 542 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 543 #define ICE_LINK_OVERRIDE_EN BIT(3) 544 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 545 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 546 u8 phy_config; 547 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 548 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 549 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 550 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 551 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 552 u8 fec_options; 553 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 554 u8 rsvd1; 555 u64 phy_type_low; 556 u64 phy_type_high; 557 }; 558 559 #define ICE_NVM_VER_LEN 32 560 561 /* Max number of port to queue branches w.r.t topology */ 562 #define ICE_MAX_TRAFFIC_CLASS 8 563 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 564 565 #define ice_for_each_traffic_class(_i) \ 566 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 567 568 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 569 * to driver defined policy for default aggregator 570 */ 571 #define ICE_INVAL_TEID 0xFFFFFFFF 572 #define ICE_DFLT_AGG_ID 0 573 574 struct ice_sched_node { 575 struct ice_sched_node *parent; 576 struct ice_sched_node *sibling; /* next sibling in the same layer */ 577 struct ice_sched_node **children; 578 struct ice_aqc_txsched_elem_data info; 579 char *name; 580 struct devlink_rate *rate_node; 581 u64 tx_max; 582 u64 tx_share; 583 u32 agg_id; /* aggregator group ID */ 584 u32 id; 585 u32 tx_priority; 586 u32 tx_weight; 587 u16 vsi_handle; 588 u8 in_use; /* suspended or in use */ 589 u8 tx_sched_layer; /* Logical Layer (1-9) */ 590 u8 num_children; 591 u8 tc_num; 592 u8 owner; 593 #define ICE_SCHED_NODE_OWNER_LAN 0 594 #define ICE_SCHED_NODE_OWNER_RDMA 2 595 }; 596 597 /* Access Macros for Tx Sched Elements data */ 598 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 599 600 /* The aggregator type determines if identifier is for a VSI group, 601 * aggregator group, aggregator of queues, or queue group. 602 */ 603 enum ice_agg_type { 604 ICE_AGG_TYPE_UNKNOWN = 0, 605 ICE_AGG_TYPE_VSI, 606 ICE_AGG_TYPE_AGG, /* aggregator */ 607 ICE_AGG_TYPE_Q, 608 ICE_AGG_TYPE_QG 609 }; 610 611 /* Rate limit types */ 612 enum ice_rl_type { 613 ICE_UNKNOWN_BW = 0, 614 ICE_MIN_BW, /* for CIR profile */ 615 ICE_MAX_BW, /* for EIR profile */ 616 ICE_SHARED_BW /* for shared profile */ 617 }; 618 619 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 620 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 621 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 622 #define ICE_SCHED_DFLT_RL_PROF_ID 0 623 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 624 #define ICE_SCHED_DFLT_BW_WT 4 625 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 626 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 627 628 #define ICE_MAX_PORT_PER_PCI_DEV 8 629 630 /* Data structure for saving BW information */ 631 enum ice_bw_type { 632 ICE_BW_TYPE_PRIO, 633 ICE_BW_TYPE_CIR, 634 ICE_BW_TYPE_CIR_WT, 635 ICE_BW_TYPE_EIR, 636 ICE_BW_TYPE_EIR_WT, 637 ICE_BW_TYPE_SHARED, 638 ICE_BW_TYPE_CNT /* This must be last */ 639 }; 640 641 struct ice_bw { 642 u32 bw; 643 u16 bw_alloc; 644 }; 645 646 struct ice_bw_type_info { 647 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 648 u8 generic; 649 struct ice_bw cir_bw; 650 struct ice_bw eir_bw; 651 u32 shared_bw; 652 }; 653 654 /* VSI queue context structure for given TC */ 655 struct ice_q_ctx { 656 u16 q_handle; 657 u32 q_teid; 658 /* bw_t_info saves queue BW information */ 659 struct ice_bw_type_info bw_t_info; 660 }; 661 662 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 663 struct ice_sched_vsi_info { 664 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 665 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 666 struct list_head list_entry; 667 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 668 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 669 /* bw_t_info saves VSI BW information */ 670 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 671 }; 672 673 /* driver defines the policy */ 674 struct ice_sched_tx_policy { 675 u16 max_num_vsis; 676 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 677 u8 rdma_ena; 678 }; 679 680 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 681 struct ice_dcb_ets_cfg { 682 u8 willing; 683 u8 cbs; 684 u8 maxtcs; 685 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 686 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 687 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 688 }; 689 690 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 691 struct ice_dcb_pfc_cfg { 692 u8 willing; 693 u8 mbc; 694 u8 pfccap; 695 u8 pfcena; 696 }; 697 698 /* CEE or IEEE 802.1Qaz Application Priority data */ 699 struct ice_dcb_app_priority_table { 700 u16 prot_id; 701 u8 priority; 702 u8 selector; 703 }; 704 705 #define ICE_MAX_USER_PRIORITY 8 706 #define ICE_DCBX_MAX_APPS 64 707 #define ICE_LLDPDU_SIZE 1500 708 #define ICE_TLV_STATUS_OPER 0x1 709 #define ICE_TLV_STATUS_SYNC 0x2 710 #define ICE_TLV_STATUS_ERR 0x4 711 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 712 #define ICE_APP_SEL_ETHTYPE 0x1 713 #define ICE_APP_SEL_TCPIP 0x2 714 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 715 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 716 #define ICE_CEE_APP_SEL_TCPIP 0x1 717 718 struct ice_dcbx_cfg { 719 u32 numapps; 720 u32 tlv_status; /* CEE mode TLV status */ 721 struct ice_dcb_ets_cfg etscfg; 722 struct ice_dcb_ets_cfg etsrec; 723 struct ice_dcb_pfc_cfg pfc; 724 #define ICE_QOS_MODE_VLAN 0x0 725 #define ICE_QOS_MODE_DSCP 0x1 726 u8 pfc_mode; 727 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 728 /* when DSCP mapping defined by user set its bit to 1 */ 729 DECLARE_BITMAP(dscp_mapped, DSCP_MAX); 730 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 731 u8 dscp_map[DSCP_MAX]; 732 u8 dcbx_mode; 733 #define ICE_DCBX_MODE_CEE 0x1 734 #define ICE_DCBX_MODE_IEEE 0x2 735 u8 app_mode; 736 #define ICE_DCBX_APPS_NON_WILLING 0x1 737 }; 738 739 struct ice_qos_cfg { 740 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 741 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 742 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 743 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 744 u8 is_sw_lldp : 1; 745 }; 746 747 struct ice_port_info { 748 struct ice_sched_node *root; /* Root Node per Port */ 749 struct ice_hw *hw; /* back pointer to HW instance */ 750 u32 last_node_teid; /* scheduler last node info */ 751 u16 sw_id; /* Initial switch ID belongs to port */ 752 u16 pf_vf_num; 753 u8 port_state; 754 u8 local_fwd_mode; 755 #define ICE_SCHED_PORT_STATE_INIT 0x0 756 #define ICE_SCHED_PORT_STATE_READY 0x1 757 u8 lport; 758 #define ICE_LPORT_MASK 0xff 759 struct ice_fc_info fc; 760 struct ice_mac_info mac; 761 struct ice_phy_info phy; 762 struct mutex sched_lock; /* protect access to TXSched tree */ 763 struct ice_sched_node * 764 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 765 /* List contain profile ID(s) and other params per layer */ 766 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 767 struct ice_qos_cfg qos_cfg; 768 u8 is_vf:1; 769 u8 is_custom_tx_enabled:1; 770 }; 771 772 struct ice_switch_info { 773 struct list_head vsi_list_map_head; 774 struct ice_sw_recipe *recp_list; 775 u16 prof_res_bm_init; 776 u16 max_used_prof_index; 777 u16 rule_cnt; 778 u8 recp_cnt; 779 780 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 781 }; 782 783 /* Enum defining the different states of the mailbox snapshot in the 784 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 785 * states: 786 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 787 * within the mailbox buffer. 788 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 789 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 790 * mailbox and mark any VFs sending more messages than the threshold limit set. 791 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 792 */ 793 enum ice_mbx_snapshot_state { 794 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 795 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 796 ICE_MAL_VF_DETECT_STATE_DETECT, 797 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 798 }; 799 800 /* Structure to hold information of the static snapshot and the mailbox 801 * buffer data used to generate and track the snapshot. 802 * 1. state: the state of the mailbox snapshot in the malicious VF 803 * detection state handler ice_mbx_vf_state_handler() 804 * 2. head: head of the mailbox snapshot in a circular mailbox buffer 805 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 806 * 4. num_iterations: number of messages traversed in circular mailbox buffer 807 * 5. num_msg_proc: number of messages processed in mailbox 808 * 6. num_pending_arq: number of pending asynchronous messages 809 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 810 * serviced work item or interrupt. 811 */ 812 struct ice_mbx_snap_buffer_data { 813 enum ice_mbx_snapshot_state state; 814 u32 head; 815 u32 tail; 816 u32 num_iterations; 817 u16 num_msg_proc; 818 u16 num_pending_arq; 819 u16 max_num_msgs_mbx; 820 }; 821 822 /* Structure used to track a single VF's messages on the mailbox: 823 * 1. list_entry: linked list entry node 824 * 2. msg_count: the number of asynchronous messages sent by this VF 825 * 3. malicious: whether this VF has been detected as malicious before 826 */ 827 struct ice_mbx_vf_info { 828 struct list_head list_entry; 829 u32 msg_count; 830 u8 malicious : 1; 831 }; 832 833 /* Structure to hold data relevant to the captured static snapshot 834 * of the PF-VF mailbox. 835 */ 836 struct ice_mbx_snapshot { 837 struct ice_mbx_snap_buffer_data mbx_buf; 838 struct list_head mbx_vf; 839 }; 840 841 /* Structure to hold data to be used for capturing or updating a 842 * static snapshot. 843 * 1. num_msg_proc: number of messages processed in mailbox 844 * 2. num_pending_arq: number of pending asynchronous messages 845 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 846 * serviced work item or interrupt. 847 * 4. async_watermark_val: An upper threshold set by caller to determine 848 * if the pending arq count is large enough to assume that there is 849 * the possibility of a mailicious VF. 850 */ 851 struct ice_mbx_data { 852 u16 num_msg_proc; 853 u16 num_pending_arq; 854 u16 max_num_msgs_mbx; 855 u16 async_watermark_val; 856 }; 857 858 #define ICE_PORTS_PER_QUAD 4 859 #define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD) 860 861 #define ATQBAL_FLAGS_INTR_IN_PROGRESS BIT(0) 862 863 struct ice_e810_params { 864 /* The wait queue lock also protects the low latency interface */ 865 wait_queue_head_t atqbal_wq; 866 unsigned int atqbal_flags; 867 }; 868 869 struct ice_eth56g_params { 870 u8 num_phys; 871 bool onestep_ena; 872 bool sfd_ena; 873 u32 peer_delay; 874 }; 875 876 union ice_phy_params { 877 struct ice_e810_params e810; 878 struct ice_eth56g_params eth56g; 879 }; 880 881 /* Global Link Topology */ 882 enum ice_global_link_topo { 883 ICE_LINK_TOPO_UP_TO_2_LINKS, 884 ICE_LINK_TOPO_UP_TO_4_LINKS, 885 ICE_LINK_TOPO_UP_TO_8_LINKS, 886 ICE_LINK_TOPO_RESERVED, 887 }; 888 889 struct ice_ptp_hw { 890 union ice_phy_params phy; 891 u8 num_lports; 892 u8 ports_per_phy; 893 }; 894 895 #define ICE_E825_MAX_PHYS 2 896 897 /* Port hardware description */ 898 struct ice_hw { 899 u8 __iomem *hw_addr; 900 void *back; 901 struct ice_aqc_layer_props *layer_info; 902 struct ice_port_info *port_info; 903 /* PSM clock frequency for calculating RL profile params */ 904 u32 psm_clk_freq; 905 u64 debug_mask; /* bitmap for debug mask */ 906 enum ice_mac_type mac_type; 907 908 u16 fd_ctr_base; /* FD counter base index */ 909 910 /* pci info */ 911 u16 device_id; 912 u16 vendor_id; 913 u16 subsystem_device_id; 914 u16 subsystem_vendor_id; 915 u8 revision_id; 916 917 u8 pf_id; /* device profile info */ 918 u8 logical_pf_id; 919 920 u16 max_burst_size; /* driver sets this value */ 921 922 u8 recp_reuse:1; /* indicates whether FW supports recipe reuse */ 923 924 /* Tx Scheduler values */ 925 u8 num_tx_sched_layers; 926 u8 num_tx_sched_phys_layers; 927 u8 flattened_layers; 928 u8 max_cgds; 929 u8 sw_entry_point_layer; 930 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 931 struct list_head agg_list; /* lists all aggregator */ 932 struct xarray sched_node_ids; 933 934 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 935 u8 evb_veb; /* true for VEB, false for VEPA */ 936 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 937 struct ice_bus_info bus; 938 struct ice_flash_info flash; 939 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 940 struct ice_hw_func_caps func_caps; /* function capabilities */ 941 942 struct ice_switch_info *switch_info; /* switch filter lists */ 943 944 /* Control Queue info */ 945 struct ice_ctl_q_info adminq; 946 struct ice_ctl_q_info sbq; 947 struct ice_ctl_q_info mailboxq; 948 949 u8 api_branch; /* API branch version */ 950 u8 api_maj_ver; /* API major version */ 951 u8 api_min_ver; /* API minor version */ 952 u8 api_patch; /* API patch version */ 953 u8 fw_branch; /* firmware branch version */ 954 u8 fw_maj_ver; /* firmware major version */ 955 u8 fw_min_ver; /* firmware minor version */ 956 u8 fw_patch; /* firmware patch version */ 957 u32 fw_build; /* firmware build number */ 958 959 struct libie_fwlog fwlog; 960 961 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 962 * register. Used for determining the ITR/INTRL granularity during 963 * initialization. 964 */ 965 #define ICE_MAX_AGG_BW_200G 0x0 966 #define ICE_MAX_AGG_BW_100G 0X1 967 #define ICE_MAX_AGG_BW_50G 0x2 968 #define ICE_MAX_AGG_BW_25G 0x3 969 /* ITR granularity for different speeds */ 970 #define ICE_ITR_GRAN_ABOVE_25 2 971 #define ICE_ITR_GRAN_MAX_25 4 972 /* ITR granularity in 1 us */ 973 u8 itr_gran; 974 /* INTRL granularity for different speeds */ 975 #define ICE_INTRL_GRAN_ABOVE_25 4 976 #define ICE_INTRL_GRAN_MAX_25 8 977 /* INTRL granularity in 1 us */ 978 u8 intrl_gran; 979 980 struct ice_ptp_hw ptp; 981 s8 lane_num; 982 983 /* Active package version (currently active) */ 984 struct ice_pkg_ver active_pkg_ver; 985 u32 pkg_seg_id; 986 u32 pkg_sign_type; 987 u32 active_track_id; 988 u8 pkg_has_signing_seg:1; 989 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 990 u8 active_pkg_in_nvm; 991 992 /* Driver's package ver - (from the Ice Metadata section) */ 993 struct ice_pkg_ver pkg_ver; 994 u8 pkg_name[ICE_PKG_NAME_SIZE]; 995 996 /* Driver's Ice segment format version and ID (from the Ice seg) */ 997 struct ice_pkg_ver ice_seg_fmt_ver; 998 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 999 1000 /* Pointer to the ice segment */ 1001 struct ice_seg *seg; 1002 1003 /* Pointer to allocated copy of pkg memory */ 1004 u8 *pkg_copy; 1005 u32 pkg_size; 1006 1007 /* tunneling info */ 1008 struct mutex tnl_lock; 1009 struct ice_tunnel_table tnl; 1010 1011 struct udp_tunnel_nic_shared udp_tunnel_shared; 1012 struct udp_tunnel_nic_info udp_tunnel_nic; 1013 1014 /* dvm boost update information */ 1015 struct ice_dvm_table dvm_upd; 1016 1017 /* HW block tables */ 1018 struct ice_blk_info blk[ICE_BLK_COUNT]; 1019 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 1020 struct list_head fl_profs[ICE_BLK_COUNT]; 1021 1022 /* ntuple filter info */ 1023 int ntuple_active_fltr_cnt; 1024 1025 struct mutex fdir_fltr_lock; /* protect Flow Director */ 1026 struct list_head fdir_list_head; 1027 1028 /* Book-keeping of side-band filter count per flow-type. 1029 * This is used to detect and handle input set changes for 1030 * respective flow-type. 1031 */ 1032 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 1033 1034 struct ice_fd_hw_prof **fdir_prof; 1035 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 1036 struct mutex rss_locks; /* protect RSS configuration */ 1037 struct list_head rss_list_head; 1038 struct ice_mbx_snapshot mbx_snapshot; 1039 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX); 1040 u8 dvm_ena; 1041 u16 io_expander_handle; 1042 u8 cgu_part_number; 1043 }; 1044 1045 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1046 struct ice_eth_stats { 1047 u64 rx_bytes; /* gorc */ 1048 u64 rx_unicast; /* uprc */ 1049 u64 rx_multicast; /* mprc */ 1050 u64 rx_broadcast; /* bprc */ 1051 u64 rx_discards; /* rdpc */ 1052 u64 rx_unknown_protocol; /* rupp */ 1053 u64 tx_bytes; /* gotc */ 1054 u64 tx_unicast; /* uptc */ 1055 u64 tx_multicast; /* mptc */ 1056 u64 tx_broadcast; /* bptc */ 1057 u64 tx_discards; /* tdpc */ 1058 u64 tx_errors; /* tepc */ 1059 }; 1060 1061 #define ICE_MAX_UP 8 1062 1063 /* Statistics collected by the MAC */ 1064 struct ice_hw_port_stats { 1065 /* eth stats collected by the port */ 1066 struct ice_eth_stats eth; 1067 /* additional port specific stats */ 1068 u64 tx_dropped_link_down; /* tdold */ 1069 u64 crc_errors; /* crcerrs */ 1070 u64 illegal_bytes; /* illerrc */ 1071 u64 error_bytes; /* errbc */ 1072 u64 mac_local_faults; /* mlfc */ 1073 u64 mac_remote_faults; /* mrfc */ 1074 u64 rx_len_errors; /* rlec */ 1075 u64 link_xon_rx; /* lxonrxc */ 1076 u64 link_xoff_rx; /* lxoffrxc */ 1077 u64 link_xon_tx; /* lxontxc */ 1078 u64 link_xoff_tx; /* lxofftxc */ 1079 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1080 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1081 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1082 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1083 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1084 u64 rx_size_64; /* prc64 */ 1085 u64 rx_size_127; /* prc127 */ 1086 u64 rx_size_255; /* prc255 */ 1087 u64 rx_size_511; /* prc511 */ 1088 u64 rx_size_1023; /* prc1023 */ 1089 u64 rx_size_1522; /* prc1522 */ 1090 u64 rx_size_big; /* prc9522 */ 1091 u64 rx_undersize; /* ruc */ 1092 u64 rx_fragments; /* rfc */ 1093 u64 rx_oversize; /* roc */ 1094 u64 rx_jabber; /* rjc */ 1095 u64 tx_size_64; /* ptc64 */ 1096 u64 tx_size_127; /* ptc127 */ 1097 u64 tx_size_255; /* ptc255 */ 1098 u64 tx_size_511; /* ptc511 */ 1099 u64 tx_size_1023; /* ptc1023 */ 1100 u64 tx_size_1522; /* ptc1522 */ 1101 u64 tx_size_big; /* ptc9522 */ 1102 /* flow director stats */ 1103 u32 fd_sb_status; 1104 u64 fd_sb_match; 1105 }; 1106 1107 enum ice_sw_fwd_act_type { 1108 ICE_FWD_TO_VSI = 0, 1109 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1110 ICE_FWD_TO_Q, 1111 ICE_FWD_TO_QGRP, 1112 ICE_DROP_PACKET, 1113 ICE_MIRROR_PACKET, 1114 ICE_NOP, 1115 ICE_INVAL_ACT 1116 }; 1117 1118 struct ice_aq_get_set_rss_lut_params { 1119 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1120 enum ice_lut_size lut_size; /* size of the LUT buffer */ 1121 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1122 u16 vsi_handle; /* software VSI handle */ 1123 u8 global_lut_id; /* only valid when lut_type is global */ 1124 }; 1125 1126 /* Checksum and Shadow RAM pointers */ 1127 #define ICE_SR_NVM_CTRL_WORD 0x00 1128 #define ICE_SR_BOOT_CFG_PTR 0x132 1129 #define ICE_SR_NVM_WOL_CFG 0x19 1130 #define ICE_NVM_OROM_VER_OFF 0x02 1131 #define ICE_SR_PBA_BLOCK_PTR 0x16 1132 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1133 #define ICE_SR_NVM_EETRACK_LO 0x2D 1134 #define ICE_SR_NVM_EETRACK_HI 0x2E 1135 #define ICE_NVM_VER_LO_SHIFT 0 1136 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1137 #define ICE_NVM_VER_HI_SHIFT 12 1138 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1139 #define ICE_OROM_VER_PATCH_SHIFT 0 1140 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1141 #define ICE_OROM_VER_BUILD_SHIFT 8 1142 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1143 #define ICE_OROM_VER_SHIFT 24 1144 #define ICE_OROM_VER_MASK (0xffU << ICE_OROM_VER_SHIFT) 1145 #define ICE_SR_PFA_PTR 0x40 1146 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1147 #define ICE_SR_NVM_BANK_SIZE 0x43 1148 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1149 #define ICE_SR_OROM_BANK_SIZE 0x45 1150 #define ICE_SR_NETLIST_BANK_PTR 0x46 1151 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1152 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1153 1154 /* CSS Header words */ 1155 #define ICE_NVM_CSS_HDR_LEN_L 0x02 1156 #define ICE_NVM_CSS_HDR_LEN_H 0x03 1157 #define ICE_NVM_CSS_SREV_L 0x14 1158 #define ICE_NVM_CSS_SREV_H 0x15 1159 1160 /* Length of Authentication header section in words */ 1161 #define ICE_NVM_AUTH_HEADER_LEN 0x08 1162 1163 /* The Link Topology Netlist section is stored as a series of words. It is 1164 * stored in the NVM as a TLV, with the first two words containing the type 1165 * and length. 1166 */ 1167 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1168 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1169 #define ICE_NETLIST_LEN_OFFSET 0x0001 1170 1171 /* The Link Topology section follows the TLV header. When reading the netlist 1172 * using ice_read_netlist_module, we need to account for the 2-word TLV 1173 * header. 1174 */ 1175 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1176 1177 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1178 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1179 1180 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 1181 1182 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1183 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1184 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1185 1186 /* netlist ID block field offsets (word offsets) */ 1187 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1188 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1189 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1190 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1191 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1192 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1193 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1194 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1195 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1196 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1197 1198 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 1199 #define ICE_SR_CTRL_WORD_1_S 0x06 1200 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1201 #define ICE_SR_CTRL_WORD_VALID 0x1 1202 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1203 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1204 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1205 1206 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1207 1208 /* Link override related */ 1209 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1210 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1211 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1212 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1213 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1214 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1215 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1216 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1217 1218 #define ICE_SR_WORDS_IN_1KB 512 1219 1220 /* AQ API version for LLDP_FILTER_CONTROL */ 1221 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1222 #define ICE_FW_API_LLDP_FLTR_MIN 7 1223 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1224 1225 /* AQ API version for report default configuration */ 1226 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1227 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1228 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1229 1230 /* AQ API version for Health Status support */ 1231 #define ICE_FW_API_HEALTH_REPORT_MAJ 1 1232 #define ICE_FW_API_HEALTH_REPORT_MIN 7 1233 #define ICE_FW_API_HEALTH_REPORT_PATCH 6 1234 1235 #endif /* _ICE_TYPE_H_ */ 1236