1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2022, Intel Corporation. */ 3 4 #include "ice.h" 5 #include "ice_lib.h" 6 #include "ice_trace.h" 7 #include <linux/dpll.h> 8 #include <linux/property.h> 9 10 #define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50 11 #define ICE_DPLL_PIN_IDX_INVALID 0xff 12 #define ICE_DPLL_RCLK_NUM_PER_PF 1 13 #define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25 14 #define ICE_DPLL_PIN_GEN_RCLK_FREQ 1953125 15 #define ICE_DPLL_PIN_PRIO_OUTPUT 0xff 16 #define ICE_DPLL_INPUT_REF_NUM 10 17 #define ICE_DPLL_PHASE_OFFSET_PERIOD 2 18 #define ICE_DPLL_SW_PIN_INPUT_BASE_SFP 4 19 #define ICE_DPLL_SW_PIN_INPUT_BASE_QSFP 6 20 #define ICE_DPLL_SW_PIN_OUTPUT_BASE 0 21 22 #define ICE_DPLL_PIN_SW_INPUT_ABS(in_idx) \ 23 (ICE_DPLL_SW_PIN_INPUT_BASE_SFP + (in_idx)) 24 25 #define ICE_DPLL_PIN_SW_1_INPUT_ABS_IDX \ 26 (ICE_DPLL_PIN_SW_INPUT_ABS(ICE_DPLL_PIN_SW_1_IDX)) 27 28 #define ICE_DPLL_PIN_SW_2_INPUT_ABS_IDX \ 29 (ICE_DPLL_PIN_SW_INPUT_ABS(ICE_DPLL_PIN_SW_2_IDX)) 30 31 #define ICE_DPLL_PIN_SW_OUTPUT_ABS(out_idx) \ 32 (ICE_DPLL_SW_PIN_OUTPUT_BASE + (out_idx)) 33 34 #define ICE_DPLL_PIN_SW_1_OUTPUT_ABS_IDX \ 35 (ICE_DPLL_PIN_SW_OUTPUT_ABS(ICE_DPLL_PIN_SW_1_IDX)) 36 37 #define ICE_DPLL_PIN_SW_2_OUTPUT_ABS_IDX \ 38 (ICE_DPLL_PIN_SW_OUTPUT_ABS(ICE_DPLL_PIN_SW_2_IDX)) 39 40 #define ICE_SR_PFA_DPLL_DEFAULTS 0x152 41 #define ICE_DPLL_PFA_REF_SYNC_TYPE 0x2420 42 #define ICE_DPLL_PFA_REF_SYNC_TYPE2 0x2424 43 #define ICE_DPLL_PFA_END 0xFFFF 44 #define ICE_DPLL_PFA_HEADER_LEN 4 45 #define ICE_DPLL_PFA_ENTRY_LEN 3 46 #define ICE_DPLL_PFA_MAILBOX_REF_SYNC_PIN_S 4 47 #define ICE_DPLL_PFA_MASK_OFFSET 1 48 #define ICE_DPLL_PFA_VALUE_OFFSET 2 49 50 #define ICE_DPLL_E810C_SFP_NC_PINS 2 51 #define ICE_DPLL_E810C_SFP_NC_START 4 52 53 /** 54 * enum ice_dpll_pin_type - enumerate ice pin types: 55 * @ICE_DPLL_PIN_INVALID: invalid pin type 56 * @ICE_DPLL_PIN_TYPE_INPUT: input pin 57 * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin 58 * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin 59 * @ICE_DPLL_PIN_TYPE_SOFTWARE: software controlled SMA/U.FL pins 60 */ 61 enum ice_dpll_pin_type { 62 ICE_DPLL_PIN_INVALID, 63 ICE_DPLL_PIN_TYPE_INPUT, 64 ICE_DPLL_PIN_TYPE_OUTPUT, 65 ICE_DPLL_PIN_TYPE_RCLK_INPUT, 66 ICE_DPLL_PIN_TYPE_SOFTWARE, 67 }; 68 69 static const char * const pin_type_name[] = { 70 [ICE_DPLL_PIN_TYPE_INPUT] = "input", 71 [ICE_DPLL_PIN_TYPE_OUTPUT] = "output", 72 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input", 73 [ICE_DPLL_PIN_TYPE_SOFTWARE] = "software", 74 }; 75 76 static const char * const ice_dpll_sw_pin_sma[] = { "SMA1", "SMA2" }; 77 static const char * const ice_dpll_sw_pin_ufl[] = { "U.FL1", "U.FL2" }; 78 79 static const struct dpll_pin_frequency ice_esync_range[] = { 80 DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ), 81 }; 82 83 /** 84 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW 85 * @pf: private board structure 86 * @index: index of a pin as understood by FW 87 * @input: true for input, false for output 88 * 89 * Check if the pin shall be controlled by SW - instead of providing raw access 90 * for pin control. For E810 NIC with dpll there is additional MUX-related logic 91 * between SMA/U.FL pins/connectors and dpll device, best to give user access 92 * with series of wrapper functions as from user perspective they convey single 93 * functionality rather then separated pins. 94 * 95 * Return: 96 * * true - pin controlled by SW 97 * * false - pin not controlled by SW 98 */ 99 static bool ice_dpll_is_sw_pin(struct ice_pf *pf, u8 index, bool input) 100 { 101 if (input && pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) 102 index -= ICE_DPLL_SW_PIN_INPUT_BASE_QSFP - 103 ICE_DPLL_SW_PIN_INPUT_BASE_SFP; 104 105 if ((input && (index == ICE_DPLL_PIN_SW_1_INPUT_ABS_IDX || 106 index == ICE_DPLL_PIN_SW_2_INPUT_ABS_IDX)) || 107 (!input && (index == ICE_DPLL_PIN_SW_1_OUTPUT_ABS_IDX || 108 index == ICE_DPLL_PIN_SW_2_OUTPUT_ABS_IDX))) 109 return true; 110 return false; 111 } 112 113 /** 114 * ice_dpll_is_reset - check if reset is in progress 115 * @pf: private board structure 116 * @extack: error reporting 117 * 118 * If reset is in progress, fill extack with error. 119 * 120 * Return: 121 * * false - no reset in progress 122 * * true - reset in progress 123 */ 124 static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack) 125 { 126 if (ice_is_reset_in_progress(pf->state)) { 127 NL_SET_ERR_MSG(extack, "PF reset in progress"); 128 return true; 129 } 130 return false; 131 } 132 133 /** 134 * ice_dpll_pin_freq_set - set pin's frequency 135 * @pf: private board structure 136 * @pin: pointer to a pin 137 * @pin_type: type of pin being configured 138 * @freq: frequency to be set 139 * @extack: error reporting 140 * 141 * Set requested frequency on a pin. 142 * 143 * Context: Called under pf->dplls.lock 144 * Return: 145 * * 0 - success 146 * * negative - error on AQ or wrong pin type given 147 */ 148 static int 149 ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin, 150 enum ice_dpll_pin_type pin_type, const u32 freq, 151 struct netlink_ext_ack *extack) 152 { 153 u8 flags; 154 int ret; 155 156 switch (pin_type) { 157 case ICE_DPLL_PIN_TYPE_INPUT: 158 flags = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ; 159 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, 160 pin->flags[0], freq, 0); 161 break; 162 case ICE_DPLL_PIN_TYPE_OUTPUT: 163 flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ; 164 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, 165 0, freq, 0); 166 break; 167 default: 168 return -EINVAL; 169 } 170 if (ret) { 171 NL_SET_ERR_MSG_FMT(extack, 172 "err:%d %s failed to set pin freq:%u on pin:%u", 173 ret, 174 libie_aq_str(pf->hw.adminq.sq_last_status), 175 freq, pin->idx); 176 return ret; 177 } 178 pin->freq = freq; 179 180 return 0; 181 } 182 183 /** 184 * ice_dpll_frequency_set - wrapper for pin callback for set frequency 185 * @pin: pointer to a pin 186 * @pin_priv: private data pointer passed on pin registration 187 * @dpll: pointer to dpll 188 * @dpll_priv: private data pointer passed on dpll registration 189 * @frequency: frequency to be set 190 * @extack: error reporting 191 * @pin_type: type of pin being configured 192 * 193 * Wraps internal set frequency command on a pin. 194 * 195 * Context: Acquires pf->dplls.lock 196 * Return: 197 * * 0 - success 198 * * negative - error pin not found or couldn't set in hw 199 */ 200 static int 201 ice_dpll_frequency_set(const struct dpll_pin *pin, void *pin_priv, 202 const struct dpll_device *dpll, void *dpll_priv, 203 const u32 frequency, 204 struct netlink_ext_ack *extack, 205 enum ice_dpll_pin_type pin_type) 206 { 207 struct ice_dpll_pin *p = pin_priv; 208 struct ice_dpll *d = dpll_priv; 209 struct ice_pf *pf = d->pf; 210 int ret; 211 212 if (ice_dpll_is_reset(pf, extack)) 213 return -EBUSY; 214 215 mutex_lock(&pf->dplls.lock); 216 ret = ice_dpll_pin_freq_set(pf, p, pin_type, frequency, extack); 217 mutex_unlock(&pf->dplls.lock); 218 219 return ret; 220 } 221 222 /** 223 * ice_dpll_input_frequency_set - input pin callback for set frequency 224 * @pin: pointer to a pin 225 * @pin_priv: private data pointer passed on pin registration 226 * @dpll: pointer to dpll 227 * @dpll_priv: private data pointer passed on dpll registration 228 * @frequency: frequency to be set 229 * @extack: error reporting 230 * 231 * Wraps internal set frequency command on a pin. 232 * 233 * Context: Calls a function which acquires pf->dplls.lock 234 * Return: 235 * * 0 - success 236 * * negative - error pin not found or couldn't set in hw 237 */ 238 static int 239 ice_dpll_input_frequency_set(const struct dpll_pin *pin, void *pin_priv, 240 const struct dpll_device *dpll, void *dpll_priv, 241 u64 frequency, struct netlink_ext_ack *extack) 242 { 243 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, 244 extack, ICE_DPLL_PIN_TYPE_INPUT); 245 } 246 247 /** 248 * ice_dpll_output_frequency_set - output pin callback for set frequency 249 * @pin: pointer to a pin 250 * @pin_priv: private data pointer passed on pin registration 251 * @dpll: pointer to dpll 252 * @dpll_priv: private data pointer passed on dpll registration 253 * @frequency: frequency to be set 254 * @extack: error reporting 255 * 256 * Wraps internal set frequency command on a pin. 257 * 258 * Context: Calls a function which acquires pf->dplls.lock 259 * Return: 260 * * 0 - success 261 * * negative - error pin not found or couldn't set in hw 262 */ 263 static int 264 ice_dpll_output_frequency_set(const struct dpll_pin *pin, void *pin_priv, 265 const struct dpll_device *dpll, void *dpll_priv, 266 u64 frequency, struct netlink_ext_ack *extack) 267 { 268 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, 269 extack, ICE_DPLL_PIN_TYPE_OUTPUT); 270 } 271 272 /** 273 * ice_dpll_frequency_get - wrapper for pin callback for get frequency 274 * @pin: pointer to a pin 275 * @pin_priv: private data pointer passed on pin registration 276 * @dpll: pointer to dpll 277 * @dpll_priv: private data pointer passed on dpll registration 278 * @frequency: on success holds pin's frequency 279 * @extack: error reporting 280 * @pin_type: type of pin being configured 281 * 282 * Wraps internal get frequency command of a pin. 283 * 284 * Context: Acquires pf->dplls.lock 285 * Return: 286 * * 0 - success 287 * * negative - error pin not found or couldn't get from hw 288 */ 289 static int 290 ice_dpll_frequency_get(const struct dpll_pin *pin, void *pin_priv, 291 const struct dpll_device *dpll, void *dpll_priv, 292 u64 *frequency, struct netlink_ext_ack *extack, 293 enum ice_dpll_pin_type pin_type) 294 { 295 struct ice_dpll_pin *p = pin_priv; 296 struct ice_dpll *d = dpll_priv; 297 struct ice_pf *pf = d->pf; 298 299 mutex_lock(&pf->dplls.lock); 300 *frequency = p->freq; 301 mutex_unlock(&pf->dplls.lock); 302 303 return 0; 304 } 305 306 /** 307 * ice_dpll_input_frequency_get - input pin callback for get frequency 308 * @pin: pointer to a pin 309 * @pin_priv: private data pointer passed on pin registration 310 * @dpll: pointer to dpll 311 * @dpll_priv: private data pointer passed on dpll registration 312 * @frequency: on success holds pin's frequency 313 * @extack: error reporting 314 * 315 * Wraps internal get frequency command of a input pin. 316 * 317 * Context: Calls a function which acquires pf->dplls.lock 318 * Return: 319 * * 0 - success 320 * * negative - error pin not found or couldn't get from hw 321 */ 322 static int 323 ice_dpll_input_frequency_get(const struct dpll_pin *pin, void *pin_priv, 324 const struct dpll_device *dpll, void *dpll_priv, 325 u64 *frequency, struct netlink_ext_ack *extack) 326 { 327 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, 328 extack, ICE_DPLL_PIN_TYPE_INPUT); 329 } 330 331 /** 332 * ice_dpll_output_frequency_get - output pin callback for get frequency 333 * @pin: pointer to a pin 334 * @pin_priv: private data pointer passed on pin registration 335 * @dpll: pointer to dpll 336 * @dpll_priv: private data pointer passed on dpll registration 337 * @frequency: on success holds pin's frequency 338 * @extack: error reporting 339 * 340 * Wraps internal get frequency command of a pin. 341 * 342 * Context: Calls a function which acquires pf->dplls.lock 343 * Return: 344 * * 0 - success 345 * * negative - error pin not found or couldn't get from hw 346 */ 347 static int 348 ice_dpll_output_frequency_get(const struct dpll_pin *pin, void *pin_priv, 349 const struct dpll_device *dpll, void *dpll_priv, 350 u64 *frequency, struct netlink_ext_ack *extack) 351 { 352 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, 353 extack, ICE_DPLL_PIN_TYPE_OUTPUT); 354 } 355 356 /** 357 * ice_dpll_sw_pin_frequency_set - callback to set frequency of SW pin 358 * @pin: pointer to a pin 359 * @pin_priv: private data pointer passed on pin registration 360 * @dpll: pointer to dpll 361 * @dpll_priv: private data pointer passed on dpll registration 362 * @frequency: on success holds pin's frequency 363 * @extack: error reporting 364 * 365 * Calls set frequency command for corresponding and active input/output pin. 366 * 367 * Context: Calls a function which acquires and releases pf->dplls.lock 368 * Return: 369 * * 0 - success 370 * * negative - error pin not active or couldn't get from hw 371 */ 372 static int 373 ice_dpll_sw_pin_frequency_set(const struct dpll_pin *pin, void *pin_priv, 374 const struct dpll_device *dpll, void *dpll_priv, 375 u64 frequency, struct netlink_ext_ack *extack) 376 { 377 struct ice_dpll_pin *sma = pin_priv; 378 int ret; 379 380 if (!sma->active) { 381 NL_SET_ERR_MSG(extack, "pin is not active"); 382 return -EINVAL; 383 } 384 if (sma->direction == DPLL_PIN_DIRECTION_INPUT) 385 ret = ice_dpll_input_frequency_set(NULL, sma->input, dpll, 386 dpll_priv, frequency, 387 extack); 388 else 389 ret = ice_dpll_output_frequency_set(NULL, sma->output, dpll, 390 dpll_priv, frequency, 391 extack); 392 393 return ret; 394 } 395 396 /** 397 * ice_dpll_sw_pin_frequency_get - callback for get frequency of SW pin 398 * @pin: pointer to a pin 399 * @pin_priv: private data pointer passed on pin registration 400 * @dpll: pointer to dpll 401 * @dpll_priv: private data pointer passed on dpll registration 402 * @frequency: on success holds pin's frequency 403 * @extack: error reporting 404 * 405 * Calls get frequency command for corresponding active input/output. 406 * 407 * Context: Calls a function which acquires and releases pf->dplls.lock 408 * Return: 409 * * 0 - success 410 * * negative - error pin not active or couldn't get from hw 411 */ 412 static int 413 ice_dpll_sw_pin_frequency_get(const struct dpll_pin *pin, void *pin_priv, 414 const struct dpll_device *dpll, void *dpll_priv, 415 u64 *frequency, struct netlink_ext_ack *extack) 416 { 417 struct ice_dpll_pin *sma = pin_priv; 418 int ret; 419 420 if (!sma->active) { 421 *frequency = 0; 422 return 0; 423 } 424 if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { 425 ret = ice_dpll_input_frequency_get(NULL, sma->input, dpll, 426 dpll_priv, frequency, 427 extack); 428 } else { 429 ret = ice_dpll_output_frequency_get(NULL, sma->output, dpll, 430 dpll_priv, frequency, 431 extack); 432 } 433 434 return ret; 435 } 436 437 /** 438 * ice_dpll_pin_enable - enable a pin on dplls 439 * @hw: board private hw structure 440 * @pin: pointer to a pin 441 * @dpll_idx: dpll index to connect to output pin 442 * @pin_type: type of pin being enabled 443 * @extack: error reporting 444 * 445 * Enable a pin on both dplls. Store current state in pin->flags. 446 * 447 * Context: Called under pf->dplls.lock 448 * Return: 449 * * 0 - OK 450 * * negative - error 451 */ 452 static int 453 ice_dpll_pin_enable(struct ice_hw *hw, struct ice_dpll_pin *pin, 454 u8 dpll_idx, enum ice_dpll_pin_type pin_type, 455 struct netlink_ext_ack *extack) 456 { 457 u8 flags = 0; 458 int ret; 459 460 switch (pin_type) { 461 case ICE_DPLL_PIN_TYPE_INPUT: 462 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) 463 flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 464 flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; 465 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); 466 break; 467 case ICE_DPLL_PIN_TYPE_OUTPUT: 468 flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL; 469 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) 470 flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 471 flags |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN; 472 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, dpll_idx, 473 0, 0); 474 break; 475 default: 476 return -EINVAL; 477 } 478 if (ret) 479 NL_SET_ERR_MSG_FMT(extack, 480 "err:%d %s failed to enable %s pin:%u", 481 ret, libie_aq_str(hw->adminq.sq_last_status), 482 pin_type_name[pin_type], pin->idx); 483 484 return ret; 485 } 486 487 /** 488 * ice_dpll_pin_disable - disable a pin on dplls 489 * @hw: board private hw structure 490 * @pin: pointer to a pin 491 * @pin_type: type of pin being disabled 492 * @extack: error reporting 493 * 494 * Disable a pin on both dplls. Store current state in pin->flags. 495 * 496 * Context: Called under pf->dplls.lock 497 * Return: 498 * * 0 - OK 499 * * negative - error 500 */ 501 static int 502 ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin, 503 enum ice_dpll_pin_type pin_type, 504 struct netlink_ext_ack *extack) 505 { 506 u8 flags = 0; 507 int ret; 508 509 switch (pin_type) { 510 case ICE_DPLL_PIN_TYPE_INPUT: 511 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) 512 flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 513 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); 514 break; 515 case ICE_DPLL_PIN_TYPE_OUTPUT: 516 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) 517 flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 518 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, 0, 0, 0); 519 break; 520 default: 521 return -EINVAL; 522 } 523 if (ret) 524 NL_SET_ERR_MSG_FMT(extack, 525 "err:%d %s failed to disable %s pin:%u", 526 ret, libie_aq_str(hw->adminq.sq_last_status), 527 pin_type_name[pin_type], pin->idx); 528 529 return ret; 530 } 531 532 /** 533 * ice_dpll_pin_store_state - updates the state of pin in SW bookkeeping 534 * @pin: pointer to a pin 535 * @parent: parent pin index 536 * @state: pin state (connected or disconnected) 537 */ 538 static void 539 ice_dpll_pin_store_state(struct ice_dpll_pin *pin, int parent, bool state) 540 { 541 pin->state[parent] = state ? DPLL_PIN_STATE_CONNECTED : 542 DPLL_PIN_STATE_DISCONNECTED; 543 } 544 545 /** 546 * ice_dpll_rclk_update_e825c - updates the state of rclk pin on e825c device 547 * @pf: private board struct 548 * @pin: pointer to a pin 549 * 550 * Update struct holding pin states info, states are separate for each parent 551 * 552 * Context: Called under pf->dplls.lock 553 * Return: 554 * * 0 - OK 555 * * negative - error 556 */ 557 static int ice_dpll_rclk_update_e825c(struct ice_pf *pf, 558 struct ice_dpll_pin *pin) 559 { 560 u8 rclk_bits; 561 int err; 562 u32 reg; 563 564 if (pf->dplls.rclk.num_parents > ICE_SYNCE_CLK_NUM) 565 return -EINVAL; 566 567 err = ice_read_cgu_reg(&pf->hw, ICE_CGU_R10, ®); 568 if (err) 569 return err; 570 571 rclk_bits = FIELD_GET(ICE_CGU_R10_SYNCE_S_REF_CLK, reg); 572 ice_dpll_pin_store_state(pin, ICE_SYNCE_CLK0, rclk_bits == 573 (pf->ptp.port.port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C)); 574 575 err = ice_read_cgu_reg(&pf->hw, ICE_CGU_R11, ®); 576 if (err) 577 return err; 578 579 rclk_bits = FIELD_GET(ICE_CGU_R11_SYNCE_S_BYP_CLK, reg); 580 ice_dpll_pin_store_state(pin, ICE_SYNCE_CLK1, rclk_bits == 581 (pf->ptp.port.port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C)); 582 583 return 0; 584 } 585 586 /** 587 * ice_dpll_rclk_update - updates the state of rclk pin on a device 588 * @pf: private board struct 589 * @pin: pointer to a pin 590 * @port_num: port number 591 * 592 * Update struct holding pin states info, states are separate for each parent 593 * 594 * Context: Called under pf->dplls.lock 595 * Return: 596 * * 0 - OK 597 * * negative - error 598 */ 599 static int ice_dpll_rclk_update(struct ice_pf *pf, struct ice_dpll_pin *pin, 600 u8 port_num) 601 { 602 int ret; 603 604 for (u8 parent = 0; parent < pf->dplls.rclk.num_parents; parent++) { 605 u8 p = parent; 606 607 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, &port_num, 608 &pin->flags[parent], NULL); 609 if (ret) 610 return ret; 611 612 ice_dpll_pin_store_state(pin, parent, 613 ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN & 614 pin->flags[parent]); 615 } 616 617 return 0; 618 } 619 620 /** 621 * ice_dpll_sw_pins_update - update status of all SW pins 622 * @pf: private board struct 623 * 624 * Determine and update pin struct fields (direction/active) of their current 625 * values for all the SW controlled pins. 626 * 627 * Context: Call with pf->dplls.lock held 628 * Return: 629 * * 0 - OK 630 * * negative - error 631 */ 632 static int 633 ice_dpll_sw_pins_update(struct ice_pf *pf) 634 { 635 struct ice_dplls *d = &pf->dplls; 636 struct ice_dpll_pin *p; 637 u8 data = 0; 638 int ret; 639 640 ret = ice_read_sma_ctrl(&pf->hw, &data); 641 if (ret) 642 return ret; 643 /* no change since last check */ 644 if (d->sma_data == data) 645 return 0; 646 647 /* 648 * SMA1/U.FL1 vs SMA2/U.FL2 are using different bit scheme to decide 649 * on their direction and if are active 650 */ 651 p = &d->sma[ICE_DPLL_PIN_SW_1_IDX]; 652 p->active = true; 653 p->direction = DPLL_PIN_DIRECTION_INPUT; 654 if (data & ICE_SMA1_DIR_EN) { 655 p->direction = DPLL_PIN_DIRECTION_OUTPUT; 656 if (data & ICE_SMA1_TX_EN) 657 p->active = false; 658 } 659 660 p = &d->sma[ICE_DPLL_PIN_SW_2_IDX]; 661 p->active = true; 662 p->direction = DPLL_PIN_DIRECTION_INPUT; 663 if ((data & ICE_SMA2_INACTIVE_MASK) == ICE_SMA2_INACTIVE_MASK) 664 p->active = false; 665 else if (data & ICE_SMA2_DIR_EN) 666 p->direction = DPLL_PIN_DIRECTION_OUTPUT; 667 668 p = &d->ufl[ICE_DPLL_PIN_SW_1_IDX]; 669 if (!(data & (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN))) 670 p->active = true; 671 else 672 p->active = false; 673 674 p = &d->ufl[ICE_DPLL_PIN_SW_2_IDX]; 675 p->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_DIS); 676 d->sma_data = data; 677 678 return 0; 679 } 680 681 /** 682 * ice_dpll_pin_state_update - update pin's state 683 * @pf: private board struct 684 * @pin: structure with pin attributes to be updated 685 * @pin_type: type of pin being updated 686 * @extack: error reporting 687 * 688 * Determine pin current state and frequency, then update struct 689 * holding the pin info. For input pin states are separated for each 690 * dpll, for rclk pins states are separated for each parent. 691 * 692 * Context: Called under pf->dplls.lock 693 * Return: 694 * * 0 - OK 695 * * negative - error 696 */ 697 static int 698 ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin, 699 enum ice_dpll_pin_type pin_type, 700 struct netlink_ext_ack *extack) 701 { 702 u8 parent, port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 703 int ret; 704 705 switch (pin_type) { 706 case ICE_DPLL_PIN_TYPE_INPUT: 707 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status, 708 NULL, NULL, &pin->flags[0], 709 &pin->freq, &pin->phase_adjust); 710 if (ret) 711 goto err; 712 if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin->flags[0]) { 713 if (pin->pin) { 714 pin->state[pf->dplls.eec.dpll_idx] = 715 pin->pin == pf->dplls.eec.active_input ? 716 DPLL_PIN_STATE_CONNECTED : 717 DPLL_PIN_STATE_SELECTABLE; 718 pin->state[pf->dplls.pps.dpll_idx] = 719 pin->pin == pf->dplls.pps.active_input ? 720 DPLL_PIN_STATE_CONNECTED : 721 DPLL_PIN_STATE_SELECTABLE; 722 } else { 723 pin->state[pf->dplls.eec.dpll_idx] = 724 DPLL_PIN_STATE_SELECTABLE; 725 pin->state[pf->dplls.pps.dpll_idx] = 726 DPLL_PIN_STATE_SELECTABLE; 727 } 728 } else { 729 pin->state[pf->dplls.eec.dpll_idx] = 730 DPLL_PIN_STATE_DISCONNECTED; 731 pin->state[pf->dplls.pps.dpll_idx] = 732 DPLL_PIN_STATE_DISCONNECTED; 733 } 734 break; 735 case ICE_DPLL_PIN_TYPE_OUTPUT: 736 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, 737 &pin->flags[0], &parent, 738 &pin->freq, NULL); 739 if (ret) 740 goto err; 741 742 parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL; 743 if (ICE_AQC_GET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) { 744 pin->state[pf->dplls.eec.dpll_idx] = 745 parent == pf->dplls.eec.dpll_idx ? 746 DPLL_PIN_STATE_CONNECTED : 747 DPLL_PIN_STATE_DISCONNECTED; 748 pin->state[pf->dplls.pps.dpll_idx] = 749 parent == pf->dplls.pps.dpll_idx ? 750 DPLL_PIN_STATE_CONNECTED : 751 DPLL_PIN_STATE_DISCONNECTED; 752 } else { 753 pin->state[pf->dplls.eec.dpll_idx] = 754 DPLL_PIN_STATE_DISCONNECTED; 755 pin->state[pf->dplls.pps.dpll_idx] = 756 DPLL_PIN_STATE_DISCONNECTED; 757 } 758 break; 759 case ICE_DPLL_PIN_TYPE_RCLK_INPUT: 760 if (pf->hw.mac_type == ICE_MAC_GENERIC_3K_E825) { 761 ret = ice_dpll_rclk_update_e825c(pf, pin); 762 if (ret) 763 goto err; 764 } else { 765 ret = ice_dpll_rclk_update(pf, pin, port_num); 766 if (ret) 767 goto err; 768 } 769 break; 770 case ICE_DPLL_PIN_TYPE_SOFTWARE: 771 ret = ice_dpll_sw_pins_update(pf); 772 if (ret) 773 goto err; 774 break; 775 default: 776 return -EINVAL; 777 } 778 779 return 0; 780 err: 781 if (extack) 782 NL_SET_ERR_MSG_FMT(extack, 783 "err:%d %s failed to update %s pin:%u", 784 ret, 785 libie_aq_str(pf->hw.adminq.sq_last_status), 786 pin_type_name[pin_type], pin->idx); 787 else 788 dev_err_ratelimited(ice_pf_to_dev(pf), 789 "err:%d %s failed to update %s pin:%u\n", 790 ret, 791 libie_aq_str(pf->hw.adminq.sq_last_status), 792 pin_type_name[pin_type], pin->idx); 793 return ret; 794 } 795 796 /** 797 * ice_dpll_hw_input_prio_set - set input priority value in hardware 798 * @pf: board private structure 799 * @dpll: ice dpll pointer 800 * @pin: ice pin pointer 801 * @prio: priority value being set on a dpll 802 * @extack: error reporting 803 * 804 * Internal wrapper for setting the priority in the hardware. 805 * 806 * Context: Called under pf->dplls.lock 807 * Return: 808 * * 0 - success 809 * * negative - failure 810 */ 811 static int 812 ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll, 813 struct ice_dpll_pin *pin, const u32 prio, 814 struct netlink_ext_ack *extack) 815 { 816 int ret; 817 818 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, 819 (u8)prio); 820 if (ret) 821 NL_SET_ERR_MSG_FMT(extack, 822 "err:%d %s failed to set pin prio:%u on pin:%u", 823 ret, 824 libie_aq_str(pf->hw.adminq.sq_last_status), 825 prio, pin->idx); 826 else 827 dpll->input_prio[pin->idx] = prio; 828 829 return ret; 830 } 831 832 /** 833 * ice_dpll_lock_status_get - get dpll lock status callback 834 * @dpll: registered dpll pointer 835 * @dpll_priv: private data pointer passed on dpll registration 836 * @status: on success holds dpll's lock status 837 * @status_error: status error value 838 * @extack: error reporting 839 * 840 * Dpll subsystem callback, provides dpll's lock status. 841 * 842 * Context: Acquires pf->dplls.lock 843 * Return: 844 * * 0 - success 845 * * negative - failure 846 */ 847 static int 848 ice_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 849 enum dpll_lock_status *status, 850 enum dpll_lock_status_error *status_error, 851 struct netlink_ext_ack *extack) 852 { 853 struct ice_dpll *d = dpll_priv; 854 struct ice_pf *pf = d->pf; 855 856 mutex_lock(&pf->dplls.lock); 857 *status = d->dpll_state; 858 mutex_unlock(&pf->dplls.lock); 859 860 return 0; 861 } 862 863 /** 864 * ice_dpll_mode_get - get dpll's working mode 865 * @dpll: registered dpll pointer 866 * @dpll_priv: private data pointer passed on dpll registration 867 * @mode: on success holds current working mode of dpll 868 * @extack: error reporting 869 * 870 * Dpll subsystem callback. Provides working mode of dpll. 871 * 872 * Context: Acquires pf->dplls.lock 873 * Return: 874 * * 0 - success 875 * * negative - failure 876 */ 877 static int ice_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 878 enum dpll_mode *mode, 879 struct netlink_ext_ack *extack) 880 { 881 struct ice_dpll *d = dpll_priv; 882 struct ice_pf *pf = d->pf; 883 884 mutex_lock(&pf->dplls.lock); 885 *mode = d->mode; 886 mutex_unlock(&pf->dplls.lock); 887 888 return 0; 889 } 890 891 /** 892 * ice_dpll_phase_offset_monitor_set - set phase offset monitor state 893 * @dpll: registered dpll pointer 894 * @dpll_priv: private data pointer passed on dpll registration 895 * @state: feature state to be set 896 * @extack: error reporting 897 * 898 * Dpll subsystem callback. Enable/disable phase offset monitor feature of dpll. 899 * 900 * Context: Acquires and releases pf->dplls.lock 901 * Return: 0 - success 902 */ 903 static int ice_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 904 void *dpll_priv, 905 enum dpll_feature_state state, 906 struct netlink_ext_ack *extack) 907 { 908 struct ice_dpll *d = dpll_priv; 909 struct ice_pf *pf = d->pf; 910 911 mutex_lock(&pf->dplls.lock); 912 if (state == DPLL_FEATURE_STATE_ENABLE) 913 d->phase_offset_monitor_period = ICE_DPLL_PHASE_OFFSET_PERIOD; 914 else 915 d->phase_offset_monitor_period = 0; 916 mutex_unlock(&pf->dplls.lock); 917 918 return 0; 919 } 920 921 /** 922 * ice_dpll_phase_offset_monitor_get - get phase offset monitor state 923 * @dpll: registered dpll pointer 924 * @dpll_priv: private data pointer passed on dpll registration 925 * @state: on success holds current state of phase offset monitor 926 * @extack: error reporting 927 * 928 * Dpll subsystem callback. Provides current state of phase offset monitor 929 * features on dpll device. 930 * 931 * Context: Acquires and releases pf->dplls.lock 932 * Return: 0 - success 933 */ 934 static int ice_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 935 void *dpll_priv, 936 enum dpll_feature_state *state, 937 struct netlink_ext_ack *extack) 938 { 939 struct ice_dpll *d = dpll_priv; 940 struct ice_pf *pf = d->pf; 941 942 mutex_lock(&pf->dplls.lock); 943 if (d->phase_offset_monitor_period) 944 *state = DPLL_FEATURE_STATE_ENABLE; 945 else 946 *state = DPLL_FEATURE_STATE_DISABLE; 947 mutex_unlock(&pf->dplls.lock); 948 949 return 0; 950 } 951 952 /** 953 * ice_dpll_pin_state_set - set pin's state on dpll 954 * @pin: pointer to a pin 955 * @pin_priv: private data pointer passed on pin registration 956 * @dpll: registered dpll pointer 957 * @dpll_priv: private data pointer passed on dpll registration 958 * @enable: if pin shalll be enabled 959 * @extack: error reporting 960 * @pin_type: type of a pin 961 * 962 * Set pin state on a pin. 963 * 964 * Context: Acquires pf->dplls.lock 965 * Return: 966 * * 0 - OK or no change required 967 * * negative - error 968 */ 969 static int 970 ice_dpll_pin_state_set(const struct dpll_pin *pin, void *pin_priv, 971 const struct dpll_device *dpll, void *dpll_priv, 972 bool enable, struct netlink_ext_ack *extack, 973 enum ice_dpll_pin_type pin_type) 974 { 975 struct ice_dpll_pin *p = pin_priv; 976 struct ice_dpll *d = dpll_priv; 977 struct ice_pf *pf = d->pf; 978 int ret; 979 980 if (ice_dpll_is_reset(pf, extack)) 981 return -EBUSY; 982 983 mutex_lock(&pf->dplls.lock); 984 if (enable) 985 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, 986 extack); 987 else 988 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); 989 if (!ret) 990 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); 991 mutex_unlock(&pf->dplls.lock); 992 993 return ret; 994 } 995 996 /** 997 * ice_dpll_output_state_set - enable/disable output pin on dpll device 998 * @pin: pointer to a pin 999 * @pin_priv: private data pointer passed on pin registration 1000 * @dpll: dpll being configured 1001 * @dpll_priv: private data pointer passed on dpll registration 1002 * @state: state of pin to be set 1003 * @extack: error reporting 1004 * 1005 * Dpll subsystem callback. Set given state on output type pin. 1006 * 1007 * Context: Calls a function which acquires pf->dplls.lock 1008 * Return: 1009 * * 0 - successfully enabled mode 1010 * * negative - failed to enable mode 1011 */ 1012 static int 1013 ice_dpll_output_state_set(const struct dpll_pin *pin, void *pin_priv, 1014 const struct dpll_device *dpll, void *dpll_priv, 1015 enum dpll_pin_state state, 1016 struct netlink_ext_ack *extack) 1017 { 1018 bool enable = state == DPLL_PIN_STATE_CONNECTED; 1019 struct ice_dpll_pin *p = pin_priv; 1020 struct ice_dpll *d = dpll_priv; 1021 1022 if (state == DPLL_PIN_STATE_SELECTABLE) 1023 return -EINVAL; 1024 if (!enable && p->state[d->dpll_idx] == DPLL_PIN_STATE_DISCONNECTED) 1025 return 0; 1026 1027 return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable, 1028 extack, ICE_DPLL_PIN_TYPE_OUTPUT); 1029 } 1030 1031 /** 1032 * ice_dpll_input_state_set - enable/disable input pin on dpll levice 1033 * @pin: pointer to a pin 1034 * @pin_priv: private data pointer passed on pin registration 1035 * @dpll: dpll being configured 1036 * @dpll_priv: private data pointer passed on dpll registration 1037 * @state: state of pin to be set 1038 * @extack: error reporting 1039 * 1040 * Dpll subsystem callback. Enables given mode on input type pin. 1041 * 1042 * Context: Calls a function which acquires pf->dplls.lock 1043 * Return: 1044 * * 0 - successfully enabled mode 1045 * * negative - failed to enable mode 1046 */ 1047 static int 1048 ice_dpll_input_state_set(const struct dpll_pin *pin, void *pin_priv, 1049 const struct dpll_device *dpll, void *dpll_priv, 1050 enum dpll_pin_state state, 1051 struct netlink_ext_ack *extack) 1052 { 1053 bool enable = state == DPLL_PIN_STATE_SELECTABLE; 1054 1055 return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable, 1056 extack, ICE_DPLL_PIN_TYPE_INPUT); 1057 } 1058 1059 /** 1060 * ice_dpll_pin_state_get - set pin's state on dpll 1061 * @pin: pointer to a pin 1062 * @pin_priv: private data pointer passed on pin registration 1063 * @dpll: registered dpll pointer 1064 * @dpll_priv: private data pointer passed on dpll registration 1065 * @state: on success holds state of the pin 1066 * @extack: error reporting 1067 * @pin_type: type of questioned pin 1068 * 1069 * Determine pin state set it on a pin. 1070 * 1071 * Context: Acquires pf->dplls.lock 1072 * Return: 1073 * * 0 - success 1074 * * negative - failed to get state 1075 */ 1076 static int 1077 ice_dpll_pin_state_get(const struct dpll_pin *pin, void *pin_priv, 1078 const struct dpll_device *dpll, void *dpll_priv, 1079 enum dpll_pin_state *state, 1080 struct netlink_ext_ack *extack, 1081 enum ice_dpll_pin_type pin_type) 1082 { 1083 struct ice_dpll_pin *p = pin_priv; 1084 struct ice_dpll *d = dpll_priv; 1085 struct ice_pf *pf = d->pf; 1086 int ret; 1087 1088 if (ice_dpll_is_reset(pf, extack)) 1089 return -EBUSY; 1090 1091 mutex_lock(&pf->dplls.lock); 1092 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); 1093 if (ret) 1094 goto unlock; 1095 if (pin_type == ICE_DPLL_PIN_TYPE_INPUT || 1096 pin_type == ICE_DPLL_PIN_TYPE_OUTPUT) 1097 *state = p->state[d->dpll_idx]; 1098 ret = 0; 1099 unlock: 1100 mutex_unlock(&pf->dplls.lock); 1101 1102 return ret; 1103 } 1104 1105 /** 1106 * ice_dpll_output_state_get - get output pin state on dpll device 1107 * @pin: pointer to a pin 1108 * @pin_priv: private data pointer passed on pin registration 1109 * @dpll: registered dpll pointer 1110 * @dpll_priv: private data pointer passed on dpll registration 1111 * @state: on success holds state of the pin 1112 * @extack: error reporting 1113 * 1114 * Dpll subsystem callback. Check state of a pin. 1115 * 1116 * Context: Calls a function which acquires pf->dplls.lock 1117 * Return: 1118 * * 0 - success 1119 * * negative - failed to get state 1120 */ 1121 static int 1122 ice_dpll_output_state_get(const struct dpll_pin *pin, void *pin_priv, 1123 const struct dpll_device *dpll, void *dpll_priv, 1124 enum dpll_pin_state *state, 1125 struct netlink_ext_ack *extack) 1126 { 1127 return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state, 1128 extack, ICE_DPLL_PIN_TYPE_OUTPUT); 1129 } 1130 1131 /** 1132 * ice_dpll_input_state_get - get input pin state on dpll device 1133 * @pin: pointer to a pin 1134 * @pin_priv: private data pointer passed on pin registration 1135 * @dpll: registered dpll pointer 1136 * @dpll_priv: private data pointer passed on dpll registration 1137 * @state: on success holds state of the pin 1138 * @extack: error reporting 1139 * 1140 * Dpll subsystem callback. Check state of a input pin. 1141 * 1142 * Context: Calls a function which acquires pf->dplls.lock 1143 * Return: 1144 * * 0 - success 1145 * * negative - failed to get state 1146 */ 1147 static int 1148 ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv, 1149 const struct dpll_device *dpll, void *dpll_priv, 1150 enum dpll_pin_state *state, 1151 struct netlink_ext_ack *extack) 1152 { 1153 return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state, 1154 extack, ICE_DPLL_PIN_TYPE_INPUT); 1155 } 1156 1157 /** 1158 * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change 1159 * @d: pointer to dplls struct 1160 * @changed: the SW pin that was explicitly changed (already notified by dpll core) 1161 * 1162 * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and 1163 * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO 1164 * expander, the paired pin's state may also change. Send a change 1165 * notification for the peer pin so userspace consumers monitoring the 1166 * peer via dpll netlink learn about the update. 1167 * 1168 * Context: Called from dpll_pin_ops callbacks after pf->dplls.lock is 1169 * released. Uses __dpll_pin_change_ntf() because dpll_lock is 1170 * still held by the dpll netlink layer. 1171 */ 1172 static void ice_dpll_sw_pin_notify_peer(struct ice_dplls *d, 1173 struct ice_dpll_pin *changed) 1174 { 1175 struct ice_dpll_pin *peer; 1176 1177 peer = (changed >= d->sma && changed < d->sma + ICE_DPLL_PIN_SW_NUM) ? 1178 &d->ufl[changed->idx] : &d->sma[changed->idx]; 1179 if (peer->pin) 1180 __dpll_pin_change_ntf(peer->pin); 1181 } 1182 1183 /** 1184 * ice_dpll_sma_direction_set - set direction of SMA pin 1185 * @p: pointer to a pin 1186 * @direction: requested direction of the pin 1187 * @extack: error reporting 1188 * 1189 * Wrapper for dpll subsystem callback. Set direction of a SMA pin. 1190 * 1191 * Context: Call with pf->dplls.lock held 1192 * Return: 1193 * * 0 - success 1194 * * negative - failed to get state 1195 */ 1196 static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p, 1197 enum dpll_pin_direction direction, 1198 struct netlink_ext_ack *extack) 1199 { 1200 struct ice_dplls *d = &p->pf->dplls; 1201 struct ice_dpll_pin *peer; 1202 u8 data; 1203 int ret; 1204 1205 if (p->direction == direction && p->active) 1206 return 0; 1207 ret = ice_read_sma_ctrl(&p->pf->hw, &data); 1208 if (ret) 1209 return ret; 1210 1211 switch (p->idx) { 1212 case ICE_DPLL_PIN_SW_1_IDX: 1213 data &= ~ICE_SMA1_MASK; 1214 if (direction == DPLL_PIN_DIRECTION_OUTPUT) 1215 data |= ICE_SMA1_DIR_EN; 1216 break; 1217 case ICE_DPLL_PIN_SW_2_IDX: 1218 if (direction == DPLL_PIN_DIRECTION_INPUT) { 1219 data &= ~ICE_SMA2_DIR_EN; 1220 data |= ICE_SMA2_UFL2_RX_DIS; 1221 } else { 1222 data &= ~(ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS); 1223 data |= ICE_SMA2_DIR_EN; 1224 } 1225 break; 1226 default: 1227 return -EINVAL; 1228 } 1229 ret = ice_write_sma_ctrl(&p->pf->hw, data); 1230 if (!ret) 1231 ret = ice_dpll_pin_state_update(p->pf, p, 1232 ICE_DPLL_PIN_TYPE_SOFTWARE, 1233 extack); 1234 if (ret) 1235 return ret; 1236 1237 /* When a direction change activates the paired U.FL pin, enable 1238 * its backing CGU pin so the pin reports as connected. Without 1239 * this the U.FL routing is correct but the CGU pin stays disabled 1240 * and userspace sees the pin as disconnected. Do not disable the 1241 * backing pin when U.FL becomes inactive because the SMA pin may 1242 * still be using it. 1243 */ 1244 peer = &d->ufl[p->idx]; 1245 if (peer->active) { 1246 struct ice_dpll_pin *target; 1247 enum ice_dpll_pin_type type; 1248 1249 if (peer->output) { 1250 target = peer->output; 1251 type = ICE_DPLL_PIN_TYPE_OUTPUT; 1252 } else { 1253 target = peer->input; 1254 type = ICE_DPLL_PIN_TYPE_INPUT; 1255 } 1256 ret = ice_dpll_pin_enable(&p->pf->hw, target, 1257 d->eec.dpll_idx, type, extack); 1258 if (!ret) 1259 ret = ice_dpll_pin_state_update(p->pf, target, 1260 type, extack); 1261 } 1262 1263 return ret; 1264 } 1265 1266 /** 1267 * ice_dpll_ufl_pin_state_set - set U.FL pin state on dpll device 1268 * @pin: pointer to a pin 1269 * @pin_priv: private data pointer passed on pin registration 1270 * @dpll: registered dpll pointer 1271 * @dpll_priv: private data pointer passed on dpll registration 1272 * @state: requested state of the pin 1273 * @extack: error reporting 1274 * 1275 * Dpll subsystem callback. Set the state of a pin. 1276 * 1277 * Context: Acquires and releases pf->dplls.lock 1278 * Return: 1279 * * 0 - success 1280 * * negative - error 1281 */ 1282 static int 1283 ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, 1284 const struct dpll_device *dpll, void *dpll_priv, 1285 enum dpll_pin_state state, 1286 struct netlink_ext_ack *extack) 1287 { 1288 struct ice_dpll_pin *p = pin_priv, *target; 1289 struct ice_dpll *d = dpll_priv; 1290 enum ice_dpll_pin_type type; 1291 struct ice_pf *pf = p->pf; 1292 struct ice_hw *hw; 1293 bool enable; 1294 u8 data; 1295 int ret; 1296 1297 if (ice_dpll_is_reset(pf, extack)) 1298 return -EBUSY; 1299 1300 mutex_lock(&pf->dplls.lock); 1301 hw = &pf->hw; 1302 ret = ice_read_sma_ctrl(hw, &data); 1303 if (ret) 1304 goto unlock; 1305 1306 ret = -EINVAL; 1307 switch (p->idx) { 1308 case ICE_DPLL_PIN_SW_1_IDX: 1309 if (state == DPLL_PIN_STATE_CONNECTED) { 1310 data &= ~ICE_SMA1_MASK; 1311 enable = true; 1312 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 1313 /* Skip if U.FL1 is not active, setting TX_EN 1314 * while DIR_EN is set would also deactivate 1315 * the paired SMA1 output. 1316 */ 1317 if (data & (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)) { 1318 ret = 0; 1319 goto unlock; 1320 } 1321 data |= ICE_SMA1_TX_EN; 1322 enable = false; 1323 } else { 1324 goto unlock; 1325 } 1326 target = p->output; 1327 type = ICE_DPLL_PIN_TYPE_OUTPUT; 1328 break; 1329 case ICE_DPLL_PIN_SW_2_IDX: 1330 if (state == DPLL_PIN_STATE_SELECTABLE) { 1331 data |= ICE_SMA2_DIR_EN; 1332 data &= ~ICE_SMA2_UFL2_RX_DIS; 1333 enable = true; 1334 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 1335 /* Skip if U.FL2 is not active, setting 1336 * UFL2_RX_DIS could also disable the paired 1337 * SMA2 input. 1338 */ 1339 if (!(data & ICE_SMA2_DIR_EN) || 1340 (data & ICE_SMA2_UFL2_RX_DIS)) { 1341 ret = 0; 1342 goto unlock; 1343 } 1344 data |= ICE_SMA2_UFL2_RX_DIS; 1345 enable = false; 1346 } else { 1347 goto unlock; 1348 } 1349 target = p->input; 1350 type = ICE_DPLL_PIN_TYPE_INPUT; 1351 break; 1352 default: 1353 goto unlock; 1354 } 1355 1356 ret = ice_write_sma_ctrl(hw, data); 1357 if (ret) 1358 goto unlock; 1359 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_SOFTWARE, 1360 extack); 1361 if (ret) 1362 goto unlock; 1363 1364 if (enable) 1365 ret = ice_dpll_pin_enable(hw, target, d->dpll_idx, type, extack); 1366 else 1367 ret = ice_dpll_pin_disable(hw, target, type, extack); 1368 if (!ret) 1369 ret = ice_dpll_pin_state_update(pf, target, type, extack); 1370 1371 unlock: 1372 mutex_unlock(&pf->dplls.lock); 1373 if (!ret) 1374 ice_dpll_sw_pin_notify_peer(&pf->dplls, p); 1375 1376 return ret; 1377 } 1378 1379 /** 1380 * ice_dpll_sw_pin_state_get - get SW pin state 1381 * @pin: pointer to a pin 1382 * @pin_priv: private data pointer passed on pin registration 1383 * @dpll: registered dpll pointer 1384 * @dpll_priv: private data pointer passed on dpll registration 1385 * @state: on success holds state of the pin 1386 * @extack: error reporting 1387 * 1388 * Dpll subsystem callback. Check state of a SW pin. 1389 * 1390 * Context: Acquires and releases pf->dplls.lock 1391 * Return: 1392 * * 0 - success 1393 * * negative - error 1394 */ 1395 static int 1396 ice_dpll_sw_pin_state_get(const struct dpll_pin *pin, void *pin_priv, 1397 const struct dpll_device *dpll, void *dpll_priv, 1398 enum dpll_pin_state *state, 1399 struct netlink_ext_ack *extack) 1400 { 1401 struct ice_dpll_pin *p = pin_priv; 1402 struct ice_dpll *d = dpll_priv; 1403 struct ice_pf *pf = p->pf; 1404 int ret = 0; 1405 1406 if (ice_dpll_is_reset(pf, extack)) 1407 return -EBUSY; 1408 mutex_lock(&pf->dplls.lock); 1409 if (!p->active) { 1410 *state = DPLL_PIN_STATE_DISCONNECTED; 1411 goto unlock; 1412 } 1413 1414 if (p->direction == DPLL_PIN_DIRECTION_INPUT) { 1415 ret = ice_dpll_pin_state_update(pf, p->input, 1416 ICE_DPLL_PIN_TYPE_INPUT, 1417 extack); 1418 if (ret) 1419 goto unlock; 1420 *state = p->input->state[d->dpll_idx]; 1421 } else { 1422 ret = ice_dpll_pin_state_update(pf, p->output, 1423 ICE_DPLL_PIN_TYPE_OUTPUT, 1424 extack); 1425 if (ret) 1426 goto unlock; 1427 *state = p->output->state[d->dpll_idx]; 1428 } 1429 unlock: 1430 mutex_unlock(&pf->dplls.lock); 1431 1432 return ret; 1433 } 1434 1435 /** 1436 * ice_dpll_sma_pin_state_set - set SMA pin state on dpll device 1437 * @pin: pointer to a pin 1438 * @pin_priv: private data pointer passed on pin registration 1439 * @dpll: registered dpll pointer 1440 * @dpll_priv: private data pointer passed on dpll registration 1441 * @state: requested state of the pin 1442 * @extack: error reporting 1443 * 1444 * Dpll subsystem callback. Set state of a pin. 1445 * 1446 * Context: Acquires and releases pf->dplls.lock 1447 * Return: 1448 * * 0 - success 1449 * * negative - failed to get state 1450 */ 1451 static int 1452 ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv, 1453 const struct dpll_device *dpll, void *dpll_priv, 1454 enum dpll_pin_state state, 1455 struct netlink_ext_ack *extack) 1456 { 1457 struct ice_dpll_pin *sma = pin_priv, *target; 1458 struct ice_dpll *d = dpll_priv; 1459 struct ice_pf *pf = sma->pf; 1460 enum ice_dpll_pin_type type; 1461 bool enable; 1462 int ret; 1463 1464 if (ice_dpll_is_reset(pf, extack)) 1465 return -EBUSY; 1466 1467 mutex_lock(&pf->dplls.lock); 1468 if (!sma->active) { 1469 ret = ice_dpll_sma_direction_set(sma, sma->direction, extack); 1470 if (ret) 1471 goto unlock; 1472 } 1473 if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { 1474 enable = state == DPLL_PIN_STATE_SELECTABLE; 1475 target = sma->input; 1476 type = ICE_DPLL_PIN_TYPE_INPUT; 1477 } else { 1478 enable = state == DPLL_PIN_STATE_CONNECTED; 1479 target = sma->output; 1480 type = ICE_DPLL_PIN_TYPE_OUTPUT; 1481 } 1482 1483 if (enable) 1484 ret = ice_dpll_pin_enable(&pf->hw, target, d->dpll_idx, type, 1485 extack); 1486 else 1487 ret = ice_dpll_pin_disable(&pf->hw, target, type, extack); 1488 if (!ret) 1489 ret = ice_dpll_pin_state_update(pf, target, type, extack); 1490 1491 unlock: 1492 mutex_unlock(&pf->dplls.lock); 1493 if (!ret) 1494 ice_dpll_sw_pin_notify_peer(&pf->dplls, sma); 1495 1496 return ret; 1497 } 1498 1499 /** 1500 * ice_dpll_input_prio_get - get dpll's input prio 1501 * @pin: pointer to a pin 1502 * @pin_priv: private data pointer passed on pin registration 1503 * @dpll: registered dpll pointer 1504 * @dpll_priv: private data pointer passed on dpll registration 1505 * @prio: on success - returns input priority on dpll 1506 * @extack: error reporting 1507 * 1508 * Dpll subsystem callback. Handler for getting priority of a input pin. 1509 * 1510 * Context: Acquires pf->dplls.lock 1511 * Return: 1512 * * 0 - success 1513 * * negative - failure 1514 */ 1515 static int 1516 ice_dpll_input_prio_get(const struct dpll_pin *pin, void *pin_priv, 1517 const struct dpll_device *dpll, void *dpll_priv, 1518 u32 *prio, struct netlink_ext_ack *extack) 1519 { 1520 struct ice_dpll_pin *p = pin_priv; 1521 struct ice_dpll *d = dpll_priv; 1522 struct ice_pf *pf = d->pf; 1523 1524 mutex_lock(&pf->dplls.lock); 1525 *prio = d->input_prio[p->idx]; 1526 mutex_unlock(&pf->dplls.lock); 1527 1528 return 0; 1529 } 1530 1531 /** 1532 * ice_dpll_input_prio_set - set dpll input prio 1533 * @pin: pointer to a pin 1534 * @pin_priv: private data pointer passed on pin registration 1535 * @dpll: registered dpll pointer 1536 * @dpll_priv: private data pointer passed on dpll registration 1537 * @prio: input priority to be set on dpll 1538 * @extack: error reporting 1539 * 1540 * Dpll subsystem callback. Handler for setting priority of a input pin. 1541 * 1542 * Context: Acquires pf->dplls.lock 1543 * Return: 1544 * * 0 - success 1545 * * negative - failure 1546 */ 1547 static int 1548 ice_dpll_input_prio_set(const struct dpll_pin *pin, void *pin_priv, 1549 const struct dpll_device *dpll, void *dpll_priv, 1550 u32 prio, struct netlink_ext_ack *extack) 1551 { 1552 struct ice_dpll_pin *p = pin_priv; 1553 struct ice_dpll *d = dpll_priv; 1554 struct ice_pf *pf = d->pf; 1555 int ret; 1556 1557 if (ice_dpll_is_reset(pf, extack)) 1558 return -EBUSY; 1559 1560 mutex_lock(&pf->dplls.lock); 1561 ret = ice_dpll_hw_input_prio_set(pf, d, p, prio, extack); 1562 mutex_unlock(&pf->dplls.lock); 1563 1564 return ret; 1565 } 1566 1567 static int 1568 ice_dpll_sw_input_prio_get(const struct dpll_pin *pin, void *pin_priv, 1569 const struct dpll_device *dpll, void *dpll_priv, 1570 u32 *prio, struct netlink_ext_ack *extack) 1571 { 1572 struct ice_dpll_pin *p = pin_priv; 1573 struct ice_dpll *d = dpll_priv; 1574 struct ice_pf *pf = d->pf; 1575 1576 mutex_lock(&pf->dplls.lock); 1577 if (p->input && p->direction == DPLL_PIN_DIRECTION_INPUT) 1578 *prio = d->input_prio[p->input->idx]; 1579 else 1580 *prio = ICE_DPLL_PIN_PRIO_OUTPUT; 1581 mutex_unlock(&pf->dplls.lock); 1582 1583 return 0; 1584 } 1585 1586 static int 1587 ice_dpll_sw_input_prio_set(const struct dpll_pin *pin, void *pin_priv, 1588 const struct dpll_device *dpll, void *dpll_priv, 1589 u32 prio, struct netlink_ext_ack *extack) 1590 { 1591 struct ice_dpll_pin *p = pin_priv; 1592 struct ice_dpll *d = dpll_priv; 1593 struct ice_pf *pf = d->pf; 1594 int ret; 1595 1596 if (!p->input || p->direction != DPLL_PIN_DIRECTION_INPUT) 1597 return -EINVAL; 1598 if (ice_dpll_is_reset(pf, extack)) 1599 return -EBUSY; 1600 1601 mutex_lock(&pf->dplls.lock); 1602 ret = ice_dpll_hw_input_prio_set(pf, d, p->input, prio, extack); 1603 mutex_unlock(&pf->dplls.lock); 1604 1605 return ret; 1606 } 1607 1608 /** 1609 * ice_dpll_input_direction - callback for get input pin direction 1610 * @pin: pointer to a pin 1611 * @pin_priv: private data pointer passed on pin registration 1612 * @dpll: registered dpll pointer 1613 * @dpll_priv: private data pointer passed on dpll registration 1614 * @direction: holds input pin direction 1615 * @extack: error reporting 1616 * 1617 * Dpll subsystem callback. Handler for getting direction of a input pin. 1618 * 1619 * Return: 1620 * * 0 - success 1621 */ 1622 static int 1623 ice_dpll_input_direction(const struct dpll_pin *pin, void *pin_priv, 1624 const struct dpll_device *dpll, void *dpll_priv, 1625 enum dpll_pin_direction *direction, 1626 struct netlink_ext_ack *extack) 1627 { 1628 *direction = DPLL_PIN_DIRECTION_INPUT; 1629 1630 return 0; 1631 } 1632 1633 /** 1634 * ice_dpll_output_direction - callback for get output pin direction 1635 * @pin: pointer to a pin 1636 * @pin_priv: private data pointer passed on pin registration 1637 * @dpll: registered dpll pointer 1638 * @dpll_priv: private data pointer passed on dpll registration 1639 * @direction: holds output pin direction 1640 * @extack: error reporting 1641 * 1642 * Dpll subsystem callback. Handler for getting direction of an output pin. 1643 * 1644 * Return: 1645 * * 0 - success 1646 */ 1647 static int 1648 ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv, 1649 const struct dpll_device *dpll, void *dpll_priv, 1650 enum dpll_pin_direction *direction, 1651 struct netlink_ext_ack *extack) 1652 { 1653 *direction = DPLL_PIN_DIRECTION_OUTPUT; 1654 1655 return 0; 1656 } 1657 1658 /** 1659 * ice_dpll_pin_sma_direction_set - callback for set SMA pin direction 1660 * @pin: pointer to a pin 1661 * @pin_priv: private data pointer passed on pin registration 1662 * @dpll: registered dpll pointer 1663 * @dpll_priv: private data pointer passed on dpll registration 1664 * @direction: requested pin direction 1665 * @extack: error reporting 1666 * 1667 * Dpll subsystem callback. Handler for setting direction of a SMA pin. 1668 * 1669 * Context: Acquires and releases pf->dplls.lock 1670 * Return: 1671 * * 0 - success 1672 * * negative - error 1673 */ 1674 static int 1675 ice_dpll_pin_sma_direction_set(const struct dpll_pin *pin, void *pin_priv, 1676 const struct dpll_device *dpll, void *dpll_priv, 1677 enum dpll_pin_direction direction, 1678 struct netlink_ext_ack *extack) 1679 { 1680 struct ice_dpll_pin *p = pin_priv; 1681 struct ice_pf *pf = p->pf; 1682 int ret; 1683 1684 if (ice_dpll_is_reset(pf, extack)) 1685 return -EBUSY; 1686 1687 mutex_lock(&pf->dplls.lock); 1688 ret = ice_dpll_sma_direction_set(p, direction, extack); 1689 mutex_unlock(&pf->dplls.lock); 1690 if (!ret) 1691 ice_dpll_sw_pin_notify_peer(&pf->dplls, p); 1692 1693 return ret; 1694 } 1695 1696 /** 1697 * ice_dpll_pin_sw_direction_get - callback for get SW pin direction 1698 * @pin: pointer to a pin 1699 * @pin_priv: private data pointer passed on pin registration 1700 * @dpll: registered dpll pointer 1701 * @dpll_priv: private data pointer passed on dpll registration 1702 * @direction: on success holds pin direction 1703 * @extack: error reporting 1704 * 1705 * Dpll subsystem callback. Handler for getting direction of a SMA pin. 1706 * 1707 * Context: Acquires and releases pf->dplls.lock 1708 * Return: 1709 * * 0 - success 1710 * * negative - error 1711 */ 1712 static int 1713 ice_dpll_pin_sw_direction_get(const struct dpll_pin *pin, void *pin_priv, 1714 const struct dpll_device *dpll, void *dpll_priv, 1715 enum dpll_pin_direction *direction, 1716 struct netlink_ext_ack *extack) 1717 { 1718 struct ice_dpll_pin *p = pin_priv; 1719 struct ice_pf *pf = p->pf; 1720 1721 if (ice_dpll_is_reset(pf, extack)) 1722 return -EBUSY; 1723 mutex_lock(&pf->dplls.lock); 1724 *direction = p->direction; 1725 mutex_unlock(&pf->dplls.lock); 1726 1727 return 0; 1728 } 1729 1730 /** 1731 * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value 1732 * @pin: pointer to a pin 1733 * @pin_priv: private data pointer passed on pin registration 1734 * @dpll: registered dpll pointer 1735 * @dpll_priv: private data pointer passed on dpll registration 1736 * @phase_adjust: on success holds pin phase_adjust value 1737 * @extack: error reporting 1738 * 1739 * Dpll subsystem callback. Handler for getting phase adjust value of a pin. 1740 * 1741 * Context: Acquires pf->dplls.lock 1742 * Return: 1743 * * 0 - success 1744 * * negative - error 1745 */ 1746 static int 1747 ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv, 1748 const struct dpll_device *dpll, void *dpll_priv, 1749 s32 *phase_adjust, 1750 struct netlink_ext_ack *extack) 1751 { 1752 struct ice_dpll_pin *p = pin_priv; 1753 struct ice_pf *pf = p->pf; 1754 1755 mutex_lock(&pf->dplls.lock); 1756 *phase_adjust = p->phase_adjust; 1757 mutex_unlock(&pf->dplls.lock); 1758 1759 return 0; 1760 } 1761 1762 /** 1763 * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value 1764 * @pin: pointer to a pin 1765 * @pin_priv: private data pointer passed on pin registration 1766 * @dpll: registered dpll pointer 1767 * @dpll_priv: private data pointer passed on dpll registration 1768 * @phase_adjust: phase_adjust to be set 1769 * @extack: error reporting 1770 * @type: type of a pin 1771 * 1772 * Helper for dpll subsystem callback. Handler for setting phase adjust value 1773 * of a pin. 1774 * 1775 * Context: Acquires pf->dplls.lock 1776 * Return: 1777 * * 0 - success 1778 * * negative - error 1779 */ 1780 static int 1781 ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv, 1782 const struct dpll_device *dpll, void *dpll_priv, 1783 s32 phase_adjust, 1784 struct netlink_ext_ack *extack, 1785 enum ice_dpll_pin_type type) 1786 { 1787 struct ice_dpll_pin *p = pin_priv; 1788 struct ice_dpll *d = dpll_priv; 1789 struct ice_pf *pf = d->pf; 1790 u8 flag, flags_en = 0; 1791 int ret; 1792 1793 if (ice_dpll_is_reset(pf, extack)) 1794 return -EBUSY; 1795 1796 mutex_lock(&pf->dplls.lock); 1797 switch (type) { 1798 case ICE_DPLL_PIN_TYPE_INPUT: 1799 flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY; 1800 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) 1801 flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 1802 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) 1803 flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; 1804 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, 1805 0, phase_adjust); 1806 break; 1807 case ICE_DPLL_PIN_TYPE_OUTPUT: 1808 flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE; 1809 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) 1810 flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN; 1811 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) 1812 flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 1813 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, 1814 phase_adjust); 1815 break; 1816 default: 1817 ret = -EINVAL; 1818 } 1819 if (!ret) 1820 p->phase_adjust = phase_adjust; 1821 mutex_unlock(&pf->dplls.lock); 1822 if (ret) 1823 NL_SET_ERR_MSG_FMT(extack, 1824 "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u", 1825 ret, 1826 libie_aq_str(pf->hw.adminq.sq_last_status), 1827 phase_adjust, p->idx, d->dpll_idx); 1828 1829 return ret; 1830 } 1831 1832 /** 1833 * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust 1834 * @pin: pointer to a pin 1835 * @pin_priv: private data pointer passed on pin registration 1836 * @dpll: registered dpll pointer 1837 * @dpll_priv: private data pointer passed on dpll registration 1838 * @phase_adjust: phase_adjust to be set 1839 * @extack: error reporting 1840 * 1841 * Dpll subsystem callback. Wraps a handler for setting phase adjust on input 1842 * pin. 1843 * 1844 * Context: Calls a function which acquires and releases pf->dplls.lock 1845 * Return: 1846 * * 0 - success 1847 * * negative - error 1848 */ 1849 static int 1850 ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv, 1851 const struct dpll_device *dpll, void *dpll_priv, 1852 s32 phase_adjust, 1853 struct netlink_ext_ack *extack) 1854 { 1855 return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv, 1856 phase_adjust, extack, 1857 ICE_DPLL_PIN_TYPE_INPUT); 1858 } 1859 1860 /** 1861 * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust 1862 * @pin: pointer to a pin 1863 * @pin_priv: private data pointer passed on pin registration 1864 * @dpll: registered dpll pointer 1865 * @dpll_priv: private data pointer passed on dpll registration 1866 * @phase_adjust: phase_adjust to be set 1867 * @extack: error reporting 1868 * 1869 * Dpll subsystem callback. Wraps a handler for setting phase adjust on output 1870 * pin. 1871 * 1872 * Context: Calls a function which acquires pf->dplls.lock 1873 * Return: 1874 * * 0 - success 1875 * * negative - error 1876 */ 1877 static int 1878 ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv, 1879 const struct dpll_device *dpll, void *dpll_priv, 1880 s32 phase_adjust, 1881 struct netlink_ext_ack *extack) 1882 { 1883 return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv, 1884 phase_adjust, extack, 1885 ICE_DPLL_PIN_TYPE_OUTPUT); 1886 } 1887 1888 /** 1889 * ice_dpll_sw_phase_adjust_get - callback for get SW pin phase adjust 1890 * @pin: pointer to a pin 1891 * @pin_priv: private data pointer passed on pin registration 1892 * @dpll: registered dpll pointer 1893 * @dpll_priv: private data pointer passed on dpll registration 1894 * @phase_adjust: on success holds phase adjust value 1895 * @extack: error reporting 1896 * 1897 * Dpll subsystem callback. Wraps a handler for getting phase adjust on sw 1898 * pin. 1899 * 1900 * Context: Calls a function which acquires and releases pf->dplls.lock 1901 * Return: 1902 * * 0 - success 1903 * * negative - error 1904 */ 1905 static int 1906 ice_dpll_sw_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv, 1907 const struct dpll_device *dpll, void *dpll_priv, 1908 s32 *phase_adjust, 1909 struct netlink_ext_ack *extack) 1910 { 1911 struct ice_dpll_pin *p = pin_priv; 1912 1913 if (p->direction == DPLL_PIN_DIRECTION_INPUT) 1914 return ice_dpll_pin_phase_adjust_get(p->input->pin, p->input, 1915 dpll, dpll_priv, 1916 phase_adjust, extack); 1917 else 1918 return ice_dpll_pin_phase_adjust_get(p->output->pin, p->output, 1919 dpll, dpll_priv, 1920 phase_adjust, extack); 1921 } 1922 1923 /** 1924 * ice_dpll_sw_phase_adjust_set - callback for set SW pin phase adjust value 1925 * @pin: pointer to a pin 1926 * @pin_priv: private data pointer passed on pin registration 1927 * @dpll: registered dpll pointer 1928 * @dpll_priv: private data pointer passed on dpll registration 1929 * @phase_adjust: phase_adjust to be set 1930 * @extack: error reporting 1931 * 1932 * Dpll subsystem callback. Wraps a handler for setting phase adjust on output 1933 * pin. 1934 * 1935 * Context: Calls a function which acquires and releases pf->dplls.lock 1936 * Return: 1937 * * 0 - success 1938 * * negative - error 1939 */ 1940 static int 1941 ice_dpll_sw_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv, 1942 const struct dpll_device *dpll, void *dpll_priv, 1943 s32 phase_adjust, 1944 struct netlink_ext_ack *extack) 1945 { 1946 struct ice_dpll_pin *p = pin_priv; 1947 1948 if (!p->active) { 1949 NL_SET_ERR_MSG(extack, "pin is not active"); 1950 return -EINVAL; 1951 } 1952 if (p->direction == DPLL_PIN_DIRECTION_INPUT) 1953 return ice_dpll_pin_phase_adjust_set(p->input->pin, p->input, 1954 dpll, dpll_priv, 1955 phase_adjust, extack, 1956 ICE_DPLL_PIN_TYPE_INPUT); 1957 else 1958 return ice_dpll_pin_phase_adjust_set(p->output->pin, p->output, 1959 dpll, dpll_priv, 1960 phase_adjust, extack, 1961 ICE_DPLL_PIN_TYPE_OUTPUT); 1962 } 1963 1964 #define ICE_DPLL_PHASE_OFFSET_DIVIDER 100 1965 #define ICE_DPLL_PHASE_OFFSET_FACTOR \ 1966 (DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER) 1967 /** 1968 * ice_dpll_phase_offset_get - callback for get dpll phase shift value 1969 * @pin: pointer to a pin 1970 * @pin_priv: private data pointer passed on pin registration 1971 * @dpll: registered dpll pointer 1972 * @dpll_priv: private data pointer passed on dpll registration 1973 * @phase_offset: on success holds pin phase_offset value 1974 * @extack: error reporting 1975 * 1976 * Dpll subsystem callback. Handler for getting phase shift value between 1977 * dpll's input and output. 1978 * 1979 * Context: Acquires pf->dplls.lock 1980 * Return: 1981 * * 0 - success 1982 * * negative - error 1983 */ 1984 static int 1985 ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv, 1986 const struct dpll_device *dpll, void *dpll_priv, 1987 s64 *phase_offset, struct netlink_ext_ack *extack) 1988 { 1989 struct ice_dpll_pin *p = pin_priv; 1990 struct ice_dpll *d = dpll_priv; 1991 struct ice_pf *pf = d->pf; 1992 1993 mutex_lock(&pf->dplls.lock); 1994 if (d->active_input == pin || (p->input && 1995 d->active_input == p->input->pin)) 1996 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; 1997 else if (d->phase_offset_monitor_period) 1998 *phase_offset = (p->input && 1999 p->direction == DPLL_PIN_DIRECTION_INPUT ? 2000 p->input->phase_offset : 2001 p->phase_offset) * ICE_DPLL_PHASE_OFFSET_FACTOR; 2002 else 2003 *phase_offset = 0; 2004 mutex_unlock(&pf->dplls.lock); 2005 2006 return 0; 2007 } 2008 2009 /** 2010 * ice_dpll_synce_update_e825c - setting PHY recovered clock pins on e825c 2011 * @hw: Pointer to the HW struct 2012 * @ena: true if enable, false in disable 2013 * @port_num: port number 2014 * @output: output pin, we have two in E825C 2015 * 2016 * DPLL subsystem callback. Set proper signals to recover clock from port. 2017 * 2018 * Context: Called under pf->dplls.lock 2019 * Return: 2020 * * 0 - success 2021 * * negative - error 2022 */ 2023 static int ice_dpll_synce_update_e825c(struct ice_hw *hw, bool ena, 2024 u32 port_num, enum ice_synce_clk output) 2025 { 2026 int err; 2027 2028 /* configure the mux to deliver proper signal to DPLL from the MUX */ 2029 err = ice_tspll_cfg_bypass_mux_e825c(hw, ena, port_num, output); 2030 if (err) 2031 return err; 2032 2033 err = ice_tspll_cfg_synce_ethdiv_e825c(hw, output); 2034 if (err) 2035 return err; 2036 2037 dev_dbg(ice_hw_to_dev(hw), "CLK_SYNCE%u recovered clock: pin %s\n", 2038 output, str_enabled_disabled(ena)); 2039 2040 return 0; 2041 } 2042 2043 /** 2044 * ice_dpll_output_esync_set - callback for setting embedded sync 2045 * @pin: pointer to a pin 2046 * @pin_priv: private data pointer passed on pin registration 2047 * @dpll: registered dpll pointer 2048 * @dpll_priv: private data pointer passed on dpll registration 2049 * @freq: requested embedded sync frequency 2050 * @extack: error reporting 2051 * 2052 * Dpll subsystem callback. Handler for setting embedded sync frequency value 2053 * on output pin. 2054 * 2055 * Context: Acquires pf->dplls.lock 2056 * Return: 2057 * * 0 - success 2058 * * negative - error 2059 */ 2060 static int 2061 ice_dpll_output_esync_set(const struct dpll_pin *pin, void *pin_priv, 2062 const struct dpll_device *dpll, void *dpll_priv, 2063 u64 freq, struct netlink_ext_ack *extack) 2064 { 2065 struct ice_dpll_pin *p = pin_priv; 2066 struct ice_dpll *d = dpll_priv; 2067 struct ice_pf *pf = d->pf; 2068 u8 flags = 0; 2069 int ret; 2070 2071 if (ice_dpll_is_reset(pf, extack)) 2072 return -EBUSY; 2073 mutex_lock(&pf->dplls.lock); 2074 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) 2075 flags = ICE_AQC_SET_CGU_OUT_CFG_OUT_EN; 2076 if (freq == DPLL_PIN_FREQUENCY_1_HZ) { 2077 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { 2078 ret = 0; 2079 } else { 2080 flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 2081 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, 2082 0, 0, 0); 2083 } 2084 } else { 2085 if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)) { 2086 ret = 0; 2087 } else { 2088 flags &= ~ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 2089 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, 2090 0, 0, 0); 2091 } 2092 } 2093 mutex_unlock(&pf->dplls.lock); 2094 2095 return ret; 2096 } 2097 2098 /** 2099 * ice_dpll_output_esync_get - callback for getting embedded sync config 2100 * @pin: pointer to a pin 2101 * @pin_priv: private data pointer passed on pin registration 2102 * @dpll: registered dpll pointer 2103 * @dpll_priv: private data pointer passed on dpll registration 2104 * @esync: on success holds embedded sync pin properties 2105 * @extack: error reporting 2106 * 2107 * Dpll subsystem callback. Handler for getting embedded sync frequency value 2108 * and capabilities on output pin. 2109 * 2110 * Context: Acquires pf->dplls.lock 2111 * Return: 2112 * * 0 - success 2113 * * negative - error 2114 */ 2115 static int 2116 ice_dpll_output_esync_get(const struct dpll_pin *pin, void *pin_priv, 2117 const struct dpll_device *dpll, void *dpll_priv, 2118 struct dpll_pin_esync *esync, 2119 struct netlink_ext_ack *extack) 2120 { 2121 struct ice_dpll_pin *p = pin_priv; 2122 struct ice_dpll *d = dpll_priv; 2123 struct ice_pf *pf = d->pf; 2124 2125 if (ice_dpll_is_reset(pf, extack)) 2126 return -EBUSY; 2127 mutex_lock(&pf->dplls.lock); 2128 if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY) || 2129 p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { 2130 mutex_unlock(&pf->dplls.lock); 2131 return -EOPNOTSUPP; 2132 } 2133 esync->range = ice_esync_range; 2134 esync->range_num = ARRAY_SIZE(ice_esync_range); 2135 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { 2136 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; 2137 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; 2138 } else { 2139 esync->freq = 0; 2140 esync->pulse = 0; 2141 } 2142 mutex_unlock(&pf->dplls.lock); 2143 2144 return 0; 2145 } 2146 2147 /** 2148 * ice_dpll_input_esync_set - callback for setting embedded sync 2149 * @pin: pointer to a pin 2150 * @pin_priv: private data pointer passed on pin registration 2151 * @dpll: registered dpll pointer 2152 * @dpll_priv: private data pointer passed on dpll registration 2153 * @freq: requested embedded sync frequency 2154 * @extack: error reporting 2155 * 2156 * Dpll subsystem callback. Handler for setting embedded sync frequency value 2157 * on input pin. 2158 * 2159 * Context: Acquires pf->dplls.lock 2160 * Return: 2161 * * 0 - success 2162 * * negative - error 2163 */ 2164 static int 2165 ice_dpll_input_esync_set(const struct dpll_pin *pin, void *pin_priv, 2166 const struct dpll_device *dpll, void *dpll_priv, 2167 u64 freq, struct netlink_ext_ack *extack) 2168 { 2169 struct ice_dpll_pin *p = pin_priv; 2170 struct ice_dpll *d = dpll_priv; 2171 struct ice_pf *pf = d->pf; 2172 u8 flags_en = 0; 2173 int ret; 2174 2175 if (ice_dpll_is_reset(pf, extack)) 2176 return -EBUSY; 2177 mutex_lock(&pf->dplls.lock); 2178 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) 2179 flags_en = ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; 2180 if (freq == DPLL_PIN_FREQUENCY_1_HZ) { 2181 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { 2182 ret = 0; 2183 } else { 2184 flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 2185 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, 2186 flags_en, 0, 0); 2187 } 2188 } else { 2189 if (!(p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)) { 2190 ret = 0; 2191 } else { 2192 flags_en &= ~ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 2193 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, 2194 flags_en, 0, 0); 2195 } 2196 } 2197 mutex_unlock(&pf->dplls.lock); 2198 2199 return ret; 2200 } 2201 2202 /** 2203 * ice_dpll_input_esync_get - callback for getting embedded sync config 2204 * @pin: pointer to a pin 2205 * @pin_priv: private data pointer passed on pin registration 2206 * @dpll: registered dpll pointer 2207 * @dpll_priv: private data pointer passed on dpll registration 2208 * @esync: on success holds embedded sync pin properties 2209 * @extack: error reporting 2210 * 2211 * Dpll subsystem callback. Handler for getting embedded sync frequency value 2212 * and capabilities on input pin. 2213 * 2214 * Context: Acquires pf->dplls.lock 2215 * Return: 2216 * * 0 - success 2217 * * negative - error 2218 */ 2219 static int 2220 ice_dpll_input_esync_get(const struct dpll_pin *pin, void *pin_priv, 2221 const struct dpll_device *dpll, void *dpll_priv, 2222 struct dpll_pin_esync *esync, 2223 struct netlink_ext_ack *extack) 2224 { 2225 struct ice_dpll_pin *p = pin_priv; 2226 struct ice_dpll *d = dpll_priv; 2227 struct ice_pf *pf = d->pf; 2228 2229 if (ice_dpll_is_reset(pf, extack)) 2230 return -EBUSY; 2231 mutex_lock(&pf->dplls.lock); 2232 if (!(p->status & ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP) || 2233 p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { 2234 mutex_unlock(&pf->dplls.lock); 2235 return -EOPNOTSUPP; 2236 } 2237 esync->range = ice_esync_range; 2238 esync->range_num = ARRAY_SIZE(ice_esync_range); 2239 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { 2240 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; 2241 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; 2242 } else { 2243 esync->freq = 0; 2244 esync->pulse = 0; 2245 } 2246 mutex_unlock(&pf->dplls.lock); 2247 2248 return 0; 2249 } 2250 2251 /** 2252 * ice_dpll_sw_esync_set - callback for setting embedded sync on SW pin 2253 * @pin: pointer to a pin 2254 * @pin_priv: private data pointer passed on pin registration 2255 * @dpll: registered dpll pointer 2256 * @dpll_priv: private data pointer passed on dpll registration 2257 * @freq: requested embedded sync frequency 2258 * @extack: error reporting 2259 * 2260 * Dpll subsystem callback. Handler for setting embedded sync frequency value 2261 * on SW pin. 2262 * 2263 * Context: Calls a function which acquires and releases pf->dplls.lock 2264 * Return: 2265 * * 0 - success 2266 * * negative - error 2267 */ 2268 static int 2269 ice_dpll_sw_esync_set(const struct dpll_pin *pin, void *pin_priv, 2270 const struct dpll_device *dpll, void *dpll_priv, 2271 u64 freq, struct netlink_ext_ack *extack) 2272 { 2273 struct ice_dpll_pin *p = pin_priv; 2274 2275 if (!p->active) { 2276 NL_SET_ERR_MSG(extack, "pin is not active"); 2277 return -EINVAL; 2278 } 2279 if (p->direction == DPLL_PIN_DIRECTION_INPUT) 2280 return ice_dpll_input_esync_set(p->input->pin, p->input, dpll, 2281 dpll_priv, freq, extack); 2282 else 2283 return ice_dpll_output_esync_set(p->output->pin, p->output, 2284 dpll, dpll_priv, freq, extack); 2285 } 2286 2287 /** 2288 * ice_dpll_sw_esync_get - callback for getting embedded sync on SW pin 2289 * @pin: pointer to a pin 2290 * @pin_priv: private data pointer passed on pin registration 2291 * @dpll: registered dpll pointer 2292 * @dpll_priv: private data pointer passed on dpll registration 2293 * @esync: on success holds embedded sync frequency and properties 2294 * @extack: error reporting 2295 * 2296 * Dpll subsystem callback. Handler for getting embedded sync frequency value 2297 * of SW pin. 2298 * 2299 * Context: Calls a function which acquires and releases pf->dplls.lock 2300 * Return: 2301 * * 0 - success 2302 * * negative - error 2303 */ 2304 static int 2305 ice_dpll_sw_esync_get(const struct dpll_pin *pin, void *pin_priv, 2306 const struct dpll_device *dpll, void *dpll_priv, 2307 struct dpll_pin_esync *esync, 2308 struct netlink_ext_ack *extack) 2309 { 2310 struct ice_dpll_pin *p = pin_priv; 2311 2312 if (p->direction == DPLL_PIN_DIRECTION_INPUT) 2313 return ice_dpll_input_esync_get(p->input->pin, p->input, dpll, 2314 dpll_priv, esync, extack); 2315 else 2316 return ice_dpll_output_esync_get(p->output->pin, p->output, 2317 dpll, dpll_priv, esync, 2318 extack); 2319 } 2320 2321 /* 2322 * ice_dpll_input_ref_sync_set - callback for setting reference sync feature 2323 * @pin: pointer to a pin 2324 * @pin_priv: private data pointer passed on pin registration 2325 * @ref_pin: pin pointer for reference sync pair 2326 * @ref_pin_priv: private data pointer of ref_pin 2327 * @state: requested state for reference sync for pin pair 2328 * @extack: error reporting 2329 * 2330 * Dpll subsystem callback. Handler for setting reference sync frequency 2331 * feature for input pin. 2332 * 2333 * Context: Acquires and releases pf->dplls.lock 2334 * Return: 2335 * * 0 - success 2336 * * negative - error 2337 */ 2338 static int 2339 ice_dpll_input_ref_sync_set(const struct dpll_pin *pin, void *pin_priv, 2340 const struct dpll_pin *ref_pin, void *ref_pin_priv, 2341 const enum dpll_pin_state state, 2342 struct netlink_ext_ack *extack) 2343 { 2344 struct ice_dpll_pin *p = pin_priv; 2345 struct ice_pf *pf = p->pf; 2346 u8 flags_en = 0; 2347 int ret; 2348 2349 if (ice_dpll_is_reset(pf, extack)) 2350 return -EBUSY; 2351 mutex_lock(&pf->dplls.lock); 2352 2353 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) 2354 flags_en = ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; 2355 if (state == DPLL_PIN_STATE_CONNECTED) 2356 flags_en |= ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN; 2357 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, flags_en, 0, 0); 2358 if (!ret) 2359 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_INPUT, 2360 extack); 2361 mutex_unlock(&pf->dplls.lock); 2362 2363 return ret; 2364 } 2365 2366 /** 2367 * ice_dpll_input_ref_sync_get - callback for getting reference sync config 2368 * @pin: pointer to a pin 2369 * @pin_priv: private data pointer passed on pin registration 2370 * @ref_pin: pin pointer for reference sync pair 2371 * @ref_pin_priv: private data pointer of ref_pin 2372 * @state: on success holds reference sync state for pin pair 2373 * @extack: error reporting 2374 * 2375 * Dpll subsystem callback. Handler for setting reference sync frequency 2376 * feature for input pin. 2377 * 2378 * Context: Acquires and releases pf->dplls.lock 2379 * Return: 2380 * * 0 - success 2381 * * negative - error 2382 */ 2383 static int 2384 ice_dpll_input_ref_sync_get(const struct dpll_pin *pin, void *pin_priv, 2385 const struct dpll_pin *ref_pin, void *ref_pin_priv, 2386 enum dpll_pin_state *state, 2387 struct netlink_ext_ack *extack) 2388 { 2389 struct ice_dpll_pin *p = pin_priv; 2390 struct ice_pf *pf = p->pf; 2391 2392 if (ice_dpll_is_reset(pf, extack)) 2393 return -EBUSY; 2394 mutex_lock(&pf->dplls.lock); 2395 if (p->flags[0] & ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN) 2396 *state = DPLL_PIN_STATE_CONNECTED; 2397 else 2398 *state = DPLL_PIN_STATE_DISCONNECTED; 2399 mutex_unlock(&pf->dplls.lock); 2400 2401 return 0; 2402 } 2403 2404 /* 2405 * ice_dpll_sw_input_ref_sync_set - callback for setting reference sync feature 2406 * @pin: pointer to a pin 2407 * @pin_priv: private data pointer passed on pin registration 2408 * @ref_pin: pin pointer for reference sync pair 2409 * @ref_pin_priv: private data pointer of ref_pin 2410 * @state: requested state for reference sync for pin pair 2411 * @extack: error reporting 2412 * 2413 * Dpll subsystem callback. Handler for setting reference sync 2414 * feature for input pins. 2415 * 2416 * Context: Calls a function which acquires and releases pf->dplls.lock 2417 * Return: 2418 * * 0 - success 2419 * * negative - error 2420 */ 2421 static int 2422 ice_dpll_sw_input_ref_sync_set(const struct dpll_pin *pin, void *pin_priv, 2423 const struct dpll_pin *ref_pin, 2424 void *ref_pin_priv, 2425 const enum dpll_pin_state state, 2426 struct netlink_ext_ack *extack) 2427 { 2428 struct ice_dpll_pin *p = pin_priv; 2429 2430 return ice_dpll_input_ref_sync_set(pin, p->input, ref_pin, ref_pin_priv, 2431 state, extack); 2432 } 2433 2434 /** 2435 * ice_dpll_sw_input_ref_sync_get - callback for getting reference sync config 2436 * @pin: pointer to a pin 2437 * @pin_priv: private data pointer passed on pin registration 2438 * @ref_pin: pin pointer for reference sync pair 2439 * @ref_pin_priv: private data pointer of ref_pin 2440 * @state: on success holds reference sync state for pin pair 2441 * @extack: error reporting 2442 * 2443 * Dpll subsystem callback. Handler for setting reference sync feature for 2444 * input pins. 2445 * 2446 * Context: Calls a function which acquires and releases pf->dplls.lock 2447 * Return: 2448 * * 0 - success 2449 * * negative - error 2450 */ 2451 static int 2452 ice_dpll_sw_input_ref_sync_get(const struct dpll_pin *pin, void *pin_priv, 2453 const struct dpll_pin *ref_pin, 2454 void *ref_pin_priv, 2455 enum dpll_pin_state *state, 2456 struct netlink_ext_ack *extack) 2457 { 2458 struct ice_dpll_pin *p = pin_priv; 2459 2460 return ice_dpll_input_ref_sync_get(pin, p->input, ref_pin, ref_pin_priv, 2461 state, extack); 2462 } 2463 2464 static int 2465 ice_dpll_pin_get_parent_num(struct ice_dpll_pin *pin, 2466 const struct dpll_pin *parent) 2467 { 2468 int i; 2469 2470 for (i = 0; i < pin->num_parents; i++) 2471 if (pin->pf->dplls.inputs[pin->parent_idx[i]].pin == parent) 2472 return i; 2473 2474 return -ENOENT; 2475 } 2476 2477 static int 2478 ice_dpll_pin_get_parent_idx(struct ice_dpll_pin *pin, 2479 const struct dpll_pin *parent) 2480 { 2481 int num = ice_dpll_pin_get_parent_num(pin, parent); 2482 2483 return num < 0 ? num : pin->parent_idx[num]; 2484 } 2485 2486 /** 2487 * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin 2488 * @pin: pointer to a pin 2489 * @pin_priv: private data pointer passed on pin registration 2490 * @parent_pin: pin parent pointer 2491 * @parent_pin_priv: parent private data pointer passed on pin registration 2492 * @state: state to be set on pin 2493 * @extack: error reporting 2494 * 2495 * Dpll subsystem callback, set a state of a rclk pin on a parent pin 2496 * 2497 * Context: Acquires pf->dplls.lock 2498 * Return: 2499 * * 0 - success 2500 * * negative - failure 2501 */ 2502 static int 2503 ice_dpll_rclk_state_on_pin_set(const struct dpll_pin *pin, void *pin_priv, 2504 const struct dpll_pin *parent_pin, 2505 void *parent_pin_priv, 2506 enum dpll_pin_state state, 2507 struct netlink_ext_ack *extack) 2508 { 2509 bool enable = state == DPLL_PIN_STATE_CONNECTED; 2510 struct ice_dpll_pin *p = pin_priv; 2511 struct ice_pf *pf = p->pf; 2512 struct ice_hw *hw; 2513 int ret = -EINVAL; 2514 int hw_idx; 2515 2516 hw = &pf->hw; 2517 2518 if (ice_dpll_is_reset(pf, extack)) 2519 return -EBUSY; 2520 2521 mutex_lock(&pf->dplls.lock); 2522 hw_idx = ice_dpll_pin_get_parent_idx(p, parent_pin); 2523 if (hw_idx < 0) 2524 goto unlock; 2525 hw_idx -= pf->dplls.base_rclk_idx; 2526 if (hw_idx >= ICE_DPLL_RCLK_NUM_MAX) 2527 goto unlock; 2528 2529 if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) || 2530 (!enable && p->state[hw_idx] == DPLL_PIN_STATE_DISCONNECTED)) { 2531 NL_SET_ERR_MSG_FMT(extack, 2532 "pin:%u state:%u on parent:%u already set", 2533 p->idx, state, 2534 ice_dpll_pin_get_parent_num(p, parent_pin)); 2535 goto unlock; 2536 } 2537 2538 ret = hw->mac_type == ICE_MAC_GENERIC_3K_E825 ? 2539 ice_dpll_synce_update_e825c(hw, enable, 2540 pf->ptp.port.port_num, 2541 (enum ice_synce_clk)hw_idx) : 2542 ice_aq_set_phy_rec_clk_out(hw, hw_idx, enable, &p->freq); 2543 if (ret) 2544 NL_SET_ERR_MSG_FMT(extack, 2545 "err:%d %s failed to set pin state:%u for pin:%u on parent:%u", 2546 ret, 2547 libie_aq_str(hw->adminq.sq_last_status), 2548 state, p->idx, 2549 ice_dpll_pin_get_parent_num(p, parent_pin)); 2550 unlock: 2551 mutex_unlock(&pf->dplls.lock); 2552 2553 return ret; 2554 } 2555 2556 /** 2557 * ice_dpll_rclk_state_on_pin_get - get a state of rclk pin 2558 * @pin: pointer to a pin 2559 * @pin_priv: private data pointer passed on pin registration 2560 * @parent_pin: pin parent pointer 2561 * @parent_pin_priv: pin parent priv data pointer passed on pin registration 2562 * @state: on success holds pin state on parent pin 2563 * @extack: error reporting 2564 * 2565 * dpll subsystem callback, get a state of a recovered clock pin. 2566 * 2567 * Context: Acquires pf->dplls.lock 2568 * Return: 2569 * * 0 - success 2570 * * negative - failure 2571 */ 2572 static int 2573 ice_dpll_rclk_state_on_pin_get(const struct dpll_pin *pin, void *pin_priv, 2574 const struct dpll_pin *parent_pin, 2575 void *parent_pin_priv, 2576 enum dpll_pin_state *state, 2577 struct netlink_ext_ack *extack) 2578 { 2579 struct ice_dpll_pin *p = pin_priv; 2580 struct ice_pf *pf = p->pf; 2581 int ret = -EINVAL; 2582 int hw_idx; 2583 2584 if (ice_dpll_is_reset(pf, extack)) 2585 return -EBUSY; 2586 2587 mutex_lock(&pf->dplls.lock); 2588 hw_idx = ice_dpll_pin_get_parent_idx(p, parent_pin); 2589 if (hw_idx < 0) 2590 goto unlock; 2591 hw_idx -= pf->dplls.base_rclk_idx; 2592 if (hw_idx >= ICE_DPLL_RCLK_NUM_MAX) 2593 goto unlock; 2594 2595 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT, 2596 extack); 2597 if (ret) 2598 goto unlock; 2599 2600 *state = p->state[hw_idx]; 2601 ret = 0; 2602 unlock: 2603 mutex_unlock(&pf->dplls.lock); 2604 2605 return ret; 2606 } 2607 2608 static const struct dpll_pin_ops ice_dpll_rclk_ops = { 2609 .state_on_pin_set = ice_dpll_rclk_state_on_pin_set, 2610 .state_on_pin_get = ice_dpll_rclk_state_on_pin_get, 2611 .direction_get = ice_dpll_input_direction, 2612 }; 2613 2614 static const struct dpll_pin_ops ice_dpll_pin_sma_ops = { 2615 .state_on_dpll_set = ice_dpll_sma_pin_state_set, 2616 .state_on_dpll_get = ice_dpll_sw_pin_state_get, 2617 .direction_get = ice_dpll_pin_sw_direction_get, 2618 .direction_set = ice_dpll_pin_sma_direction_set, 2619 .prio_get = ice_dpll_sw_input_prio_get, 2620 .prio_set = ice_dpll_sw_input_prio_set, 2621 .frequency_get = ice_dpll_sw_pin_frequency_get, 2622 .frequency_set = ice_dpll_sw_pin_frequency_set, 2623 .phase_adjust_get = ice_dpll_sw_phase_adjust_get, 2624 .phase_adjust_set = ice_dpll_sw_phase_adjust_set, 2625 .phase_offset_get = ice_dpll_phase_offset_get, 2626 .esync_set = ice_dpll_sw_esync_set, 2627 .esync_get = ice_dpll_sw_esync_get, 2628 .ref_sync_set = ice_dpll_sw_input_ref_sync_set, 2629 .ref_sync_get = ice_dpll_sw_input_ref_sync_get, 2630 }; 2631 2632 static const struct dpll_pin_ops ice_dpll_pin_ufl_ops = { 2633 .state_on_dpll_set = ice_dpll_ufl_pin_state_set, 2634 .state_on_dpll_get = ice_dpll_sw_pin_state_get, 2635 .direction_get = ice_dpll_pin_sw_direction_get, 2636 .prio_get = ice_dpll_sw_input_prio_get, 2637 .prio_set = ice_dpll_sw_input_prio_set, 2638 .frequency_get = ice_dpll_sw_pin_frequency_get, 2639 .frequency_set = ice_dpll_sw_pin_frequency_set, 2640 .esync_set = ice_dpll_sw_esync_set, 2641 .esync_get = ice_dpll_sw_esync_get, 2642 .phase_adjust_get = ice_dpll_sw_phase_adjust_get, 2643 .phase_adjust_set = ice_dpll_sw_phase_adjust_set, 2644 .phase_offset_get = ice_dpll_phase_offset_get, 2645 }; 2646 2647 static const struct dpll_pin_ops ice_dpll_input_ops = { 2648 .frequency_get = ice_dpll_input_frequency_get, 2649 .frequency_set = ice_dpll_input_frequency_set, 2650 .state_on_dpll_get = ice_dpll_input_state_get, 2651 .state_on_dpll_set = ice_dpll_input_state_set, 2652 .prio_get = ice_dpll_input_prio_get, 2653 .prio_set = ice_dpll_input_prio_set, 2654 .direction_get = ice_dpll_input_direction, 2655 .phase_adjust_get = ice_dpll_pin_phase_adjust_get, 2656 .phase_adjust_set = ice_dpll_input_phase_adjust_set, 2657 .phase_offset_get = ice_dpll_phase_offset_get, 2658 .esync_set = ice_dpll_input_esync_set, 2659 .esync_get = ice_dpll_input_esync_get, 2660 .ref_sync_set = ice_dpll_input_ref_sync_set, 2661 .ref_sync_get = ice_dpll_input_ref_sync_get, 2662 }; 2663 2664 static const struct dpll_pin_ops ice_dpll_output_ops = { 2665 .frequency_get = ice_dpll_output_frequency_get, 2666 .frequency_set = ice_dpll_output_frequency_set, 2667 .state_on_dpll_get = ice_dpll_output_state_get, 2668 .state_on_dpll_set = ice_dpll_output_state_set, 2669 .direction_get = ice_dpll_output_direction, 2670 .phase_adjust_get = ice_dpll_pin_phase_adjust_get, 2671 .phase_adjust_set = ice_dpll_output_phase_adjust_set, 2672 .esync_set = ice_dpll_output_esync_set, 2673 .esync_get = ice_dpll_output_esync_get, 2674 }; 2675 2676 static const struct dpll_device_ops ice_dpll_ops = { 2677 .lock_status_get = ice_dpll_lock_status_get, 2678 .mode_get = ice_dpll_mode_get, 2679 }; 2680 2681 static const struct dpll_device_ops ice_dpll_pom_ops = { 2682 .lock_status_get = ice_dpll_lock_status_get, 2683 .mode_get = ice_dpll_mode_get, 2684 .phase_offset_monitor_set = ice_dpll_phase_offset_monitor_set, 2685 .phase_offset_monitor_get = ice_dpll_phase_offset_monitor_get, 2686 }; 2687 2688 /** 2689 * ice_generate_clock_id - generates unique clock_id for registering dpll. 2690 * @pf: board private structure 2691 * 2692 * Generates unique (per board) clock_id for allocation and search of dpll 2693 * devices in Linux dpll subsystem. 2694 * 2695 * Return: generated clock id for the board 2696 */ 2697 static u64 ice_generate_clock_id(struct ice_pf *pf) 2698 { 2699 return pci_get_dsn(pf->pdev); 2700 } 2701 2702 /** 2703 * ice_dpll_pin_ntf - notify pin change including any SW pin wrappers 2704 * @dplls: pointer to dplls struct 2705 * @pin: the dpll_pin that changed 2706 * 2707 * Send a change notification for @pin and for any registered SMA/U.FL pin 2708 * whose backing CGU input matches @pin. 2709 */ 2710 static void ice_dpll_pin_ntf(struct ice_dplls *dplls, struct dpll_pin *pin) 2711 { 2712 dpll_pin_change_ntf(pin); 2713 for (int i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) { 2714 if (dplls->sma[i].pin && dplls->sma[i].input && 2715 dplls->sma[i].input->pin == pin) 2716 dpll_pin_change_ntf(dplls->sma[i].pin); 2717 if (dplls->ufl[i].pin && dplls->ufl[i].input && 2718 dplls->ufl[i].input->pin == pin) 2719 dpll_pin_change_ntf(dplls->ufl[i].pin); 2720 } 2721 } 2722 2723 /** 2724 * ice_dpll_notify_changes - notify dpll subsystem about changes 2725 * @d: pointer do dpll 2726 * 2727 * Once change detected appropriate event is submitted to the dpll subsystem. 2728 */ 2729 static void ice_dpll_notify_changes(struct ice_dpll *d) 2730 { 2731 struct ice_dplls *dplls = &d->pf->dplls; 2732 bool pin_notified = false; 2733 2734 if (d->prev_dpll_state != d->dpll_state) { 2735 d->prev_dpll_state = d->dpll_state; 2736 dpll_device_change_ntf(d->dpll); 2737 } 2738 if (d->prev_input != d->active_input) { 2739 if (d->prev_input) 2740 ice_dpll_pin_ntf(dplls, d->prev_input); 2741 d->prev_input = d->active_input; 2742 if (d->active_input) { 2743 ice_dpll_pin_ntf(dplls, d->active_input); 2744 pin_notified = true; 2745 } 2746 } 2747 if (d->prev_phase_offset != d->phase_offset) { 2748 d->prev_phase_offset = d->phase_offset; 2749 if (!pin_notified && d->active_input) 2750 ice_dpll_pin_ntf(dplls, d->active_input); 2751 } 2752 } 2753 2754 /** 2755 * ice_dpll_is_pps_phase_monitor - check if dpll capable of phase offset monitor 2756 * @pf: pf private structure 2757 * 2758 * Check if firmware is capable of supporting admin command to provide 2759 * phase offset monitoring on all the input pins on PPS dpll. 2760 * 2761 * Returns: 2762 * * true - PPS dpll phase offset monitoring is supported 2763 * * false - PPS dpll phase offset monitoring is not supported 2764 */ 2765 static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf) 2766 { 2767 struct ice_cgu_input_measure meas[ICE_DPLL_INPUT_REF_NUM]; 2768 int ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, 2769 ARRAY_SIZE(meas)); 2770 2771 if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_ESRCH) 2772 return false; 2773 2774 return true; 2775 } 2776 2777 /** 2778 * ice_dpll_pins_notify_mask - notify dpll subsystem about bulk pin changes 2779 * @dplls: pointer to dplls struct 2780 * @pins: array of ice_dpll_pin pointers registered within dpll subsystem 2781 * @pin_num: number of pins 2782 * @phase_offset_ntf_mask: bitmask of pin indexes to notify 2783 * 2784 * Iterate over array of pins and call dpll subsystem pin notify if 2785 * corresponding pin index within bitmask is set. 2786 * 2787 * Context: Must be called while pf->dplls.lock is released. 2788 */ 2789 static void ice_dpll_pins_notify_mask(struct ice_dplls *dplls, 2790 struct ice_dpll_pin *pins, 2791 u8 pin_num, 2792 u32 phase_offset_ntf_mask) 2793 { 2794 for (int i = 0; i < pin_num; i++) 2795 if (phase_offset_ntf_mask & BIT(i)) 2796 ice_dpll_pin_ntf(dplls, pins[i].pin); 2797 } 2798 2799 /** 2800 * ice_dpll_pps_update_phase_offsets - update phase offset measurements 2801 * @pf: pf private structure 2802 * @phase_offset_pins_updated: returns mask of updated input pin indexes 2803 * 2804 * Read phase offset measurements for PPS dpll device and store values in 2805 * input pins array. On success phase_offset_pins_updated - fills bitmask of 2806 * updated input pin indexes, pins shall be notified. 2807 * 2808 * Context: Shall be called with pf->dplls.lock being locked. 2809 * Returns: 2810 * * 0 - success or no data available 2811 * * negative - AQ failure 2812 */ 2813 static int ice_dpll_pps_update_phase_offsets(struct ice_pf *pf, 2814 u32 *phase_offset_pins_updated) 2815 { 2816 struct ice_cgu_input_measure meas[ICE_DPLL_INPUT_REF_NUM]; 2817 struct ice_dpll_pin *p; 2818 s64 phase_offset, tmp; 2819 int i, j, ret; 2820 2821 *phase_offset_pins_updated = 0; 2822 ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, 2823 ARRAY_SIZE(meas)); 2824 if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_EAGAIN) { 2825 return 0; 2826 } else if (ret) { 2827 dev_err(ice_pf_to_dev(pf), 2828 "failed to get input pin measurements dpll=%d, ret=%d %s\n", 2829 DPLL_TYPE_PPS, ret, 2830 libie_aq_str(pf->hw.adminq.sq_last_status)); 2831 return ret; 2832 } 2833 for (i = 0; i < pf->dplls.num_inputs; i++) { 2834 p = &pf->dplls.inputs[i]; 2835 phase_offset = 0; 2836 for (j = 0; j < ICE_CGU_INPUT_PHASE_OFFSET_BYTES; j++) { 2837 tmp = meas[i].phase_offset[j]; 2838 #ifdef __LITTLE_ENDIAN 2839 phase_offset += tmp << 8 * j; 2840 #else 2841 phase_offset += tmp << 8 * 2842 (ICE_CGU_INPUT_PHASE_OFFSET_BYTES - 1 - j); 2843 #endif 2844 } 2845 phase_offset = sign_extend64(phase_offset, 47); 2846 if (p->phase_offset != phase_offset) { 2847 dev_dbg(ice_pf_to_dev(pf), 2848 "phase offset changed for pin:%d old:%llx, new:%llx\n", 2849 p->idx, p->phase_offset, phase_offset); 2850 p->phase_offset = phase_offset; 2851 *phase_offset_pins_updated |= (1 << i); 2852 } 2853 } 2854 2855 return 0; 2856 } 2857 2858 /** 2859 * ice_dpll_update_state - update dpll state 2860 * @pf: pf private structure 2861 * @d: pointer to queried dpll device 2862 * @init: if function called on initialization of ice dpll 2863 * 2864 * Poll current state of dpll from hw and update ice_dpll struct. 2865 * 2866 * Context: Called by kworker under pf->dplls.lock 2867 * Return: 2868 * * 0 - success 2869 * * negative - AQ failure 2870 */ 2871 static int 2872 ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init) 2873 { 2874 struct ice_dpll_pin *p = NULL; 2875 int ret; 2876 2877 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, 2878 &d->input_idx, &d->ref_state, &d->eec_mode, 2879 &d->phase_offset, &d->dpll_state); 2880 2881 dev_dbg(ice_pf_to_dev(pf), 2882 "update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n", 2883 d->dpll_idx, d->prev_input_idx, d->input_idx, 2884 d->dpll_state, d->prev_dpll_state, d->mode); 2885 if (ret) { 2886 dev_err(ice_pf_to_dev(pf), 2887 "update dpll=%d state failed, ret=%d %s\n", 2888 d->dpll_idx, ret, 2889 libie_aq_str(pf->hw.adminq.sq_last_status)); 2890 return ret; 2891 } 2892 if (init) { 2893 if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED || 2894 d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ) 2895 d->active_input = pf->dplls.inputs[d->input_idx].pin; 2896 p = &pf->dplls.inputs[d->input_idx]; 2897 return ice_dpll_pin_state_update(pf, p, 2898 ICE_DPLL_PIN_TYPE_INPUT, NULL); 2899 } 2900 if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER || 2901 d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) { 2902 d->active_input = NULL; 2903 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) 2904 p = &pf->dplls.inputs[d->input_idx]; 2905 d->prev_input_idx = ICE_DPLL_PIN_IDX_INVALID; 2906 d->input_idx = ICE_DPLL_PIN_IDX_INVALID; 2907 if (!p) 2908 return 0; 2909 ret = ice_dpll_pin_state_update(pf, p, 2910 ICE_DPLL_PIN_TYPE_INPUT, NULL); 2911 } else if (d->input_idx != d->prev_input_idx) { 2912 if (d->prev_input_idx != ICE_DPLL_PIN_IDX_INVALID) { 2913 p = &pf->dplls.inputs[d->prev_input_idx]; 2914 ice_dpll_pin_state_update(pf, p, 2915 ICE_DPLL_PIN_TYPE_INPUT, 2916 NULL); 2917 } 2918 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) { 2919 p = &pf->dplls.inputs[d->input_idx]; 2920 d->active_input = p->pin; 2921 ice_dpll_pin_state_update(pf, p, 2922 ICE_DPLL_PIN_TYPE_INPUT, 2923 NULL); 2924 } 2925 d->prev_input_idx = d->input_idx; 2926 } 2927 2928 return ret; 2929 } 2930 2931 /** 2932 * ice_dpll_periodic_work - DPLLs periodic worker 2933 * @work: pointer to kthread_work structure 2934 * 2935 * DPLLs periodic worker is responsible for polling state of dpll. 2936 * Context: Holds pf->dplls.lock 2937 */ 2938 static void ice_dpll_periodic_work(struct kthread_work *work) 2939 { 2940 struct ice_dplls *d = container_of(work, struct ice_dplls, work.work); 2941 struct ice_pf *pf = container_of(d, struct ice_pf, dplls); 2942 struct ice_dpll *de = &pf->dplls.eec; 2943 struct ice_dpll *dp = &pf->dplls.pps; 2944 u32 phase_offset_ntf = 0; 2945 int ret = 0; 2946 2947 if (ice_is_reset_in_progress(pf->state)) 2948 goto resched; 2949 mutex_lock(&pf->dplls.lock); 2950 d->periodic_counter++; 2951 ret = ice_dpll_update_state(pf, de, false); 2952 if (!ret) 2953 ret = ice_dpll_update_state(pf, dp, false); 2954 if (!ret && dp->phase_offset_monitor_period && 2955 d->periodic_counter % dp->phase_offset_monitor_period == 0) 2956 ret = ice_dpll_pps_update_phase_offsets(pf, &phase_offset_ntf); 2957 if (ret) { 2958 d->cgu_state_acq_err_num++; 2959 /* stop rescheduling this worker */ 2960 if (d->cgu_state_acq_err_num > 2961 ICE_CGU_STATE_ACQ_ERR_THRESHOLD) { 2962 dev_err(ice_pf_to_dev(pf), 2963 "EEC/PPS DPLLs periodic work disabled\n"); 2964 mutex_unlock(&pf->dplls.lock); 2965 return; 2966 } 2967 } 2968 mutex_unlock(&pf->dplls.lock); 2969 ice_dpll_notify_changes(de); 2970 ice_dpll_notify_changes(dp); 2971 if (phase_offset_ntf) 2972 ice_dpll_pins_notify_mask(d, d->inputs, d->num_inputs, 2973 phase_offset_ntf); 2974 2975 resched: 2976 /* Run twice a second or reschedule if update failed */ 2977 kthread_queue_delayed_work(d->kworker, &d->work, 2978 ret ? msecs_to_jiffies(10) : 2979 msecs_to_jiffies(500)); 2980 } 2981 2982 /** 2983 * ice_dpll_init_ref_sync_inputs - initialize reference sync pin pairs 2984 * @pf: pf private structure 2985 * 2986 * Read DPLL TLV capabilities and initialize reference sync pin pairs in 2987 * dpll subsystem. 2988 * 2989 * Return: 2990 * * 0 - success or nothing to do (no ref-sync tlv are present) 2991 * * negative - AQ failure 2992 */ 2993 static int ice_dpll_init_ref_sync_inputs(struct ice_pf *pf) 2994 { 2995 struct ice_dpll_pin *inputs = pf->dplls.inputs; 2996 struct ice_hw *hw = &pf->hw; 2997 u16 addr, len, end, hdr; 2998 int ret; 2999 3000 ret = ice_get_pfa_module_tlv(hw, &hdr, &len, ICE_SR_PFA_DPLL_DEFAULTS); 3001 if (ret) { 3002 dev_err(ice_pf_to_dev(pf), 3003 "Failed to read PFA dpll defaults TLV ret=%d\n", ret); 3004 return ret; 3005 } 3006 end = hdr + len; 3007 3008 for (addr = hdr + ICE_DPLL_PFA_HEADER_LEN; addr < end; 3009 addr += ICE_DPLL_PFA_ENTRY_LEN) { 3010 unsigned long bit, ul_mask, offset; 3011 u16 pin, mask, buf; 3012 bool valid = false; 3013 3014 ret = ice_read_sr_word(hw, addr, &buf); 3015 if (ret) 3016 return ret; 3017 3018 switch (buf) { 3019 case ICE_DPLL_PFA_REF_SYNC_TYPE: 3020 case ICE_DPLL_PFA_REF_SYNC_TYPE2: 3021 { 3022 u16 mask_addr = addr + ICE_DPLL_PFA_MASK_OFFSET; 3023 u16 val_addr = addr + ICE_DPLL_PFA_VALUE_OFFSET; 3024 3025 ret = ice_read_sr_word(hw, mask_addr, &mask); 3026 if (ret) 3027 return ret; 3028 ret = ice_read_sr_word(hw, val_addr, &pin); 3029 if (ret) 3030 return ret; 3031 if (buf == ICE_DPLL_PFA_REF_SYNC_TYPE) 3032 pin >>= ICE_DPLL_PFA_MAILBOX_REF_SYNC_PIN_S; 3033 valid = true; 3034 break; 3035 } 3036 case ICE_DPLL_PFA_END: 3037 addr = end; 3038 break; 3039 default: 3040 continue; 3041 } 3042 if (!valid) 3043 continue; 3044 3045 ul_mask = mask; 3046 offset = 0; 3047 for_each_set_bit(bit, &ul_mask, BITS_PER_TYPE(u16)) { 3048 int i, j; 3049 3050 if (hw->device_id == ICE_DEV_ID_E810C_SFP && 3051 pin > ICE_DPLL_E810C_SFP_NC_START) 3052 offset = -ICE_DPLL_E810C_SFP_NC_PINS; 3053 i = pin + offset; 3054 j = bit + offset; 3055 if (i < 0 || j < 0) 3056 return -ERANGE; 3057 inputs[i].ref_sync = j; 3058 } 3059 } 3060 3061 return 0; 3062 } 3063 3064 /** 3065 * ice_dpll_release_pins - release pins resources from dpll subsystem 3066 * @pins: pointer to pins array 3067 * @count: number of pins 3068 * 3069 * Release resources of given pins array in the dpll subsystem. 3070 */ 3071 static void ice_dpll_release_pins(struct ice_dpll_pin *pins, int count) 3072 { 3073 int i; 3074 3075 for (i = 0; i < count; i++) 3076 if (!IS_ERR_OR_NULL(pins[i].pin)) 3077 dpll_pin_put(pins[i].pin, &pins[i].tracker); 3078 } 3079 3080 /** 3081 * ice_dpll_get_pins - get pins from dpll subsystem 3082 * @pf: board private structure 3083 * @pins: pointer to pins array 3084 * @start_idx: get starts from this pin idx value 3085 * @count: number of pins 3086 * @clock_id: clock_id of dpll device 3087 * 3088 * Get pins - allocate - in dpll subsystem, store them in pin field of given 3089 * pins array. 3090 * 3091 * Return: 3092 * * 0 - success 3093 * * negative - allocation failure reason 3094 */ 3095 static int 3096 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, 3097 int start_idx, int count, u64 clock_id) 3098 { 3099 u32 pin_index; 3100 int i, ret; 3101 3102 for (i = 0; i < count; i++) { 3103 pin_index = start_idx; 3104 if (start_idx != DPLL_PIN_IDX_UNSPEC) 3105 pin_index += i; 3106 pins[i].pin = dpll_pin_get(clock_id, pin_index, THIS_MODULE, 3107 &pins[i].prop, &pins[i].tracker); 3108 if (IS_ERR(pins[i].pin)) { 3109 ret = PTR_ERR(pins[i].pin); 3110 goto release_pins; 3111 } 3112 } 3113 3114 return 0; 3115 3116 release_pins: 3117 while (--i >= 0) 3118 dpll_pin_put(pins[i].pin, &pins[i].tracker); 3119 return ret; 3120 } 3121 3122 /** 3123 * ice_dpll_unregister_pins - unregister pins from a dpll 3124 * @dpll: dpll device pointer 3125 * @pins: pointer to pins array 3126 * @ops: callback ops registered with the pins 3127 * @count: number of pins 3128 * 3129 * Unregister pins of a given array of pins from given dpll device registered in 3130 * dpll subsystem. 3131 */ 3132 static void 3133 ice_dpll_unregister_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins, 3134 const struct dpll_pin_ops *ops, int count) 3135 { 3136 int i; 3137 3138 for (i = 0; i < count; i++) 3139 if (!pins[i].hidden) 3140 dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]); 3141 } 3142 3143 /** 3144 * ice_dpll_pin_ref_sync_register - register reference sync pins 3145 * @pins: pointer to pins array 3146 * @count: number of pins 3147 * 3148 * Register reference sync pins in dpll subsystem. 3149 * 3150 * Return: 3151 * * 0 - success 3152 * * negative - registration failure reason 3153 */ 3154 static int 3155 ice_dpll_pin_ref_sync_register(struct ice_dpll_pin *pins, int count) 3156 { 3157 int ret, i; 3158 3159 for (i = 0; i < count; i++) { 3160 if (!pins[i].hidden && pins[i].ref_sync) { 3161 int j = pins[i].ref_sync; 3162 3163 ret = dpll_pin_ref_sync_pair_add(pins[i].pin, 3164 pins[j].pin); 3165 if (ret) 3166 return ret; 3167 } 3168 } 3169 3170 return 0; 3171 } 3172 3173 /** 3174 * ice_dpll_register_pins - register pins with a dpll 3175 * @dpll: dpll pointer to register pins with 3176 * @pins: pointer to pins array 3177 * @ops: callback ops registered with the pins 3178 * @count: number of pins 3179 * 3180 * Register pins of a given array with given dpll in dpll subsystem. 3181 * 3182 * Return: 3183 * * 0 - success 3184 * * negative - registration failure reason 3185 */ 3186 static int 3187 ice_dpll_register_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins, 3188 const struct dpll_pin_ops *ops, int count) 3189 { 3190 int ret, i; 3191 3192 for (i = 0; i < count; i++) { 3193 if (!pins[i].hidden) { 3194 ret = dpll_pin_register(dpll, pins[i].pin, ops, &pins[i]); 3195 if (ret) 3196 goto unregister_pins; 3197 } 3198 } 3199 3200 return 0; 3201 3202 unregister_pins: 3203 while (--i >= 0) 3204 if (!pins[i].hidden) 3205 dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]); 3206 return ret; 3207 } 3208 3209 /** 3210 * ice_dpll_deinit_direct_pins - deinitialize direct pins 3211 * @pf: board private structure 3212 * @cgu: if cgu is present and controlled by this NIC 3213 * @pins: pointer to pins array 3214 * @count: number of pins 3215 * @ops: callback ops registered with the pins 3216 * @first: dpll device pointer 3217 * @second: dpll device pointer 3218 * 3219 * If cgu is owned unregister pins from given dplls. 3220 * Release pins resources to the dpll subsystem. 3221 */ 3222 static void 3223 ice_dpll_deinit_direct_pins(struct ice_pf *pf, bool cgu, 3224 struct ice_dpll_pin *pins, int count, 3225 const struct dpll_pin_ops *ops, 3226 struct dpll_device *first, 3227 struct dpll_device *second) 3228 { 3229 if (cgu) { 3230 ice_dpll_unregister_pins(first, pins, ops, count); 3231 ice_dpll_unregister_pins(second, pins, ops, count); 3232 } 3233 ice_dpll_release_pins(pins, count); 3234 } 3235 3236 /** 3237 * ice_dpll_init_direct_pins - initialize direct pins 3238 * @pf: board private structure 3239 * @cgu: if cgu is present and controlled by this NIC 3240 * @pins: pointer to pins array 3241 * @start_idx: on which index shall allocation start in dpll subsystem 3242 * @count: number of pins 3243 * @ops: callback ops registered with the pins 3244 * @first: dpll device pointer 3245 * @second: dpll device pointer 3246 * 3247 * Allocate directly connected pins of a given array in dpll subsystem. 3248 * If cgu is owned register allocated pins with given dplls. 3249 * 3250 * Return: 3251 * * 0 - success 3252 * * negative - registration failure reason 3253 */ 3254 static int 3255 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu, 3256 struct ice_dpll_pin *pins, int start_idx, int count, 3257 const struct dpll_pin_ops *ops, 3258 struct dpll_device *first, struct dpll_device *second) 3259 { 3260 int ret; 3261 3262 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); 3263 if (ret) 3264 return ret; 3265 if (cgu) { 3266 ret = ice_dpll_register_pins(first, pins, ops, count); 3267 if (ret) 3268 goto release_pins; 3269 ret = ice_dpll_register_pins(second, pins, ops, count); 3270 if (ret) 3271 goto unregister_first; 3272 } 3273 3274 return 0; 3275 3276 unregister_first: 3277 ice_dpll_unregister_pins(first, pins, ops, count); 3278 release_pins: 3279 ice_dpll_release_pins(pins, count); 3280 return ret; 3281 } 3282 3283 /** 3284 * ice_dpll_deinit_rclk_pin - release rclk pin resources 3285 * @pf: board private structure 3286 * 3287 * Deregister rclk pin from parent pins and release resources in dpll subsystem. 3288 */ 3289 static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf) 3290 { 3291 struct ice_dpll_pin *rclk = &pf->dplls.rclk; 3292 struct ice_vsi *vsi = ice_get_main_vsi(pf); 3293 struct ice_dpll_pin *parent; 3294 int i; 3295 3296 for (i = 0; i < rclk->num_parents; i++) { 3297 parent = &pf->dplls.inputs[rclk->parent_idx[i]]; 3298 if (IS_ERR_OR_NULL(parent->pin)) 3299 continue; 3300 dpll_pin_on_pin_unregister(parent->pin, rclk->pin, 3301 &ice_dpll_rclk_ops, rclk); 3302 } 3303 if (WARN_ON_ONCE(!vsi || !vsi->netdev)) 3304 return; 3305 dpll_netdev_pin_clear(vsi->netdev); 3306 dpll_pin_put(rclk->pin, &rclk->tracker); 3307 } 3308 3309 static bool ice_dpll_is_fwnode_pin(struct ice_dpll_pin *pin) 3310 { 3311 return !IS_ERR_OR_NULL(pin->fwnode); 3312 } 3313 3314 static void ice_dpll_pin_notify_work(struct work_struct *work) 3315 { 3316 struct ice_dpll_pin_work *w = container_of(work, 3317 struct ice_dpll_pin_work, 3318 work); 3319 struct ice_dpll_pin *pin, *parent = w->pin; 3320 struct ice_pf *pf = parent->pf; 3321 int ret; 3322 3323 wait_for_completion(&pf->dplls.dpll_init); 3324 if (!test_bit(ICE_FLAG_DPLL, pf->flags)) 3325 goto out; /* DPLL initialization failed */ 3326 3327 switch (w->action) { 3328 case DPLL_PIN_CREATED: 3329 if (!IS_ERR_OR_NULL(parent->pin)) { 3330 /* We have already our pin registered */ 3331 goto out; 3332 } 3333 3334 /* Grab reference on fwnode pin */ 3335 parent->pin = fwnode_dpll_pin_find(parent->fwnode, 3336 &parent->tracker); 3337 if (IS_ERR_OR_NULL(parent->pin)) { 3338 dev_err(ice_pf_to_dev(pf), 3339 "Cannot get fwnode pin reference\n"); 3340 goto out; 3341 } 3342 3343 /* Register rclk pin */ 3344 pin = &pf->dplls.rclk; 3345 ret = dpll_pin_on_pin_register(parent->pin, pin->pin, 3346 &ice_dpll_rclk_ops, pin); 3347 if (ret) { 3348 dev_err(ice_pf_to_dev(pf), 3349 "Failed to register pin: %pe\n", ERR_PTR(ret)); 3350 dpll_pin_put(parent->pin, &parent->tracker); 3351 parent->pin = NULL; 3352 goto out; 3353 } 3354 break; 3355 case DPLL_PIN_DELETED: 3356 if (IS_ERR_OR_NULL(parent->pin)) { 3357 /* We have already our pin unregistered */ 3358 goto out; 3359 } 3360 3361 /* Unregister rclk pin */ 3362 pin = &pf->dplls.rclk; 3363 dpll_pin_on_pin_unregister(parent->pin, pin->pin, 3364 &ice_dpll_rclk_ops, pin); 3365 3366 /* Drop fwnode pin reference */ 3367 dpll_pin_put(parent->pin, &parent->tracker); 3368 parent->pin = NULL; 3369 break; 3370 default: 3371 break; 3372 } 3373 out: 3374 kfree(w); 3375 } 3376 3377 static int ice_dpll_pin_notify(struct notifier_block *nb, unsigned long action, 3378 void *data) 3379 { 3380 struct ice_dpll_pin *pin = container_of(nb, struct ice_dpll_pin, nb); 3381 struct dpll_pin_notifier_info *info = data; 3382 struct ice_dpll_pin_work *work; 3383 3384 if (action != DPLL_PIN_CREATED && action != DPLL_PIN_DELETED) 3385 return NOTIFY_DONE; 3386 3387 /* Check if the reported pin is this one */ 3388 if (pin->fwnode != info->fwnode) 3389 return NOTIFY_DONE; /* Not this pin */ 3390 3391 work = kzalloc_obj(*work); 3392 if (!work) 3393 return NOTIFY_DONE; 3394 3395 INIT_WORK(&work->work, ice_dpll_pin_notify_work); 3396 work->action = action; 3397 work->pin = pin; 3398 3399 queue_work(pin->pf->dplls.wq, &work->work); 3400 3401 return NOTIFY_OK; 3402 } 3403 3404 /** 3405 * ice_dpll_init_pin_common - initialize pin 3406 * @pf: board private structure 3407 * @pin: pin to register 3408 * @start_idx: on which index shall allocation start in dpll subsystem 3409 * @ops: callback ops registered with the pins 3410 * 3411 * Allocate resource for given pin in dpll subsystem. Register the pin with 3412 * the parents it has in the info. 3413 * 3414 * Return: 3415 * * 0 - success 3416 * * negative - registration failure reason 3417 */ 3418 static int 3419 ice_dpll_init_pin_common(struct ice_pf *pf, struct ice_dpll_pin *pin, 3420 int start_idx, const struct dpll_pin_ops *ops) 3421 { 3422 struct ice_dpll_pin *parent; 3423 int ret, i; 3424 3425 ret = ice_dpll_get_pins(pf, pin, start_idx, 1, pf->dplls.clock_id); 3426 if (ret) 3427 return ret; 3428 3429 for (i = 0; i < pin->num_parents; i++) { 3430 parent = &pf->dplls.inputs[pin->parent_idx[i]]; 3431 if (IS_ERR_OR_NULL(parent->pin)) { 3432 if (!ice_dpll_is_fwnode_pin(parent)) { 3433 ret = -ENODEV; 3434 goto unregister_pins; 3435 } 3436 parent->pin = fwnode_dpll_pin_find(parent->fwnode, 3437 &parent->tracker); 3438 if (IS_ERR_OR_NULL(parent->pin)) { 3439 dev_info(ice_pf_to_dev(pf), 3440 "Mux pin not registered yet\n"); 3441 continue; 3442 } 3443 } 3444 ret = dpll_pin_on_pin_register(parent->pin, pin->pin, ops, pin); 3445 if (ret) 3446 goto unregister_pins; 3447 } 3448 3449 return 0; 3450 3451 unregister_pins: 3452 while (i) { 3453 parent = &pf->dplls.inputs[pin->parent_idx[--i]]; 3454 if (IS_ERR_OR_NULL(parent->pin)) 3455 continue; 3456 dpll_pin_on_pin_unregister(parent->pin, pin->pin, ops, pin); 3457 } 3458 ice_dpll_release_pins(pin, 1); 3459 3460 return ret; 3461 } 3462 3463 /** 3464 * ice_dpll_init_rclk_pin - initialize recovered clock pin 3465 * @pf: board private structure 3466 * @start_idx: on which index shall allocation start in dpll subsystem 3467 * @ops: callback ops registered with the pins 3468 * 3469 * Allocate resource for recovered clock pin in dpll subsystem. Register the 3470 * pin with the parents it has in the info. 3471 * 3472 * Return: 3473 * * 0 - success 3474 * * negative - registration failure reason 3475 */ 3476 static int 3477 ice_dpll_init_rclk_pin(struct ice_pf *pf, int start_idx, 3478 const struct dpll_pin_ops *ops) 3479 { 3480 struct ice_vsi *vsi = ice_get_main_vsi(pf); 3481 int ret; 3482 3483 ret = ice_dpll_init_pin_common(pf, &pf->dplls.rclk, start_idx, ops); 3484 if (ret) 3485 return ret; 3486 3487 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); 3488 3489 return 0; 3490 } 3491 3492 static void 3493 ice_dpll_deinit_fwnode_pin(struct ice_dpll_pin *pin) 3494 { 3495 unregister_dpll_notifier(&pin->nb); 3496 flush_workqueue(pin->pf->dplls.wq); 3497 if (!IS_ERR_OR_NULL(pin->pin)) { 3498 dpll_pin_put(pin->pin, &pin->tracker); 3499 pin->pin = NULL; 3500 } 3501 fwnode_handle_put(pin->fwnode); 3502 pin->fwnode = NULL; 3503 } 3504 3505 static void 3506 ice_dpll_deinit_fwnode_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, 3507 int start_idx) 3508 { 3509 int i; 3510 3511 for (i = 0; i < pf->dplls.rclk.num_parents; i++) 3512 ice_dpll_deinit_fwnode_pin(&pins[start_idx + i]); 3513 destroy_workqueue(pf->dplls.wq); 3514 } 3515 3516 /** 3517 * ice_dpll_deinit_pins - deinitialize direct pins 3518 * @pf: board private structure 3519 * @cgu: if cgu is controlled by this pf 3520 * 3521 * If cgu is owned unregister directly connected pins from the dplls. 3522 * Release resources of directly connected pins from the dpll subsystem. 3523 */ 3524 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu) 3525 { 3526 struct ice_dpll_pin *outputs = pf->dplls.outputs; 3527 struct ice_dpll_pin *inputs = pf->dplls.inputs; 3528 int num_outputs = pf->dplls.num_outputs; 3529 int num_inputs = pf->dplls.num_inputs; 3530 struct ice_dplls *d = &pf->dplls; 3531 struct ice_dpll *de = &d->eec; 3532 struct ice_dpll *dp = &d->pps; 3533 3534 ice_dpll_deinit_rclk_pin(pf); 3535 if (pf->hw.mac_type == ICE_MAC_GENERIC_3K_E825) 3536 ice_dpll_deinit_fwnode_pins(pf, pf->dplls.inputs, 0); 3537 if (cgu) { 3538 ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops, 3539 num_inputs); 3540 ice_dpll_unregister_pins(de->dpll, inputs, &ice_dpll_input_ops, 3541 num_inputs); 3542 } 3543 ice_dpll_release_pins(inputs, num_inputs); 3544 if (cgu) { 3545 ice_dpll_unregister_pins(dp->dpll, outputs, 3546 &ice_dpll_output_ops, num_outputs); 3547 ice_dpll_unregister_pins(de->dpll, outputs, 3548 &ice_dpll_output_ops, num_outputs); 3549 ice_dpll_release_pins(outputs, num_outputs); 3550 if (!pf->dplls.generic) { 3551 ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.ufl, 3552 ICE_DPLL_PIN_SW_NUM, 3553 &ice_dpll_pin_ufl_ops, 3554 pf->dplls.pps.dpll, 3555 pf->dplls.eec.dpll); 3556 ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.sma, 3557 ICE_DPLL_PIN_SW_NUM, 3558 &ice_dpll_pin_sma_ops, 3559 pf->dplls.pps.dpll, 3560 pf->dplls.eec.dpll); 3561 } 3562 } 3563 } 3564 3565 static struct fwnode_handle * 3566 ice_dpll_pin_node_get(struct ice_pf *pf, const char *name) 3567 { 3568 struct fwnode_handle *fwnode = dev_fwnode(ice_pf_to_dev(pf)); 3569 int index; 3570 3571 index = fwnode_property_match_string(fwnode, "dpll-pin-names", name); 3572 if (index < 0) 3573 return ERR_PTR(-ENOENT); 3574 3575 return fwnode_find_reference(fwnode, "dpll-pins", index); 3576 } 3577 3578 static int 3579 ice_dpll_init_fwnode_pin(struct ice_dpll_pin *pin, const char *name) 3580 { 3581 struct ice_pf *pf = pin->pf; 3582 int ret; 3583 3584 pin->fwnode = ice_dpll_pin_node_get(pf, name); 3585 if (IS_ERR(pin->fwnode)) { 3586 dev_err(ice_pf_to_dev(pf), 3587 "Failed to find %s firmware node: %pe\n", name, 3588 pin->fwnode); 3589 pin->fwnode = NULL; 3590 return -ENODEV; 3591 } 3592 3593 dev_dbg(ice_pf_to_dev(pf), "Found fwnode node for %s\n", name); 3594 3595 pin->pin = fwnode_dpll_pin_find(pin->fwnode, &pin->tracker); 3596 if (IS_ERR_OR_NULL(pin->pin)) { 3597 dev_info(ice_pf_to_dev(pf), 3598 "DPLL pin for %pfwp not registered yet\n", 3599 pin->fwnode); 3600 pin->pin = NULL; 3601 } 3602 3603 pin->nb.notifier_call = ice_dpll_pin_notify; 3604 ret = register_dpll_notifier(&pin->nb); 3605 if (ret) { 3606 dev_err(ice_pf_to_dev(pf), 3607 "Failed to subscribe for DPLL notifications\n"); 3608 3609 if (!IS_ERR_OR_NULL(pin->pin)) { 3610 dpll_pin_put(pin->pin, &pin->tracker); 3611 pin->pin = NULL; 3612 } 3613 fwnode_handle_put(pin->fwnode); 3614 pin->fwnode = NULL; 3615 3616 return ret; 3617 } 3618 3619 return ret; 3620 } 3621 3622 /** 3623 * ice_dpll_init_fwnode_pins - initialize pins from device tree 3624 * @pf: board private structure 3625 * @pins: pointer to pins array 3626 * @start_idx: starting index for pins 3627 * @count: number of pins to initialize 3628 * 3629 * Initialize input pins for E825 RCLK support. The parent pins (rclk0, rclk1) 3630 * are expected to be defined by the system firmware (ACPI). This function 3631 * allocates them in the dpll subsystem and stores their indices for later 3632 * registration with the rclk pin. 3633 * 3634 * Return: 3635 * * 0 - success 3636 * * negative - initialization failure reason 3637 */ 3638 static int 3639 ice_dpll_init_fwnode_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, 3640 int start_idx) 3641 { 3642 char pin_name[8]; 3643 int i, ret; 3644 3645 pf->dplls.wq = create_singlethread_workqueue("ice_dpll_wq"); 3646 if (!pf->dplls.wq) 3647 return -ENOMEM; 3648 3649 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { 3650 pins[start_idx + i].pf = pf; 3651 snprintf(pin_name, sizeof(pin_name), "rclk%u", i); 3652 ret = ice_dpll_init_fwnode_pin(&pins[start_idx + i], pin_name); 3653 if (ret) 3654 goto error; 3655 } 3656 3657 return 0; 3658 error: 3659 while (i--) 3660 ice_dpll_deinit_fwnode_pin(&pins[start_idx + i]); 3661 3662 destroy_workqueue(pf->dplls.wq); 3663 3664 return ret; 3665 } 3666 3667 /** 3668 * ice_dpll_init_pins_e825 - init pins and register pins with a dplls 3669 * @pf: board private structure 3670 * @cgu: if cgu is present and controlled by this NIC 3671 * 3672 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll 3673 * subsystem. 3674 * 3675 * Return: 3676 * * 0 - success 3677 * * negative - initialization failure reason 3678 */ 3679 static int ice_dpll_init_pins_e825(struct ice_pf *pf) 3680 { 3681 int ret; 3682 3683 ret = ice_dpll_init_fwnode_pins(pf, pf->dplls.inputs, 0); 3684 if (ret) 3685 return ret; 3686 3687 ret = ice_dpll_init_rclk_pin(pf, DPLL_PIN_IDX_UNSPEC, 3688 &ice_dpll_rclk_ops); 3689 if (ret) { 3690 /* Inform DPLL notifier works that DPLL init was finished 3691 * unsuccessfully (ICE_DPLL_FLAG not set). 3692 */ 3693 complete_all(&pf->dplls.dpll_init); 3694 ice_dpll_deinit_fwnode_pins(pf, pf->dplls.inputs, 0); 3695 } 3696 3697 return ret; 3698 } 3699 3700 /** 3701 * ice_dpll_init_pins - init pins and register pins with a dplls 3702 * @pf: board private structure 3703 * @cgu: if cgu is present and controlled by this NIC 3704 * 3705 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll 3706 * subsystem. 3707 * 3708 * Return: 3709 * * 0 - success 3710 * * negative - initialization failure reason 3711 */ 3712 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) 3713 { 3714 const struct dpll_pin_ops *output_ops; 3715 const struct dpll_pin_ops *input_ops; 3716 int ret, count; 3717 3718 input_ops = &ice_dpll_input_ops; 3719 output_ops = &ice_dpll_output_ops; 3720 3721 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, 3722 pf->dplls.num_inputs, input_ops, 3723 pf->dplls.eec.dpll, 3724 pf->dplls.pps.dpll); 3725 if (ret) 3726 return ret; 3727 count = pf->dplls.num_inputs; 3728 if (cgu) { 3729 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, 3730 count, pf->dplls.num_outputs, 3731 output_ops, pf->dplls.eec.dpll, 3732 pf->dplls.pps.dpll); 3733 if (ret) 3734 goto deinit_inputs; 3735 count += pf->dplls.num_outputs; 3736 if (!pf->dplls.generic) { 3737 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.sma, 3738 count, 3739 ICE_DPLL_PIN_SW_NUM, 3740 &ice_dpll_pin_sma_ops, 3741 pf->dplls.eec.dpll, 3742 pf->dplls.pps.dpll); 3743 if (ret) 3744 goto deinit_outputs; 3745 count += ICE_DPLL_PIN_SW_NUM; 3746 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.ufl, 3747 count, 3748 ICE_DPLL_PIN_SW_NUM, 3749 &ice_dpll_pin_ufl_ops, 3750 pf->dplls.eec.dpll, 3751 pf->dplls.pps.dpll); 3752 if (ret) 3753 goto deinit_sma; 3754 count += ICE_DPLL_PIN_SW_NUM; 3755 } 3756 ret = ice_dpll_pin_ref_sync_register(pf->dplls.inputs, 3757 pf->dplls.num_inputs); 3758 if (ret) 3759 goto deinit_ufl; 3760 ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma, 3761 ICE_DPLL_PIN_SW_NUM); 3762 if (ret) 3763 goto deinit_ufl; 3764 } else { 3765 count += pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM; 3766 } 3767 3768 ret = ice_dpll_init_rclk_pin(pf, count + pf->ptp.port.port_num, 3769 &ice_dpll_rclk_ops); 3770 if (ret) 3771 goto deinit_ufl; 3772 3773 return 0; 3774 deinit_ufl: 3775 ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.ufl, ICE_DPLL_PIN_SW_NUM, 3776 &ice_dpll_pin_ufl_ops, pf->dplls.pps.dpll, 3777 pf->dplls.eec.dpll); 3778 deinit_sma: 3779 ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.sma, ICE_DPLL_PIN_SW_NUM, 3780 &ice_dpll_pin_sma_ops, pf->dplls.pps.dpll, 3781 pf->dplls.eec.dpll); 3782 deinit_outputs: 3783 ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.outputs, 3784 pf->dplls.num_outputs, 3785 output_ops, pf->dplls.pps.dpll, 3786 pf->dplls.eec.dpll); 3787 deinit_inputs: 3788 ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.inputs, 3789 pf->dplls.num_inputs, 3790 input_ops, pf->dplls.pps.dpll, 3791 pf->dplls.eec.dpll); 3792 return ret; 3793 } 3794 3795 /** 3796 * ice_dpll_deinit_dpll - deinitialize dpll device 3797 * @pf: board private structure 3798 * @d: pointer to ice_dpll 3799 * @cgu: if cgu is present and controlled by this NIC 3800 * 3801 * If cgu is owned, unregister the DPLL from DPLL subsystem. 3802 * Release resources of DPLL device from DPLL subsystem. 3803 */ 3804 static void 3805 ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu) 3806 { 3807 if (cgu) 3808 dpll_device_unregister(d->dpll, d->ops, d); 3809 dpll_device_put(d->dpll, &d->tracker); 3810 } 3811 3812 /** 3813 * ice_dpll_init_dpll - initialize dpll device in dpll subsystem 3814 * @pf: board private structure 3815 * @d: dpll to be initialized 3816 * @cgu: if cgu is present and controlled by this NIC 3817 * @type: type of dpll being initialized 3818 * 3819 * Allocate DPLL instance for this board in dpll subsystem, if cgu is controlled 3820 * by this NIC, register DPLL with the callback ops. 3821 * 3822 * Return: 3823 * * 0 - success 3824 * * negative - initialization failure reason 3825 */ 3826 static int 3827 ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu, 3828 enum dpll_type type) 3829 { 3830 u64 clock_id = pf->dplls.clock_id; 3831 int ret; 3832 3833 d->dpll = dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE, 3834 &d->tracker); 3835 if (IS_ERR(d->dpll)) { 3836 ret = PTR_ERR(d->dpll); 3837 dev_err(ice_pf_to_dev(pf), 3838 "dpll_device_get failed (%p) err=%d\n", d, ret); 3839 return ret; 3840 } 3841 d->pf = pf; 3842 if (cgu) { 3843 const struct dpll_device_ops *ops = &ice_dpll_ops; 3844 3845 if (type == DPLL_TYPE_PPS && ice_dpll_is_pps_phase_monitor(pf)) 3846 ops = &ice_dpll_pom_ops; 3847 ice_dpll_update_state(pf, d, true); 3848 ret = dpll_device_register(d->dpll, type, ops, d); 3849 if (ret) { 3850 dpll_device_put(d->dpll, &d->tracker); 3851 d->dpll = NULL; 3852 return ret; 3853 } 3854 d->ops = ops; 3855 } 3856 3857 return 0; 3858 } 3859 3860 /** 3861 * ice_dpll_deinit_worker - deinitialize dpll kworker 3862 * @pf: board private structure 3863 * 3864 * Stop dpll's kworker, release it's resources. 3865 */ 3866 static void ice_dpll_deinit_worker(struct ice_pf *pf) 3867 { 3868 struct ice_dplls *d = &pf->dplls; 3869 3870 kthread_cancel_delayed_work_sync(&d->work); 3871 kthread_destroy_worker(d->kworker); 3872 } 3873 3874 /** 3875 * ice_dpll_init_worker - Initialize DPLLs periodic worker 3876 * @pf: board private structure 3877 * 3878 * Create and start DPLLs periodic worker. 3879 * 3880 * Context: Shall be called after pf->dplls.lock is initialized. 3881 * Return: 3882 * * 0 - success 3883 * * negative - create worker failure 3884 */ 3885 static int ice_dpll_init_worker(struct ice_pf *pf) 3886 { 3887 struct ice_dplls *d = &pf->dplls; 3888 struct kthread_worker *kworker; 3889 3890 kthread_init_delayed_work(&d->work, ice_dpll_periodic_work); 3891 kworker = kthread_run_worker(0, "ice-dplls-%s", 3892 dev_name(ice_pf_to_dev(pf))); 3893 if (IS_ERR(kworker)) 3894 return PTR_ERR(kworker); 3895 d->kworker = kworker; 3896 d->cgu_state_acq_err_num = 0; 3897 kthread_queue_delayed_work(d->kworker, &d->work, 0); 3898 3899 return 0; 3900 } 3901 3902 /** 3903 * ice_dpll_phase_range_set - initialize phase adjust range helper 3904 * @range: pointer to phase adjust range struct to be initialized 3905 * @phase_adj: a value to be used as min(-)/max(+) boundary 3906 */ 3907 static void ice_dpll_phase_range_set(struct dpll_pin_phase_adjust_range *range, 3908 u32 phase_adj) 3909 { 3910 range->min = -phase_adj; 3911 range->max = phase_adj; 3912 } 3913 3914 /** 3915 * ice_dpll_init_info_pins_generic - initializes generic pins info 3916 * @pf: board private structure 3917 * @input: if input pins initialized 3918 * 3919 * Init information for generic pins, cache them in PF's pins structures. 3920 * 3921 * Return: 3922 * * 0 - success 3923 * * negative - init failure reason 3924 */ 3925 static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input) 3926 { 3927 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; 3928 static const char labels[][sizeof("99")] = { 3929 "0", "1", "2", "3", "4", "5", "6", "7", "8", 3930 "9", "10", "11", "12", "13", "14", "15" }; 3931 u32 cap = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 3932 enum ice_dpll_pin_type pin_type; 3933 int i, pin_num, ret = -EINVAL; 3934 struct ice_dpll_pin *pins; 3935 u32 phase_adj_max; 3936 3937 if (input) { 3938 pin_num = pf->dplls.num_inputs; 3939 pins = pf->dplls.inputs; 3940 phase_adj_max = pf->dplls.input_phase_adj_max; 3941 pin_type = ICE_DPLL_PIN_TYPE_INPUT; 3942 cap |= DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE; 3943 } else { 3944 pin_num = pf->dplls.num_outputs; 3945 pins = pf->dplls.outputs; 3946 phase_adj_max = pf->dplls.output_phase_adj_max; 3947 pin_type = ICE_DPLL_PIN_TYPE_OUTPUT; 3948 } 3949 if (pin_num > ARRAY_SIZE(labels)) 3950 return ret; 3951 3952 for (i = 0; i < pin_num; i++) { 3953 pins[i].idx = i; 3954 pins[i].prop.board_label = labels[i]; 3955 ice_dpll_phase_range_set(&pins[i].prop.phase_range, 3956 phase_adj_max); 3957 pins[i].prop.capabilities = cap; 3958 pins[i].pf = pf; 3959 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); 3960 if (ret) 3961 break; 3962 if (input && pins[i].freq == ICE_DPLL_PIN_GEN_RCLK_FREQ) 3963 pins[i].prop.type = DPLL_PIN_TYPE_MUX; 3964 else 3965 pins[i].prop.type = DPLL_PIN_TYPE_EXT; 3966 if (!input) 3967 continue; 3968 ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i, 3969 &de->input_prio[i]); 3970 if (ret) 3971 break; 3972 ret = ice_aq_get_cgu_ref_prio(&pf->hw, dp->dpll_idx, i, 3973 &dp->input_prio[i]); 3974 if (ret) 3975 break; 3976 } 3977 3978 return ret; 3979 } 3980 3981 /** 3982 * ice_dpll_init_info_direct_pins - initializes direct pins info 3983 * @pf: board private structure 3984 * @pin_type: type of pins being initialized 3985 * 3986 * Init information for directly connected pins, cache them in pf's pins 3987 * structures. 3988 * 3989 * Return: 3990 * * 0 - success 3991 * * negative - init failure reason 3992 */ 3993 static int 3994 ice_dpll_init_info_direct_pins(struct ice_pf *pf, 3995 enum ice_dpll_pin_type pin_type) 3996 { 3997 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; 3998 int num_pins, i, ret = -EINVAL; 3999 struct ice_hw *hw = &pf->hw; 4000 struct ice_dpll_pin *pins; 4001 unsigned long caps; 4002 u32 phase_adj_max; 4003 u8 freq_supp_num; 4004 bool input; 4005 4006 switch (pin_type) { 4007 case ICE_DPLL_PIN_TYPE_INPUT: 4008 pins = pf->dplls.inputs; 4009 num_pins = pf->dplls.num_inputs; 4010 phase_adj_max = pf->dplls.input_phase_adj_max; 4011 input = true; 4012 break; 4013 case ICE_DPLL_PIN_TYPE_OUTPUT: 4014 pins = pf->dplls.outputs; 4015 num_pins = pf->dplls.num_outputs; 4016 phase_adj_max = pf->dplls.output_phase_adj_max; 4017 input = false; 4018 break; 4019 default: 4020 return -EINVAL; 4021 } 4022 if (num_pins != ice_cgu_get_num_pins(hw, input)) { 4023 pf->dplls.generic = true; 4024 return ice_dpll_init_info_pins_generic(pf, input); 4025 } 4026 4027 for (i = 0; i < num_pins; i++) { 4028 caps = 0; 4029 pins[i].idx = i; 4030 pins[i].prop.board_label = ice_cgu_get_pin_name(hw, i, input); 4031 pins[i].prop.type = ice_cgu_get_pin_type(hw, i, input); 4032 if (input) { 4033 ret = ice_aq_get_cgu_ref_prio(hw, de->dpll_idx, i, 4034 &de->input_prio[i]); 4035 if (ret) 4036 return ret; 4037 ret = ice_aq_get_cgu_ref_prio(hw, dp->dpll_idx, i, 4038 &dp->input_prio[i]); 4039 if (ret) 4040 return ret; 4041 caps |= (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | 4042 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE); 4043 if (ice_dpll_is_sw_pin(pf, i, true)) 4044 pins[i].hidden = true; 4045 } else { 4046 ret = ice_cgu_get_output_pin_state_caps(hw, i, &caps); 4047 if (ret) 4048 return ret; 4049 if (ice_dpll_is_sw_pin(pf, i, false)) 4050 pins[i].hidden = true; 4051 } 4052 ice_dpll_phase_range_set(&pins[i].prop.phase_range, 4053 phase_adj_max); 4054 pins[i].prop.capabilities = caps; 4055 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); 4056 if (ret) 4057 return ret; 4058 pins[i].prop.freq_supported = 4059 ice_cgu_get_pin_freq_supp(hw, i, input, &freq_supp_num); 4060 pins[i].prop.freq_supported_num = freq_supp_num; 4061 pins[i].pf = pf; 4062 } 4063 if (input) 4064 ret = ice_dpll_init_ref_sync_inputs(pf); 4065 4066 return ret; 4067 } 4068 4069 /** 4070 * ice_dpll_init_info_pin_on_pin_e825c - initializes rclk pin information 4071 * @pf: board private structure 4072 * 4073 * Init information for rclk pin, cache them in pf->dplls.rclk. 4074 * 4075 * Return: 4076 * * 0 - success 4077 */ 4078 static int ice_dpll_init_info_pin_on_pin_e825c(struct ice_pf *pf) 4079 { 4080 struct ice_dpll_pin *rclk_pin = &pf->dplls.rclk; 4081 4082 rclk_pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT; 4083 rclk_pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 4084 rclk_pin->pf = pf; 4085 4086 return 0; 4087 } 4088 4089 /** 4090 * ice_dpll_init_info_rclk_pin - initializes rclk pin information 4091 * @pf: board private structure 4092 * 4093 * Init information for rclk pin, cache them in pf->dplls.rclk. 4094 * 4095 * Return: 4096 * * 0 - success 4097 * * negative - init failure reason 4098 */ 4099 static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf) 4100 { 4101 struct ice_dpll_pin *pin = &pf->dplls.rclk; 4102 4103 pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT; 4104 pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 4105 pin->pf = pf; 4106 4107 return ice_dpll_pin_state_update(pf, pin, 4108 ICE_DPLL_PIN_TYPE_RCLK_INPUT, NULL); 4109 } 4110 4111 /** 4112 * ice_dpll_init_info_sw_pins - initializes software controlled pin information 4113 * @pf: board private structure 4114 * 4115 * Init information for software controlled pins, cache them in 4116 * pf->dplls.sma and pf->dplls.ufl. 4117 * 4118 * Return: 4119 * * 0 - success 4120 * * negative - init failure reason 4121 */ 4122 static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) 4123 { 4124 u8 freq_supp_num, pin_abs_idx, input_idx_offset = 0; 4125 struct ice_dplls *d = &pf->dplls; 4126 struct ice_dpll_pin *pin; 4127 u32 phase_adj_max, caps; 4128 int i, ret; 4129 u8 data; 4130 4131 if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) 4132 input_idx_offset = ICE_E810_RCLK_PINS_NUM; 4133 phase_adj_max = max(d->input_phase_adj_max, d->output_phase_adj_max); 4134 caps = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 4135 for (i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) { 4136 pin = &d->sma[i]; 4137 pin->idx = i; 4138 pin->prop.type = DPLL_PIN_TYPE_EXT; 4139 pin_abs_idx = ICE_DPLL_PIN_SW_INPUT_ABS(i) + input_idx_offset; 4140 pin->prop.freq_supported = 4141 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, 4142 true, &freq_supp_num); 4143 pin->prop.freq_supported_num = freq_supp_num; 4144 pin->prop.capabilities = 4145 (DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE | 4146 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | 4147 caps); 4148 pin->pf = pf; 4149 pin->prop.board_label = ice_dpll_sw_pin_sma[i]; 4150 pin->input = &d->inputs[pin_abs_idx]; 4151 if (pin->input->ref_sync) 4152 pin->ref_sync = pin->input->ref_sync - pin_abs_idx; 4153 pin->output = &d->outputs[ICE_DPLL_PIN_SW_OUTPUT_ABS(i)]; 4154 ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); 4155 } 4156 for (i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) { 4157 pin = &d->ufl[i]; 4158 pin->idx = i; 4159 pin->prop.type = DPLL_PIN_TYPE_EXT; 4160 pin->prop.capabilities = caps; 4161 pin->pf = pf; 4162 pin->prop.board_label = ice_dpll_sw_pin_ufl[i]; 4163 if (i == ICE_DPLL_PIN_SW_1_IDX) { 4164 pin->direction = DPLL_PIN_DIRECTION_OUTPUT; 4165 pin_abs_idx = ICE_DPLL_PIN_SW_OUTPUT_ABS(i); 4166 pin->prop.freq_supported = 4167 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, 4168 false, 4169 &freq_supp_num); 4170 pin->prop.freq_supported_num = freq_supp_num; 4171 pin->input = NULL; 4172 pin->output = &d->outputs[pin_abs_idx]; 4173 } else if (i == ICE_DPLL_PIN_SW_2_IDX) { 4174 pin->direction = DPLL_PIN_DIRECTION_INPUT; 4175 pin_abs_idx = ICE_DPLL_PIN_SW_INPUT_ABS(i) + 4176 input_idx_offset; 4177 pin->output = NULL; 4178 pin->input = &d->inputs[pin_abs_idx]; 4179 pin->prop.freq_supported = 4180 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, 4181 true, &freq_supp_num); 4182 pin->prop.freq_supported_num = freq_supp_num; 4183 pin->prop.capabilities = 4184 (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | 4185 caps); 4186 } 4187 ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); 4188 } 4189 4190 /* Initialize the SMA control register to a known-good default state. 4191 * Without this write the PCA9575 GPIO expander retains its power-on 4192 * default (all outputs high) which makes all SW pins appear inactive. 4193 * Set SMA1 and SMA2 as active inputs, disable U.FL1 output and 4194 * U.FL2 input. 4195 */ 4196 ret = ice_read_sma_ctrl(&pf->hw, &data); 4197 if (ret) 4198 return ret; 4199 data &= ~ICE_ALL_SMA_MASK; 4200 data |= ICE_SMA1_TX_EN | ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS; 4201 ret = ice_write_sma_ctrl(&pf->hw, data); 4202 if (ret) 4203 return ret; 4204 4205 ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, 4206 NULL); 4207 if (ret) 4208 return ret; 4209 4210 return 0; 4211 } 4212 4213 /** 4214 * ice_dpll_init_pins_info - init pins info wrapper 4215 * @pf: board private structure 4216 * @pin_type: type of pins being initialized 4217 * 4218 * Wraps functions for pin initialization. 4219 * 4220 * Return: 4221 * * 0 - success 4222 * * negative - init failure reason 4223 */ 4224 static int 4225 ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type) 4226 { 4227 switch (pin_type) { 4228 case ICE_DPLL_PIN_TYPE_INPUT: 4229 case ICE_DPLL_PIN_TYPE_OUTPUT: 4230 return ice_dpll_init_info_direct_pins(pf, pin_type); 4231 case ICE_DPLL_PIN_TYPE_RCLK_INPUT: 4232 if (pf->hw.mac_type == ICE_MAC_GENERIC_3K_E825) 4233 return ice_dpll_init_info_pin_on_pin_e825c(pf); 4234 else 4235 return ice_dpll_init_info_rclk_pin(pf); 4236 case ICE_DPLL_PIN_TYPE_SOFTWARE: 4237 return ice_dpll_init_info_sw_pins(pf); 4238 default: 4239 return -EINVAL; 4240 } 4241 } 4242 4243 /** 4244 * ice_dpll_deinit_info - release memory allocated for pins info 4245 * @pf: board private structure 4246 * 4247 * Release memory allocated for pins by ice_dpll_init_info function. 4248 */ 4249 static void ice_dpll_deinit_info(struct ice_pf *pf) 4250 { 4251 kfree(pf->dplls.inputs); 4252 kfree(pf->dplls.outputs); 4253 kfree(pf->dplls.eec.input_prio); 4254 kfree(pf->dplls.pps.input_prio); 4255 } 4256 4257 /** 4258 * ice_dpll_init_info_e825c - prepare pf's dpll information structure for e825c 4259 * device 4260 * @pf: board private structure 4261 * 4262 * Acquire (from HW) and set basic DPLL information (on pf->dplls struct). 4263 * 4264 * Return: 4265 * * 0 - success 4266 * * negative - init failure reason 4267 */ 4268 static int ice_dpll_init_info_e825c(struct ice_pf *pf) 4269 { 4270 struct ice_dplls *d = &pf->dplls; 4271 int ret = 0; 4272 int i; 4273 4274 d->clock_id = ice_generate_clock_id(pf); 4275 d->num_inputs = ICE_SYNCE_CLK_NUM; 4276 4277 d->inputs = kzalloc_objs(*d->inputs, d->num_inputs); 4278 if (!d->inputs) 4279 return -ENOMEM; 4280 4281 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, 4282 &pf->dplls.rclk.num_parents); 4283 if (ret) 4284 goto deinit_info; 4285 4286 for (i = 0; i < pf->dplls.rclk.num_parents; i++) 4287 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; 4288 4289 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT); 4290 if (ret) 4291 goto deinit_info; 4292 dev_dbg(ice_pf_to_dev(pf), 4293 "%s - success, inputs: %u, outputs: %u, rclk-parents: %u\n", 4294 __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents); 4295 return 0; 4296 deinit_info: 4297 ice_dpll_deinit_info(pf); 4298 return ret; 4299 } 4300 4301 /** 4302 * ice_dpll_init_info - prepare pf's dpll information structure 4303 * @pf: board private structure 4304 * @cgu: if cgu is present and controlled by this NIC 4305 * 4306 * Acquire (from HW) and set basic dpll information (on pf->dplls struct). 4307 * 4308 * Return: 4309 * * 0 - success 4310 * * negative - init failure reason 4311 */ 4312 static int ice_dpll_init_info(struct ice_pf *pf, bool cgu) 4313 { 4314 struct ice_aqc_get_cgu_abilities abilities; 4315 struct ice_dpll *de = &pf->dplls.eec; 4316 struct ice_dpll *dp = &pf->dplls.pps; 4317 struct ice_dplls *d = &pf->dplls; 4318 struct ice_hw *hw = &pf->hw; 4319 int ret, alloc_size, i; 4320 4321 d->clock_id = ice_generate_clock_id(pf); 4322 ret = ice_aq_get_cgu_abilities(hw, &abilities); 4323 if (ret) { 4324 dev_err(ice_pf_to_dev(pf), 4325 "err:%d %s failed to read cgu abilities\n", 4326 ret, libie_aq_str(hw->adminq.sq_last_status)); 4327 return ret; 4328 } 4329 4330 de->dpll_idx = abilities.eec_dpll_idx; 4331 dp->dpll_idx = abilities.pps_dpll_idx; 4332 d->num_inputs = abilities.num_inputs; 4333 d->num_outputs = abilities.num_outputs; 4334 d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj) & 4335 ICE_AQC_GET_CGU_MAX_PHASE_ADJ; 4336 d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj) & 4337 ICE_AQC_GET_CGU_MAX_PHASE_ADJ; 4338 4339 alloc_size = sizeof(*d->inputs) * d->num_inputs; 4340 d->inputs = kzalloc(alloc_size, GFP_KERNEL); 4341 if (!d->inputs) 4342 return -ENOMEM; 4343 4344 alloc_size = sizeof(*de->input_prio) * d->num_inputs; 4345 de->input_prio = kzalloc(alloc_size, GFP_KERNEL); 4346 if (!de->input_prio) 4347 return -ENOMEM; 4348 4349 dp->input_prio = kzalloc(alloc_size, GFP_KERNEL); 4350 if (!dp->input_prio) 4351 return -ENOMEM; 4352 4353 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT); 4354 if (ret) 4355 goto deinit_info; 4356 4357 if (cgu) { 4358 alloc_size = sizeof(*d->outputs) * d->num_outputs; 4359 d->outputs = kzalloc(alloc_size, GFP_KERNEL); 4360 if (!d->outputs) { 4361 ret = -ENOMEM; 4362 goto deinit_info; 4363 } 4364 4365 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT); 4366 if (ret) 4367 goto deinit_info; 4368 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_SOFTWARE); 4369 if (ret) 4370 goto deinit_info; 4371 } 4372 4373 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, 4374 &pf->dplls.rclk.num_parents); 4375 if (ret) 4376 return ret; 4377 for (i = 0; i < pf->dplls.rclk.num_parents; i++) 4378 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; 4379 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT); 4380 if (ret) 4381 return ret; 4382 de->mode = DPLL_MODE_AUTOMATIC; 4383 dp->mode = DPLL_MODE_AUTOMATIC; 4384 4385 dev_dbg(ice_pf_to_dev(pf), 4386 "%s - success, inputs:%u, outputs:%u rclk-parents:%u\n", 4387 __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents); 4388 4389 return 0; 4390 4391 deinit_info: 4392 dev_err(ice_pf_to_dev(pf), 4393 "%s - fail: d->inputs:%p, de->input_prio:%p, dp->input_prio:%p, d->outputs:%p\n", 4394 __func__, d->inputs, de->input_prio, 4395 dp->input_prio, d->outputs); 4396 ice_dpll_deinit_info(pf); 4397 return ret; 4398 } 4399 4400 /** 4401 * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem 4402 * the dpll device. 4403 * @pf: board private structure 4404 * 4405 * Handles the cleanup work required after dpll initialization, freeing 4406 * resources and unregistering the dpll, pin and all resources used for 4407 * handling them. 4408 * 4409 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set. 4410 */ 4411 void ice_dpll_deinit(struct ice_pf *pf) 4412 { 4413 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); 4414 4415 clear_bit(ICE_FLAG_DPLL, pf->flags); 4416 if (cgu) 4417 ice_dpll_deinit_worker(pf); 4418 4419 ice_dpll_deinit_pins(pf, cgu); 4420 if (!IS_ERR_OR_NULL(pf->dplls.pps.dpll)) 4421 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); 4422 if (!IS_ERR_OR_NULL(pf->dplls.eec.dpll)) 4423 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); 4424 ice_dpll_deinit_info(pf); 4425 mutex_destroy(&pf->dplls.lock); 4426 } 4427 4428 /** 4429 * ice_dpll_init_e825 - initialize support for dpll subsystem 4430 * @pf: board private structure 4431 * 4432 * Set up the device dplls, register them and pins connected within Linux dpll 4433 * subsystem. Allow userspace to obtain state of DPLL and handling of DPLL 4434 * configuration requests. 4435 * 4436 * Context: Initializes pf->dplls.lock mutex. 4437 */ 4438 static void ice_dpll_init_e825(struct ice_pf *pf) 4439 { 4440 struct ice_dplls *d = &pf->dplls; 4441 int err; 4442 4443 mutex_init(&d->lock); 4444 init_completion(&d->dpll_init); 4445 4446 err = ice_dpll_init_info_e825c(pf); 4447 if (err) 4448 goto err_exit; 4449 err = ice_dpll_init_pins_e825(pf); 4450 if (err) 4451 goto deinit_info; 4452 set_bit(ICE_FLAG_DPLL, pf->flags); 4453 complete_all(&d->dpll_init); 4454 4455 return; 4456 4457 deinit_info: 4458 ice_dpll_deinit_info(pf); 4459 err_exit: 4460 mutex_destroy(&d->lock); 4461 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); 4462 } 4463 4464 /** 4465 * ice_dpll_init_e810 - initialize support for dpll subsystem 4466 * @pf: board private structure 4467 * 4468 * Set up the device dplls, register them and pins connected within Linux dpll 4469 * subsystem. Allow userspace to obtain state of DPLL and handling of DPLL 4470 * configuration requests. 4471 * 4472 * Context: Initializes pf->dplls.lock mutex. 4473 */ 4474 static void ice_dpll_init_e810(struct ice_pf *pf) 4475 { 4476 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); 4477 struct ice_dplls *d = &pf->dplls; 4478 int err = 0; 4479 4480 mutex_init(&d->lock); 4481 err = ice_dpll_init_info(pf, cgu); 4482 if (err) 4483 goto err_exit; 4484 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); 4485 if (err) 4486 goto deinit_info; 4487 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); 4488 if (err) 4489 goto deinit_eec; 4490 err = ice_dpll_init_pins(pf, cgu); 4491 if (err) 4492 goto deinit_pps; 4493 if (cgu) { 4494 err = ice_dpll_init_worker(pf); 4495 if (err) 4496 goto deinit_pins; 4497 } 4498 set_bit(ICE_FLAG_DPLL, pf->flags); 4499 4500 return; 4501 4502 deinit_pins: 4503 ice_dpll_deinit_pins(pf, cgu); 4504 deinit_pps: 4505 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); 4506 deinit_eec: 4507 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); 4508 deinit_info: 4509 ice_dpll_deinit_info(pf); 4510 err_exit: 4511 mutex_destroy(&d->lock); 4512 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); 4513 } 4514 4515 void ice_dpll_init(struct ice_pf *pf) 4516 { 4517 switch (pf->hw.mac_type) { 4518 case ICE_MAC_GENERIC_3K_E825: 4519 ice_dpll_init_e825(pf); 4520 break; 4521 default: 4522 ice_dpll_init_e810(pf); 4523 break; 4524 } 4525 } 4526