1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/spinlock.h>
20
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm_params.h>
23
24 #define STM32_I2S_CR1_REG 0x0
25 #define STM32_I2S_CFG1_REG 0x08
26 #define STM32_I2S_CFG2_REG 0x0C
27 #define STM32_I2S_IER_REG 0x10
28 #define STM32_I2S_SR_REG 0x14
29 #define STM32_I2S_IFCR_REG 0x18
30 #define STM32_I2S_TXDR_REG 0X20
31 #define STM32_I2S_RXDR_REG 0x30
32 #define STM32_I2S_CGFR_REG 0X50
33 #define STM32_I2S_HWCFGR_REG 0x3F0
34 #define STM32_I2S_VERR_REG 0x3F4
35 #define STM32_I2S_IPIDR_REG 0x3F8
36 #define STM32_I2S_SIDR_REG 0x3FC
37
38 /* Bit definition for SPI2S_CR1 register */
39 #define I2S_CR1_SPE BIT(0)
40 #define I2S_CR1_CSTART BIT(9)
41 #define I2S_CR1_CSUSP BIT(10)
42 #define I2S_CR1_HDDIR BIT(11)
43 #define I2S_CR1_SSI BIT(12)
44 #define I2S_CR1_CRC33_17 BIT(13)
45 #define I2S_CR1_RCRCI BIT(14)
46 #define I2S_CR1_TCRCI BIT(15)
47
48 /* Bit definition for SPI_CFG2 register */
49 #define I2S_CFG2_IOSWP_SHIFT 15
50 #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
51 #define I2S_CFG2_LSBFRST BIT(23)
52 #define I2S_CFG2_AFCNTR BIT(31)
53
54 /* Bit definition for SPI_CFG1 register */
55 #define I2S_CFG1_FTHVL_SHIFT 5
56 #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
57 #define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
58
59 #define I2S_CFG1_TXDMAEN BIT(15)
60 #define I2S_CFG1_RXDMAEN BIT(14)
61
62 /* Bit definition for SPI2S_IER register */
63 #define I2S_IER_RXPIE BIT(0)
64 #define I2S_IER_TXPIE BIT(1)
65 #define I2S_IER_DPXPIE BIT(2)
66 #define I2S_IER_EOTIE BIT(3)
67 #define I2S_IER_TXTFIE BIT(4)
68 #define I2S_IER_UDRIE BIT(5)
69 #define I2S_IER_OVRIE BIT(6)
70 #define I2S_IER_CRCEIE BIT(7)
71 #define I2S_IER_TIFREIE BIT(8)
72 #define I2S_IER_MODFIE BIT(9)
73 #define I2S_IER_TSERFIE BIT(10)
74
75 /* Bit definition for SPI2S_SR register */
76 #define I2S_SR_RXP BIT(0)
77 #define I2S_SR_TXP BIT(1)
78 #define I2S_SR_DPXP BIT(2)
79 #define I2S_SR_EOT BIT(3)
80 #define I2S_SR_TXTF BIT(4)
81 #define I2S_SR_UDR BIT(5)
82 #define I2S_SR_OVR BIT(6)
83 #define I2S_SR_CRCERR BIT(7)
84 #define I2S_SR_TIFRE BIT(8)
85 #define I2S_SR_MODF BIT(9)
86 #define I2S_SR_TSERF BIT(10)
87 #define I2S_SR_SUSP BIT(11)
88 #define I2S_SR_TXC BIT(12)
89 #define I2S_SR_RXPLVL GENMASK(14, 13)
90 #define I2S_SR_RXWNE BIT(15)
91
92 #define I2S_SR_MASK GENMASK(15, 0)
93
94 /* Bit definition for SPI_IFCR register */
95 #define I2S_IFCR_EOTC BIT(3)
96 #define I2S_IFCR_TXTFC BIT(4)
97 #define I2S_IFCR_UDRC BIT(5)
98 #define I2S_IFCR_OVRC BIT(6)
99 #define I2S_IFCR_CRCEC BIT(7)
100 #define I2S_IFCR_TIFREC BIT(8)
101 #define I2S_IFCR_MODFC BIT(9)
102 #define I2S_IFCR_TSERFC BIT(10)
103 #define I2S_IFCR_SUSPC BIT(11)
104
105 #define I2S_IFCR_MASK GENMASK(11, 3)
106
107 /* Bit definition for SPI_I2SCGFR register */
108 #define I2S_CGFR_I2SMOD BIT(0)
109
110 #define I2S_CGFR_I2SCFG_SHIFT 1
111 #define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
112 #define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
113
114 #define I2S_CGFR_I2SSTD_SHIFT 4
115 #define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
116 #define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
117
118 #define I2S_CGFR_PCMSYNC BIT(7)
119
120 #define I2S_CGFR_DATLEN_SHIFT 8
121 #define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
122 #define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
123
124 #define I2S_CGFR_CHLEN_SHIFT 10
125 #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
126 #define I2S_CGFR_CKPOL BIT(11)
127 #define I2S_CGFR_FIXCH BIT(12)
128 #define I2S_CGFR_WSINV BIT(13)
129 #define I2S_CGFR_DATFMT BIT(14)
130
131 #define I2S_CGFR_I2SDIV_SHIFT 16
132 #define I2S_CGFR_I2SDIV_BIT_H 23
133 #define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
134 I2S_CGFR_I2SDIV_SHIFT)
135 #define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
138
139 #define I2S_CGFR_ODD_SHIFT 24
140 #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
141 #define I2S_CGFR_MCKOE BIT(25)
142
143 /* Registers below apply to I2S version 1.1 and more */
144
145 /* Bit definition for SPI_HWCFGR register */
146 #define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
147
148 /* Bit definition for SPI_VERR register */
149 #define I2S_VERR_MIN_MASK GENMASK(3, 0)
150 #define I2S_VERR_MAJ_MASK GENMASK(7, 4)
151
152 /* Bit definition for SPI_IPIDR register */
153 #define I2S_IPIDR_ID_MASK GENMASK(31, 0)
154
155 /* Bit definition for SPI_SIDR register */
156 #define I2S_SIDR_ID_MASK GENMASK(31, 0)
157
158 #define I2S_IPIDR_NUMBER 0x00130022
159
160 enum i2s_master_mode {
161 I2S_MS_NOT_SET,
162 I2S_MS_MASTER,
163 I2S_MS_SLAVE,
164 };
165
166 enum i2s_mode {
167 I2S_I2SMOD_TX_SLAVE,
168 I2S_I2SMOD_RX_SLAVE,
169 I2S_I2SMOD_TX_MASTER,
170 I2S_I2SMOD_RX_MASTER,
171 I2S_I2SMOD_FD_SLAVE,
172 I2S_I2SMOD_FD_MASTER,
173 };
174
175 enum i2s_fifo_th {
176 I2S_FIFO_TH_NONE,
177 I2S_FIFO_TH_ONE_QUARTER,
178 I2S_FIFO_TH_HALF,
179 I2S_FIFO_TH_THREE_QUARTER,
180 I2S_FIFO_TH_FULL,
181 };
182
183 enum i2s_std {
184 I2S_STD_I2S,
185 I2S_STD_LEFT_J,
186 I2S_STD_RIGHT_J,
187 I2S_STD_DSP,
188 };
189
190 enum i2s_datlen {
191 I2S_I2SMOD_DATLEN_16,
192 I2S_I2SMOD_DATLEN_24,
193 I2S_I2SMOD_DATLEN_32,
194 };
195
196 #define STM32_I2S_FIFO_SIZE 16
197
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
200
201 #define STM32_I2S_NAME_LEN 32
202 #define STM32_I2S_RATE_11K 11025
203 #define STM32_I2S_MAX_SAMPLE_RATE_8K 192000
204 #define STM32_I2S_MAX_SAMPLE_RATE_11K 176400
205 #define STM32_I2S_CLK_RATE_TOLERANCE 1000 /* ppm */
206
207 /**
208 * struct stm32_i2s_data - private data of I2S
209 * @conf: I2S configuration pointer
210 * @regmap: I2S register map pointer
211 * @pdev: device data pointer
212 * @dai_drv: DAI driver pointer
213 * @dma_data_tx: dma configuration data for tx channel
214 * @dma_data_rx: dma configuration data for tx channel
215 * @substream: PCM substream data pointer
216 * @i2sclk: kernel clock feeding the I2S clock generator
217 * @i2smclk: master clock from I2S mclk provider
218 * @pclk: peripheral clock driving bus interface
219 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
220 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
221 * @base: mmio register base virtual address
222 * @phys_addr: I2S registers physical base address
223 * @lock_fd: lock to manage race conditions in full duplex mode
224 * @irq_lock: prevent race condition with IRQ
225 * @mclk_rate: master clock frequency (Hz)
226 * @fmt: DAI protocol
227 * @divider: prescaler division ratio
228 * @div: prescaler div field
229 * @odd: prescaler odd field
230 * @i2s_clk_flg: flag set while exclusivity on I2S kernel clock is active
231 * @refcount: keep count of opened streams on I2S
232 * @ms_flg: master mode flag.
233 * @set_i2s_clk_rate: set I2S kernel clock rate
234 * @put_i2s_clk_rate: put I2S kernel clock rate
235 */
236 struct stm32_i2s_data {
237 const struct stm32_i2s_conf *conf;
238 struct regmap *regmap;
239 struct platform_device *pdev;
240 struct snd_soc_dai_driver *dai_drv;
241 struct snd_dmaengine_dai_dma_data dma_data_tx;
242 struct snd_dmaengine_dai_dma_data dma_data_rx;
243 struct snd_pcm_substream *substream;
244 struct clk *i2sclk;
245 struct clk *i2smclk;
246 struct clk *pclk;
247 struct clk *x8kclk;
248 struct clk *x11kclk;
249 void __iomem *base;
250 dma_addr_t phys_addr;
251 spinlock_t lock_fd; /* Manage race conditions for full duplex */
252 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
253 unsigned int mclk_rate;
254 unsigned int fmt;
255 unsigned int divider;
256 unsigned int div;
257 bool odd;
258 bool i2s_clk_flg;
259 int refcount;
260 int ms_flg;
261 int (*set_i2s_clk_rate)(struct stm32_i2s_data *i2s, unsigned int rate);
262 void (*put_i2s_clk_rate)(struct stm32_i2s_data *i2s);
263 };
264
265 /**
266 * struct stm32_i2s_conf - I2S configuration
267 * @regmap_conf: regmap configuration pointer
268 * @get_i2s_clk_parent: get parent clock of I2S kernel clock
269 */
270 struct stm32_i2s_conf {
271 const struct regmap_config *regmap_conf;
272 int (*get_i2s_clk_parent)(struct stm32_i2s_data *i2s);
273 };
274
275 struct stm32_i2smclk_data {
276 struct clk_hw hw;
277 unsigned long freq;
278 struct stm32_i2s_data *i2s_data;
279 };
280
281 #define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
282
283 static int stm32_i2s_get_parent_clk(struct stm32_i2s_data *i2s);
284
stm32_i2s_calc_clk_div(struct stm32_i2s_data * i2s,unsigned long input_rate,unsigned long output_rate)285 static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
286 unsigned long input_rate,
287 unsigned long output_rate)
288 {
289 unsigned int ratio, div, divider = 1;
290 bool odd;
291
292 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
293
294 /* Check the parity of the divider */
295 odd = ratio & 0x1;
296
297 /* Compute the div prescaler */
298 div = ratio >> 1;
299
300 /* If div is 0 actual divider is 1 */
301 if (div) {
302 divider = ((2 * div) + odd);
303 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
304 div, odd, divider);
305 }
306
307 /* Division by three is not allowed by I2S prescaler */
308 if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
309 dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
310 return -EINVAL;
311 }
312
313 if (input_rate % divider)
314 dev_dbg(&i2s->pdev->dev,
315 "Rate not accurate. requested (%ld), actual (%ld)\n",
316 output_rate, input_rate / divider);
317
318 i2s->div = div;
319 i2s->odd = odd;
320 i2s->divider = divider;
321
322 return 0;
323 }
324
stm32_i2s_set_clk_div(struct stm32_i2s_data * i2s)325 static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
326 {
327 u32 cgfr, cgfr_mask;
328
329 cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
330 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
331
332 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
333 cgfr_mask, cgfr);
334 }
335
stm32_i2s_rate_accurate(struct stm32_i2s_data * i2s,unsigned int max_rate,unsigned int rate)336 static bool stm32_i2s_rate_accurate(struct stm32_i2s_data *i2s,
337 unsigned int max_rate, unsigned int rate)
338 {
339 struct platform_device *pdev = i2s->pdev;
340 u64 delta, dividend;
341 int ratio;
342
343 if (!rate) {
344 dev_err(&pdev->dev, "Unexpected null rate\n");
345 return false;
346 }
347
348 ratio = DIV_ROUND_CLOSEST(max_rate, rate);
349 if (!ratio)
350 return false;
351
352 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));
353 delta = div_u64(dividend, max_rate);
354
355 if (delta <= STM32_I2S_CLK_RATE_TOLERANCE)
356 return true;
357
358 dev_dbg(&pdev->dev, "Rate [%u] not accurate\n", rate);
359
360 return false;
361 }
362
stm32_i2s_set_parent_clock(struct stm32_i2s_data * i2s,unsigned int rate)363 static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
364 unsigned int rate)
365 {
366 struct platform_device *pdev = i2s->pdev;
367 struct clk *parent_clk;
368 int ret;
369
370 if (!(rate % STM32_I2S_RATE_11K))
371 parent_clk = i2s->x11kclk;
372 else
373 parent_clk = i2s->x8kclk;
374
375 ret = clk_set_parent(i2s->i2sclk, parent_clk);
376 if (ret)
377 dev_err(&pdev->dev,
378 "Error %d setting i2sclk parent clock\n", ret);
379
380 return ret;
381 }
382
stm32_i2s_put_parent_rate(struct stm32_i2s_data * i2s)383 static void stm32_i2s_put_parent_rate(struct stm32_i2s_data *i2s)
384 {
385 if (i2s->i2s_clk_flg) {
386 i2s->i2s_clk_flg = false;
387 clk_rate_exclusive_put(i2s->i2sclk);
388 }
389 }
390
stm32_i2s_set_parent_rate(struct stm32_i2s_data * i2s,unsigned int rate)391 static int stm32_i2s_set_parent_rate(struct stm32_i2s_data *i2s,
392 unsigned int rate)
393 {
394 struct platform_device *pdev = i2s->pdev;
395 unsigned int i2s_clk_rate, i2s_clk_max_rate, i2s_curr_rate, i2s_new_rate;
396 int ret, div;
397
398 /*
399 * Set maximum expected kernel clock frequency
400 * - mclk on:
401 * f_i2s_ck = MCKDIV * mclk-fs * fs
402 * Here typical 256 ratio is assumed for mclk-fs
403 * - mclk off:
404 * f_i2s_ck = MCKDIV * FRL * fs
405 * Where FRL=[16,32], MCKDIV=[1..256]
406 * f_i2s_ck = i2s_clk_max_rate * 32 / 256
407 */
408 if (!(rate % STM32_I2S_RATE_11K))
409 i2s_clk_max_rate = STM32_I2S_MAX_SAMPLE_RATE_11K * 256;
410 else
411 i2s_clk_max_rate = STM32_I2S_MAX_SAMPLE_RATE_8K * 256;
412
413 if (!i2s->i2smclk)
414 i2s_clk_max_rate /= 8;
415
416 /* Request exclusivity, as the clock may be shared by I2S instances */
417 clk_rate_exclusive_get(i2s->i2sclk);
418 i2s->i2s_clk_flg = true;
419
420 /*
421 * Check current kernel clock rate. If it gives the expected accuracy
422 * return immediately.
423 */
424 i2s_curr_rate = clk_get_rate(i2s->i2sclk);
425 if (stm32_i2s_rate_accurate(i2s, i2s_clk_max_rate, i2s_curr_rate))
426 return 0;
427
428 /*
429 * Otherwise try to set the maximum rate and check the new actual rate.
430 * If the new rate does not give the expected accuracy, try to set
431 * lower rates for the kernel clock.
432 */
433 i2s_clk_rate = i2s_clk_max_rate;
434 div = 1;
435 do {
436 /* Check new rate accuracy. Return if ok */
437 i2s_new_rate = clk_round_rate(i2s->i2sclk, i2s_clk_rate);
438 if (stm32_i2s_rate_accurate(i2s, i2s_clk_rate, i2s_new_rate)) {
439 ret = clk_set_rate(i2s->i2sclk, i2s_clk_rate);
440 if (ret) {
441 dev_err(&pdev->dev, "Error %d setting i2s_clk_rate rate. %s",
442 ret, ret == -EBUSY ?
443 "Active stream rates may be in conflict\n" : "\n");
444 goto err;
445 }
446
447 return 0;
448 }
449
450 /* Try a lower frequency */
451 div++;
452 i2s_clk_rate = i2s_clk_max_rate / div;
453 } while (i2s_clk_rate > rate);
454
455 /* no accurate rate found */
456 dev_err(&pdev->dev, "Failed to find an accurate rate");
457
458 err:
459 stm32_i2s_put_parent_rate(i2s);
460
461 return -EINVAL;
462 }
463
stm32_i2smclk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)464 static int stm32_i2smclk_determine_rate(struct clk_hw *hw,
465 struct clk_rate_request *req)
466 {
467 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
468 struct stm32_i2s_data *i2s = mclk->i2s_data;
469 int ret;
470
471 ret = stm32_i2s_calc_clk_div(i2s, req->best_parent_rate, req->rate);
472 if (ret) {
473 req->rate = ret;
474
475 return 0;
476 }
477
478 mclk->freq = req->best_parent_rate / i2s->divider;
479
480 req->rate = mclk->freq;
481
482 return 0;
483 }
484
stm32_i2smclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)485 static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
486 unsigned long parent_rate)
487 {
488 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
489
490 return mclk->freq;
491 }
492
stm32_i2smclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)493 static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
494 unsigned long parent_rate)
495 {
496 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
497 struct stm32_i2s_data *i2s = mclk->i2s_data;
498 int ret;
499
500 ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
501 if (ret)
502 return ret;
503
504 ret = stm32_i2s_set_clk_div(i2s);
505 if (ret)
506 return ret;
507
508 mclk->freq = rate;
509
510 return 0;
511 }
512
stm32_i2smclk_enable(struct clk_hw * hw)513 static int stm32_i2smclk_enable(struct clk_hw *hw)
514 {
515 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
516 struct stm32_i2s_data *i2s = mclk->i2s_data;
517
518 dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
519
520 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
521 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
522 }
523
stm32_i2smclk_disable(struct clk_hw * hw)524 static void stm32_i2smclk_disable(struct clk_hw *hw)
525 {
526 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
527 struct stm32_i2s_data *i2s = mclk->i2s_data;
528
529 dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
530
531 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
532 }
533
534 static const struct clk_ops mclk_ops = {
535 .enable = stm32_i2smclk_enable,
536 .disable = stm32_i2smclk_disable,
537 .recalc_rate = stm32_i2smclk_recalc_rate,
538 .determine_rate = stm32_i2smclk_determine_rate,
539 .set_rate = stm32_i2smclk_set_rate,
540 };
541
stm32_i2s_add_mclk_provider(struct stm32_i2s_data * i2s)542 static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
543 {
544 struct clk_hw *hw;
545 struct stm32_i2smclk_data *mclk;
546 struct device *dev = &i2s->pdev->dev;
547 const char *pname = __clk_get_name(i2s->i2sclk);
548 char *mclk_name, *p, *s = (char *)pname;
549 int ret, i = 0;
550
551 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
552 if (!mclk)
553 return -ENOMEM;
554
555 mclk_name = devm_kcalloc(dev, sizeof(char),
556 STM32_I2S_NAME_LEN, GFP_KERNEL);
557 if (!mclk_name)
558 return -ENOMEM;
559
560 /*
561 * Forge mclk clock name from parent clock name and suffix.
562 * String after "_" char is stripped in parent name.
563 */
564 p = mclk_name;
565 while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
566 *p++ = *s++;
567 i++;
568 }
569 strcat(p, "_mclk");
570
571 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
572 mclk->i2s_data = i2s;
573 hw = &mclk->hw;
574
575 dev_dbg(dev, "Register master clock %s\n", mclk_name);
576 ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
577 if (ret) {
578 dev_err(dev, "mclk register fails with error %d\n", ret);
579 return ret;
580 }
581 i2s->i2smclk = hw->clk;
582
583 /* register mclk provider */
584 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
585 }
586
stm32_i2s_isr(int irq,void * devid)587 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
588 {
589 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
590 struct platform_device *pdev = i2s->pdev;
591 u32 sr, ier;
592 unsigned long flags;
593 int err = 0;
594
595 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
596 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
597
598 flags = sr & ier;
599 if (!flags) {
600 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
601 sr, ier);
602 return IRQ_NONE;
603 }
604
605 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
606 I2S_IFCR_MASK, flags);
607
608 if (flags & I2S_SR_OVR) {
609 dev_dbg(&pdev->dev, "Overrun\n");
610 err = 1;
611 }
612
613 if (flags & I2S_SR_UDR) {
614 dev_dbg(&pdev->dev, "Underrun\n");
615 err = 1;
616 }
617
618 if (flags & I2S_SR_TIFRE)
619 dev_dbg(&pdev->dev, "Frame error\n");
620
621 spin_lock(&i2s->irq_lock);
622 if (err && i2s->substream)
623 snd_pcm_stop_xrun(i2s->substream);
624 spin_unlock(&i2s->irq_lock);
625
626 return IRQ_HANDLED;
627 }
628
stm32_i2s_readable_reg(struct device * dev,unsigned int reg)629 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
630 {
631 switch (reg) {
632 case STM32_I2S_CR1_REG:
633 case STM32_I2S_CFG1_REG:
634 case STM32_I2S_CFG2_REG:
635 case STM32_I2S_IER_REG:
636 case STM32_I2S_SR_REG:
637 case STM32_I2S_RXDR_REG:
638 case STM32_I2S_CGFR_REG:
639 case STM32_I2S_HWCFGR_REG:
640 case STM32_I2S_VERR_REG:
641 case STM32_I2S_IPIDR_REG:
642 case STM32_I2S_SIDR_REG:
643 return true;
644 default:
645 return false;
646 }
647 }
648
stm32_i2s_volatile_reg(struct device * dev,unsigned int reg)649 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
650 {
651 switch (reg) {
652 case STM32_I2S_SR_REG:
653 case STM32_I2S_RXDR_REG:
654 return true;
655 default:
656 return false;
657 }
658 }
659
stm32_i2s_writeable_reg(struct device * dev,unsigned int reg)660 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
661 {
662 switch (reg) {
663 case STM32_I2S_CR1_REG:
664 case STM32_I2S_CFG1_REG:
665 case STM32_I2S_CFG2_REG:
666 case STM32_I2S_IER_REG:
667 case STM32_I2S_IFCR_REG:
668 case STM32_I2S_TXDR_REG:
669 case STM32_I2S_CGFR_REG:
670 return true;
671 default:
672 return false;
673 }
674 }
675
stm32_i2s_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)676 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
677 {
678 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
679 u32 cgfr;
680 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
681 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
682
683 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
684
685 /*
686 * winv = 0 : default behavior (high/low) for all standards
687 * ckpol = 0 for all standards.
688 */
689 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
690 case SND_SOC_DAIFMT_I2S:
691 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
692 break;
693 case SND_SOC_DAIFMT_MSB:
694 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
695 break;
696 case SND_SOC_DAIFMT_LSB:
697 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
698 break;
699 case SND_SOC_DAIFMT_DSP_A:
700 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
701 break;
702 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
703 default:
704 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
705 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
706 return -EINVAL;
707 }
708
709 /* DAI clock strobing */
710 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
711 case SND_SOC_DAIFMT_NB_NF:
712 break;
713 case SND_SOC_DAIFMT_IB_NF:
714 cgfr |= I2S_CGFR_CKPOL;
715 break;
716 case SND_SOC_DAIFMT_NB_IF:
717 cgfr |= I2S_CGFR_WSINV;
718 break;
719 case SND_SOC_DAIFMT_IB_IF:
720 cgfr |= I2S_CGFR_CKPOL;
721 cgfr |= I2S_CGFR_WSINV;
722 break;
723 default:
724 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
725 fmt & SND_SOC_DAIFMT_INV_MASK);
726 return -EINVAL;
727 }
728
729 /* DAI clock master masks */
730 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
731 case SND_SOC_DAIFMT_BC_FC:
732 i2s->ms_flg = I2S_MS_SLAVE;
733 break;
734 case SND_SOC_DAIFMT_BP_FP:
735 i2s->ms_flg = I2S_MS_MASTER;
736 break;
737 default:
738 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
739 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
740 return -EINVAL;
741 }
742
743 i2s->fmt = fmt;
744 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
745 cgfr_mask, cgfr);
746 }
747
stm32_i2s_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)748 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
749 int clk_id, unsigned int freq, int dir)
750 {
751 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
752 int ret = 0;
753
754 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
755 freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
756 dir ? "output" : "input");
757
758 /* MCLK generation is available only in master mode */
759 if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
760 if (!i2s->i2smclk) {
761 dev_dbg(cpu_dai->dev, "No MCLK registered\n");
762 return 0;
763 }
764
765 /* Assume shutdown if requested frequency is 0Hz */
766 if (!freq) {
767 /* Release mclk rate only if rate was actually set */
768 if (i2s->mclk_rate) {
769 clk_rate_exclusive_put(i2s->i2smclk);
770 i2s->mclk_rate = 0;
771 }
772
773 if (i2s->put_i2s_clk_rate)
774 i2s->put_i2s_clk_rate(i2s);
775
776 return regmap_update_bits(i2s->regmap,
777 STM32_I2S_CGFR_REG,
778 I2S_CGFR_MCKOE, 0);
779 }
780 /* If master clock is used, set parent clock now */
781 ret = i2s->set_i2s_clk_rate(i2s, freq);
782 if (ret)
783 return ret;
784 ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
785 if (ret) {
786 dev_err(cpu_dai->dev, "Could not set mclk rate\n");
787 return ret;
788 }
789 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
790 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
791 if (!ret)
792 i2s->mclk_rate = freq;
793 }
794
795 return ret;
796 }
797
stm32_i2s_configure_clock(struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * params)798 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
799 struct snd_pcm_hw_params *params)
800 {
801 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
802 unsigned long i2s_clock_rate;
803 unsigned int nb_bits, frame_len;
804 unsigned int rate = params_rate(params);
805 u32 cgfr;
806 int ret;
807
808 if (!i2s->mclk_rate) {
809 ret = i2s->set_i2s_clk_rate(i2s, rate);
810 if (ret)
811 return ret;
812 }
813 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
814
815 /*
816 * mckl = mclk_ratio x ws
817 * i2s mode : mclk_ratio = 256
818 * dsp mode : mclk_ratio = 128
819 *
820 * mclk on
821 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
822 * dsp mode : div = i2s_clk / (mclk_ratio * ws)
823 * mclk off
824 * i2s mode : div = i2s_clk / (nb_bits x ws)
825 * dsp mode : div = i2s_clk / (nb_bits x ws)
826 */
827 if (i2s->mclk_rate) {
828 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
829 i2s->mclk_rate);
830 if (ret)
831 return ret;
832 } else {
833 frame_len = 32;
834 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
835 SND_SOC_DAIFMT_DSP_A)
836 frame_len = 16;
837
838 /* master clock not enabled */
839 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
840 if (ret < 0)
841 return ret;
842
843 nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
844 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
845 (nb_bits * rate));
846 if (ret)
847 return ret;
848 }
849
850 ret = stm32_i2s_set_clk_div(i2s);
851 if (ret < 0)
852 return ret;
853
854 /* Set bitclock and frameclock to their inactive state */
855 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
856 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
857 }
858
stm32_i2s_configure(struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * params,struct snd_pcm_substream * substream)859 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
860 struct snd_pcm_hw_params *params,
861 struct snd_pcm_substream *substream)
862 {
863 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
864 int format = params_width(params);
865 u32 cfgr, cfgr_mask, cfg1;
866 unsigned int fthlv;
867 int ret;
868
869 switch (format) {
870 case 16:
871 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
872 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
873 break;
874 case 32:
875 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
876 I2S_CGFR_CHLEN;
877 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
878 break;
879 default:
880 dev_err(cpu_dai->dev, "Unexpected format %d", format);
881 return -EINVAL;
882 }
883
884 if (STM32_I2S_IS_SLAVE(i2s)) {
885 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
886
887 /* As data length is either 16 or 32 bits, fixch always set */
888 cfgr |= I2S_CGFR_FIXCH;
889 cfgr_mask |= I2S_CGFR_FIXCH;
890 } else {
891 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
892 }
893 cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
894
895 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
896 cfgr_mask, cfgr);
897 if (ret < 0)
898 return ret;
899
900 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
901 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
902
903 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
904 I2S_CFG1_FTHVL_MASK, cfg1);
905 }
906
stm32_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)907 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
908 struct snd_soc_dai *cpu_dai)
909 {
910 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
911 unsigned long flags;
912 int ret;
913
914 spin_lock_irqsave(&i2s->irq_lock, flags);
915 i2s->substream = substream;
916 spin_unlock_irqrestore(&i2s->irq_lock, flags);
917
918 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
919 snd_pcm_hw_constraint_single(substream->runtime,
920 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
921
922 ret = clk_prepare_enable(i2s->i2sclk);
923 if (ret < 0) {
924 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
925 return ret;
926 }
927
928 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
929 I2S_IFCR_MASK, I2S_IFCR_MASK);
930 }
931
stm32_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)932 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
933 struct snd_pcm_hw_params *params,
934 struct snd_soc_dai *cpu_dai)
935 {
936 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
937 int ret;
938
939 ret = stm32_i2s_configure(cpu_dai, params, substream);
940 if (ret < 0) {
941 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
942 return ret;
943 }
944
945 if (STM32_I2S_IS_MASTER(i2s))
946 ret = stm32_i2s_configure_clock(cpu_dai, params);
947
948 return ret;
949 }
950
stm32_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)951 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
952 struct snd_soc_dai *cpu_dai)
953 {
954 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
955 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
956 u32 cfg1_mask, ier;
957 int ret;
958
959 switch (cmd) {
960 case SNDRV_PCM_TRIGGER_START:
961 case SNDRV_PCM_TRIGGER_RESUME:
962 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
963 /* Enable i2s */
964 dev_dbg(cpu_dai->dev, "start I2S %s\n",
965 snd_pcm_direction_name(substream->stream));
966
967 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
968 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
969 cfg1_mask, cfg1_mask);
970
971 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
972 I2S_CR1_SPE, I2S_CR1_SPE);
973 if (ret < 0) {
974 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
975 return ret;
976 }
977
978 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
979 I2S_CR1_CSTART, I2S_CR1_CSTART);
980 if (ret < 0) {
981 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
982 return ret;
983 }
984
985 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
986 I2S_IFCR_MASK, I2S_IFCR_MASK);
987
988 spin_lock(&i2s->lock_fd);
989 i2s->refcount++;
990 if (playback_flg) {
991 ier = I2S_IER_UDRIE;
992 } else {
993 ier = I2S_IER_OVRIE;
994
995 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
996 /* dummy write to gate bus clocks */
997 regmap_write(i2s->regmap,
998 STM32_I2S_TXDR_REG, 0);
999 }
1000 spin_unlock(&i2s->lock_fd);
1001
1002 if (STM32_I2S_IS_SLAVE(i2s))
1003 ier |= I2S_IER_TIFREIE;
1004
1005 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
1006 break;
1007 case SNDRV_PCM_TRIGGER_STOP:
1008 case SNDRV_PCM_TRIGGER_SUSPEND:
1009 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1010 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
1011 snd_pcm_direction_name(substream->stream));
1012
1013 if (playback_flg)
1014 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
1015 I2S_IER_UDRIE,
1016 (unsigned int)~I2S_IER_UDRIE);
1017 else
1018 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
1019 I2S_IER_OVRIE,
1020 (unsigned int)~I2S_IER_OVRIE);
1021
1022 spin_lock(&i2s->lock_fd);
1023 i2s->refcount--;
1024 if (i2s->refcount) {
1025 spin_unlock(&i2s->lock_fd);
1026 break;
1027 }
1028
1029 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
1030 I2S_CR1_SPE, 0);
1031 if (ret < 0) {
1032 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
1033 spin_unlock(&i2s->lock_fd);
1034 return ret;
1035 }
1036 spin_unlock(&i2s->lock_fd);
1037
1038 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
1039 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
1040 cfg1_mask, 0);
1041 break;
1042 default:
1043 return -EINVAL;
1044 }
1045
1046 return 0;
1047 }
1048
stm32_i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1049 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
1050 struct snd_soc_dai *cpu_dai)
1051 {
1052 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
1053 unsigned long flags;
1054
1055 clk_disable_unprepare(i2s->i2sclk);
1056
1057 /*
1058 * Release kernel clock if following conditions are fulfilled
1059 * - Master clock is not used. Kernel clock won't be released trough sysclk
1060 * - Put handler is defined. Involve that clock is managed exclusively
1061 */
1062 if (!i2s->i2smclk && i2s->put_i2s_clk_rate)
1063 i2s->put_i2s_clk_rate(i2s);
1064
1065 spin_lock_irqsave(&i2s->irq_lock, flags);
1066 i2s->substream = NULL;
1067 spin_unlock_irqrestore(&i2s->irq_lock, flags);
1068 }
1069
stm32_i2s_dai_probe(struct snd_soc_dai * cpu_dai)1070 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
1071 {
1072 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
1073 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
1074 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
1075
1076 /* Buswidth will be set by framework */
1077 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1078 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
1079 dma_data_tx->maxburst = 1;
1080 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1081 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
1082 dma_data_rx->maxburst = 1;
1083
1084 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
1085
1086 return 0;
1087 }
1088
1089 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
1090 .reg_bits = 32,
1091 .reg_stride = 4,
1092 .val_bits = 32,
1093 .max_register = STM32_I2S_SIDR_REG,
1094 .readable_reg = stm32_i2s_readable_reg,
1095 .volatile_reg = stm32_i2s_volatile_reg,
1096 .writeable_reg = stm32_i2s_writeable_reg,
1097 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
1098 .fast_io = true,
1099 .cache_type = REGCACHE_FLAT,
1100 };
1101
1102 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
1103 .probe = stm32_i2s_dai_probe,
1104 .set_sysclk = stm32_i2s_set_sysclk,
1105 .set_fmt = stm32_i2s_set_dai_fmt,
1106 .startup = stm32_i2s_startup,
1107 .hw_params = stm32_i2s_hw_params,
1108 .trigger = stm32_i2s_trigger,
1109 .shutdown = stm32_i2s_shutdown,
1110 };
1111
1112 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
1113 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1114 .buffer_bytes_max = 8 * PAGE_SIZE,
1115 .period_bytes_min = 1024,
1116 .period_bytes_max = 4 * PAGE_SIZE,
1117 .periods_min = 2,
1118 .periods_max = 8,
1119 };
1120
1121 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
1122 .pcm_hardware = &stm32_i2s_pcm_hw,
1123 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1124 .prealloc_buffer_size = PAGE_SIZE * 8,
1125 };
1126
1127 static const struct snd_soc_component_driver stm32_i2s_component = {
1128 .name = "stm32-i2s",
1129 .legacy_dai_naming = 1,
1130 };
1131
stm32_i2s_dai_init(struct snd_soc_pcm_stream * stream,char * stream_name)1132 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
1133 char *stream_name)
1134 {
1135 stream->stream_name = stream_name;
1136 stream->channels_min = 1;
1137 stream->channels_max = 2;
1138 stream->rates = SNDRV_PCM_RATE_8000_192000;
1139 stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
1140 SNDRV_PCM_FMTBIT_S32_LE;
1141 }
1142
stm32_i2s_dais_init(struct platform_device * pdev,struct stm32_i2s_data * i2s)1143 static int stm32_i2s_dais_init(struct platform_device *pdev,
1144 struct stm32_i2s_data *i2s)
1145 {
1146 struct snd_soc_dai_driver *dai_ptr;
1147
1148 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
1149 GFP_KERNEL);
1150 if (!dai_ptr)
1151 return -ENOMEM;
1152
1153 dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
1154 dai_ptr->id = 1;
1155 stm32_i2s_dai_init(&dai_ptr->playback, "playback");
1156 stm32_i2s_dai_init(&dai_ptr->capture, "capture");
1157 i2s->dai_drv = dai_ptr;
1158
1159 return 0;
1160 }
1161
1162 static const struct stm32_i2s_conf stm32_i2s_conf_h7 = {
1163 .regmap_conf = &stm32_h7_i2s_regmap_conf,
1164 .get_i2s_clk_parent = stm32_i2s_get_parent_clk,
1165 };
1166
1167 static const struct stm32_i2s_conf stm32_i2s_conf_mp25 = {
1168 .regmap_conf = &stm32_h7_i2s_regmap_conf
1169 };
1170
1171 static const struct of_device_id stm32_i2s_ids[] = {
1172 { .compatible = "st,stm32h7-i2s", .data = &stm32_i2s_conf_h7 },
1173 { .compatible = "st,stm32mp25-i2s", .data = &stm32_i2s_conf_mp25 },
1174 {},
1175 };
1176
stm32_i2s_get_parent_clk(struct stm32_i2s_data * i2s)1177 static int stm32_i2s_get_parent_clk(struct stm32_i2s_data *i2s)
1178 {
1179 struct device *dev = &i2s->pdev->dev;
1180
1181 i2s->x8kclk = devm_clk_get(dev, "x8k");
1182 if (IS_ERR(i2s->x8kclk))
1183 return dev_err_probe(dev, PTR_ERR(i2s->x8kclk), "Cannot get x8k parent clock\n");
1184
1185 i2s->x11kclk = devm_clk_get(dev, "x11k");
1186 if (IS_ERR(i2s->x11kclk))
1187 return dev_err_probe(dev, PTR_ERR(i2s->x11kclk), "Cannot get x11k parent clock\n");
1188
1189 return 0;
1190 }
1191
stm32_i2s_parse_dt(struct platform_device * pdev,struct stm32_i2s_data * i2s)1192 static int stm32_i2s_parse_dt(struct platform_device *pdev,
1193 struct stm32_i2s_data *i2s)
1194 {
1195 struct device_node *np = pdev->dev.of_node;
1196 struct reset_control *rst;
1197 struct resource *res;
1198 int irq, ret;
1199
1200 if (!np)
1201 return -ENODEV;
1202
1203 i2s->conf = device_get_match_data(&pdev->dev);
1204 if (!i2s->conf)
1205 return -EINVAL;
1206
1207 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1208 if (IS_ERR(i2s->base))
1209 return PTR_ERR(i2s->base);
1210
1211 i2s->phys_addr = res->start;
1212
1213 /* Get clocks */
1214 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1215 if (IS_ERR(i2s->pclk))
1216 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
1217 "Could not get pclk\n");
1218
1219 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1220 if (IS_ERR(i2s->i2sclk))
1221 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
1222 "Could not get i2sclk\n");
1223
1224 if (i2s->conf->get_i2s_clk_parent) {
1225 i2s->set_i2s_clk_rate = stm32_i2s_set_parent_clock;
1226 } else {
1227 i2s->set_i2s_clk_rate = stm32_i2s_set_parent_rate;
1228 i2s->put_i2s_clk_rate = stm32_i2s_put_parent_rate;
1229 }
1230
1231 if (i2s->conf->get_i2s_clk_parent) {
1232 ret = i2s->conf->get_i2s_clk_parent(i2s);
1233 if (ret)
1234 return ret;
1235 }
1236
1237 /* Register mclk provider if requested */
1238 if (of_property_present(np, "#clock-cells")) {
1239 ret = stm32_i2s_add_mclk_provider(i2s);
1240 if (ret < 0)
1241 return ret;
1242 }
1243
1244 /* Get irqs */
1245 irq = platform_get_irq(pdev, 0);
1246 if (irq < 0)
1247 return irq;
1248
1249 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0,
1250 dev_name(&pdev->dev), i2s);
1251 if (ret) {
1252 dev_err(&pdev->dev, "irq request returned %d\n", ret);
1253 return ret;
1254 }
1255
1256 /* Reset */
1257 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1258 if (IS_ERR(rst))
1259 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
1260 "Reset controller error\n");
1261
1262 reset_control_assert(rst);
1263 udelay(2);
1264 reset_control_deassert(rst);
1265
1266 return 0;
1267 }
1268
stm32_i2s_remove(struct platform_device * pdev)1269 static void stm32_i2s_remove(struct platform_device *pdev)
1270 {
1271 snd_dmaengine_pcm_unregister(&pdev->dev);
1272 snd_soc_unregister_component(&pdev->dev);
1273 pm_runtime_disable(&pdev->dev);
1274 }
1275
stm32_i2s_probe(struct platform_device * pdev)1276 static int stm32_i2s_probe(struct platform_device *pdev)
1277 {
1278 struct stm32_i2s_data *i2s;
1279 u32 val;
1280 int ret;
1281
1282 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1283 if (!i2s)
1284 return -ENOMEM;
1285
1286 i2s->pdev = pdev;
1287 i2s->ms_flg = I2S_MS_NOT_SET;
1288 spin_lock_init(&i2s->lock_fd);
1289 spin_lock_init(&i2s->irq_lock);
1290 platform_set_drvdata(pdev, i2s);
1291
1292 ret = stm32_i2s_parse_dt(pdev, i2s);
1293 if (ret)
1294 return ret;
1295
1296 ret = stm32_i2s_dais_init(pdev, i2s);
1297 if (ret)
1298 return ret;
1299
1300 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1301 i2s->base, i2s->conf->regmap_conf);
1302 if (IS_ERR(i2s->regmap))
1303 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
1304 "Regmap init error\n");
1305
1306 ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
1307 if (ret)
1308 return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
1309
1310 ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
1311 i2s->dai_drv, 1);
1312 if (ret) {
1313 snd_dmaengine_pcm_unregister(&pdev->dev);
1314 return ret;
1315 }
1316
1317 /* Set SPI/I2S in i2s mode */
1318 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1319 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
1320 if (ret)
1321 goto error;
1322
1323 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1324 if (ret)
1325 goto error;
1326
1327 if (val == I2S_IPIDR_NUMBER) {
1328 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1329 if (ret)
1330 goto error;
1331
1332 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
1333 dev_err(&pdev->dev,
1334 "Device does not support i2s mode\n");
1335 ret = -EPERM;
1336 goto error;
1337 }
1338
1339 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1340 if (ret)
1341 goto error;
1342
1343 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
1344 FIELD_GET(I2S_VERR_MAJ_MASK, val),
1345 FIELD_GET(I2S_VERR_MIN_MASK, val));
1346 }
1347
1348 pm_runtime_enable(&pdev->dev);
1349
1350 return ret;
1351
1352 error:
1353 stm32_i2s_remove(pdev);
1354
1355 return ret;
1356 }
1357
1358 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
1359
stm32_i2s_suspend(struct device * dev)1360 static int stm32_i2s_suspend(struct device *dev)
1361 {
1362 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1363
1364 regcache_cache_only(i2s->regmap, true);
1365 regcache_mark_dirty(i2s->regmap);
1366
1367 return 0;
1368 }
1369
stm32_i2s_resume(struct device * dev)1370 static int stm32_i2s_resume(struct device *dev)
1371 {
1372 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1373
1374 regcache_cache_only(i2s->regmap, false);
1375 return regcache_sync(i2s->regmap);
1376 }
1377
1378 static const struct dev_pm_ops stm32_i2s_pm_ops = {
1379 SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1380 };
1381
1382 static struct platform_driver stm32_i2s_driver = {
1383 .driver = {
1384 .name = "st,stm32-i2s",
1385 .of_match_table = stm32_i2s_ids,
1386 .pm = pm_ptr(&stm32_i2s_pm_ops),
1387 },
1388 .probe = stm32_i2s_probe,
1389 .remove = stm32_i2s_remove,
1390 };
1391
1392 module_platform_driver(stm32_i2s_driver);
1393
1394 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1395 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1396 MODULE_ALIAS("platform:stm32-i2s");
1397 MODULE_LICENSE("GPL v2");
1398