1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Type definitions for the Microsoft hypervisor. 4 */ 5 #ifndef _HV_HVGDK_MINI_H 6 #define _HV_HVGDK_MINI_H 7 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 11 struct hv_u128 { 12 u64 low_part; 13 u64 high_part; 14 } __packed; 15 16 /* NOTE: when adding below, update hv_result_to_string() */ 17 #define HV_STATUS_SUCCESS 0x0 18 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 19 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 20 #define HV_STATUS_INVALID_ALIGNMENT 0x4 21 #define HV_STATUS_INVALID_PARAMETER 0x5 22 #define HV_STATUS_ACCESS_DENIED 0x6 23 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 24 #define HV_STATUS_OPERATION_DENIED 0x8 25 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 26 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA 27 #define HV_STATUS_INSUFFICIENT_MEMORY 0xB 28 #define HV_STATUS_INVALID_PARTITION_ID 0xD 29 #define HV_STATUS_INVALID_VP_INDEX 0xE 30 #define HV_STATUS_NOT_FOUND 0x10 31 #define HV_STATUS_INVALID_PORT_ID 0x11 32 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 33 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 34 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 35 #define HV_STATUS_INVALID_VP_STATE 0x15 36 #define HV_STATUS_NO_RESOURCES 0x1D 37 #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 38 #define HV_STATUS_INVALID_LP_INDEX 0x41 39 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 40 #define HV_STATUS_DEVICE_ALREADY_IN_DOMAIN 0x66 41 #define HV_STATUS_OPERATION_FAILED 0x71 42 #define HV_STATUS_INSUFFICIENT_ROOT_MEMORY 0x73 43 #define HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY 0x75 44 #define HV_STATUS_TIME_OUT 0x78 45 #define HV_STATUS_CALL_PENDING 0x79 46 #define HV_STATUS_INSUFFICIENT_CONTIGUOUS_ROOT_MEMORY 0x83 47 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 48 49 /* 50 * The Hyper-V TimeRefCount register and the TSC 51 * page provide a guest VM clock with 100ns tick rate 52 */ 53 #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) 54 55 #define HV_HYP_PAGE_SHIFT 12 56 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 57 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 58 #define HV_HYP_LARGE_PAGE_SHIFT 21 59 60 #define HV_PARTITION_ID_INVALID ((u64)0) 61 #define HV_PARTITION_ID_SELF ((u64)-1) 62 63 /* Hyper-V specific model specific registers (MSRs) */ 64 65 #if defined(CONFIG_X86) 66 /* HV_X64_SYNTHETIC_MSR */ 67 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 68 #define HV_X64_MSR_HYPERCALL 0x40000001 69 #define HV_X64_MSR_VP_INDEX 0x40000002 70 #define HV_X64_MSR_RESET 0x40000003 71 #define HV_X64_MSR_VP_RUNTIME 0x40000010 72 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 73 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 74 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 75 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 76 77 /* Define the virtual APIC registers */ 78 #define HV_X64_MSR_EOI 0x40000070 79 #define HV_X64_MSR_ICR 0x40000071 80 #define HV_X64_MSR_TPR 0x40000072 81 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 82 83 /* Define synthetic interrupt controller model specific registers. */ 84 #define HV_X64_MSR_SCONTROL 0x40000080 85 #define HV_X64_MSR_SVERSION 0x40000081 86 #define HV_X64_MSR_SIEFP 0x40000082 87 #define HV_X64_MSR_SIMP 0x40000083 88 #define HV_X64_MSR_EOM 0x40000084 89 #define HV_X64_MSR_SIRBP 0x40000085 90 #define HV_X64_MSR_SINT0 0x40000090 91 #define HV_X64_MSR_SINT1 0x40000091 92 #define HV_X64_MSR_SINT2 0x40000092 93 #define HV_X64_MSR_SINT3 0x40000093 94 #define HV_X64_MSR_SINT4 0x40000094 95 #define HV_X64_MSR_SINT5 0x40000095 96 #define HV_X64_MSR_SINT6 0x40000096 97 #define HV_X64_MSR_SINT7 0x40000097 98 #define HV_X64_MSR_SINT8 0x40000098 99 #define HV_X64_MSR_SINT9 0x40000099 100 #define HV_X64_MSR_SINT10 0x4000009A 101 #define HV_X64_MSR_SINT11 0x4000009B 102 #define HV_X64_MSR_SINT12 0x4000009C 103 #define HV_X64_MSR_SINT13 0x4000009D 104 #define HV_X64_MSR_SINT14 0x4000009E 105 #define HV_X64_MSR_SINT15 0x4000009F 106 107 /* Define synthetic interrupt controller model specific registers for nested hypervisor */ 108 #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 109 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 110 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 111 #define HV_X64_MSR_NESTED_SIMP 0x40001083 112 #define HV_X64_MSR_NESTED_EOM 0x40001084 113 #define HV_X64_MSR_NESTED_SINT0 0x40001090 114 115 /* 116 * Synthetic Timer MSRs. Four timers per vcpu. 117 */ 118 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 119 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 120 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 121 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 122 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 123 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 124 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 125 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 126 127 /* Hyper-V guest idle MSR */ 128 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 129 130 /* Hyper-V guest crash notification MSR's */ 131 #define HV_X64_MSR_CRASH_P0 0x40000100 132 #define HV_X64_MSR_CRASH_P1 0x40000101 133 #define HV_X64_MSR_CRASH_P2 0x40000102 134 #define HV_X64_MSR_CRASH_P3 0x40000103 135 #define HV_X64_MSR_CRASH_P4 0x40000104 136 #define HV_X64_MSR_CRASH_CTL 0x40000105 137 138 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 139 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 140 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 141 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 142 143 #define HV_X64_MSR_CRASH_PARAMS \ 144 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 145 146 #define HV_IPI_LOW_VECTOR 0x10 147 #define HV_IPI_HIGH_VECTOR 0xff 148 149 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 150 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 151 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 152 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 153 154 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 155 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 156 157 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 158 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 159 160 /* Number of XMM registers used in hypercall input/output */ 161 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 162 163 struct hv_reenlightenment_control { 164 u64 vector : 8; 165 u64 reserved1 : 8; 166 u64 enabled : 1; 167 u64 reserved2 : 15; 168 u64 target_vp : 32; 169 } __packed; 170 171 struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ 172 u64 inprogress : 1; 173 u64 reserved : 63; 174 } __packed; 175 176 struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ 177 u64 enabled : 1; 178 u64 reserved : 63; 179 } __packed; 180 181 /* TSC emulation after migration */ 182 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 183 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 184 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 185 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 186 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 187 188 #endif /* CONFIG_X86 */ 189 190 struct hv_output_get_partition_id { 191 u64 partition_id; 192 } __packed; 193 194 /* HV_CRASH_CTL_REG_CONTENTS */ 195 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 196 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 197 198 union hv_reference_tsc_msr { 199 u64 as_uint64; 200 struct { 201 u64 enable : 1; 202 u64 reserved : 11; 203 u64 pfn : 52; 204 } __packed; 205 }; 206 207 /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */ 208 #define HV_MAX_SPARSE_VCPU_BANKS (64) 209 /* The number of vCPUs in one sparse bank */ 210 #define HV_VCPUS_PER_SPARSE_BANK (64) 211 212 /* 213 * Some of Hyper-V structs do not use hv_vpset where linux uses them. 214 * 215 * struct hv_vpset is usually used as part of hypercall input. The portion 216 * that counts as "fixed size input header" vs. "variable size input header" 217 * varies per hypercall. See comments at relevant hypercall call sites as to 218 * how the "valid_bank_mask" field should be accounted. 219 */ 220 struct hv_vpset { /* HV_VP_SET */ 221 u64 format; 222 u64 valid_bank_mask; 223 u64 bank_contents[]; 224 } __packed; 225 226 /* 227 * Version info reported by hypervisor 228 * Changed to a union for convenience 229 */ 230 union hv_hypervisor_version_info { 231 struct { 232 u32 build_number; 233 234 u32 minor_version : 16; 235 u32 major_version : 16; 236 237 u32 service_pack; 238 239 u32 service_number : 24; 240 u32 service_branch : 8; 241 }; 242 struct { 243 u32 eax; 244 u32 ebx; 245 u32 ecx; 246 u32 edx; 247 }; 248 }; 249 250 /* HV_CPUID_FUNCTION */ 251 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 252 #define HYPERV_CPUID_INTERFACE 0x40000001 253 #define HYPERV_CPUID_VERSION 0x40000002 254 #define HYPERV_CPUID_FEATURES 0x40000003 255 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 256 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 257 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 258 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 259 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 260 261 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 262 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 263 264 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 265 /* Support for the extended IOAPIC RTE format */ 266 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 267 #define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3) 268 269 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 270 #define HYPERV_CPUID_MIN 0x40000005 271 #define HYPERV_CPUID_MAX 0x4000ffff 272 273 /* 274 * HV_X64_HYPERVISOR_FEATURES (EAX), or 275 * HV_PARTITION_PRIVILEGE_MASK [31-0] 276 */ 277 #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0) 278 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 279 #define HV_MSR_SYNIC_AVAILABLE BIT(2) 280 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 281 #define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4) 282 #define HV_MSR_HYPERCALL_AVAILABLE BIT(5) 283 #define HV_MSR_VP_INDEX_AVAILABLE BIT(6) 284 #define HV_MSR_RESET_AVAILABLE BIT(7) 285 #define HV_MSR_STAT_PAGES_AVAILABLE BIT(8) 286 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 287 #define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10) 288 #define HV_ACCESS_FREQUENCY_MSRS BIT(11) 289 #define HV_ACCESS_REENLIGHTENMENT BIT(13) 290 #define HV_ACCESS_TSC_INVARIANT BIT(15) 291 292 /* 293 * HV_X64_HYPERVISOR_FEATURES (EBX), or 294 * HV_PARTITION_PRIVILEGE_MASK [63-32] 295 */ 296 #define HV_CREATE_PARTITIONS BIT(0) 297 #define HV_ACCESS_PARTITION_ID BIT(1) 298 #define HV_ACCESS_MEMORY_POOL BIT(2) 299 #define HV_ADJUST_MESSAGE_BUFFERS BIT(3) 300 #define HV_POST_MESSAGES BIT(4) 301 #define HV_SIGNAL_EVENTS BIT(5) 302 #define HV_CREATE_PORT BIT(6) 303 #define HV_CONNECT_PORT BIT(7) 304 #define HV_ACCESS_STATS BIT(8) 305 #define HV_DEBUGGING BIT(11) 306 #define HV_CPU_MANAGEMENT BIT(12) 307 #define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20) 308 #define HV_ISOLATION BIT(22) 309 310 #if defined(CONFIG_X86) 311 /* HV_X64_HYPERVISOR_FEATURES (EDX) */ 312 #define HV_X64_MWAIT_AVAILABLE BIT(0) 313 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 314 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 315 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 316 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 317 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 318 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 319 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 320 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 321 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 322 /* 323 * Support for returning hypercall output block via XMM 324 * registers is available 325 */ 326 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 327 /* stimer Direct Mode is available */ 328 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 329 330 /* 331 * Implementation recommendations. Indicates which behaviors the hypervisor 332 * recommends the OS implement for optimal performance. 333 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 334 */ 335 /* HV_X64_ENLIGHTENMENT_INFORMATION */ 336 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 337 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 338 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 339 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 340 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 341 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 342 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 343 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 344 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 345 #define HV_X64_HYPERV_NESTED BIT(12) 346 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 347 #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) 348 349 /* 350 * CPU management features identification. 351 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 352 */ 353 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 354 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 355 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 356 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 357 358 /* 359 * Virtual processor will never share a physical core with another virtual 360 * processor, except for virtual processors that are reported as sibling SMT 361 * threads. 362 */ 363 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 364 365 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 366 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 367 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 368 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 369 370 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 371 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 372 373 /* 374 * This is specific to AMD and specifies that enlightened TLB flush is 375 * supported. If guest opts in to this feature, ASID invalidations only 376 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 377 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 378 * or HvFlushGuestPhysicalAddressList). 379 */ 380 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 381 382 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 383 #define HV_PARAVISOR_PRESENT BIT(0) 384 385 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 386 #define HV_ISOLATION_TYPE GENMASK(3, 0) 387 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 388 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 389 390 /* HYPERV_CPUID_FEATURES.ECX bits. */ 391 #define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9) 392 #define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10) 393 394 enum hv_isolation_type { 395 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ 396 HV_ISOLATION_TYPE_VBS = 1, 397 HV_ISOLATION_TYPE_SNP = 2, 398 HV_ISOLATION_TYPE_TDX = 3 399 }; 400 401 union hv_x64_msr_hypercall_contents { 402 u64 as_uint64; 403 struct { 404 u64 enable : 1; 405 u64 reserved : 11; 406 u64 guest_physical_address : 52; 407 } __packed; 408 }; 409 #endif /* CONFIG_X86 */ 410 411 #if defined(CONFIG_ARM64) 412 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8) 413 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) 414 #endif /* CONFIG_ARM64 */ 415 416 #if defined(CONFIG_X86) 417 #define HV_MAXIMUM_PROCESSORS 2048 418 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 419 #define HV_MAXIMUM_PROCESSORS 320 420 #endif /* CONFIG_ARM64 */ 421 422 #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1) 423 #define HV_VP_INDEX_SELF ((u32)-2) 424 #define HV_ANY_VP ((u32)-1) 425 426 union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ 427 u64 as_uint64; 428 struct { 429 u64 enable : 1; 430 u64 reserved : 11; 431 u64 pfn : 52; 432 } __packed; 433 }; 434 435 /* Declare the various hypercall operations. */ 436 /* HV_CALL_CODE */ 437 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 438 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 439 #define HVCALL_GET_LOGICAL_PROCESSOR_RUN_TIME 0x0004 440 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 441 #define HVCALL_SEND_IPI 0x000b 442 #define HVCALL_ENABLE_VP_VTL 0x000f 443 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 444 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 445 #define HVCALL_SEND_IPI_EX 0x0015 446 #define HVCALL_CREATE_PARTITION 0x0040 447 #define HVCALL_INITIALIZE_PARTITION 0x0041 448 #define HVCALL_FINALIZE_PARTITION 0x0042 449 #define HVCALL_DELETE_PARTITION 0x0043 450 #define HVCALL_GET_PARTITION_PROPERTY 0x0044 451 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 452 #define HVCALL_GET_PARTITION_ID 0x0046 453 #define HVCALL_DEPOSIT_MEMORY 0x0048 454 #define HVCALL_WITHDRAW_MEMORY 0x0049 455 #define HVCALL_MAP_GPA_PAGES 0x004b 456 #define HVCALL_UNMAP_GPA_PAGES 0x004c 457 #define HVCALL_INSTALL_INTERCEPT 0x004d 458 #define HVCALL_CREATE_VP 0x004e 459 #define HVCALL_DELETE_VP 0x004f 460 #define HVCALL_GET_VP_REGISTERS 0x0050 461 #define HVCALL_SET_VP_REGISTERS 0x0051 462 #define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052 463 #define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056 464 #define HVCALL_DELETE_PORT 0x0058 465 #define HVCALL_DISCONNECT_PORT 0x005b 466 #define HVCALL_POST_MESSAGE 0x005c 467 #define HVCALL_SIGNAL_EVENT 0x005d 468 #define HVCALL_POST_DEBUG_DATA 0x0069 469 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a 470 #define HVCALL_RESET_DEBUG_SESSION 0x006b 471 #define HVCALL_MAP_STATS_PAGE 0x006c 472 #define HVCALL_UNMAP_STATS_PAGE 0x006d 473 #define HVCALL_SET_SYSTEM_PROPERTY 0x006f 474 #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076 475 #define HVCALL_GET_SYSTEM_PROPERTY 0x007b 476 #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c 477 #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d 478 #define HVCALL_RETARGET_INTERRUPT 0x007e 479 #define HVCALL_NOTIFY_PARTITION_EVENT 0x0087 480 #define HVCALL_ENTER_SLEEP_STATE 0x0084 481 #define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b 482 #define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091 483 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094 484 #define HVCALL_CREATE_PORT 0x0095 485 #define HVCALL_CONNECT_PORT 0x0096 486 #define HVCALL_START_VP 0x0099 487 #define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a 488 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 489 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 490 #define HVCALL_CREATE_DEVICE_DOMAIN 0x00b1 491 #define HVCALL_ATTACH_DEVICE_DOMAIN 0x00b2 492 #define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0 493 #define HVCALL_POST_MESSAGE_DIRECT 0x00c1 494 #define HVCALL_DISPATCH_VP 0x00c2 495 #define HVCALL_DETACH_DEVICE_DOMAIN 0x00c4 496 #define HVCALL_DELETE_DEVICE_DOMAIN 0x00c5 497 #define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9 498 #define HVCALL_CONFIGURE_DEVICE_DOMAIN 0x00ce 499 #define HVCALL_FLUSH_DEVICE_DOMAIN 0x00d0 500 #define HVCALL_FLUSH_DEVICE_DOMAIN_LIST 0x00d1 501 #define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7 502 #define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8 503 #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db 504 #define HVCALL_MAP_VP_STATE_PAGE 0x00e1 505 #define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2 506 #define HVCALL_GET_VP_STATE 0x00e3 507 #define HVCALL_SET_VP_STATE 0x00e4 508 #define HVCALL_GET_VP_CPUID_VALUES 0x00f4 509 #define HVCALL_GET_PARTITION_PROPERTY_EX 0x0101 510 #define HVCALL_MMIO_READ 0x0106 511 #define HVCALL_MMIO_WRITE 0x0107 512 #define HVCALL_DISABLE_HYP_EX 0x010f 513 #define HVCALL_GET_IOMMU_CAPABILITIES 0x0125 514 #define HVCALL_GET_LOGICAL_DEVICE_PROPERTY 0x0127 515 #define HVCALL_MAP_STATS_PAGE2 0x0131 516 517 /* HV_HYPERCALL_INPUT */ 518 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 519 #define HV_HYPERCALL_FAST_BIT BIT(16) 520 #define HV_HYPERCALL_VARHEAD_OFFSET 17 521 #define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17) 522 #define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27) 523 #define HV_HYPERCALL_NESTED BIT_ULL(31) 524 #define HV_HYPERCALL_REP_COMP_OFFSET 32 525 #define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32) 526 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 527 #define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44) 528 #define HV_HYPERCALL_REP_START_OFFSET 48 529 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 530 #define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60) 531 #define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \ 532 HV_HYPERCALL_RSVD1_MASK | \ 533 HV_HYPERCALL_RSVD2_MASK) 534 535 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 536 struct hv_guest_mapping_flush { 537 u64 address_space; 538 u64 flags; 539 } __packed; 540 541 /* 542 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 543 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 544 */ 545 #define HV_MAX_FLUSH_PAGES (2048) 546 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0 547 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1 548 549 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 550 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 551 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 552 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 553 554 /* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */ 555 union hv_gpa_page_range { 556 u64 address_space; 557 struct { 558 u64 additional_pages : 11; 559 u64 largepage : 1; 560 u64 basepfn : 52; 561 } page; 562 struct { 563 u64 reserved : 12; 564 u64 page_size : 1; 565 u64 reserved1 : 8; 566 u64 base_large_pfn : 43; 567 }; 568 }; 569 570 /* 571 * All input flush parameters should be in single page. The max flush 572 * count is equal with how many entries of union hv_gpa_page_range can 573 * be populated into the input parameter page. 574 */ 575 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 576 sizeof(union hv_gpa_page_range)) 577 578 struct hv_guest_mapping_flush_list { 579 u64 address_space; 580 u64 flags; 581 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 582 }; 583 584 struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */ 585 u64 address_space; 586 u64 flags; 587 u64 processor_mask; 588 u64 gva_list[]; 589 } __packed; 590 591 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 592 struct hv_tlb_flush_ex { 593 u64 address_space; 594 u64 flags; 595 __TRAILING_OVERLAP(struct hv_vpset, hv_vp_set, bank_contents, __packed, 596 u64 gva_list[]; 597 ); 598 } __packed; 599 static_assert(offsetof(struct hv_tlb_flush_ex, hv_vp_set.bank_contents) == 600 offsetof(struct hv_tlb_flush_ex, gva_list)); 601 602 struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */ 603 volatile u32 tsc_sequence; 604 u32 reserved1; 605 volatile u64 tsc_scale; 606 volatile s64 tsc_offset; 607 } __packed; 608 609 /* Define the number of synthetic interrupt sources. */ 610 #define HV_SYNIC_SINT_COUNT (16) 611 612 /* Define the expected SynIC version. */ 613 #define HV_SYNIC_VERSION_1 (0x1) 614 /* Valid SynIC vectors are 16-255. */ 615 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 616 617 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 618 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 619 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 620 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 621 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 622 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 623 624 /* Hyper-V defined statically assigned SINTs */ 625 #define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000 626 #define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001 627 #define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002 628 #define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005 629 630 /* mshv assigned SINT for doorbell */ 631 #define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX 632 633 enum hv_interrupt_type { 634 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 635 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 636 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 637 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 638 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 639 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 640 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 641 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 642 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 643 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 644 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 645 }; 646 647 /* Define synthetic interrupt source. */ 648 union hv_synic_sint { 649 u64 as_uint64; 650 struct { 651 u64 vector : 8; 652 u64 reserved1 : 8; 653 u64 masked : 1; 654 u64 auto_eoi : 1; 655 u64 polling : 1; 656 u64 as_intercept : 1; 657 u64 proxy : 1; 658 u64 reserved2 : 43; 659 } __packed; 660 }; 661 662 union hv_x64_xsave_xfem_register { 663 u64 as_uint64; 664 struct { 665 u32 low_uint32; 666 u32 high_uint32; 667 } __packed; 668 struct { 669 u64 legacy_x87 : 1; 670 u64 legacy_sse : 1; 671 u64 avx : 1; 672 u64 mpx_bndreg : 1; 673 u64 mpx_bndcsr : 1; 674 u64 avx_512_op_mask : 1; 675 u64 avx_512_zmmhi : 1; 676 u64 avx_512_zmm16_31 : 1; 677 u64 rsvd8_9 : 2; 678 u64 pasid : 1; 679 u64 cet_u : 1; 680 u64 cet_s : 1; 681 u64 rsvd13_16 : 4; 682 u64 xtile_cfg : 1; 683 u64 xtile_data : 1; 684 u64 rsvd19_63 : 45; 685 } __packed; 686 }; 687 688 /* Synthetic timer configuration */ 689 union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */ 690 u64 as_uint64; 691 struct { 692 u64 enable : 1; 693 u64 periodic : 1; 694 u64 lazy : 1; 695 u64 auto_enable : 1; 696 u64 apic_vector : 8; 697 u64 direct_mode : 1; 698 u64 reserved_z0 : 3; 699 u64 sintx : 4; 700 u64 reserved_z1 : 44; 701 } __packed; 702 }; 703 704 /* Define the number of synthetic timers */ 705 #define HV_SYNIC_STIMER_COUNT (4) 706 707 /* Define port identifier type. */ 708 union hv_port_id { 709 u32 asu32; 710 struct { 711 u32 id : 24; 712 u32 reserved : 8; 713 } __packed u; 714 }; 715 716 #define HV_MESSAGE_SIZE (256) 717 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 718 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 719 720 /* Define hypervisor message types. */ 721 enum hv_message_type { 722 HVMSG_NONE = 0x00000000, 723 724 /* Memory access messages. */ 725 HVMSG_UNMAPPED_GPA = 0x80000000, 726 HVMSG_GPA_INTERCEPT = 0x80000001, 727 728 /* Timer notification messages. */ 729 HVMSG_TIMER_EXPIRED = 0x80000010, 730 731 /* Error messages. */ 732 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 733 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 734 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 735 736 /* 737 * Opaque intercept message. The original intercept message is only 738 * accessible from the mapped intercept message page. 739 */ 740 HVMSG_OPAQUE_INTERCEPT = 0x8000003F, 741 742 /* Trace buffer complete messages. */ 743 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 744 745 /* Hypercall intercept */ 746 HVMSG_HYPERCALL_INTERCEPT = 0x80000050, 747 748 /* SynIC intercepts */ 749 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060, 750 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061, 751 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062, 752 753 /* Async call completion intercept */ 754 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070, 755 756 /* Root scheduler messages */ 757 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100, 758 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101, 759 760 /* Platform-specific processor intercept messages. */ 761 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000, 762 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 763 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 764 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 765 HVMSG_X64_APIC_EOI = 0x80010004, 766 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005, 767 HVMSG_X64_IOMMU_PRQ = 0x80010006, 768 HVMSG_X64_HALT = 0x80010007, 769 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008, 770 HVMSG_X64_SIPI_INTERCEPT = 0x80010009, 771 }; 772 773 /* Define the format of the SIMP register */ 774 union hv_synic_simp { 775 u64 as_uint64; 776 struct { 777 u64 simp_enabled : 1; 778 u64 preserved : 11; 779 u64 base_simp_gpa : 52; 780 } __packed; 781 }; 782 783 union hv_message_flags { 784 u8 asu8; 785 struct { 786 u8 msg_pending : 1; 787 u8 reserved : 7; 788 } __packed; 789 }; 790 791 struct hv_message_header { 792 u32 message_type; 793 u8 payload_size; 794 union hv_message_flags message_flags; 795 u8 reserved[2]; 796 union { 797 u64 sender; 798 union hv_port_id port; 799 }; 800 } __packed; 801 802 /* 803 * Message format for notifications delivered via 804 * intercept message(as_intercept=1) 805 */ 806 struct hv_notification_message_payload { 807 u32 sint_index; 808 } __packed; 809 810 struct hv_message { 811 struct hv_message_header header; 812 union { 813 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 814 } u; 815 } __packed; 816 817 /* Define the synthetic interrupt message page layout. */ 818 struct hv_message_page { 819 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 820 } __packed; 821 822 /* Define timer message payload structure. */ 823 struct hv_timer_message_payload { 824 u32 timer_index; 825 u32 reserved; 826 u64 expiration_time; /* When the timer expired */ 827 u64 delivery_time; /* When the message was delivered */ 828 } __packed; 829 830 struct hv_x64_segment_register { 831 u64 base; 832 u32 limit; 833 u16 selector; 834 union { 835 struct { 836 u16 segment_type : 4; 837 u16 non_system_segment : 1; 838 u16 descriptor_privilege_level : 2; 839 u16 present : 1; 840 u16 reserved : 4; 841 u16 available : 1; 842 u16 _long : 1; 843 u16 _default : 1; 844 u16 granularity : 1; 845 } __packed; 846 u16 attributes; 847 }; 848 } __packed; 849 850 struct hv_x64_table_register { 851 u16 pad[3]; 852 u16 limit; 853 u64 base; 854 } __packed; 855 856 #define HV_NORMAL_VTL 0 857 858 union hv_input_vtl { 859 u8 as_uint8; 860 struct { 861 u8 target_vtl : 4; 862 u8 use_target_vtl : 1; 863 u8 reserved_z : 3; 864 }; 865 } __packed; 866 867 struct hv_init_vp_context { 868 u64 rip; 869 u64 rsp; 870 u64 rflags; 871 872 struct hv_x64_segment_register cs; 873 struct hv_x64_segment_register ds; 874 struct hv_x64_segment_register es; 875 struct hv_x64_segment_register fs; 876 struct hv_x64_segment_register gs; 877 struct hv_x64_segment_register ss; 878 struct hv_x64_segment_register tr; 879 struct hv_x64_segment_register ldtr; 880 881 struct hv_x64_table_register idtr; 882 struct hv_x64_table_register gdtr; 883 884 u64 efer; 885 u64 cr0; 886 u64 cr3; 887 u64 cr4; 888 u64 msr_cr_pat; 889 } __packed; 890 891 struct hv_enable_vp_vtl { 892 u64 partition_id; 893 u32 vp_index; 894 union hv_input_vtl target_vtl; 895 u8 mbz0; 896 u16 mbz1; 897 struct hv_init_vp_context vp_context; 898 } __packed; 899 900 struct hv_get_vp_from_apic_id_in { 901 u64 partition_id; 902 union hv_input_vtl target_vtl; 903 u8 res[7]; 904 u32 apic_ids[]; 905 } __packed; 906 907 union hv_register_vsm_partition_config { 908 u64 as_uint64; 909 struct { 910 u64 enable_vtl_protection : 1; 911 u64 default_vtl_protection_mask : 4; 912 u64 zero_memory_on_reset : 1; 913 u64 deny_lower_vtl_startup : 1; 914 u64 intercept_acceptance : 1; 915 u64 intercept_enable_vtl_protection : 1; 916 u64 intercept_vp_startup : 1; 917 u64 intercept_cpuid_unimplemented : 1; 918 u64 intercept_unrecoverable_exception : 1; 919 u64 intercept_page : 1; 920 u64 mbz : 51; 921 } __packed; 922 }; 923 924 union hv_register_vsm_capabilities { 925 u64 as_uint64; 926 struct { 927 u64 dr6_shared: 1; 928 u64 mbec_vtl_mask: 16; 929 u64 deny_lower_vtl_startup: 1; 930 u64 supervisor_shadow_stack: 1; 931 u64 hardware_hvpt_available: 1; 932 u64 software_hvpt_available: 1; 933 u64 hardware_hvpt_range_bits: 6; 934 u64 intercept_page_available: 1; 935 u64 return_action_available: 1; 936 u64 reserved: 35; 937 } __packed; 938 }; 939 940 union hv_register_vsm_page_offsets { 941 struct { 942 u64 vtl_call_offset : 12; 943 u64 vtl_return_offset : 12; 944 u64 reserved_mbz : 40; 945 } __packed; 946 u64 as_uint64; 947 }; 948 949 struct hv_nested_enlightenments_control { 950 struct { 951 u32 directhypercall : 1; 952 u32 reserved : 31; 953 } __packed features; 954 struct { 955 u32 inter_partition_comm : 1; 956 u32 reserved : 31; 957 } __packed hypercall_controls; 958 } __packed; 959 960 /* Define virtual processor assist page structure. */ 961 struct hv_vp_assist_page { 962 u32 apic_assist; 963 u32 reserved1; 964 u32 vtl_entry_reason; 965 u32 vtl_reserved; 966 u64 vtl_ret_x64rax; 967 u64 vtl_ret_x64rcx; 968 struct hv_nested_enlightenments_control nested_control; 969 u8 enlighten_vmentry; 970 u8 reserved2[7]; 971 u64 current_nested_vmcs; 972 u8 synthetic_time_unhalted_timer_expired; 973 u8 reserved3[7]; 974 u8 virtualization_fault_information[40]; 975 u8 reserved4[8]; 976 u8 intercept_message[256]; 977 u8 vtl_ret_actions[256]; 978 } __packed; 979 980 enum hv_register_name { 981 /* Suspend Registers */ 982 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000, 983 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001, 984 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003, 985 986 /* Version - 128-bit result same as CPUID 0x40000002 */ 987 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100, 988 989 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */ 990 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200, 991 HV_REGISTER_FEATURES_INFO = 0x00000201, 992 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202, 993 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203, 994 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204, 995 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205, 996 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206, 997 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207, 998 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208, 999 1000 /* Guest Crash Registers */ 1001 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210, 1002 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211, 1003 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212, 1004 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213, 1005 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214, 1006 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215, 1007 1008 /* Misc */ 1009 HV_REGISTER_VP_RUNTIME = 0x00090000, 1010 HV_REGISTER_GUEST_OS_ID = 0x00090002, 1011 HV_REGISTER_VP_INDEX = 0x00090003, 1012 HV_REGISTER_TIME_REF_COUNT = 0x00090004, 1013 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007, 1014 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013, 1015 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014, 1016 HV_REGISTER_REFERENCE_TSC = 0x00090017, 1017 1018 /* Hypervisor-defined Registers (Synic) */ 1019 HV_REGISTER_SINT0 = 0x000A0000, 1020 HV_REGISTER_SINT1 = 0x000A0001, 1021 HV_REGISTER_SINT2 = 0x000A0002, 1022 HV_REGISTER_SINT3 = 0x000A0003, 1023 HV_REGISTER_SINT4 = 0x000A0004, 1024 HV_REGISTER_SINT5 = 0x000A0005, 1025 HV_REGISTER_SINT6 = 0x000A0006, 1026 HV_REGISTER_SINT7 = 0x000A0007, 1027 HV_REGISTER_SINT8 = 0x000A0008, 1028 HV_REGISTER_SINT9 = 0x000A0009, 1029 HV_REGISTER_SINT10 = 0x000A000A, 1030 HV_REGISTER_SINT11 = 0x000A000B, 1031 HV_REGISTER_SINT12 = 0x000A000C, 1032 HV_REGISTER_SINT13 = 0x000A000D, 1033 HV_REGISTER_SINT14 = 0x000A000E, 1034 HV_REGISTER_SINT15 = 0x000A000F, 1035 HV_REGISTER_SCONTROL = 0x000A0010, 1036 HV_REGISTER_SVERSION = 0x000A0011, 1037 HV_REGISTER_SIEFP = 0x000A0012, 1038 HV_REGISTER_SIMP = 0x000A0013, 1039 HV_REGISTER_EOM = 0x000A0014, 1040 HV_REGISTER_SIRBP = 0x000A0015, 1041 1042 HV_REGISTER_NESTED_SINT0 = 0x000A1000, 1043 HV_REGISTER_NESTED_SINT1 = 0x000A1001, 1044 HV_REGISTER_NESTED_SINT2 = 0x000A1002, 1045 HV_REGISTER_NESTED_SINT3 = 0x000A1003, 1046 HV_REGISTER_NESTED_SINT4 = 0x000A1004, 1047 HV_REGISTER_NESTED_SINT5 = 0x000A1005, 1048 HV_REGISTER_NESTED_SINT6 = 0x000A1006, 1049 HV_REGISTER_NESTED_SINT7 = 0x000A1007, 1050 HV_REGISTER_NESTED_SINT8 = 0x000A1008, 1051 HV_REGISTER_NESTED_SINT9 = 0x000A1009, 1052 HV_REGISTER_NESTED_SINT10 = 0x000A100A, 1053 HV_REGISTER_NESTED_SINT11 = 0x000A100B, 1054 HV_REGISTER_NESTED_SINT12 = 0x000A100C, 1055 HV_REGISTER_NESTED_SINT13 = 0x000A100D, 1056 HV_REGISTER_NESTED_SINT14 = 0x000A100E, 1057 HV_REGISTER_NESTED_SINT15 = 0x000A100F, 1058 HV_REGISTER_NESTED_SCONTROL = 0x000A1010, 1059 HV_REGISTER_NESTED_SVERSION = 0x000A1011, 1060 HV_REGISTER_NESTED_SIFP = 0x000A1012, 1061 HV_REGISTER_NESTED_SIPP = 0x000A1013, 1062 HV_REGISTER_NESTED_EOM = 0x000A1014, 1063 HV_REGISTER_NESTED_SIRBP = 0x000a1015, 1064 1065 /* Hypervisor-defined Registers (Synthetic Timers) */ 1066 HV_REGISTER_STIMER0_CONFIG = 0x000B0000, 1067 HV_REGISTER_STIMER0_COUNT = 0x000B0001, 1068 1069 /* VSM */ 1070 HV_REGISTER_VSM_VP_STATUS = 0x000D0003, 1071 1072 /* Synthetic VSM registers */ 1073 HV_REGISTER_VSM_CODE_PAGE_OFFSETS = 0x000D0002, 1074 HV_REGISTER_VSM_CAPABILITIES = 0x000D0006, 1075 HV_REGISTER_VSM_PARTITION_CONFIG = 0x000D0007, 1076 1077 #if defined(CONFIG_X86) 1078 /* X64 Debug Registers */ 1079 HV_X64_REGISTER_DR0 = 0x00050000, 1080 HV_X64_REGISTER_DR1 = 0x00050001, 1081 HV_X64_REGISTER_DR2 = 0x00050002, 1082 HV_X64_REGISTER_DR3 = 0x00050003, 1083 HV_X64_REGISTER_DR6 = 0x00050004, 1084 HV_X64_REGISTER_DR7 = 0x00050005, 1085 1086 /* X64 Cache control MSRs */ 1087 HV_X64_REGISTER_MSR_MTRR_CAP = 0x0008000D, 1088 HV_X64_REGISTER_MSR_MTRR_DEF_TYPE = 0x0008000E, 1089 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 = 0x00080010, 1090 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1 = 0x00080011, 1091 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2 = 0x00080012, 1092 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3 = 0x00080013, 1093 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4 = 0x00080014, 1094 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5 = 0x00080015, 1095 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6 = 0x00080016, 1096 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7 = 0x00080017, 1097 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8 = 0x00080018, 1098 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9 = 0x00080019, 1099 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA = 0x0008001A, 1100 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB = 0x0008001B, 1101 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC = 0x0008001C, 1102 HV_X64_REGISTER_MSR_MTRR_PHYS_BASED = 0x0008001D, 1103 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE = 0x0008001E, 1104 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF = 0x0008001F, 1105 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 = 0x00080040, 1106 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1 = 0x00080041, 1107 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2 = 0x00080042, 1108 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3 = 0x00080043, 1109 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4 = 0x00080044, 1110 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5 = 0x00080045, 1111 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6 = 0x00080046, 1112 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7 = 0x00080047, 1113 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8 = 0x00080048, 1114 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9 = 0x00080049, 1115 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA = 0x0008004A, 1116 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB = 0x0008004B, 1117 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC = 0x0008004C, 1118 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD = 0x0008004D, 1119 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE = 0x0008004E, 1120 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF = 0x0008004F, 1121 HV_X64_REGISTER_MSR_MTRR_FIX64K00000 = 0x00080070, 1122 HV_X64_REGISTER_MSR_MTRR_FIX16K80000 = 0x00080071, 1123 HV_X64_REGISTER_MSR_MTRR_FIX16KA0000 = 0x00080072, 1124 HV_X64_REGISTER_MSR_MTRR_FIX4KC0000 = 0x00080073, 1125 HV_X64_REGISTER_MSR_MTRR_FIX4KC8000 = 0x00080074, 1126 HV_X64_REGISTER_MSR_MTRR_FIX4KD0000 = 0x00080075, 1127 HV_X64_REGISTER_MSR_MTRR_FIX4KD8000 = 0x00080076, 1128 HV_X64_REGISTER_MSR_MTRR_FIX4KE0000 = 0x00080077, 1129 HV_X64_REGISTER_MSR_MTRR_FIX4KE8000 = 0x00080078, 1130 HV_X64_REGISTER_MSR_MTRR_FIX4KF0000 = 0x00080079, 1131 HV_X64_REGISTER_MSR_MTRR_FIX4KF8000 = 0x0008007A, 1132 1133 HV_X64_REGISTER_REG_PAGE = 0x0009001C, 1134 #elif defined(CONFIG_ARM64) 1135 HV_ARM64_REGISTER_SINT_RESERVED_INTERRUPT_ID = 0x00070001, 1136 #endif 1137 }; 1138 1139 /* 1140 * Arch compatibility regs for use with hv_set/get_register 1141 */ 1142 #if defined(CONFIG_X86) 1143 1144 /* 1145 * To support arch-generic code calling hv_set/get_register: 1146 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq 1147 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 1148 */ 1149 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0) 1150 #define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1) 1151 #define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2) 1152 #define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3) 1153 #define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4) 1154 #define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL) 1155 1156 #define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX) 1157 #define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) 1158 #define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) 1159 1160 #define HV_MSR_SINT0 (HV_X64_MSR_SINT0) 1161 #define HV_MSR_SVERSION (HV_X64_MSR_SVERSION) 1162 #define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL) 1163 #define HV_MSR_SIEFP (HV_X64_MSR_SIEFP) 1164 #define HV_MSR_SIMP (HV_X64_MSR_SIMP) 1165 #define HV_MSR_EOM (HV_X64_MSR_EOM) 1166 #define HV_MSR_SIRBP (HV_X64_MSR_SIRBP) 1167 1168 #define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL) 1169 #define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION) 1170 #define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP) 1171 #define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP) 1172 #define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM) 1173 #define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0) 1174 1175 #define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) 1176 #define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) 1177 1178 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1179 1180 #define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0) 1181 #define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1) 1182 #define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2) 1183 #define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3) 1184 #define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4) 1185 #define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL) 1186 1187 #define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX) 1188 #define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) 1189 #define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) 1190 1191 #define HV_MSR_SINT0 (HV_REGISTER_SINT0) 1192 #define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL) 1193 #define HV_MSR_SIEFP (HV_REGISTER_SIEFP) 1194 #define HV_MSR_SIMP (HV_REGISTER_SIMP) 1195 #define HV_MSR_EOM (HV_REGISTER_EOM) 1196 #define HV_MSR_SIRBP (HV_REGISTER_SIRBP) 1197 1198 #define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) 1199 #define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) 1200 1201 #endif /* CONFIG_ARM64 */ 1202 1203 union hv_explicit_suspend_register { 1204 u64 as_uint64; 1205 struct { 1206 u64 suspended : 1; 1207 u64 reserved : 63; 1208 } __packed; 1209 }; 1210 1211 union hv_intercept_suspend_register { 1212 u64 as_uint64; 1213 struct { 1214 u64 suspended : 1; 1215 u64 reserved : 63; 1216 } __packed; 1217 }; 1218 1219 union hv_dispatch_suspend_register { 1220 u64 as_uint64; 1221 struct { 1222 u64 suspended : 1; 1223 u64 reserved : 63; 1224 } __packed; 1225 }; 1226 1227 union hv_arm64_pending_interruption_register { 1228 u64 as_uint64; 1229 struct { 1230 u64 interruption_pending : 1; 1231 u64 interruption_type: 1; 1232 u64 reserved : 30; 1233 u64 error_code : 32; 1234 } __packed; 1235 }; 1236 1237 union hv_arm64_interrupt_state_register { 1238 u64 as_uint64; 1239 struct { 1240 u64 interrupt_shadow : 1; 1241 u64 reserved : 63; 1242 } __packed; 1243 }; 1244 1245 union hv_arm64_pending_synthetic_exception_event { 1246 u64 as_uint64[2]; 1247 struct { 1248 u8 event_pending : 1; 1249 u8 event_type : 3; 1250 u8 reserved : 4; 1251 u8 rsvd[3]; 1252 u32 exception_type; 1253 u64 context; 1254 } __packed; 1255 }; 1256 1257 union hv_x64_interrupt_state_register { 1258 u64 as_uint64; 1259 struct { 1260 u64 interrupt_shadow : 1; 1261 u64 nmi_masked : 1; 1262 u64 reserved : 62; 1263 } __packed; 1264 }; 1265 1266 union hv_x64_pending_interruption_register { 1267 u64 as_uint64; 1268 struct { 1269 u32 interruption_pending : 1; 1270 u32 interruption_type : 3; 1271 u32 deliver_error_code : 1; 1272 u32 instruction_length : 4; 1273 u32 nested_event : 1; 1274 u32 reserved : 6; 1275 u32 interruption_vector : 16; 1276 u32 error_code; 1277 } __packed; 1278 }; 1279 1280 union hv_register_value { 1281 struct hv_u128 reg128; 1282 u64 reg64; 1283 u32 reg32; 1284 u16 reg16; 1285 u8 reg8; 1286 1287 struct hv_x64_segment_register segment; 1288 struct hv_x64_table_register table; 1289 union hv_explicit_suspend_register explicit_suspend; 1290 union hv_intercept_suspend_register intercept_suspend; 1291 union hv_dispatch_suspend_register dispatch_suspend; 1292 #ifdef CONFIG_ARM64 1293 union hv_arm64_interrupt_state_register interrupt_state; 1294 union hv_arm64_pending_interruption_register pending_interruption; 1295 #endif 1296 #ifdef CONFIG_X86 1297 union hv_x64_interrupt_state_register interrupt_state; 1298 union hv_x64_pending_interruption_register pending_interruption; 1299 #endif 1300 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event; 1301 }; 1302 1303 /* NOTE: Linux helper struct - NOT from Hyper-V code. */ 1304 struct hv_output_get_vp_registers { 1305 DECLARE_FLEX_ARRAY(union hv_register_value, values); 1306 }; 1307 1308 #if defined(CONFIG_ARM64) 1309 /* HvGetVpRegisters returns an array of these output elements */ 1310 struct hv_get_vp_registers_output { 1311 union { 1312 struct { 1313 u32 a; 1314 u32 b; 1315 u32 c; 1316 u32 d; 1317 } as32 __packed; 1318 struct { 1319 u64 low; 1320 u64 high; 1321 } as64 __packed; 1322 }; 1323 }; 1324 1325 #endif /* CONFIG_ARM64 */ 1326 1327 struct hv_register_assoc { 1328 u32 name; /* enum hv_register_name */ 1329 u32 reserved1; 1330 u64 reserved2; 1331 union hv_register_value value; 1332 } __packed; 1333 1334 struct hv_input_get_vp_registers { 1335 u64 partition_id; 1336 u32 vp_index; 1337 union hv_input_vtl input_vtl; 1338 u8 rsvd_z8; 1339 u16 rsvd_z16; 1340 u32 names[]; 1341 } __packed; 1342 1343 struct hv_input_set_vp_registers { 1344 u64 partition_id; 1345 u32 vp_index; 1346 union hv_input_vtl input_vtl; 1347 u8 rsvd_z8; 1348 u16 rsvd_z16; 1349 struct hv_register_assoc elements[]; 1350 } __packed; 1351 1352 #define HV_UNMAP_GPA_LARGE_PAGE 0x2 1353 1354 /* HvCallSendSyntheticClusterIpi hypercall */ 1355 struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */ 1356 u32 vector; 1357 u32 reserved; 1358 u64 cpu_mask; 1359 } __packed; 1360 1361 #define HV_VTL_MASK GENMASK(3, 0) 1362 1363 /* Hyper-V memory host visibility */ 1364 enum hv_mem_host_visibility { 1365 VMBUS_PAGE_NOT_VISIBLE = 0, 1366 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 1367 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 1368 }; 1369 1370 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 1371 #define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2) 1372 struct hv_gpa_range_for_visibility { 1373 u64 partition_id; 1374 u32 host_visibility : 2; 1375 u32 reserved0 : 30; 1376 u32 reserved1; 1377 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 1378 } __packed; 1379 1380 #if defined(CONFIG_X86) 1381 union hv_msi_address_register { /* HV_MSI_ADDRESS */ 1382 u32 as_uint32; 1383 struct { 1384 u32 reserved1 : 2; 1385 u32 destination_mode : 1; 1386 u32 redirection_hint : 1; 1387 u32 reserved2 : 8; 1388 u32 destination_id : 8; 1389 u32 msi_base : 12; 1390 }; 1391 } __packed; 1392 1393 union hv_msi_data_register { /* HV_MSI_ENTRY.Data */ 1394 u32 as_uint32; 1395 struct { 1396 u32 vector : 8; 1397 u32 delivery_mode : 3; 1398 u32 reserved1 : 3; 1399 u32 level_assert : 1; 1400 u32 trigger_mode : 1; 1401 u32 reserved2 : 16; 1402 }; 1403 } __packed; 1404 1405 union hv_msi_entry { /* HV_MSI_ENTRY */ 1406 1407 u64 as_uint64; 1408 struct { 1409 union hv_msi_address_register address; 1410 union hv_msi_data_register data; 1411 } __packed; 1412 }; 1413 1414 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1415 1416 union hv_msi_entry { 1417 u64 as_uint64[2]; 1418 struct { 1419 u64 address; 1420 u32 data; 1421 u32 reserved; 1422 } __packed; 1423 }; 1424 #endif /* CONFIG_ARM64 */ 1425 1426 union hv_ioapic_rte { 1427 u64 as_uint64; 1428 1429 struct { 1430 u32 vector : 8; 1431 u32 delivery_mode : 3; 1432 u32 destination_mode : 1; 1433 u32 delivery_status : 1; 1434 u32 interrupt_polarity : 1; 1435 u32 remote_irr : 1; 1436 u32 trigger_mode : 1; 1437 u32 interrupt_mask : 1; 1438 u32 reserved1 : 15; 1439 1440 u32 reserved2 : 24; 1441 u32 destination_id : 8; 1442 }; 1443 1444 struct { 1445 u32 low_uint32; 1446 u32 high_uint32; 1447 }; 1448 } __packed; 1449 1450 enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */ 1451 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */ 1452 HV_INTERRUPT_SOURCE_IOAPIC, 1453 }; 1454 1455 struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */ 1456 u32 source; 1457 u32 reserved1; 1458 union { 1459 union hv_msi_entry msi_entry; 1460 union hv_ioapic_rte ioapic_rte; 1461 }; 1462 } __packed; 1463 1464 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1 1465 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2 1466 1467 struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */ 1468 u32 vector; 1469 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */ 1470 union { 1471 u64 vp_mask; 1472 struct hv_vpset vp_set; 1473 }; 1474 } __packed; 1475 1476 struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */ 1477 u64 partition_id; /* use "self" */ 1478 u64 device_id; 1479 struct hv_interrupt_entry int_entry; 1480 u64 reserved2; 1481 struct hv_device_interrupt_target int_target; 1482 } __packed __aligned(8); 1483 1484 enum hv_intercept_type { 1485 #if defined(CONFIG_X86) 1486 HV_INTERCEPT_TYPE_X64_IO_PORT = 0x00000000, 1487 HV_INTERCEPT_TYPE_X64_MSR = 0x00000001, 1488 HV_INTERCEPT_TYPE_X64_CPUID = 0x00000002, 1489 #endif 1490 HV_INTERCEPT_TYPE_EXCEPTION = 0x00000003, 1491 /* Used to be HV_INTERCEPT_TYPE_REGISTER */ 1492 HV_INTERCEPT_TYPE_RESERVED0 = 0x00000004, 1493 HV_INTERCEPT_TYPE_MMIO = 0x00000005, 1494 #if defined(CONFIG_X86) 1495 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0x00000006, 1496 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0x00000007, 1497 #endif 1498 HV_INTERCEPT_TYPE_HYPERCALL = 0x00000008, 1499 #if defined(CONFIG_X86) 1500 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0x00000009, 1501 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0x0000000A, 1502 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0x0000000B, 1503 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0x0000000C, 1504 #endif 1505 HV_INTERCEPT_TYPE_MAX, 1506 HV_INTERCEPT_TYPE_INVALID = 0xFFFFFFFF, 1507 }; 1508 1509 union hv_intercept_parameters { 1510 /* HV_INTERCEPT_PARAMETERS is defined to be an 8-byte field. */ 1511 u64 as_uint64; 1512 #if defined(CONFIG_X86) 1513 /* HV_INTERCEPT_TYPE_X64_IO_PORT */ 1514 u16 io_port; 1515 /* HV_INTERCEPT_TYPE_X64_CPUID */ 1516 u32 cpuid_index; 1517 /* HV_INTERCEPT_TYPE_X64_APIC_WRITE */ 1518 u32 apic_write_mask; 1519 /* HV_INTERCEPT_TYPE_EXCEPTION */ 1520 u16 exception_vector; 1521 /* HV_INTERCEPT_TYPE_X64_MSR_INDEX */ 1522 u32 msr_index; 1523 #endif 1524 /* N.B. Other intercept types do not have any parameters. */ 1525 }; 1526 1527 /* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */ 1528 #define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64 1529 1530 struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */ 1531 u64 gpa; 1532 u32 size; 1533 u32 reserved; 1534 } __packed; 1535 1536 struct hv_mmio_read_output { 1537 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1538 } __packed; 1539 1540 struct hv_mmio_write_input { 1541 u64 gpa; 1542 u32 size; 1543 u32 reserved; 1544 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1545 } __packed; 1546 1547 enum hv_intercept_access_type { 1548 HV_INTERCEPT_ACCESS_READ = 0, 1549 HV_INTERCEPT_ACCESS_WRITE = 1, 1550 HV_INTERCEPT_ACCESS_EXECUTE = 2 1551 }; 1552 1553 #endif /* _HV_HVGDK_MINI_H */ 1554