1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com> 4 * Loongson HyperTransport Interrupt Vector support 5 */ 6 7 #define pr_fmt(fmt) "htvec: " fmt 8 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqdomain.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/kernel.h> 15 #include <linux/platform_device.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/syscore_ops.h> 19 20 #include "irq-loongson.h" 21 22 /* Registers */ 23 #define HTVEC_EN_OFF 0x20 24 #define HTVEC_MAX_PARENT_IRQ 8 25 #define VEC_COUNT_PER_REG 32 26 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) 27 #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) 28 29 struct htvec { 30 int num_parents; 31 void __iomem *base; 32 struct irq_domain *htvec_domain; 33 raw_spinlock_t htvec_lock; 34 u32 saved_vec_en[HTVEC_MAX_PARENT_IRQ]; 35 }; 36 37 static struct htvec *htvec_priv; 38 39 static void htvec_irq_dispatch(struct irq_desc *desc) 40 { 41 int i; 42 u32 pending; 43 bool handled = false; 44 struct irq_chip *chip = irq_desc_get_chip(desc); 45 struct htvec *priv = irq_desc_get_handler_data(desc); 46 47 chained_irq_enter(chip, desc); 48 49 for (i = 0; i < priv->num_parents; i++) { 50 pending = readl(priv->base + 4 * i); 51 while (pending) { 52 int bit = __ffs(pending); 53 54 generic_handle_domain_irq(priv->htvec_domain, 55 bit + VEC_COUNT_PER_REG * i); 56 pending &= ~BIT(bit); 57 handled = true; 58 } 59 } 60 61 if (!handled) 62 spurious_interrupt(); 63 64 chained_irq_exit(chip, desc); 65 } 66 67 static void htvec_ack_irq(struct irq_data *d) 68 { 69 struct htvec *priv = irq_data_get_irq_chip_data(d); 70 71 writel(BIT(VEC_REG_BIT(d->hwirq)), 72 priv->base + VEC_REG_IDX(d->hwirq) * 4); 73 } 74 75 static void htvec_mask_irq(struct irq_data *d) 76 { 77 u32 reg; 78 void __iomem *addr; 79 struct htvec *priv = irq_data_get_irq_chip_data(d); 80 81 raw_spin_lock(&priv->htvec_lock); 82 addr = priv->base + HTVEC_EN_OFF; 83 addr += VEC_REG_IDX(d->hwirq) * 4; 84 reg = readl(addr); 85 reg &= ~BIT(VEC_REG_BIT(d->hwirq)); 86 writel(reg, addr); 87 raw_spin_unlock(&priv->htvec_lock); 88 } 89 90 static void htvec_unmask_irq(struct irq_data *d) 91 { 92 u32 reg; 93 void __iomem *addr; 94 struct htvec *priv = irq_data_get_irq_chip_data(d); 95 96 raw_spin_lock(&priv->htvec_lock); 97 addr = priv->base + HTVEC_EN_OFF; 98 addr += VEC_REG_IDX(d->hwirq) * 4; 99 reg = readl(addr); 100 reg |= BIT(VEC_REG_BIT(d->hwirq)); 101 writel(reg, addr); 102 raw_spin_unlock(&priv->htvec_lock); 103 } 104 105 static struct irq_chip htvec_irq_chip = { 106 .name = "LOONGSON_HTVEC", 107 .irq_mask = htvec_mask_irq, 108 .irq_unmask = htvec_unmask_irq, 109 .irq_ack = htvec_ack_irq, 110 }; 111 112 static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq, 113 unsigned int nr_irqs, void *arg) 114 { 115 int ret; 116 unsigned long hwirq; 117 unsigned int type, i; 118 struct htvec *priv = domain->host_data; 119 120 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type); 121 if (ret) 122 return ret; 123 124 for (i = 0; i < nr_irqs; i++) { 125 irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip, 126 priv, handle_edge_irq, NULL, NULL); 127 } 128 129 return 0; 130 } 131 132 static void htvec_domain_free(struct irq_domain *domain, unsigned int virq, 133 unsigned int nr_irqs) 134 { 135 int i; 136 137 for (i = 0; i < nr_irqs; i++) { 138 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 139 140 irq_set_handler(virq + i, NULL); 141 irq_domain_reset_irq_data(d); 142 } 143 } 144 145 static const struct irq_domain_ops htvec_domain_ops = { 146 .translate = irq_domain_translate_onecell, 147 .alloc = htvec_domain_alloc, 148 .free = htvec_domain_free, 149 }; 150 151 static void htvec_reset(struct htvec *priv) 152 { 153 u32 idx; 154 155 /* Clear IRQ cause registers, mask all interrupts */ 156 for (idx = 0; idx < priv->num_parents; idx++) { 157 writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx); 158 writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx); 159 } 160 } 161 162 static int htvec_suspend(void *data) 163 { 164 int i; 165 166 for (i = 0; i < htvec_priv->num_parents; i++) 167 htvec_priv->saved_vec_en[i] = readl(htvec_priv->base + HTVEC_EN_OFF + 4 * i); 168 169 return 0; 170 } 171 172 static void htvec_resume(void *data) 173 { 174 int i; 175 176 for (i = 0; i < htvec_priv->num_parents; i++) 177 writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i); 178 } 179 180 static const struct syscore_ops htvec_syscore_ops = { 181 .suspend = htvec_suspend, 182 .resume = htvec_resume, 183 }; 184 185 static struct syscore htvec_syscore = { 186 .ops = &htvec_syscore_ops, 187 }; 188 189 static int htvec_init(phys_addr_t addr, unsigned long size, 190 int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) 191 { 192 int i; 193 struct htvec *priv; 194 195 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 196 if (!priv) 197 return -ENOMEM; 198 199 priv->num_parents = num_parents; 200 priv->base = ioremap(addr, size); 201 raw_spin_lock_init(&priv->htvec_lock); 202 203 /* Setup IRQ domain */ 204 priv->htvec_domain = irq_domain_create_linear(domain_handle, 205 (VEC_COUNT_PER_REG * priv->num_parents), 206 &htvec_domain_ops, priv); 207 if (!priv->htvec_domain) { 208 pr_err("loongson-htvec: cannot add IRQ domain\n"); 209 goto iounmap_base; 210 } 211 212 htvec_reset(priv); 213 214 for (i = 0; i < priv->num_parents; i++) { 215 irq_set_chained_handler_and_data(parent_irq[i], 216 htvec_irq_dispatch, priv); 217 } 218 219 htvec_priv = priv; 220 221 register_syscore(&htvec_syscore); 222 223 return 0; 224 225 iounmap_base: 226 iounmap(priv->base); 227 kfree(priv); 228 229 return -EINVAL; 230 } 231 232 #ifdef CONFIG_OF 233 234 static int htvec_of_init(struct device_node *node, 235 struct device_node *parent) 236 { 237 int i, err; 238 int parent_irq[8]; 239 int num_parents = 0; 240 struct resource res; 241 242 if (of_address_to_resource(node, 0, &res)) 243 return -EINVAL; 244 245 /* Interrupt may come from any of the 8 interrupt lines */ 246 for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) { 247 parent_irq[i] = irq_of_parse_and_map(node, i); 248 if (parent_irq[i] <= 0) 249 break; 250 251 num_parents++; 252 } 253 254 err = htvec_init(res.start, resource_size(&res), 255 num_parents, parent_irq, of_fwnode_handle(node)); 256 if (err < 0) 257 return err; 258 259 return 0; 260 } 261 262 IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init); 263 264 #endif 265 266 #ifdef CONFIG_ACPI 267 static int __init pch_pic_parse_madt(union acpi_subtable_headers *header, 268 const unsigned long end) 269 { 270 struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header; 271 272 return pch_pic_acpi_init(htvec_priv->htvec_domain, pchpic_entry); 273 } 274 275 static int __init pch_msi_parse_madt(union acpi_subtable_headers *header, 276 const unsigned long end) 277 { 278 struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header; 279 280 return pch_msi_acpi_init(htvec_priv->htvec_domain, pchmsi_entry); 281 } 282 283 static int __init acpi_cascade_irqdomain_init(void) 284 { 285 int r; 286 287 r = acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC, pch_pic_parse_madt, 0); 288 if (r < 0) 289 return r; 290 291 r = acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, 0); 292 if (r < 0) 293 return r; 294 295 return 0; 296 } 297 298 int __init htvec_acpi_init(struct irq_domain *parent, struct acpi_madt_ht_pic *acpi_htvec) 299 { 300 int i, ret, num_parents, parent_irq[8]; 301 struct fwnode_handle *domain_handle; 302 phys_addr_t addr; 303 304 if (!acpi_htvec) 305 return -EINVAL; 306 307 num_parents = HTVEC_MAX_PARENT_IRQ; 308 addr = (phys_addr_t)acpi_htvec->address; 309 310 domain_handle = irq_domain_alloc_fwnode(&addr); 311 if (!domain_handle) { 312 pr_err("Unable to allocate domain handle\n"); 313 return -ENOMEM; 314 } 315 316 /* Interrupt may come from any of the 8 interrupt lines */ 317 for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) 318 parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]); 319 320 ret = htvec_init(addr, acpi_htvec->size, num_parents, parent_irq, domain_handle); 321 if (ret == 0) 322 ret = acpi_cascade_irqdomain_init(); 323 else 324 irq_domain_free_fwnode(domain_handle); 325 326 return ret; 327 } 328 329 #endif 330