1 // SPDX-License-Identifier: GPL-2.0 2 /* Ethernet device driver for Cortina Systems Gemini SoC 3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus 4 * Net Engine and Gigabit Ethernet MAC (GMAC) 5 * This hardware contains a TCP Offload Engine (TOE) but currently the 6 * driver does not make use of it. 7 * 8 * Authors: 9 * Linus Walleij <linus.walleij@linaro.org> 10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT) 11 * Michał Mirosław <mirq-linux@rere.qmqm.pl> 12 * Paulius Zaleckas <paulius.zaleckas@gmail.com> 13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it> 14 * Gary Chen & Ch Hsu Storlink Semiconductor 15 */ 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/cache.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 #include <linux/clk.h> 27 #include <linux/of.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/of_platform.h> 31 #include <linux/etherdevice.h> 32 #include <linux/if_vlan.h> 33 #include <linux/skbuff.h> 34 #include <linux/phy.h> 35 #include <linux/crc32.h> 36 #include <linux/ethtool.h> 37 #include <linux/tcp.h> 38 #include <linux/u64_stats_sync.h> 39 40 #include <linux/in.h> 41 #include <linux/ip.h> 42 #include <linux/ipv6.h> 43 #include <net/gro.h> 44 45 #include "gemini.h" 46 47 #define DRV_NAME "gmac-gemini" 48 49 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 50 static int debug = -1; 51 module_param(debug, int, 0); 52 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 53 54 #define HSIZE_8 0x00 55 #define HSIZE_16 0x01 56 #define HSIZE_32 0x02 57 58 #define HBURST_SINGLE 0x00 59 #define HBURST_INCR 0x01 60 #define HBURST_INCR4 0x02 61 #define HBURST_INCR8 0x03 62 63 #define HPROT_DATA_CACHE BIT(0) 64 #define HPROT_PRIVILIGED BIT(1) 65 #define HPROT_BUFFERABLE BIT(2) 66 #define HPROT_CACHABLE BIT(3) 67 68 #define DEFAULT_RX_COALESCE_NSECS 0 69 #define DEFAULT_GMAC_RXQ_ORDER 9 70 #define DEFAULT_GMAC_TXQ_ORDER 8 71 #define DEFAULT_RX_BUF_ORDER 11 72 #define TX_MAX_FRAGS 16 73 #define TX_QUEUE_NUM 1 /* max: 6 */ 74 #define RX_MAX_ALLOC_ORDER 2 75 76 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \ 77 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT) 78 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \ 79 GMAC0_SWTQ00_FIN_INT_BIT) 80 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT) 81 82 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \ 83 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \ 84 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) 85 86 /** 87 * struct gmac_queue_page - page buffer per-page info 88 * @page: the page struct 89 * @mapping: the dma address handle 90 */ 91 struct gmac_queue_page { 92 struct page *page; 93 dma_addr_t mapping; 94 }; 95 96 struct gmac_txq { 97 struct gmac_txdesc *ring; 98 struct sk_buff **skb; 99 unsigned int cptr; 100 unsigned int noirq_packets; 101 }; 102 103 struct gemini_ethernet; 104 105 struct gemini_ethernet_port { 106 u8 id; /* 0 or 1 */ 107 108 struct gemini_ethernet *geth; 109 struct net_device *netdev; 110 struct device *dev; 111 void __iomem *dma_base; 112 void __iomem *gmac_base; 113 struct clk *pclk; 114 struct reset_control *reset; 115 int irq; 116 __le32 mac_addr[3]; 117 118 void __iomem *rxq_rwptr; 119 struct gmac_rxdesc *rxq_ring; 120 unsigned int rxq_order; 121 122 struct napi_struct napi; 123 struct hrtimer rx_coalesce_timer; 124 unsigned int rx_coalesce_nsecs; 125 struct sk_buff *rx_skb; 126 unsigned int rx_frag_nr; 127 bool rx_dropping; 128 129 unsigned int freeq_refill; 130 struct gmac_txq txq[TX_QUEUE_NUM]; 131 unsigned int txq_order; 132 unsigned int irq_every_tx_packets; 133 134 dma_addr_t rxq_dma_base; 135 dma_addr_t txq_dma_base; 136 137 unsigned int msg_enable; 138 spinlock_t config_lock; /* Locks config register */ 139 140 struct u64_stats_sync tx_stats_syncp; 141 struct u64_stats_sync rx_stats_syncp; 142 struct u64_stats_sync ir_stats_syncp; 143 144 struct rtnl_link_stats64 stats; 145 u64 hw_stats[RX_STATS_NUM]; 146 u64 rx_stats[RX_STATUS_NUM]; 147 u64 rx_csum_stats[RX_CHKSUM_NUM]; 148 u64 rx_napi_exits; 149 u64 tx_frag_stats[TX_MAX_FRAGS]; 150 u64 tx_frags_linearized; 151 u64 tx_hw_csummed; 152 }; 153 154 struct gemini_ethernet { 155 struct device *dev; 156 void __iomem *base; 157 struct gemini_ethernet_port *port0; 158 struct gemini_ethernet_port *port1; 159 bool initialized; 160 161 spinlock_t irq_lock; /* Locks IRQ-related registers */ 162 unsigned int freeq_order; 163 unsigned int freeq_frag_order; 164 struct gmac_rxdesc *freeq_ring; 165 dma_addr_t freeq_dma_base; 166 struct gmac_queue_page *freeq_pages; 167 unsigned int num_freeq_pages; 168 spinlock_t freeq_lock; /* Locks queue from reentrance */ 169 }; 170 171 #define GMAC_STATS_NUM ( \ 172 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \ 173 TX_MAX_FRAGS + 2) 174 175 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = { 176 "GMAC_IN_DISCARDS", 177 "GMAC_IN_ERRORS", 178 "GMAC_IN_MCAST", 179 "GMAC_IN_BCAST", 180 "GMAC_IN_MAC1", 181 "GMAC_IN_MAC2", 182 "RX_STATUS_GOOD_FRAME", 183 "RX_STATUS_TOO_LONG_GOOD_CRC", 184 "RX_STATUS_RUNT_FRAME", 185 "RX_STATUS_SFD_NOT_FOUND", 186 "RX_STATUS_CRC_ERROR", 187 "RX_STATUS_TOO_LONG_BAD_CRC", 188 "RX_STATUS_ALIGNMENT_ERROR", 189 "RX_STATUS_TOO_LONG_BAD_ALIGN", 190 "RX_STATUS_RX_ERR", 191 "RX_STATUS_DA_FILTERED", 192 "RX_STATUS_BUFFER_FULL", 193 "RX_STATUS_11", 194 "RX_STATUS_12", 195 "RX_STATUS_13", 196 "RX_STATUS_14", 197 "RX_STATUS_15", 198 "RX_CHKSUM_IP_UDP_TCP_OK", 199 "RX_CHKSUM_IP_OK_ONLY", 200 "RX_CHKSUM_NONE", 201 "RX_CHKSUM_3", 202 "RX_CHKSUM_IP_ERR_UNKNOWN", 203 "RX_CHKSUM_IP_ERR", 204 "RX_CHKSUM_TCP_UDP_ERR", 205 "RX_CHKSUM_7", 206 "RX_NAPI_EXITS", 207 "TX_FRAGS[1]", 208 "TX_FRAGS[2]", 209 "TX_FRAGS[3]", 210 "TX_FRAGS[4]", 211 "TX_FRAGS[5]", 212 "TX_FRAGS[6]", 213 "TX_FRAGS[7]", 214 "TX_FRAGS[8]", 215 "TX_FRAGS[9]", 216 "TX_FRAGS[10]", 217 "TX_FRAGS[11]", 218 "TX_FRAGS[12]", 219 "TX_FRAGS[13]", 220 "TX_FRAGS[14]", 221 "TX_FRAGS[15]", 222 "TX_FRAGS[16+]", 223 "TX_FRAGS_LINEARIZED", 224 "TX_HW_CSUMMED", 225 }; 226 227 static void gmac_dump_dma_state(struct net_device *netdev); 228 229 static void gmac_update_config0_reg(struct net_device *netdev, 230 u32 val, u32 vmask) 231 { 232 struct gemini_ethernet_port *port = netdev_priv(netdev); 233 unsigned long flags; 234 u32 reg; 235 236 spin_lock_irqsave(&port->config_lock, flags); 237 238 reg = readl(port->gmac_base + GMAC_CONFIG0); 239 reg = (reg & ~vmask) | val; 240 writel(reg, port->gmac_base + GMAC_CONFIG0); 241 242 spin_unlock_irqrestore(&port->config_lock, flags); 243 } 244 245 static void gmac_enable_tx_rx(struct net_device *netdev) 246 { 247 struct gemini_ethernet_port *port = netdev_priv(netdev); 248 unsigned long flags; 249 u32 reg; 250 251 spin_lock_irqsave(&port->config_lock, flags); 252 253 reg = readl(port->gmac_base + GMAC_CONFIG0); 254 reg &= ~CONFIG0_TX_RX_DISABLE; 255 writel(reg, port->gmac_base + GMAC_CONFIG0); 256 257 spin_unlock_irqrestore(&port->config_lock, flags); 258 } 259 260 static void gmac_disable_tx_rx(struct net_device *netdev) 261 { 262 struct gemini_ethernet_port *port = netdev_priv(netdev); 263 unsigned long flags; 264 u32 val; 265 266 spin_lock_irqsave(&port->config_lock, flags); 267 268 val = readl(port->gmac_base + GMAC_CONFIG0); 269 val |= CONFIG0_TX_RX_DISABLE; 270 writel(val, port->gmac_base + GMAC_CONFIG0); 271 272 spin_unlock_irqrestore(&port->config_lock, flags); 273 274 mdelay(10); /* let GMAC consume packet */ 275 } 276 277 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx) 278 { 279 struct gemini_ethernet_port *port = netdev_priv(netdev); 280 unsigned long flags; 281 u32 val; 282 283 spin_lock_irqsave(&port->config_lock, flags); 284 285 val = readl(port->gmac_base + GMAC_CONFIG0); 286 val &= ~CONFIG0_FLOW_CTL; 287 if (tx) 288 val |= CONFIG0_FLOW_TX; 289 if (rx) 290 val |= CONFIG0_FLOW_RX; 291 writel(val, port->gmac_base + GMAC_CONFIG0); 292 293 spin_unlock_irqrestore(&port->config_lock, flags); 294 } 295 296 static void gmac_adjust_link(struct net_device *netdev) 297 { 298 struct gemini_ethernet_port *port = netdev_priv(netdev); 299 struct phy_device *phydev = netdev->phydev; 300 union gmac_status status, old_status; 301 bool pause_tx = false; 302 bool pause_rx = false; 303 304 status.bits32 = readl(port->gmac_base + GMAC_STATUS); 305 old_status.bits32 = status.bits32; 306 status.bits.link = phydev->link; 307 status.bits.duplex = phydev->duplex; 308 309 switch (phydev->speed) { 310 case 1000: 311 status.bits.speed = GMAC_SPEED_1000; 312 if (phy_interface_mode_is_rgmii(phydev->interface)) 313 status.bits.mii_rmii = GMAC_PHY_RGMII_1000; 314 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n", 315 phydev_name(phydev)); 316 break; 317 case 100: 318 status.bits.speed = GMAC_SPEED_100; 319 if (phy_interface_mode_is_rgmii(phydev->interface)) 320 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 321 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n", 322 phydev_name(phydev)); 323 break; 324 case 10: 325 status.bits.speed = GMAC_SPEED_10; 326 if (phy_interface_mode_is_rgmii(phydev->interface)) 327 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 328 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n", 329 phydev_name(phydev)); 330 break; 331 default: 332 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n", 333 phydev->speed, phydev_name(phydev)); 334 } 335 336 if (phydev->duplex == DUPLEX_FULL) { 337 phy_get_pause(phydev, &pause_tx, &pause_rx); 338 netdev_dbg(netdev, "set negotiated pause params pause TX = %s, pause RX = %s\n", 339 pause_tx ? "ON" : "OFF", pause_rx ? "ON" : "OFF"); 340 } 341 342 gmac_set_flow_control(netdev, pause_tx, pause_rx); 343 344 if (old_status.bits32 == status.bits32) 345 return; 346 347 if (netif_msg_link(port)) { 348 phy_print_status(phydev); 349 netdev_info(netdev, "link flow control: %s\n", 350 phydev->pause 351 ? (phydev->asym_pause ? "tx" : "both") 352 : (phydev->asym_pause ? "rx" : "none") 353 ); 354 } 355 356 gmac_disable_tx_rx(netdev); 357 writel(status.bits32, port->gmac_base + GMAC_STATUS); 358 gmac_enable_tx_rx(netdev); 359 } 360 361 static int gmac_setup_phy(struct net_device *netdev) 362 { 363 struct gemini_ethernet_port *port = netdev_priv(netdev); 364 union gmac_status status = { .bits32 = 0 }; 365 struct device *dev = port->dev; 366 struct phy_device *phy; 367 368 phy = of_phy_get_and_connect(netdev, 369 dev->of_node, 370 gmac_adjust_link); 371 if (!phy) 372 return -ENODEV; 373 netdev->phydev = phy; 374 375 phy_set_max_speed(phy, SPEED_1000); 376 phy_support_asym_pause(phy); 377 378 /* set PHY interface type */ 379 switch (phy->interface) { 380 case PHY_INTERFACE_MODE_MII: 381 netdev_dbg(netdev, 382 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n"); 383 status.bits.mii_rmii = GMAC_PHY_MII; 384 break; 385 case PHY_INTERFACE_MODE_GMII: 386 netdev_dbg(netdev, 387 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n"); 388 status.bits.mii_rmii = GMAC_PHY_GMII; 389 break; 390 case PHY_INTERFACE_MODE_RGMII: 391 case PHY_INTERFACE_MODE_RGMII_ID: 392 case PHY_INTERFACE_MODE_RGMII_TXID: 393 case PHY_INTERFACE_MODE_RGMII_RXID: 394 netdev_dbg(netdev, 395 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n"); 396 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 397 break; 398 default: 399 netdev_err(netdev, "Unsupported MII interface\n"); 400 phy_disconnect(phy); 401 netdev->phydev = NULL; 402 return -EINVAL; 403 } 404 writel(status.bits32, port->gmac_base + GMAC_STATUS); 405 406 if (netif_msg_link(port)) 407 phy_attached_info(phy); 408 409 return 0; 410 } 411 412 /* The maximum frame length is not logically enumerated in the 413 * hardware, so we do a table lookup to find the applicable max 414 * frame length. 415 */ 416 struct gmac_max_framelen { 417 unsigned int max_l3_len; 418 u8 val; 419 }; 420 421 static const struct gmac_max_framelen gmac_maxlens[] = { 422 { 423 .max_l3_len = 1518, 424 .val = CONFIG0_MAXLEN_1518, 425 }, 426 { 427 .max_l3_len = 1522, 428 .val = CONFIG0_MAXLEN_1522, 429 }, 430 { 431 .max_l3_len = 1536, 432 .val = CONFIG0_MAXLEN_1536, 433 }, 434 { 435 .max_l3_len = 1548, 436 .val = CONFIG0_MAXLEN_1548, 437 }, 438 { 439 .max_l3_len = 9212, 440 .val = CONFIG0_MAXLEN_9k, 441 }, 442 { 443 .max_l3_len = 10236, 444 .val = CONFIG0_MAXLEN_10k, 445 }, 446 }; 447 448 static int gmac_pick_rx_max_len(unsigned int max_l3_len) 449 { 450 const struct gmac_max_framelen *maxlen; 451 int maxtot; 452 int i; 453 454 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN; 455 456 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) { 457 maxlen = &gmac_maxlens[i]; 458 if (maxtot <= maxlen->max_l3_len) 459 return maxlen->val; 460 } 461 462 return -1; 463 } 464 465 static int gmac_init(struct net_device *netdev) 466 { 467 struct gemini_ethernet_port *port = netdev_priv(netdev); 468 union gmac_config0 config0 = { .bits = { 469 .dis_tx = 1, 470 .dis_rx = 1, 471 .ipv4_rx_chksum = 1, 472 .ipv6_rx_chksum = 1, 473 .rx_err_detect = 1, 474 .rgmm_edge = 1, 475 .port0_chk_hwq = 1, 476 .port1_chk_hwq = 1, 477 .port0_chk_toeq = 1, 478 .port1_chk_toeq = 1, 479 .port0_chk_classq = 1, 480 .port1_chk_classq = 1, 481 } }; 482 union gmac_ahb_weight ahb_weight = { .bits = { 483 .rx_weight = 1, 484 .tx_weight = 1, 485 .hash_weight = 1, 486 .pre_req = 0x1f, 487 .tq_dv_threshold = 0, 488 } }; 489 union gmac_tx_wcr0 hw_weigh = { .bits = { 490 .hw_tq3 = 1, 491 .hw_tq2 = 1, 492 .hw_tq1 = 1, 493 .hw_tq0 = 1, 494 } }; 495 union gmac_tx_wcr1 sw_weigh = { .bits = { 496 .sw_tq5 = 1, 497 .sw_tq4 = 1, 498 .sw_tq3 = 1, 499 .sw_tq2 = 1, 500 .sw_tq1 = 1, 501 .sw_tq0 = 1, 502 } }; 503 union gmac_config1 config1 = { .bits = { 504 .set_threshold = 16, 505 .rel_threshold = 24, 506 } }; 507 union gmac_config2 config2 = { .bits = { 508 .set_threshold = 16, 509 .rel_threshold = 32, 510 } }; 511 union gmac_config3 config3 = { .bits = { 512 .set_threshold = 0, 513 .rel_threshold = 0, 514 } }; 515 union gmac_config0 tmp; 516 517 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu); 518 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 519 config0.bits.reserved = tmp.bits.reserved; 520 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0); 521 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1); 522 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2); 523 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3); 524 525 readl(port->dma_base + GMAC_AHB_WEIGHT_REG); 526 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG); 527 528 writel(hw_weigh.bits32, 529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG); 530 writel(sw_weigh.bits32, 531 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG); 532 533 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER; 534 port->txq_order = DEFAULT_GMAC_TXQ_ORDER; 535 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS; 536 537 /* Mark every quarter of the queue a packet for interrupt 538 * in order to be able to wake up the queue if it was stopped 539 */ 540 port->irq_every_tx_packets = 1 << (port->txq_order - 2); 541 542 return 0; 543 } 544 545 static int gmac_setup_txqs(struct net_device *netdev) 546 { 547 struct gemini_ethernet_port *port = netdev_priv(netdev); 548 unsigned int n_txq = netdev->num_tx_queues; 549 struct gemini_ethernet *geth = port->geth; 550 size_t entries = 1 << port->txq_order; 551 struct gmac_txq *txq = port->txq; 552 struct gmac_txdesc *desc_ring; 553 size_t len = n_txq * entries; 554 struct sk_buff **skb_tab; 555 void __iomem *rwptr_reg; 556 unsigned int r; 557 int i; 558 559 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 560 561 skb_tab = kzalloc_objs(*skb_tab, len); 562 if (!skb_tab) 563 return -ENOMEM; 564 565 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring), 566 &port->txq_dma_base, GFP_KERNEL); 567 568 if (!desc_ring) { 569 kfree(skb_tab); 570 return -ENOMEM; 571 } 572 573 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) { 574 dev_warn(geth->dev, "TX queue base is not aligned\n"); 575 dma_free_coherent(geth->dev, len * sizeof(*desc_ring), 576 desc_ring, port->txq_dma_base); 577 kfree(skb_tab); 578 return -ENOMEM; 579 } 580 581 writel(port->txq_dma_base | port->txq_order, 582 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); 583 584 for (i = 0; i < n_txq; i++) { 585 txq->ring = desc_ring; 586 txq->skb = skb_tab; 587 txq->noirq_packets = 0; 588 589 r = readw(rwptr_reg); 590 rwptr_reg += 2; 591 writew(r, rwptr_reg); 592 rwptr_reg += 2; 593 txq->cptr = r; 594 595 txq++; 596 desc_ring += entries; 597 skb_tab += entries; 598 } 599 600 return 0; 601 } 602 603 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq, 604 unsigned int r) 605 { 606 struct gemini_ethernet_port *port = netdev_priv(netdev); 607 unsigned int m = (1 << port->txq_order) - 1; 608 struct gemini_ethernet *geth = port->geth; 609 unsigned int c = txq->cptr; 610 union gmac_txdesc_0 word0; 611 union gmac_txdesc_1 word1; 612 unsigned int hwchksum = 0; 613 unsigned long bytes = 0; 614 struct gmac_txdesc *txd; 615 unsigned short nfrags; 616 unsigned int errs = 0; 617 unsigned int pkts = 0; 618 unsigned int word3; 619 dma_addr_t mapping; 620 621 if (c == r) 622 return; 623 624 while (c != r) { 625 txd = txq->ring + c; 626 word0 = txd->word0; 627 word1 = txd->word1; 628 mapping = txd->word2.buf_adr; 629 word3 = txd->word3.bits32; 630 631 dma_unmap_single(geth->dev, mapping, 632 word0.bits.buffer_size, DMA_TO_DEVICE); 633 634 if (word3 & EOF_BIT) 635 dev_kfree_skb(txq->skb[c]); 636 637 c++; 638 c &= m; 639 640 if (!(word3 & SOF_BIT)) 641 continue; 642 643 if (!word0.bits.status_tx_ok) { 644 errs++; 645 continue; 646 } 647 648 pkts++; 649 bytes += txd->word1.bits.byte_count; 650 651 if (word1.bits32 & TSS_CHECKUM_ENABLE) 652 hwchksum++; 653 654 nfrags = word0.bits.desc_count - 1; 655 if (nfrags) { 656 if (nfrags >= TX_MAX_FRAGS) 657 nfrags = TX_MAX_FRAGS - 1; 658 659 u64_stats_update_begin(&port->tx_stats_syncp); 660 port->tx_frag_stats[nfrags]++; 661 u64_stats_update_end(&port->tx_stats_syncp); 662 } 663 } 664 665 u64_stats_update_begin(&port->ir_stats_syncp); 666 port->stats.tx_errors += errs; 667 port->stats.tx_packets += pkts; 668 port->stats.tx_bytes += bytes; 669 port->tx_hw_csummed += hwchksum; 670 u64_stats_update_end(&port->ir_stats_syncp); 671 672 txq->cptr = c; 673 } 674 675 static void gmac_cleanup_txqs(struct net_device *netdev) 676 { 677 struct gemini_ethernet_port *port = netdev_priv(netdev); 678 unsigned int n_txq = netdev->num_tx_queues; 679 struct gemini_ethernet *geth = port->geth; 680 void __iomem *rwptr_reg; 681 unsigned int r, i; 682 683 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 684 685 for (i = 0; i < n_txq; i++) { 686 r = readw(rwptr_reg); 687 rwptr_reg += 2; 688 writew(r, rwptr_reg); 689 rwptr_reg += 2; 690 691 gmac_clean_txq(netdev, port->txq + i, r); 692 } 693 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); 694 695 kfree(port->txq->skb); 696 dma_free_coherent(geth->dev, 697 n_txq * sizeof(*port->txq->ring) << port->txq_order, 698 port->txq->ring, port->txq_dma_base); 699 } 700 701 static int gmac_setup_rxq(struct net_device *netdev) 702 { 703 struct gemini_ethernet_port *port = netdev_priv(netdev); 704 struct gemini_ethernet *geth = port->geth; 705 struct nontoe_qhdr __iomem *qhdr; 706 707 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); 708 port->rxq_rwptr = &qhdr->word1; 709 710 /* Remap a slew of memory to use for the RX queue */ 711 port->rxq_ring = dma_alloc_coherent(geth->dev, 712 sizeof(*port->rxq_ring) << port->rxq_order, 713 &port->rxq_dma_base, GFP_KERNEL); 714 if (!port->rxq_ring) 715 return -ENOMEM; 716 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) { 717 dev_warn(geth->dev, "RX queue base is not aligned\n"); 718 return -ENOMEM; 719 } 720 721 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0); 722 writel(0, port->rxq_rwptr); 723 return 0; 724 } 725 726 static struct gmac_queue_page * 727 gmac_get_queue_page(struct gemini_ethernet *geth, 728 struct gemini_ethernet_port *port, 729 dma_addr_t addr) 730 { 731 struct gmac_queue_page *gpage; 732 dma_addr_t mapping; 733 int i; 734 735 /* Only look for even pages */ 736 mapping = addr & PAGE_MASK; 737 738 if (!geth->freeq_pages) { 739 dev_err(geth->dev, "try to get page with no page list\n"); 740 return NULL; 741 } 742 743 /* Look up a ring buffer page from virtual mapping */ 744 for (i = 0; i < geth->num_freeq_pages; i++) { 745 gpage = &geth->freeq_pages[i]; 746 if (gpage->mapping == mapping) 747 return gpage; 748 } 749 750 return NULL; 751 } 752 753 static void gmac_cleanup_rxq(struct net_device *netdev) 754 { 755 struct gemini_ethernet_port *port = netdev_priv(netdev); 756 struct gemini_ethernet *geth = port->geth; 757 struct gmac_rxdesc *rxd = port->rxq_ring; 758 static struct gmac_queue_page *gpage; 759 struct nontoe_qhdr __iomem *qhdr; 760 void __iomem *dma_reg; 761 void __iomem *ptr_reg; 762 dma_addr_t mapping; 763 union dma_rwptr rw; 764 unsigned int r, w; 765 766 qhdr = geth->base + 767 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); 768 dma_reg = &qhdr->word0; 769 ptr_reg = &qhdr->word1; 770 771 rw.bits32 = readl(ptr_reg); 772 r = rw.bits.rptr; 773 w = rw.bits.wptr; 774 writew(r, ptr_reg + 2); 775 776 writel(0, dma_reg); 777 778 /* Loop from read pointer to write pointer of the RX queue 779 * and free up all pages by the queue. 780 */ 781 while (r != w) { 782 mapping = rxd[r].word2.buf_adr; 783 r++; 784 r &= ((1 << port->rxq_order) - 1); 785 786 if (!mapping) 787 continue; 788 789 /* Freeq pointers are one page off */ 790 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); 791 if (!gpage) { 792 dev_err(geth->dev, "could not find page\n"); 793 continue; 794 } 795 /* Release the RX queue reference to the page */ 796 put_page(gpage->page); 797 } 798 799 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order, 800 port->rxq_ring, port->rxq_dma_base); 801 } 802 803 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth, 804 int pn) 805 { 806 struct gmac_rxdesc *freeq_entry; 807 struct gmac_queue_page *gpage; 808 unsigned int fpp_order; 809 unsigned int frag_len; 810 dma_addr_t mapping; 811 struct page *page; 812 int i; 813 814 /* First allocate and DMA map a single page */ 815 page = alloc_page(GFP_ATOMIC); 816 if (!page) 817 return NULL; 818 819 mapping = dma_map_single(geth->dev, page_address(page), 820 PAGE_SIZE, DMA_FROM_DEVICE); 821 if (dma_mapping_error(geth->dev, mapping)) { 822 put_page(page); 823 return NULL; 824 } 825 826 /* The assign the page mapping (physical address) to the buffer address 827 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes, 828 * 4k), and the default RX frag order is 11 (fragments are up 20 2048 829 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus 830 * each page normally needs two entries in the queue. 831 */ 832 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */ 833 fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 834 freeq_entry = geth->freeq_ring + (pn << fpp_order); 835 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n", 836 pn, frag_len, (1 << fpp_order), freeq_entry); 837 for (i = (1 << fpp_order); i > 0; i--) { 838 freeq_entry->word2.buf_adr = mapping; 839 freeq_entry++; 840 mapping += frag_len; 841 } 842 843 /* If the freeq entry already has a page mapped, then unmap it. */ 844 gpage = &geth->freeq_pages[pn]; 845 if (gpage->page) { 846 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 847 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 848 /* This should be the last reference to the page so it gets 849 * released 850 */ 851 put_page(gpage->page); 852 } 853 854 /* Then put our new mapping into the page table */ 855 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n", 856 pn, (unsigned int)mapping, page); 857 gpage->mapping = mapping; 858 gpage->page = page; 859 860 return page; 861 } 862 863 /** 864 * geth_fill_freeq() - Fill the freeq with empty fragments to use 865 * @geth: the ethernet adapter 866 * @refill: whether to reset the queue by filling in all freeq entries or 867 * just refill it, usually the interrupt to refill the queue happens when 868 * the queue is half empty. 869 */ 870 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill) 871 { 872 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 873 unsigned int count = 0; 874 unsigned int pn, epn; 875 unsigned long flags; 876 union dma_rwptr rw; 877 unsigned int m_pn; 878 879 /* Mask for page */ 880 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1; 881 882 spin_lock_irqsave(&geth->freeq_lock, flags); 883 884 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); 885 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order; 886 epn = (rw.bits.rptr >> fpp_order) - 1; 887 epn &= m_pn; 888 889 /* Loop over the freeq ring buffer entries */ 890 while (pn != epn) { 891 struct gmac_queue_page *gpage; 892 struct page *page; 893 894 gpage = &geth->freeq_pages[pn]; 895 page = gpage->page; 896 897 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n", 898 pn, page_ref_count(page), 1 << fpp_order); 899 900 if (page_ref_count(page) > 1) { 901 unsigned int fl = (pn - epn) & m_pn; 902 903 if (fl > 64 >> fpp_order) 904 break; 905 906 page = geth_freeq_alloc_map_page(geth, pn); 907 if (!page) 908 break; 909 } 910 911 /* Add one reference per fragment in the page */ 912 page_ref_add(page, 1 << fpp_order); 913 count += 1 << fpp_order; 914 pn++; 915 pn &= m_pn; 916 } 917 918 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); 919 920 spin_unlock_irqrestore(&geth->freeq_lock, flags); 921 922 return count; 923 } 924 925 static int geth_setup_freeq(struct gemini_ethernet *geth) 926 { 927 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 928 unsigned int frag_len = 1 << geth->freeq_frag_order; 929 unsigned int len = 1 << geth->freeq_order; 930 unsigned int pages = len >> fpp_order; 931 union queue_threshold qt; 932 union dma_skb_size skbsz; 933 unsigned int filled; 934 unsigned int pn; 935 936 geth->freeq_ring = dma_alloc_coherent(geth->dev, 937 sizeof(*geth->freeq_ring) << geth->freeq_order, 938 &geth->freeq_dma_base, GFP_KERNEL); 939 if (!geth->freeq_ring) 940 return -ENOMEM; 941 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) { 942 dev_warn(geth->dev, "queue ring base is not aligned\n"); 943 goto err_freeq; 944 } 945 946 /* Allocate a mapping to page look-up index */ 947 geth->freeq_pages = kzalloc_objs(*geth->freeq_pages, pages); 948 if (!geth->freeq_pages) 949 goto err_freeq; 950 geth->num_freeq_pages = pages; 951 952 dev_info(geth->dev, "allocate %d pages for queue\n", pages); 953 for (pn = 0; pn < pages; pn++) 954 if (!geth_freeq_alloc_map_page(geth, pn)) 955 goto err_freeq_alloc; 956 957 filled = geth_fill_freeq(geth, false); 958 if (!filled) 959 goto err_freeq_alloc; 960 961 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); 962 qt.bits.swfq_empty = 32; 963 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG); 964 965 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order; 966 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG); 967 writel(geth->freeq_dma_base | geth->freeq_order, 968 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 969 970 return 0; 971 972 err_freeq_alloc: 973 while (pn > 0) { 974 struct gmac_queue_page *gpage; 975 dma_addr_t mapping; 976 977 --pn; 978 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 979 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 980 gpage = &geth->freeq_pages[pn]; 981 put_page(gpage->page); 982 } 983 984 kfree(geth->freeq_pages); 985 err_freeq: 986 dma_free_coherent(geth->dev, 987 sizeof(*geth->freeq_ring) << geth->freeq_order, 988 geth->freeq_ring, geth->freeq_dma_base); 989 geth->freeq_ring = NULL; 990 return -ENOMEM; 991 } 992 993 /** 994 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue 995 * @geth: the Gemini global ethernet state 996 */ 997 static void geth_cleanup_freeq(struct gemini_ethernet *geth) 998 { 999 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 1000 unsigned int frag_len = 1 << geth->freeq_frag_order; 1001 unsigned int len = 1 << geth->freeq_order; 1002 unsigned int pages = len >> fpp_order; 1003 unsigned int pn; 1004 1005 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG), 1006 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); 1007 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 1008 1009 for (pn = 0; pn < pages; pn++) { 1010 struct gmac_queue_page *gpage; 1011 dma_addr_t mapping; 1012 1013 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 1014 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 1015 1016 gpage = &geth->freeq_pages[pn]; 1017 while (page_ref_count(gpage->page) > 0) 1018 put_page(gpage->page); 1019 } 1020 1021 kfree(geth->freeq_pages); 1022 1023 dma_free_coherent(geth->dev, 1024 sizeof(*geth->freeq_ring) << geth->freeq_order, 1025 geth->freeq_ring, geth->freeq_dma_base); 1026 } 1027 1028 /** 1029 * geth_resize_freeq() - resize the software queue depth 1030 * @port: the port requesting the change 1031 * 1032 * This gets called at least once during probe() so the device queue gets 1033 * "resized" from the hardware defaults. Since both ports/net devices share 1034 * the same hardware queue, some synchronization between the ports is 1035 * needed. 1036 */ 1037 static int geth_resize_freeq(struct gemini_ethernet_port *port) 1038 { 1039 struct gemini_ethernet *geth = port->geth; 1040 struct net_device *netdev = port->netdev; 1041 struct gemini_ethernet_port *other_port; 1042 struct net_device *other_netdev; 1043 unsigned int new_size = 0; 1044 unsigned int new_order; 1045 unsigned long flags; 1046 u32 en; 1047 int ret; 1048 1049 if (netdev->dev_id == 0) 1050 other_netdev = geth->port1->netdev; 1051 else 1052 other_netdev = geth->port0->netdev; 1053 1054 if (other_netdev && netif_running(other_netdev)) 1055 return -EBUSY; 1056 1057 new_size = 1 << (port->rxq_order + 1); 1058 netdev_dbg(netdev, "port %d size: %d order %d\n", 1059 netdev->dev_id, 1060 new_size, 1061 port->rxq_order); 1062 if (other_netdev) { 1063 other_port = netdev_priv(other_netdev); 1064 new_size += 1 << (other_port->rxq_order + 1); 1065 netdev_dbg(other_netdev, "port %d size: %d order %d\n", 1066 other_netdev->dev_id, 1067 (1 << (other_port->rxq_order + 1)), 1068 other_port->rxq_order); 1069 } 1070 1071 new_order = min(15, ilog2(new_size - 1) + 1); 1072 dev_dbg(geth->dev, "set shared queue to size %d order %d\n", 1073 new_size, new_order); 1074 if (geth->freeq_order == new_order) 1075 return 0; 1076 1077 spin_lock_irqsave(&geth->irq_lock, flags); 1078 1079 /* Disable the software queue IRQs */ 1080 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1081 en &= ~SWFQ_EMPTY_INT_BIT; 1082 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1083 spin_unlock_irqrestore(&geth->irq_lock, flags); 1084 1085 /* Drop the old queue */ 1086 if (geth->freeq_ring) 1087 geth_cleanup_freeq(geth); 1088 1089 /* Allocate a new queue with the desired order */ 1090 geth->freeq_order = new_order; 1091 ret = geth_setup_freeq(geth); 1092 1093 /* Restart the interrupts - NOTE if this is the first resize 1094 * after probe(), this is where the interrupts get turned on 1095 * in the first place. 1096 */ 1097 spin_lock_irqsave(&geth->irq_lock, flags); 1098 en |= SWFQ_EMPTY_INT_BIT; 1099 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1100 spin_unlock_irqrestore(&geth->irq_lock, flags); 1101 1102 return ret; 1103 } 1104 1105 static void gmac_tx_irq_enable(struct net_device *netdev, 1106 unsigned int txq, int en) 1107 { 1108 struct gemini_ethernet_port *port = netdev_priv(netdev); 1109 struct gemini_ethernet *geth = port->geth; 1110 unsigned long flags; 1111 u32 val, mask; 1112 1113 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id); 1114 1115 spin_lock_irqsave(&geth->irq_lock, flags); 1116 1117 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq); 1118 1119 if (en) 1120 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 1121 1122 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1123 val = en ? val | mask : val & ~mask; 1124 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1125 1126 spin_unlock_irqrestore(&geth->irq_lock, flags); 1127 } 1128 1129 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num) 1130 { 1131 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num); 1132 1133 gmac_tx_irq_enable(netdev, txq_num, 0); 1134 netif_tx_wake_queue(ntxq); 1135 } 1136 1137 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, 1138 struct gmac_txq *txq, unsigned short *desc) 1139 { 1140 struct gemini_ethernet_port *port = netdev_priv(netdev); 1141 struct skb_shared_info *skb_si = skb_shinfo(skb); 1142 unsigned short m = (1 << port->txq_order) - 1; 1143 short frag, last_frag = skb_si->nr_frags - 1; 1144 struct gemini_ethernet *geth = port->geth; 1145 unsigned int word1, word3, buflen; 1146 unsigned short w = *desc; 1147 struct gmac_txdesc *txd; 1148 skb_frag_t *skb_frag; 1149 dma_addr_t mapping; 1150 bool tcp = false; 1151 void *buffer; 1152 u16 mss; 1153 int ret; 1154 1155 word1 = skb->len; 1156 word3 = SOF_BIT; 1157 1158 /* Determine if we are doing TCP */ 1159 if (skb->protocol == htons(ETH_P_IP)) 1160 tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP); 1161 else 1162 /* IPv6 */ 1163 tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP); 1164 1165 mss = skb_shinfo(skb)->gso_size; 1166 if (mss) { 1167 /* This means we are dealing with TCP and skb->len is the 1168 * sum total of all the segments. The TSO will deal with 1169 * chopping this up for us. 1170 */ 1171 /* The accelerator needs the full frame size here */ 1172 mss += skb_tcp_all_headers(skb); 1173 netdev_dbg(netdev, "segment offloading mss = %04x len=%04x\n", 1174 mss, skb->len); 1175 word1 |= TSS_MTU_ENABLE_BIT; 1176 word3 |= mss; 1177 } else if (tcp) { 1178 /* Even if we are not using TSO, use the hardware offloader 1179 * for transferring the TCP frame: this hardware has partial 1180 * TCP awareness (called TOE - TCP Offload Engine) and will 1181 * according to the datasheet put packets belonging to the 1182 * same TCP connection in the same queue for the TOE/TSO 1183 * engine to process. The engine will deal with chopping 1184 * up frames that exceed ETH_DATA_LEN which the 1185 * checksumming engine cannot handle (see below) into 1186 * manageable chunks. It flawlessly deals with quite big 1187 * frames and frames containing custom DSA EtherTypes. 1188 */ 1189 mss = netdev->mtu + skb_tcp_all_headers(skb); 1190 mss = min(mss, skb->len); 1191 netdev_dbg(netdev, "TOE/TSO len %04x mtu %04x mss %04x\n", 1192 skb->len, netdev->mtu, mss); 1193 word1 |= TSS_MTU_ENABLE_BIT; 1194 word3 |= mss; 1195 } else if (skb->len >= ETH_FRAME_LEN) { 1196 /* Hardware offloaded checksumming isn't working on non-TCP frames 1197 * bigger than 1514 bytes. A hypothesis about this is that the 1198 * checksum buffer is only 1518 bytes, so when the frames get 1199 * bigger they get truncated, or the last few bytes get 1200 * overwritten by the FCS. 1201 * 1202 * Just use software checksumming and bypass on bigger frames. 1203 */ 1204 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1205 ret = skb_checksum_help(skb); 1206 if (ret) 1207 return ret; 1208 } 1209 word1 |= TSS_BYPASS_BIT; 1210 } 1211 1212 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1213 /* We do not switch off the checksumming on non TCP/UDP 1214 * frames: as is shown from tests, the checksumming engine 1215 * is smart enough to see that a frame is not actually TCP 1216 * or UDP and then just pass it through without any changes 1217 * to the frame. 1218 */ 1219 if (skb->protocol == htons(ETH_P_IP)) 1220 word1 |= TSS_IP_CHKSUM_BIT; 1221 else 1222 word1 |= TSS_IPV6_ENABLE_BIT; 1223 1224 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; 1225 } 1226 1227 frag = -1; 1228 while (frag <= last_frag) { 1229 if (frag == -1) { 1230 buffer = skb->data; 1231 buflen = skb_headlen(skb); 1232 } else { 1233 skb_frag = skb_si->frags + frag; 1234 buffer = skb_frag_address(skb_frag); 1235 buflen = skb_frag_size(skb_frag); 1236 } 1237 1238 if (frag == last_frag) { 1239 word3 |= EOF_BIT; 1240 txq->skb[w] = skb; 1241 } 1242 1243 mapping = dma_map_single(geth->dev, buffer, buflen, 1244 DMA_TO_DEVICE); 1245 if (dma_mapping_error(geth->dev, mapping)) 1246 goto map_error; 1247 1248 txd = txq->ring + w; 1249 txd->word0.bits32 = buflen; 1250 txd->word1.bits32 = word1; 1251 txd->word2.buf_adr = mapping; 1252 txd->word3.bits32 = word3; 1253 1254 word3 &= MTU_SIZE_BIT_MASK; 1255 w++; 1256 w &= m; 1257 frag++; 1258 } 1259 1260 *desc = w; 1261 return 0; 1262 1263 map_error: 1264 while (w != *desc) { 1265 w--; 1266 w &= m; 1267 1268 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr, 1269 txq->ring[w].word0.bits.buffer_size, 1270 DMA_TO_DEVICE); 1271 } 1272 return -ENOMEM; 1273 } 1274 1275 static netdev_tx_t gmac_start_xmit(struct sk_buff *skb, 1276 struct net_device *netdev) 1277 { 1278 struct gemini_ethernet_port *port = netdev_priv(netdev); 1279 unsigned short m = (1 << port->txq_order) - 1; 1280 struct netdev_queue *ntxq; 1281 unsigned short r, w, d; 1282 void __iomem *ptr_reg; 1283 struct gmac_txq *txq; 1284 int txq_num, nfrags; 1285 union dma_rwptr rw; 1286 1287 if (skb->len >= 0x10000) 1288 goto out_drop_free; 1289 1290 txq_num = skb_get_queue_mapping(skb); 1291 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); 1292 txq = &port->txq[txq_num]; 1293 ntxq = netdev_get_tx_queue(netdev, txq_num); 1294 nfrags = skb_shinfo(skb)->nr_frags; 1295 1296 rw.bits32 = readl(ptr_reg); 1297 r = rw.bits.rptr; 1298 w = rw.bits.wptr; 1299 1300 d = txq->cptr - w - 1; 1301 d &= m; 1302 1303 if (d < nfrags + 2) { 1304 gmac_clean_txq(netdev, txq, r); 1305 d = txq->cptr - w - 1; 1306 d &= m; 1307 1308 if (d < nfrags + 2) { 1309 netif_tx_stop_queue(ntxq); 1310 1311 d = txq->cptr + nfrags + 16; 1312 d &= m; 1313 txq->ring[d].word3.bits.eofie = 1; 1314 gmac_tx_irq_enable(netdev, txq_num, 1); 1315 1316 u64_stats_update_begin(&port->tx_stats_syncp); 1317 netdev->stats.tx_fifo_errors++; 1318 u64_stats_update_end(&port->tx_stats_syncp); 1319 return NETDEV_TX_BUSY; 1320 } 1321 } 1322 1323 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) { 1324 if (skb_linearize(skb)) 1325 goto out_drop; 1326 1327 u64_stats_update_begin(&port->tx_stats_syncp); 1328 port->tx_frags_linearized++; 1329 u64_stats_update_end(&port->tx_stats_syncp); 1330 1331 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) 1332 goto out_drop_free; 1333 } 1334 1335 writew(w, ptr_reg + 2); 1336 1337 gmac_clean_txq(netdev, txq, r); 1338 return NETDEV_TX_OK; 1339 1340 out_drop_free: 1341 dev_kfree_skb(skb); 1342 out_drop: 1343 u64_stats_update_begin(&port->tx_stats_syncp); 1344 port->stats.tx_dropped++; 1345 u64_stats_update_end(&port->tx_stats_syncp); 1346 return NETDEV_TX_OK; 1347 } 1348 1349 static void gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1350 { 1351 netdev_err(netdev, "Tx timeout\n"); 1352 gmac_dump_dma_state(netdev); 1353 } 1354 1355 static void gmac_enable_irq(struct net_device *netdev, int enable) 1356 { 1357 struct gemini_ethernet_port *port = netdev_priv(netdev); 1358 struct gemini_ethernet *geth = port->geth; 1359 unsigned long flags; 1360 u32 val, mask; 1361 1362 netdev_dbg(netdev, "%s device %d %s\n", __func__, 1363 netdev->dev_id, enable ? "enable" : "disable"); 1364 spin_lock_irqsave(&geth->irq_lock, flags); 1365 1366 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2); 1367 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1368 val = enable ? (val | mask) : (val & ~mask); 1369 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1370 1371 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; 1372 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1373 val = enable ? (val | mask) : (val & ~mask); 1374 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1375 1376 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8); 1377 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1378 val = enable ? (val | mask) : (val & ~mask); 1379 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1380 1381 spin_unlock_irqrestore(&geth->irq_lock, flags); 1382 } 1383 1384 static void gmac_enable_rx_irq(struct net_device *netdev, int enable) 1385 { 1386 struct gemini_ethernet_port *port = netdev_priv(netdev); 1387 struct gemini_ethernet *geth = port->geth; 1388 unsigned long flags; 1389 u32 val, mask; 1390 1391 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id, 1392 enable ? "enable" : "disable"); 1393 spin_lock_irqsave(&geth->irq_lock, flags); 1394 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; 1395 1396 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1397 val = enable ? (val | mask) : (val & ~mask); 1398 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1399 1400 spin_unlock_irqrestore(&geth->irq_lock, flags); 1401 } 1402 1403 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port, 1404 union gmac_rxdesc_0 word0, 1405 unsigned int frame_len) 1406 { 1407 unsigned int rx_csum = word0.bits.chksum_status; 1408 unsigned int rx_status = word0.bits.status; 1409 struct sk_buff *skb = NULL; 1410 1411 port->rx_stats[rx_status]++; 1412 port->rx_csum_stats[rx_csum]++; 1413 1414 if (word0.bits.derr || word0.bits.perr || 1415 rx_status || frame_len < ETH_ZLEN || 1416 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) { 1417 port->stats.rx_errors++; 1418 1419 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status)) 1420 port->stats.rx_length_errors++; 1421 if (RX_ERROR_OVER(rx_status)) 1422 port->stats.rx_over_errors++; 1423 if (RX_ERROR_CRC(rx_status)) 1424 port->stats.rx_crc_errors++; 1425 if (RX_ERROR_FRAME(rx_status)) 1426 port->stats.rx_frame_errors++; 1427 return NULL; 1428 } 1429 1430 skb = napi_get_frags(&port->napi); 1431 if (!skb) 1432 goto update_exit; 1433 1434 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK) 1435 skb->ip_summed = CHECKSUM_UNNECESSARY; 1436 1437 update_exit: 1438 port->stats.rx_bytes += frame_len; 1439 port->stats.rx_packets++; 1440 return skb; 1441 } 1442 1443 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget, 1444 unsigned int *freeq_consumed) 1445 { 1446 struct gemini_ethernet_port *port = netdev_priv(netdev); 1447 unsigned short m = (1 << port->rxq_order) - 1; 1448 struct gemini_ethernet *geth = port->geth; 1449 void __iomem *ptr_reg = port->rxq_rwptr; 1450 unsigned int frag_nr = port->rx_frag_nr; 1451 struct sk_buff *skb = port->rx_skb; 1452 unsigned int consumed = 0; 1453 unsigned int frame_len, frag_len; 1454 struct gmac_rxdesc *rx = NULL; 1455 struct gmac_queue_page *gpage; 1456 unsigned int received = 0; 1457 bool dropping = port->rx_dropping; 1458 union gmac_rxdesc_0 word0; 1459 union gmac_rxdesc_1 word1; 1460 union gmac_rxdesc_3 word3; 1461 struct page *page = NULL; 1462 unsigned int page_offs; 1463 unsigned long flags; 1464 unsigned short r, w; 1465 union dma_rwptr rw; 1466 dma_addr_t mapping; 1467 1468 spin_lock_irqsave(&geth->irq_lock, flags); 1469 rw.bits32 = readl(ptr_reg); 1470 /* Reset interrupt as all packages until here are taken into account */ 1471 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id, 1472 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 1473 spin_unlock_irqrestore(&geth->irq_lock, flags); 1474 1475 r = rw.bits.rptr; 1476 w = rw.bits.wptr; 1477 1478 while (budget && w != r) { 1479 page = NULL; 1480 rx = port->rxq_ring + r; 1481 word0 = rx->word0; 1482 word1 = rx->word1; 1483 mapping = rx->word2.buf_adr; 1484 word3 = rx->word3; 1485 1486 r++; 1487 r &= m; 1488 consumed++; 1489 1490 frag_len = word0.bits.buffer_size; 1491 frame_len = word1.bits.byte_count; 1492 page_offs = mapping & ~PAGE_MASK; 1493 1494 if (word3.bits32 & SOF_BIT) { 1495 if (skb) { 1496 napi_free_frags(&port->napi); 1497 port->stats.rx_dropped++; 1498 skb = NULL; 1499 frag_nr = 0; 1500 } 1501 dropping = false; 1502 } 1503 1504 if (!mapping) { 1505 netdev_err(netdev, 1506 "rxq[%u]: HW BUG: zero DMA desc\n", r); 1507 goto err_drop; 1508 } 1509 1510 /* Freeq pointers are one page off */ 1511 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); 1512 if (!gpage) { 1513 dev_err(geth->dev, "could not find mapping\n"); 1514 goto err_drop; 1515 } 1516 page = gpage->page; 1517 1518 if (word3.bits32 & SOF_BIT) { 1519 skb = gmac_skb_if_good_frame(port, word0, frame_len); 1520 if (!skb) 1521 goto err_drop; 1522 1523 page_offs += NET_IP_ALIGN; 1524 frag_len -= NET_IP_ALIGN; 1525 frag_nr = 0; 1526 1527 } else if (!skb) { 1528 goto err_drop; 1529 } 1530 1531 if (word3.bits32 & EOF_BIT) 1532 frag_len = frame_len - skb->len; 1533 1534 /* append page frag to skb */ 1535 if (frag_nr == MAX_SKB_FRAGS) 1536 goto err_drop; 1537 1538 if (frag_len == 0) 1539 netdev_err(netdev, "Received fragment with len = 0\n"); 1540 1541 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len); 1542 skb->len += frag_len; 1543 skb->data_len += frag_len; 1544 skb->truesize += frag_len; 1545 frag_nr++; 1546 1547 if (word3.bits32 & EOF_BIT) { 1548 napi_gro_frags(&port->napi); 1549 skb = NULL; 1550 frag_nr = 0; 1551 } 1552 goto next_desc; 1553 1554 err_drop: 1555 if (skb) { 1556 napi_free_frags(&port->napi); 1557 skb = NULL; 1558 frag_nr = 0; 1559 } 1560 1561 if (page) 1562 put_page(page); 1563 1564 if (!dropping) { 1565 port->stats.rx_dropped++; 1566 dropping = true; 1567 } 1568 1569 next_desc: 1570 /* Final or single-descriptor fragment, advance things */ 1571 if (word3.bits32 & EOF_BIT) { 1572 budget--; 1573 received++; 1574 dropping = false; 1575 } 1576 } 1577 1578 port->rx_skb = skb; 1579 port->rx_frag_nr = frag_nr; 1580 port->rx_dropping = dropping; 1581 *freeq_consumed = consumed; 1582 writew(r, ptr_reg); 1583 return received; 1584 } 1585 1586 static int gmac_napi_poll(struct napi_struct *napi, int budget) 1587 { 1588 struct gemini_ethernet_port *port = netdev_priv(napi->dev); 1589 struct gemini_ethernet *geth = port->geth; 1590 unsigned int freeq_threshold; 1591 unsigned int freeq_consumed; 1592 unsigned int received; 1593 1594 freeq_threshold = 1 << (geth->freeq_order - 1); 1595 u64_stats_update_begin(&port->rx_stats_syncp); 1596 1597 received = gmac_rx(napi->dev, budget, &freeq_consumed); 1598 if (received < budget) 1599 ++port->rx_napi_exits; 1600 1601 u64_stats_update_end(&port->rx_stats_syncp); 1602 1603 port->freeq_refill += freeq_consumed; 1604 if (port->freeq_refill > freeq_threshold) { 1605 port->freeq_refill -= freeq_threshold; 1606 geth_fill_freeq(geth, true); 1607 } 1608 1609 if (received < budget && napi_complete_done(napi, received)) 1610 gmac_enable_rx_irq(napi->dev, 1); 1611 1612 return received; 1613 } 1614 1615 static void gmac_dump_dma_state(struct net_device *netdev) 1616 { 1617 struct gemini_ethernet_port *port = netdev_priv(netdev); 1618 struct gemini_ethernet *geth = port->geth; 1619 void __iomem *ptr_reg; 1620 u32 reg[5]; 1621 1622 /* Interrupt status */ 1623 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 1624 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 1625 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); 1626 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); 1627 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1628 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1629 reg[0], reg[1], reg[2], reg[3], reg[4]); 1630 1631 /* Interrupt enable */ 1632 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1633 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1634 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); 1635 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); 1636 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1637 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1638 reg[0], reg[1], reg[2], reg[3], reg[4]); 1639 1640 /* RX DMA status */ 1641 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG); 1642 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG); 1643 reg[2] = GET_RPTR(port->rxq_rwptr); 1644 reg[3] = GET_WPTR(port->rxq_rwptr); 1645 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", 1646 reg[0], reg[1], reg[2], reg[3]); 1647 1648 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG); 1649 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG); 1650 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG); 1651 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG); 1652 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", 1653 reg[0], reg[1], reg[2], reg[3]); 1654 1655 /* TX DMA status */ 1656 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 1657 1658 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG); 1659 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG); 1660 reg[2] = GET_RPTR(ptr_reg); 1661 reg[3] = GET_WPTR(ptr_reg); 1662 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", 1663 reg[0], reg[1], reg[2], reg[3]); 1664 1665 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG); 1666 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG); 1667 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG); 1668 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG); 1669 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", 1670 reg[0], reg[1], reg[2], reg[3]); 1671 1672 /* FREE queues status */ 1673 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG; 1674 1675 reg[0] = GET_RPTR(ptr_reg); 1676 reg[1] = GET_WPTR(ptr_reg); 1677 1678 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG; 1679 1680 reg[2] = GET_RPTR(ptr_reg); 1681 reg[3] = GET_WPTR(ptr_reg); 1682 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n", 1683 reg[0], reg[1], reg[2], reg[3]); 1684 } 1685 1686 static void gmac_update_hw_stats(struct net_device *netdev) 1687 { 1688 struct gemini_ethernet_port *port = netdev_priv(netdev); 1689 unsigned int rx_discards, rx_mcast, rx_bcast; 1690 struct gemini_ethernet *geth = port->geth; 1691 unsigned long flags; 1692 1693 spin_lock_irqsave(&geth->irq_lock, flags); 1694 u64_stats_update_begin(&port->ir_stats_syncp); 1695 1696 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS); 1697 port->hw_stats[0] += rx_discards; 1698 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS); 1699 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST); 1700 port->hw_stats[2] += rx_mcast; 1701 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST); 1702 port->hw_stats[3] += rx_bcast; 1703 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1); 1704 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2); 1705 1706 port->stats.rx_missed_errors += rx_discards; 1707 port->stats.multicast += rx_mcast; 1708 port->stats.multicast += rx_bcast; 1709 1710 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8), 1711 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1712 1713 u64_stats_update_end(&port->ir_stats_syncp); 1714 spin_unlock_irqrestore(&geth->irq_lock, flags); 1715 } 1716 1717 /** 1718 * gmac_get_intr_flags() - get interrupt status flags for a port from 1719 * @netdev: the net device for the port to get flags from 1720 * @i: the interrupt status register 0..4 1721 */ 1722 static u32 gmac_get_intr_flags(struct net_device *netdev, int i) 1723 { 1724 struct gemini_ethernet_port *port = netdev_priv(netdev); 1725 struct gemini_ethernet *geth = port->geth; 1726 void __iomem *irqif_reg, *irqen_reg; 1727 unsigned int offs, val; 1728 1729 /* Calculate the offset using the stride of the status registers */ 1730 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - 1731 GLOBAL_INTERRUPT_STATUS_0_REG); 1732 1733 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs; 1734 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; 1735 1736 val = readl(irqif_reg) & readl(irqen_reg); 1737 return val; 1738 } 1739 1740 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer) 1741 { 1742 struct gemini_ethernet_port *port = 1743 container_of(timer, struct gemini_ethernet_port, 1744 rx_coalesce_timer); 1745 1746 napi_schedule(&port->napi); 1747 return HRTIMER_NORESTART; 1748 } 1749 1750 static irqreturn_t gmac_irq(int irq, void *data) 1751 { 1752 struct gemini_ethernet_port *port; 1753 struct net_device *netdev = data; 1754 struct gemini_ethernet *geth; 1755 u32 val, orr = 0; 1756 1757 port = netdev_priv(netdev); 1758 geth = port->geth; 1759 1760 val = gmac_get_intr_flags(netdev, 0); 1761 orr |= val; 1762 1763 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) { 1764 /* Oh, crap */ 1765 netdev_err(netdev, "hw failure/sw bug\n"); 1766 gmac_dump_dma_state(netdev); 1767 1768 /* don't know how to recover, just reduce losses */ 1769 gmac_enable_irq(netdev, 0); 1770 return IRQ_HANDLED; 1771 } 1772 1773 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6))) 1774 gmac_tx_irq(netdev, 0); 1775 1776 val = gmac_get_intr_flags(netdev, 1); 1777 orr |= val; 1778 1779 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) { 1780 gmac_enable_rx_irq(netdev, 0); 1781 1782 if (!port->rx_coalesce_nsecs) { 1783 napi_schedule(&port->napi); 1784 } else { 1785 ktime_t ktime; 1786 1787 ktime = ktime_set(0, port->rx_coalesce_nsecs); 1788 hrtimer_start(&port->rx_coalesce_timer, ktime, 1789 HRTIMER_MODE_REL); 1790 } 1791 } 1792 1793 val = gmac_get_intr_flags(netdev, 4); 1794 orr |= val; 1795 1796 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8))) 1797 gmac_update_hw_stats(netdev); 1798 1799 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) { 1800 spin_lock(&geth->irq_lock); 1801 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8), 1802 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1803 u64_stats_update_begin(&port->ir_stats_syncp); 1804 ++port->stats.rx_fifo_errors; 1805 u64_stats_update_end(&port->ir_stats_syncp); 1806 spin_unlock(&geth->irq_lock); 1807 } 1808 1809 return orr ? IRQ_HANDLED : IRQ_NONE; 1810 } 1811 1812 static void gmac_start_dma(struct gemini_ethernet_port *port) 1813 { 1814 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; 1815 union gmac_dma_ctrl dma_ctrl; 1816 1817 dma_ctrl.bits32 = readl(dma_ctrl_reg); 1818 dma_ctrl.bits.rd_enable = 1; 1819 dma_ctrl.bits.td_enable = 1; 1820 dma_ctrl.bits.loopback = 0; 1821 dma_ctrl.bits.drop_small_ack = 0; 1822 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN; 1823 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED; 1824 dma_ctrl.bits.rd_burst_size = HBURST_INCR8; 1825 dma_ctrl.bits.rd_bus = HSIZE_8; 1826 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE; 1827 dma_ctrl.bits.td_burst_size = HBURST_INCR8; 1828 dma_ctrl.bits.td_bus = HSIZE_8; 1829 1830 writel(dma_ctrl.bits32, dma_ctrl_reg); 1831 } 1832 1833 static void gmac_stop_dma(struct gemini_ethernet_port *port) 1834 { 1835 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; 1836 union gmac_dma_ctrl dma_ctrl; 1837 1838 dma_ctrl.bits32 = readl(dma_ctrl_reg); 1839 dma_ctrl.bits.rd_enable = 0; 1840 dma_ctrl.bits.td_enable = 0; 1841 writel(dma_ctrl.bits32, dma_ctrl_reg); 1842 } 1843 1844 static int gmac_open(struct net_device *netdev) 1845 { 1846 struct gemini_ethernet_port *port = netdev_priv(netdev); 1847 int err; 1848 1849 err = request_irq(netdev->irq, gmac_irq, 1850 IRQF_SHARED, netdev->name, netdev); 1851 if (err) { 1852 netdev_err(netdev, "no IRQ\n"); 1853 return err; 1854 } 1855 1856 netif_carrier_off(netdev); 1857 phy_start(netdev->phydev); 1858 1859 err = geth_resize_freeq(port); 1860 /* It's fine if it's just busy, the other port has set up 1861 * the freeq in that case. 1862 */ 1863 if (err && (err != -EBUSY)) { 1864 netdev_err(netdev, "could not resize freeq\n"); 1865 goto err_stop_phy; 1866 } 1867 1868 err = gmac_setup_rxq(netdev); 1869 if (err) { 1870 netdev_err(netdev, "could not setup RXQ\n"); 1871 goto err_stop_phy; 1872 } 1873 1874 err = gmac_setup_txqs(netdev); 1875 if (err) { 1876 netdev_err(netdev, "could not setup TXQs\n"); 1877 gmac_cleanup_rxq(netdev); 1878 goto err_stop_phy; 1879 } 1880 1881 napi_enable(&port->napi); 1882 1883 gmac_start_dma(port); 1884 gmac_enable_irq(netdev, 1); 1885 gmac_enable_tx_rx(netdev); 1886 netif_tx_start_all_queues(netdev); 1887 1888 hrtimer_setup(&port->rx_coalesce_timer, &gmac_coalesce_delay_expired, CLOCK_MONOTONIC, 1889 HRTIMER_MODE_REL); 1890 1891 netdev_dbg(netdev, "opened\n"); 1892 1893 return 0; 1894 1895 err_stop_phy: 1896 phy_stop(netdev->phydev); 1897 free_irq(netdev->irq, netdev); 1898 return err; 1899 } 1900 1901 static int gmac_stop(struct net_device *netdev) 1902 { 1903 struct gemini_ethernet_port *port = netdev_priv(netdev); 1904 1905 hrtimer_cancel(&port->rx_coalesce_timer); 1906 netif_tx_stop_all_queues(netdev); 1907 gmac_disable_tx_rx(netdev); 1908 gmac_stop_dma(port); 1909 napi_disable(&port->napi); 1910 port->rx_skb = NULL; 1911 port->rx_frag_nr = 0; 1912 port->rx_dropping = false; 1913 1914 gmac_enable_irq(netdev, 0); 1915 gmac_cleanup_rxq(netdev); 1916 gmac_cleanup_txqs(netdev); 1917 1918 phy_stop(netdev->phydev); 1919 free_irq(netdev->irq, netdev); 1920 1921 gmac_update_hw_stats(netdev); 1922 return 0; 1923 } 1924 1925 static void gmac_set_rx_mode(struct net_device *netdev) 1926 { 1927 struct gemini_ethernet_port *port = netdev_priv(netdev); 1928 union gmac_rx_fltr filter = { .bits = { 1929 .broadcast = 1, 1930 .multicast = 1, 1931 .unicast = 1, 1932 } }; 1933 struct netdev_hw_addr *ha; 1934 unsigned int bit_nr; 1935 u32 mc_filter[2]; 1936 1937 mc_filter[1] = 0; 1938 mc_filter[0] = 0; 1939 1940 if (netdev->flags & IFF_PROMISC) { 1941 filter.bits.error = 1; 1942 filter.bits.promiscuous = 1; 1943 mc_filter[1] = ~0; 1944 mc_filter[0] = ~0; 1945 } else if (netdev->flags & IFF_ALLMULTI) { 1946 mc_filter[1] = ~0; 1947 mc_filter[0] = ~0; 1948 } else { 1949 netdev_for_each_mc_addr(ha, netdev) { 1950 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f; 1951 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f); 1952 } 1953 } 1954 1955 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0); 1956 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1); 1957 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR); 1958 } 1959 1960 static void gmac_write_mac_address(struct net_device *netdev) 1961 { 1962 struct gemini_ethernet_port *port = netdev_priv(netdev); 1963 __le32 addr[3]; 1964 1965 memset(addr, 0, sizeof(addr)); 1966 memcpy(addr, netdev->dev_addr, ETH_ALEN); 1967 1968 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0); 1969 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1); 1970 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2); 1971 } 1972 1973 static int gmac_set_mac_address(struct net_device *netdev, void *addr) 1974 { 1975 struct sockaddr *sa = addr; 1976 1977 eth_hw_addr_set(netdev, sa->sa_data); 1978 gmac_write_mac_address(netdev); 1979 1980 return 0; 1981 } 1982 1983 static void gmac_clear_hw_stats(struct net_device *netdev) 1984 { 1985 struct gemini_ethernet_port *port = netdev_priv(netdev); 1986 1987 readl(port->gmac_base + GMAC_IN_DISCARDS); 1988 readl(port->gmac_base + GMAC_IN_ERRORS); 1989 readl(port->gmac_base + GMAC_IN_MCAST); 1990 readl(port->gmac_base + GMAC_IN_BCAST); 1991 readl(port->gmac_base + GMAC_IN_MAC1); 1992 readl(port->gmac_base + GMAC_IN_MAC2); 1993 } 1994 1995 static void gmac_get_stats64(struct net_device *netdev, 1996 struct rtnl_link_stats64 *stats) 1997 { 1998 struct gemini_ethernet_port *port = netdev_priv(netdev); 1999 unsigned int start; 2000 2001 gmac_update_hw_stats(netdev); 2002 2003 /* Racing with RX NAPI */ 2004 do { 2005 start = u64_stats_fetch_begin(&port->rx_stats_syncp); 2006 2007 stats->rx_packets = port->stats.rx_packets; 2008 stats->rx_bytes = port->stats.rx_bytes; 2009 stats->rx_errors = port->stats.rx_errors; 2010 stats->rx_dropped = port->stats.rx_dropped; 2011 2012 stats->rx_length_errors = port->stats.rx_length_errors; 2013 stats->rx_over_errors = port->stats.rx_over_errors; 2014 stats->rx_crc_errors = port->stats.rx_crc_errors; 2015 stats->rx_frame_errors = port->stats.rx_frame_errors; 2016 2017 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); 2018 2019 /* Racing with MIB and TX completion interrupts */ 2020 do { 2021 start = u64_stats_fetch_begin(&port->ir_stats_syncp); 2022 2023 stats->tx_errors = port->stats.tx_errors; 2024 stats->tx_packets = port->stats.tx_packets; 2025 stats->tx_bytes = port->stats.tx_bytes; 2026 2027 stats->multicast = port->stats.multicast; 2028 stats->rx_missed_errors = port->stats.rx_missed_errors; 2029 stats->rx_fifo_errors = port->stats.rx_fifo_errors; 2030 2031 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); 2032 2033 /* Racing with hard_start_xmit */ 2034 do { 2035 start = u64_stats_fetch_begin(&port->tx_stats_syncp); 2036 2037 stats->tx_dropped = port->stats.tx_dropped; 2038 2039 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); 2040 2041 stats->rx_dropped += stats->rx_missed_errors; 2042 } 2043 2044 static int gmac_change_mtu(struct net_device *netdev, int new_mtu) 2045 { 2046 int max_len = gmac_pick_rx_max_len(new_mtu); 2047 2048 if (max_len < 0) 2049 return -EINVAL; 2050 2051 gmac_disable_tx_rx(netdev); 2052 2053 WRITE_ONCE(netdev->mtu, new_mtu); 2054 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT, 2055 CONFIG0_MAXLEN_MASK); 2056 2057 netdev_update_features(netdev); 2058 2059 gmac_enable_tx_rx(netdev); 2060 2061 return 0; 2062 } 2063 2064 static int gmac_set_features(struct net_device *netdev, 2065 netdev_features_t features) 2066 { 2067 struct gemini_ethernet_port *port = netdev_priv(netdev); 2068 int enable = features & NETIF_F_RXCSUM; 2069 unsigned long flags; 2070 u32 reg; 2071 2072 spin_lock_irqsave(&port->config_lock, flags); 2073 2074 reg = readl(port->gmac_base + GMAC_CONFIG0); 2075 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; 2076 writel(reg, port->gmac_base + GMAC_CONFIG0); 2077 2078 spin_unlock_irqrestore(&port->config_lock, flags); 2079 return 0; 2080 } 2081 2082 static int gmac_get_sset_count(struct net_device *netdev, int sset) 2083 { 2084 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0; 2085 } 2086 2087 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2088 { 2089 if (stringset != ETH_SS_STATS) 2090 return; 2091 2092 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings)); 2093 } 2094 2095 static void gmac_get_ethtool_stats(struct net_device *netdev, 2096 struct ethtool_stats *estats, u64 *values) 2097 { 2098 struct gemini_ethernet_port *port = netdev_priv(netdev); 2099 unsigned int start; 2100 u64 *p; 2101 int i; 2102 2103 gmac_update_hw_stats(netdev); 2104 2105 /* Racing with MIB interrupt */ 2106 do { 2107 p = values; 2108 start = u64_stats_fetch_begin(&port->ir_stats_syncp); 2109 2110 for (i = 0; i < RX_STATS_NUM; i++) 2111 *p++ = port->hw_stats[i]; 2112 2113 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); 2114 values = p; 2115 2116 /* Racing with RX NAPI */ 2117 do { 2118 p = values; 2119 start = u64_stats_fetch_begin(&port->rx_stats_syncp); 2120 2121 for (i = 0; i < RX_STATUS_NUM; i++) 2122 *p++ = port->rx_stats[i]; 2123 for (i = 0; i < RX_CHKSUM_NUM; i++) 2124 *p++ = port->rx_csum_stats[i]; 2125 *p++ = port->rx_napi_exits; 2126 2127 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); 2128 values = p; 2129 2130 /* Racing with TX start_xmit */ 2131 do { 2132 p = values; 2133 start = u64_stats_fetch_begin(&port->tx_stats_syncp); 2134 2135 for (i = 0; i < TX_MAX_FRAGS; i++) { 2136 *values++ = port->tx_frag_stats[i]; 2137 port->tx_frag_stats[i] = 0; 2138 } 2139 *values++ = port->tx_frags_linearized; 2140 *values++ = port->tx_hw_csummed; 2141 2142 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); 2143 } 2144 2145 static int gmac_get_ksettings(struct net_device *netdev, 2146 struct ethtool_link_ksettings *cmd) 2147 { 2148 if (!netdev->phydev) 2149 return -ENXIO; 2150 phy_ethtool_ksettings_get(netdev->phydev, cmd); 2151 2152 return 0; 2153 } 2154 2155 static int gmac_set_ksettings(struct net_device *netdev, 2156 const struct ethtool_link_ksettings *cmd) 2157 { 2158 if (!netdev->phydev) 2159 return -ENXIO; 2160 return phy_ethtool_ksettings_set(netdev->phydev, cmd); 2161 } 2162 2163 static int gmac_nway_reset(struct net_device *netdev) 2164 { 2165 if (!netdev->phydev) 2166 return -ENXIO; 2167 return phy_start_aneg(netdev->phydev); 2168 } 2169 2170 static void gmac_get_pauseparam(struct net_device *netdev, 2171 struct ethtool_pauseparam *pparam) 2172 { 2173 struct gemini_ethernet_port *port = netdev_priv(netdev); 2174 union gmac_config0 config0; 2175 2176 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 2177 2178 pparam->rx_pause = config0.bits.rx_fc_en; 2179 pparam->tx_pause = config0.bits.tx_fc_en; 2180 pparam->autoneg = true; 2181 } 2182 2183 static int gmac_set_pauseparam(struct net_device *netdev, 2184 struct ethtool_pauseparam *pparam) 2185 { 2186 struct phy_device *phydev = netdev->phydev; 2187 2188 if (!pparam->autoneg) 2189 return -EOPNOTSUPP; 2190 2191 phy_set_asym_pause(phydev, pparam->rx_pause, pparam->tx_pause); 2192 2193 return 0; 2194 } 2195 2196 static void gmac_get_ringparam(struct net_device *netdev, 2197 struct ethtool_ringparam *rp, 2198 struct kernel_ethtool_ringparam *kernel_rp, 2199 struct netlink_ext_ack *extack) 2200 { 2201 struct gemini_ethernet_port *port = netdev_priv(netdev); 2202 2203 readl(port->gmac_base + GMAC_CONFIG0); 2204 2205 rp->rx_max_pending = 1 << 15; 2206 rp->rx_mini_max_pending = 0; 2207 rp->rx_jumbo_max_pending = 0; 2208 rp->tx_max_pending = 1 << 15; 2209 2210 rp->rx_pending = 1 << port->rxq_order; 2211 rp->rx_mini_pending = 0; 2212 rp->rx_jumbo_pending = 0; 2213 rp->tx_pending = 1 << port->txq_order; 2214 } 2215 2216 static int gmac_set_ringparam(struct net_device *netdev, 2217 struct ethtool_ringparam *rp, 2218 struct kernel_ethtool_ringparam *kernel_rp, 2219 struct netlink_ext_ack *extack) 2220 { 2221 struct gemini_ethernet_port *port = netdev_priv(netdev); 2222 int err = 0; 2223 2224 if (netif_running(netdev)) 2225 return -EBUSY; 2226 2227 if (rp->rx_pending) { 2228 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1); 2229 err = geth_resize_freeq(port); 2230 } 2231 if (rp->tx_pending) { 2232 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1); 2233 port->irq_every_tx_packets = 1 << (port->txq_order - 2); 2234 } 2235 2236 return err; 2237 } 2238 2239 static int gmac_get_coalesce(struct net_device *netdev, 2240 struct ethtool_coalesce *ecmd, 2241 struct kernel_ethtool_coalesce *kernel_coal, 2242 struct netlink_ext_ack *extack) 2243 { 2244 struct gemini_ethernet_port *port = netdev_priv(netdev); 2245 2246 ecmd->rx_max_coalesced_frames = 1; 2247 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets; 2248 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000; 2249 2250 return 0; 2251 } 2252 2253 static int gmac_set_coalesce(struct net_device *netdev, 2254 struct ethtool_coalesce *ecmd, 2255 struct kernel_ethtool_coalesce *kernel_coal, 2256 struct netlink_ext_ack *extack) 2257 { 2258 struct gemini_ethernet_port *port = netdev_priv(netdev); 2259 2260 if (ecmd->tx_max_coalesced_frames < 1) 2261 return -EINVAL; 2262 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order) 2263 return -EINVAL; 2264 2265 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames; 2266 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000; 2267 2268 return 0; 2269 } 2270 2271 static u32 gmac_get_msglevel(struct net_device *netdev) 2272 { 2273 struct gemini_ethernet_port *port = netdev_priv(netdev); 2274 2275 return port->msg_enable; 2276 } 2277 2278 static void gmac_set_msglevel(struct net_device *netdev, u32 level) 2279 { 2280 struct gemini_ethernet_port *port = netdev_priv(netdev); 2281 2282 port->msg_enable = level; 2283 } 2284 2285 static void gmac_get_drvinfo(struct net_device *netdev, 2286 struct ethtool_drvinfo *info) 2287 { 2288 strcpy(info->driver, DRV_NAME); 2289 strcpy(info->bus_info, netdev->dev_id ? "1" : "0"); 2290 } 2291 2292 static const struct net_device_ops gmac_351x_ops = { 2293 .ndo_init = gmac_init, 2294 .ndo_open = gmac_open, 2295 .ndo_stop = gmac_stop, 2296 .ndo_start_xmit = gmac_start_xmit, 2297 .ndo_tx_timeout = gmac_tx_timeout, 2298 .ndo_set_rx_mode = gmac_set_rx_mode, 2299 .ndo_set_mac_address = gmac_set_mac_address, 2300 .ndo_get_stats64 = gmac_get_stats64, 2301 .ndo_change_mtu = gmac_change_mtu, 2302 .ndo_set_features = gmac_set_features, 2303 }; 2304 2305 static const struct ethtool_ops gmac_351x_ethtool_ops = { 2306 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 2307 ETHTOOL_COALESCE_MAX_FRAMES, 2308 .get_sset_count = gmac_get_sset_count, 2309 .get_strings = gmac_get_strings, 2310 .get_ethtool_stats = gmac_get_ethtool_stats, 2311 .get_link = ethtool_op_get_link, 2312 .get_link_ksettings = gmac_get_ksettings, 2313 .set_link_ksettings = gmac_set_ksettings, 2314 .nway_reset = gmac_nway_reset, 2315 .get_pauseparam = gmac_get_pauseparam, 2316 .set_pauseparam = gmac_set_pauseparam, 2317 .get_ringparam = gmac_get_ringparam, 2318 .set_ringparam = gmac_set_ringparam, 2319 .get_coalesce = gmac_get_coalesce, 2320 .set_coalesce = gmac_set_coalesce, 2321 .get_msglevel = gmac_get_msglevel, 2322 .set_msglevel = gmac_set_msglevel, 2323 .get_drvinfo = gmac_get_drvinfo, 2324 }; 2325 2326 static irqreturn_t gemini_port_irq_thread(int irq, void *data) 2327 { 2328 unsigned long irqmask = SWFQ_EMPTY_INT_BIT; 2329 struct gemini_ethernet_port *port = data; 2330 struct gemini_ethernet *geth; 2331 unsigned long flags; 2332 2333 geth = port->geth; 2334 /* The queue is half empty so refill it */ 2335 geth_fill_freeq(geth, true); 2336 2337 spin_lock_irqsave(&geth->irq_lock, flags); 2338 /* ACK queue interrupt */ 2339 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2340 /* Enable queue interrupt again */ 2341 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2342 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2343 spin_unlock_irqrestore(&geth->irq_lock, flags); 2344 2345 return IRQ_HANDLED; 2346 } 2347 2348 static irqreturn_t gemini_port_irq(int irq, void *data) 2349 { 2350 struct gemini_ethernet_port *port = data; 2351 struct gemini_ethernet *geth; 2352 irqreturn_t ret = IRQ_NONE; 2353 u32 val, en; 2354 2355 geth = port->geth; 2356 spin_lock(&geth->irq_lock); 2357 2358 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2359 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2360 2361 if (val & en & SWFQ_EMPTY_INT_BIT) { 2362 /* Disable the queue empty interrupt while we work on 2363 * processing the queue. Also disable overrun interrupts 2364 * as there is not much we can do about it here. 2365 */ 2366 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT 2367 | GMAC1_RX_OVERRUN_INT_BIT); 2368 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2369 ret = IRQ_WAKE_THREAD; 2370 } 2371 2372 spin_unlock(&geth->irq_lock); 2373 2374 return ret; 2375 } 2376 2377 static void gemini_port_remove(struct gemini_ethernet_port *port) 2378 { 2379 if (port->netdev) { 2380 phy_disconnect(port->netdev->phydev); 2381 unregister_netdev(port->netdev); 2382 } 2383 clk_disable_unprepare(port->pclk); 2384 geth_cleanup_freeq(port->geth); 2385 } 2386 2387 static void gemini_ethernet_init(struct gemini_ethernet *geth) 2388 { 2389 /* Only do this once both ports are online */ 2390 if (geth->initialized) 2391 return; 2392 if (geth->port0 && geth->port1) 2393 geth->initialized = true; 2394 else 2395 return; 2396 2397 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 2398 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 2399 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); 2400 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); 2401 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2402 2403 /* Interrupt config: 2404 * 2405 * GMAC0 intr bits ------> int0 ----> eth0 2406 * GMAC1 intr bits ------> int1 ----> eth1 2407 * TOE intr -------------> int1 ----> eth1 2408 * Classification Intr --> int0 ----> eth0 2409 * Default Q0 -----------> int0 ----> eth0 2410 * Default Q1 -----------> int1 ----> eth1 2411 * FreeQ intr -----------> int1 ----> eth1 2412 */ 2413 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG); 2414 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG); 2415 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG); 2416 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG); 2417 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG); 2418 2419 /* edge-triggered interrupts packed to level-triggered one... */ 2420 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 2421 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 2422 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); 2423 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); 2424 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2425 2426 /* Set up queue */ 2427 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 2428 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG); 2429 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG); 2430 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG); 2431 2432 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER; 2433 /* This makes the queue resize on probe() so that we 2434 * set up and enable the queue IRQ. FIXME: fragile. 2435 */ 2436 geth->freeq_order = 1; 2437 } 2438 2439 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port) 2440 { 2441 port->mac_addr[0] = 2442 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0)); 2443 port->mac_addr[1] = 2444 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1)); 2445 port->mac_addr[2] = 2446 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2)); 2447 } 2448 2449 static int gemini_ethernet_port_probe(struct platform_device *pdev) 2450 { 2451 char *port_names[2] = { "ethernet0", "ethernet1" }; 2452 struct device_node *np = pdev->dev.of_node; 2453 struct gemini_ethernet_port *port; 2454 struct device *dev = &pdev->dev; 2455 struct gemini_ethernet *geth; 2456 struct net_device *netdev; 2457 struct device *parent; 2458 u8 mac[ETH_ALEN]; 2459 unsigned int id; 2460 int irq; 2461 int ret; 2462 2463 parent = dev->parent; 2464 geth = dev_get_drvdata(parent); 2465 2466 if (!strcmp(dev_name(dev), "60008000.ethernet-port")) 2467 id = 0; 2468 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port")) 2469 id = 1; 2470 else 2471 return -ENODEV; 2472 2473 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id); 2474 2475 netdev = devm_alloc_etherdev_mqs(dev, sizeof(*port), TX_QUEUE_NUM, TX_QUEUE_NUM); 2476 if (!netdev) { 2477 dev_err(dev, "Can't allocate ethernet device #%d\n", id); 2478 return -ENOMEM; 2479 } 2480 2481 port = netdev_priv(netdev); 2482 SET_NETDEV_DEV(netdev, dev); 2483 port->netdev = netdev; 2484 port->id = id; 2485 port->geth = geth; 2486 port->dev = dev; 2487 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2488 2489 /* DMA memory */ 2490 port->dma_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 2491 if (IS_ERR(port->dma_base)) { 2492 dev_err(dev, "get DMA address failed\n"); 2493 return PTR_ERR(port->dma_base); 2494 } 2495 2496 /* GMAC config memory */ 2497 port->gmac_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 2498 if (IS_ERR(port->gmac_base)) { 2499 dev_err(dev, "get GMAC address failed\n"); 2500 return PTR_ERR(port->gmac_base); 2501 } 2502 2503 /* Interrupt */ 2504 irq = platform_get_irq(pdev, 0); 2505 if (irq < 0) 2506 return irq; 2507 port->irq = irq; 2508 2509 /* Clock the port */ 2510 port->pclk = devm_clk_get(dev, "PCLK"); 2511 if (IS_ERR(port->pclk)) { 2512 dev_err(dev, "no PCLK\n"); 2513 return PTR_ERR(port->pclk); 2514 } 2515 ret = clk_prepare_enable(port->pclk); 2516 if (ret) 2517 return ret; 2518 2519 /* Maybe there is a nice ethernet address we should use */ 2520 gemini_port_save_mac_addr(port); 2521 2522 /* Reset the port */ 2523 port->reset = devm_reset_control_get_exclusive(dev, NULL); 2524 if (IS_ERR(port->reset)) { 2525 dev_err(dev, "no reset\n"); 2526 ret = PTR_ERR(port->reset); 2527 goto unprepare; 2528 } 2529 reset_control_reset(port->reset); 2530 usleep_range(100, 500); 2531 2532 /* Assign pointer in the main state container */ 2533 if (!id) 2534 geth->port0 = port; 2535 else 2536 geth->port1 = port; 2537 2538 /* This will just be done once both ports are up and reset */ 2539 gemini_ethernet_init(geth); 2540 2541 platform_set_drvdata(pdev, port); 2542 2543 /* Set up and register the netdev */ 2544 netdev->dev_id = port->id; 2545 netdev->irq = irq; 2546 netdev->netdev_ops = &gmac_351x_ops; 2547 netdev->ethtool_ops = &gmac_351x_ethtool_ops; 2548 2549 spin_lock_init(&port->config_lock); 2550 gmac_clear_hw_stats(netdev); 2551 2552 netdev->hw_features = GMAC_OFFLOAD_FEATURES; 2553 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; 2554 /* We can receive jumbo frames up to 10236 bytes but only 2555 * transmit 2047 bytes so, let's accept payloads of 2047 2556 * bytes minus VLAN and ethernet header 2557 */ 2558 netdev->min_mtu = ETH_MIN_MTU; 2559 netdev->max_mtu = MTU_SIZE_BIT_MASK - VLAN_ETH_HLEN; 2560 2561 port->freeq_refill = 0; 2562 netif_napi_add(netdev, &port->napi, gmac_napi_poll); 2563 2564 ret = of_get_mac_address(np, mac); 2565 if (!ret) { 2566 dev_info(dev, "Setting macaddr from DT %pM\n", mac); 2567 memcpy(port->mac_addr, mac, ETH_ALEN); 2568 } 2569 2570 if (is_valid_ether_addr((void *)port->mac_addr)) { 2571 eth_hw_addr_set(netdev, (u8 *)port->mac_addr); 2572 } else { 2573 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n", 2574 port->mac_addr[0], port->mac_addr[1], 2575 port->mac_addr[2]); 2576 dev_info(dev, "using a random ethernet address\n"); 2577 eth_hw_addr_random(netdev); 2578 } 2579 gmac_write_mac_address(netdev); 2580 2581 ret = devm_request_threaded_irq(port->dev, 2582 port->irq, 2583 gemini_port_irq, 2584 gemini_port_irq_thread, 2585 IRQF_SHARED, 2586 port_names[port->id], 2587 port); 2588 if (ret) 2589 goto unprepare; 2590 2591 ret = gmac_setup_phy(netdev); 2592 if (ret) { 2593 netdev_err(netdev, 2594 "PHY init failed\n"); 2595 goto unprepare; 2596 } 2597 2598 ret = register_netdev(netdev); 2599 if (ret) 2600 goto unprepare; 2601 2602 return 0; 2603 2604 unprepare: 2605 clk_disable_unprepare(port->pclk); 2606 return ret; 2607 } 2608 2609 static void gemini_ethernet_port_remove(struct platform_device *pdev) 2610 { 2611 struct gemini_ethernet_port *port = platform_get_drvdata(pdev); 2612 2613 gemini_port_remove(port); 2614 } 2615 2616 static const struct of_device_id gemini_ethernet_port_of_match[] = { 2617 { 2618 .compatible = "cortina,gemini-ethernet-port", 2619 }, 2620 {}, 2621 }; 2622 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match); 2623 2624 static struct platform_driver gemini_ethernet_port_driver = { 2625 .driver = { 2626 .name = "gemini-ethernet-port", 2627 .of_match_table = gemini_ethernet_port_of_match, 2628 }, 2629 .probe = gemini_ethernet_port_probe, 2630 .remove = gemini_ethernet_port_remove, 2631 }; 2632 2633 static int gemini_ethernet_probe(struct platform_device *pdev) 2634 { 2635 struct device *dev = &pdev->dev; 2636 struct gemini_ethernet *geth; 2637 unsigned int retry = 5; 2638 u32 val; 2639 2640 /* Global registers */ 2641 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL); 2642 if (!geth) 2643 return -ENOMEM; 2644 geth->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 2645 if (IS_ERR(geth->base)) 2646 return PTR_ERR(geth->base); 2647 geth->dev = dev; 2648 2649 /* Wait for ports to stabilize */ 2650 do { 2651 udelay(2); 2652 val = readl(geth->base + GLOBAL_TOE_VERSION_REG); 2653 barrier(); 2654 } while (!val && --retry); 2655 if (!retry) { 2656 dev_err(dev, "failed to reset ethernet\n"); 2657 return -EIO; 2658 } 2659 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n", 2660 (val >> 4) & 0xFFFU, val & 0xFU); 2661 2662 spin_lock_init(&geth->irq_lock); 2663 spin_lock_init(&geth->freeq_lock); 2664 2665 /* The children will use this */ 2666 platform_set_drvdata(pdev, geth); 2667 2668 /* Spawn child devices for the two ports */ 2669 return devm_of_platform_populate(dev); 2670 } 2671 2672 static void gemini_ethernet_remove(struct platform_device *pdev) 2673 { 2674 struct gemini_ethernet *geth = platform_get_drvdata(pdev); 2675 2676 geth_cleanup_freeq(geth); 2677 geth->initialized = false; 2678 } 2679 2680 static const struct of_device_id gemini_ethernet_of_match[] = { 2681 { 2682 .compatible = "cortina,gemini-ethernet", 2683 }, 2684 {}, 2685 }; 2686 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match); 2687 2688 static struct platform_driver gemini_ethernet_driver = { 2689 .driver = { 2690 .name = DRV_NAME, 2691 .of_match_table = gemini_ethernet_of_match, 2692 }, 2693 .probe = gemini_ethernet_probe, 2694 .remove = gemini_ethernet_remove, 2695 }; 2696 2697 static int __init gemini_ethernet_module_init(void) 2698 { 2699 int ret; 2700 2701 ret = platform_driver_register(&gemini_ethernet_port_driver); 2702 if (ret) 2703 return ret; 2704 2705 ret = platform_driver_register(&gemini_ethernet_driver); 2706 if (ret) { 2707 platform_driver_unregister(&gemini_ethernet_port_driver); 2708 return ret; 2709 } 2710 2711 return 0; 2712 } 2713 module_init(gemini_ethernet_module_init); 2714 2715 static void __exit gemini_ethernet_module_exit(void) 2716 { 2717 platform_driver_unregister(&gemini_ethernet_driver); 2718 platform_driver_unregister(&gemini_ethernet_port_driver); 2719 } 2720 module_exit(gemini_ethernet_module_exit); 2721 2722 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 2723 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver"); 2724 MODULE_LICENSE("GPL"); 2725 MODULE_ALIAS("platform:" DRV_NAME); 2726