1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/iommu.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/gro.h>
21 #include <net/ip6_checksum.h>
22 #include <net/page_pool/helpers.h>
23 #include <net/pkt_cls.h>
24 #include <net/pkt_sched.h>
25 #include <net/tcp.h>
26 #include <net/vxlan.h>
27 #include <net/geneve.h>
28
29 #include "hnae3.h"
30 #include "hns3_enet.h"
31 /* All hns3 tracepoints are defined by the include below, which
32 * must be included exactly once across the whole kernel with
33 * CREATE_TRACE_POINTS defined
34 */
35 #define CREATE_TRACE_POINTS
36 #include "hns3_trace.h"
37
38 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
39 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
40
41 #define hns3_rl_err(fmt, ...) \
42 do { \
43 if (net_ratelimit()) \
44 netdev_err(fmt, ##__VA_ARGS__); \
45 } while (0)
46
47 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
48
49 static const char hns3_driver_name[] = "hns3";
50 static const char hns3_driver_string[] =
51 "Hisilicon Ethernet Network Driver for Hip08 Family";
52 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
53 static struct hnae3_client client;
54
55 static int debug = -1;
56 module_param(debug, int, 0);
57 MODULE_PARM_DESC(debug, " Network interface message level setting");
58
59 static unsigned int tx_sgl = 1;
60 module_param(tx_sgl, uint, 0600);
61 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
62
63 static bool page_pool_enabled = true;
64 module_param(page_pool_enabled, bool, 0400);
65
66 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
67 sizeof(struct sg_table))
68 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
69 dma_get_cache_alignment())
70
71 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
72 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
73
74 #define HNS3_INNER_VLAN_TAG 1
75 #define HNS3_OUTER_VLAN_TAG 2
76
77 #define HNS3_MIN_TX_LEN 33U
78 #define HNS3_MIN_TUN_PKT_LEN 65U
79
80 /* hns3_pci_tbl - PCI Device ID Table
81 *
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id hns3_pci_tbl[] = {
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
104 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
105 /* required last entry */
106 {0,}
107 };
108 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
109
110 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
111 { ptype, \
112 l, \
113 CHECKSUM_##s, \
114 HNS3_L3_TYPE_##t, \
115 1, \
116 h}
117
118 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
120 PKT_HASH_TYPE_NONE }
121
122 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
123 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
124 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
138 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
139 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
142 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
144 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
145 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
146 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
148 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
151 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
152 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
154 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
156 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
159 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
161 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
162 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
164 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
167 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
233 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
234 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
236 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
238 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
239 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
240 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
242 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
245 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
246 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
248 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
250 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
253 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
255 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
256 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
258 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
261 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
378 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
379 };
380
381 #define HNS3_INVALID_PTYPE \
382 ARRAY_SIZE(hns3_rx_ptype_tbl)
383
hns3_irq_handle(int irq,void * vector)384 static irqreturn_t hns3_irq_handle(int irq, void *vector)
385 {
386 struct hns3_enet_tqp_vector *tqp_vector = vector;
387
388 napi_schedule_irqoff(&tqp_vector->napi);
389 tqp_vector->event_cnt++;
390
391 return IRQ_HANDLED;
392 }
393
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)394 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
395 {
396 struct hns3_enet_tqp_vector *tqp_vectors;
397 unsigned int i;
398
399 for (i = 0; i < priv->vector_num; i++) {
400 tqp_vectors = &priv->tqp_vector[i];
401
402 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
403 continue;
404
405 /* clear the affinity mask */
406 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
407
408 /* release the irq resource */
409 free_irq(tqp_vectors->vector_irq, tqp_vectors);
410 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
411 }
412 }
413
hns3_nic_init_irq(struct hns3_nic_priv * priv)414 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
415 {
416 struct hns3_enet_tqp_vector *tqp_vectors;
417 int txrx_int_idx = 0;
418 int rx_int_idx = 0;
419 int tx_int_idx = 0;
420 unsigned int i;
421 int ret;
422
423 for (i = 0; i < priv->vector_num; i++) {
424 tqp_vectors = &priv->tqp_vector[i];
425
426 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
427 continue;
428
429 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
430 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
431 "%s-%s-%s-%d", hns3_driver_name,
432 pci_name(priv->ae_handle->pdev),
433 "TxRx", txrx_int_idx++);
434 txrx_int_idx++;
435 } else if (tqp_vectors->rx_group.ring) {
436 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
437 "%s-%s-%s-%d", hns3_driver_name,
438 pci_name(priv->ae_handle->pdev),
439 "Rx", rx_int_idx++);
440 } else if (tqp_vectors->tx_group.ring) {
441 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
442 "%s-%s-%s-%d", hns3_driver_name,
443 pci_name(priv->ae_handle->pdev),
444 "Tx", tx_int_idx++);
445 } else {
446 /* Skip this unused q_vector */
447 continue;
448 }
449
450 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
451
452 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
453 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
454 tqp_vectors->name, tqp_vectors);
455 if (ret) {
456 netdev_err(priv->netdev, "request irq(%d) fail\n",
457 tqp_vectors->vector_irq);
458 hns3_nic_uninit_irq(priv);
459 return ret;
460 }
461
462 irq_set_affinity_hint(tqp_vectors->vector_irq,
463 &tqp_vectors->affinity_mask);
464
465 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
466 }
467
468 return 0;
469 }
470
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)471 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
472 u32 mask_en)
473 {
474 writel(mask_en, tqp_vector->mask_addr);
475 }
476
hns3_irq_enable(struct hns3_enet_tqp_vector * tqp_vector)477 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector)
478 {
479 napi_enable(&tqp_vector->napi);
480 enable_irq(tqp_vector->vector_irq);
481 }
482
hns3_irq_disable(struct hns3_enet_tqp_vector * tqp_vector)483 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector)
484 {
485 disable_irq(tqp_vector->vector_irq);
486 napi_disable(&tqp_vector->napi);
487 cancel_work_sync(&tqp_vector->rx_group.dim.work);
488 cancel_work_sync(&tqp_vector->tx_group.dim.work);
489 }
490
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)491 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
492 u32 rl_value)
493 {
494 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
495
496 /* this defines the configuration for RL (Interrupt Rate Limiter).
497 * Rl defines rate of interrupts i.e. number of interrupts-per-second
498 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
499 */
500 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
501 !tqp_vector->rx_group.coal.adapt_enable)
502 /* According to the hardware, the range of rl_reg is
503 * 0-59 and the unit is 4.
504 */
505 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
506
507 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
508 }
509
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)510 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
511 u32 gl_value)
512 {
513 u32 new_val;
514
515 if (tqp_vector->rx_group.coal.unit_1us)
516 new_val = gl_value | HNS3_INT_GL_1US;
517 else
518 new_val = hns3_gl_usec_to_reg(gl_value);
519
520 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
521 }
522
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)523 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
524 u32 gl_value)
525 {
526 u32 new_val;
527
528 if (tqp_vector->tx_group.coal.unit_1us)
529 new_val = gl_value | HNS3_INT_GL_1US;
530 else
531 new_val = hns3_gl_usec_to_reg(gl_value);
532
533 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
534 }
535
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)536 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
537 u32 ql_value)
538 {
539 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
540 }
541
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)542 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
543 u32 ql_value)
544 {
545 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
546 }
547
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)548 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
549 struct hns3_nic_priv *priv)
550 {
551 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
552 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
553 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
554 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
555 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
556
557 tx_coal->adapt_enable = ptx_coal->adapt_enable;
558 rx_coal->adapt_enable = prx_coal->adapt_enable;
559
560 tx_coal->int_gl = ptx_coal->int_gl;
561 rx_coal->int_gl = prx_coal->int_gl;
562
563 rx_coal->flow_level = prx_coal->flow_level;
564 tx_coal->flow_level = ptx_coal->flow_level;
565
566 /* device version above V3(include V3), GL can configure 1us
567 * unit, so uses 1us unit.
568 */
569 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
570 tx_coal->unit_1us = 1;
571 rx_coal->unit_1us = 1;
572 }
573
574 if (ae_dev->dev_specs.int_ql_max) {
575 tx_coal->ql_enable = 1;
576 rx_coal->ql_enable = 1;
577 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
578 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
579 tx_coal->int_ql = ptx_coal->int_ql;
580 rx_coal->int_ql = prx_coal->int_ql;
581 }
582 }
583
584 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)585 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
586 struct hns3_nic_priv *priv)
587 {
588 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
589 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
590 struct hnae3_handle *h = priv->ae_handle;
591
592 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
593 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
594 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
595
596 if (tx_coal->ql_enable)
597 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
598
599 if (rx_coal->ql_enable)
600 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
601 }
602
hns3_nic_set_real_num_queue(struct net_device * netdev)603 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
604 {
605 struct hnae3_handle *h = hns3_get_handle(netdev);
606 struct hnae3_knic_private_info *kinfo = &h->kinfo;
607 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
608 unsigned int queue_size = kinfo->num_tqps;
609 int i, ret;
610
611 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
612 netdev_reset_tc(netdev);
613 } else {
614 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
615 if (ret) {
616 netdev_err(netdev,
617 "netdev_set_num_tc fail, ret=%d!\n", ret);
618 return ret;
619 }
620
621 for (i = 0; i < tc_info->num_tc; i++)
622 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
623 tc_info->tqp_offset[i]);
624 }
625
626 ret = netif_set_real_num_tx_queues(netdev, queue_size);
627 if (ret) {
628 netdev_err(netdev,
629 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
630 return ret;
631 }
632
633 ret = netif_set_real_num_rx_queues(netdev, queue_size);
634 if (ret) {
635 netdev_err(netdev,
636 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
637 return ret;
638 }
639
640 return 0;
641 }
642
hns3_get_max_available_channels(struct hnae3_handle * h)643 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
644 {
645 u16 alloc_tqps, max_rss_size, rss_size;
646
647 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
648 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
649
650 return min_t(u16, rss_size, max_rss_size);
651 }
652
hns3_tqp_enable(struct hnae3_queue * tqp)653 static void hns3_tqp_enable(struct hnae3_queue *tqp)
654 {
655 u32 rcb_reg;
656
657 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
658 rcb_reg |= BIT(HNS3_RING_EN_B);
659 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
660 }
661
hns3_tqp_disable(struct hnae3_queue * tqp)662 static void hns3_tqp_disable(struct hnae3_queue *tqp)
663 {
664 u32 rcb_reg;
665
666 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
667 rcb_reg &= ~BIT(HNS3_RING_EN_B);
668 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
669 }
670
hns3_free_rx_cpu_rmap(struct net_device * netdev)671 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
672 {
673 #ifdef CONFIG_RFS_ACCEL
674 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
675 netdev->rx_cpu_rmap = NULL;
676 #endif
677 }
678
hns3_set_rx_cpu_rmap(struct net_device * netdev)679 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
680 {
681 #ifdef CONFIG_RFS_ACCEL
682 struct hns3_nic_priv *priv = netdev_priv(netdev);
683 struct hns3_enet_tqp_vector *tqp_vector;
684 int i, ret;
685
686 if (!netdev->rx_cpu_rmap) {
687 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
688 if (!netdev->rx_cpu_rmap)
689 return -ENOMEM;
690 }
691
692 for (i = 0; i < priv->vector_num; i++) {
693 tqp_vector = &priv->tqp_vector[i];
694 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
695 tqp_vector->vector_irq);
696 if (ret) {
697 hns3_free_rx_cpu_rmap(netdev);
698 return ret;
699 }
700 }
701 #endif
702 return 0;
703 }
704
hns3_enable_irqs_and_tqps(struct net_device * netdev)705 static void hns3_enable_irqs_and_tqps(struct net_device *netdev)
706 {
707 struct hns3_nic_priv *priv = netdev_priv(netdev);
708 struct hnae3_handle *h = priv->ae_handle;
709 u16 i;
710
711 for (i = 0; i < priv->vector_num; i++)
712 hns3_irq_enable(&priv->tqp_vector[i]);
713
714 for (i = 0; i < priv->vector_num; i++)
715 hns3_mask_vector_irq(&priv->tqp_vector[i], 1);
716
717 for (i = 0; i < h->kinfo.num_tqps; i++)
718 hns3_tqp_enable(h->kinfo.tqp[i]);
719 }
720
hns3_disable_irqs_and_tqps(struct net_device * netdev)721 static void hns3_disable_irqs_and_tqps(struct net_device *netdev)
722 {
723 struct hns3_nic_priv *priv = netdev_priv(netdev);
724 struct hnae3_handle *h = priv->ae_handle;
725 u16 i;
726
727 for (i = 0; i < h->kinfo.num_tqps; i++)
728 hns3_tqp_disable(h->kinfo.tqp[i]);
729
730 for (i = 0; i < priv->vector_num; i++)
731 hns3_mask_vector_irq(&priv->tqp_vector[i], 0);
732
733 for (i = 0; i < priv->vector_num; i++)
734 hns3_irq_disable(&priv->tqp_vector[i]);
735 }
736
hns3_nic_net_up(struct net_device * netdev)737 static int hns3_nic_net_up(struct net_device *netdev)
738 {
739 struct hns3_nic_priv *priv = netdev_priv(netdev);
740 struct hnae3_handle *h = priv->ae_handle;
741 int ret;
742
743 ret = hns3_nic_reset_all_ring(h);
744 if (ret)
745 return ret;
746
747 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
748
749 hns3_enable_irqs_and_tqps(netdev);
750
751 /* start the ae_dev */
752 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
753 if (ret) {
754 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
755 hns3_disable_irqs_and_tqps(netdev);
756 }
757
758 return ret;
759 }
760
hns3_config_xps(struct hns3_nic_priv * priv)761 static void hns3_config_xps(struct hns3_nic_priv *priv)
762 {
763 int i;
764
765 for (i = 0; i < priv->vector_num; i++) {
766 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
767 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
768
769 while (ring) {
770 int ret;
771
772 ret = netif_set_xps_queue(priv->netdev,
773 &tqp_vector->affinity_mask,
774 ring->tqp->tqp_index);
775 if (ret)
776 netdev_warn(priv->netdev,
777 "set xps queue failed: %d", ret);
778
779 ring = ring->next;
780 }
781 }
782 }
783
hns3_nic_net_open(struct net_device * netdev)784 static int hns3_nic_net_open(struct net_device *netdev)
785 {
786 struct hns3_nic_priv *priv = netdev_priv(netdev);
787 struct hnae3_handle *h = hns3_get_handle(netdev);
788 struct hnae3_knic_private_info *kinfo;
789 int i, ret;
790
791 if (hns3_nic_resetting(netdev))
792 return -EBUSY;
793
794 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
795 netdev_warn(netdev, "net open repeatedly!\n");
796 return 0;
797 }
798
799 netif_carrier_off(netdev);
800
801 ret = hns3_nic_set_real_num_queue(netdev);
802 if (ret)
803 return ret;
804
805 ret = hns3_nic_net_up(netdev);
806 if (ret) {
807 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
808 return ret;
809 }
810
811 kinfo = &h->kinfo;
812 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
813 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
814
815 if (h->ae_algo->ops->set_timer_task)
816 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
817
818 hns3_config_xps(priv);
819
820 netif_dbg(h, drv, netdev, "net open\n");
821
822 return 0;
823 }
824
hns3_reset_tx_queue(struct hnae3_handle * h)825 static void hns3_reset_tx_queue(struct hnae3_handle *h)
826 {
827 struct net_device *ndev = h->kinfo.netdev;
828 struct hns3_nic_priv *priv = netdev_priv(ndev);
829 struct netdev_queue *dev_queue;
830 u32 i;
831
832 for (i = 0; i < h->kinfo.num_tqps; i++) {
833 dev_queue = netdev_get_tx_queue(ndev,
834 priv->ring[i].queue_index);
835 netdev_tx_reset_queue(dev_queue);
836 }
837 }
838
hns3_nic_net_down(struct net_device * netdev)839 static void hns3_nic_net_down(struct net_device *netdev)
840 {
841 struct hns3_nic_priv *priv = netdev_priv(netdev);
842 const struct hnae3_ae_ops *ops;
843
844 hns3_disable_irqs_and_tqps(netdev);
845
846 /* stop ae_dev */
847 ops = priv->ae_handle->ae_algo->ops;
848 if (ops->stop)
849 ops->stop(priv->ae_handle);
850
851 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
852 * during reset process, because driver may not be able
853 * to disable the ring through firmware when downing the netdev.
854 */
855 if (!hns3_nic_resetting(netdev))
856 hns3_clear_all_ring(priv->ae_handle, false);
857
858 hns3_reset_tx_queue(priv->ae_handle);
859 }
860
hns3_nic_net_stop(struct net_device * netdev)861 static int hns3_nic_net_stop(struct net_device *netdev)
862 {
863 struct hns3_nic_priv *priv = netdev_priv(netdev);
864 struct hnae3_handle *h = hns3_get_handle(netdev);
865
866 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
867 return 0;
868
869 netif_dbg(h, drv, netdev, "net stop\n");
870
871 if (h->ae_algo->ops->set_timer_task)
872 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
873
874 netif_carrier_off(netdev);
875 netif_tx_disable(netdev);
876
877 hns3_nic_net_down(netdev);
878
879 return 0;
880 }
881
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)882 static int hns3_nic_uc_sync(struct net_device *netdev,
883 const unsigned char *addr)
884 {
885 struct hnae3_handle *h = hns3_get_handle(netdev);
886
887 if (h->ae_algo->ops->add_uc_addr)
888 return h->ae_algo->ops->add_uc_addr(h, addr);
889
890 return 0;
891 }
892
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)893 static int hns3_nic_uc_unsync(struct net_device *netdev,
894 const unsigned char *addr)
895 {
896 struct hnae3_handle *h = hns3_get_handle(netdev);
897
898 /* need ignore the request of removing device address, because
899 * we store the device address and other addresses of uc list
900 * in the function's mac filter list.
901 */
902 if (ether_addr_equal(addr, netdev->dev_addr))
903 return 0;
904
905 if (h->ae_algo->ops->rm_uc_addr)
906 return h->ae_algo->ops->rm_uc_addr(h, addr);
907
908 return 0;
909 }
910
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)911 static int hns3_nic_mc_sync(struct net_device *netdev,
912 const unsigned char *addr)
913 {
914 struct hnae3_handle *h = hns3_get_handle(netdev);
915
916 if (h->ae_algo->ops->add_mc_addr)
917 return h->ae_algo->ops->add_mc_addr(h, addr);
918
919 return 0;
920 }
921
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)922 static int hns3_nic_mc_unsync(struct net_device *netdev,
923 const unsigned char *addr)
924 {
925 struct hnae3_handle *h = hns3_get_handle(netdev);
926
927 if (h->ae_algo->ops->rm_mc_addr)
928 return h->ae_algo->ops->rm_mc_addr(h, addr);
929
930 return 0;
931 }
932
hns3_get_netdev_flags(struct net_device * netdev)933 static u8 hns3_get_netdev_flags(struct net_device *netdev)
934 {
935 u8 flags = 0;
936
937 if (netdev->flags & IFF_PROMISC)
938 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
939 else if (netdev->flags & IFF_ALLMULTI)
940 flags = HNAE3_USER_MPE;
941
942 return flags;
943 }
944
hns3_nic_set_rx_mode(struct net_device * netdev)945 static void hns3_nic_set_rx_mode(struct net_device *netdev)
946 {
947 struct hnae3_handle *h = hns3_get_handle(netdev);
948 u8 new_flags;
949
950 new_flags = hns3_get_netdev_flags(netdev);
951
952 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
953 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
954
955 /* User mode Promisc mode enable and vlan filtering is disabled to
956 * let all packets in.
957 */
958 h->netdev_flags = new_flags;
959 hns3_request_update_promisc_mode(h);
960 }
961
hns3_request_update_promisc_mode(struct hnae3_handle * handle)962 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
963 {
964 const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
965
966 if (ops->request_update_promisc_mode)
967 ops->request_update_promisc_mode(handle);
968 }
969
hns3_tx_spare_space(struct hns3_enet_ring * ring)970 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
971 {
972 struct hns3_tx_spare *tx_spare = ring->tx_spare;
973 u32 ntc, ntu;
974
975 /* This smp_load_acquire() pairs with smp_store_release() in
976 * hns3_tx_spare_update() called in tx desc cleaning process.
977 */
978 ntc = smp_load_acquire(&tx_spare->last_to_clean);
979 ntu = tx_spare->next_to_use;
980
981 if (ntc > ntu)
982 return ntc - ntu - 1;
983
984 /* The free tx buffer is divided into two part, so pick the
985 * larger one.
986 */
987 return max(ntc, tx_spare->len - ntu) - 1;
988 }
989
hns3_tx_spare_update(struct hns3_enet_ring * ring)990 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
991 {
992 struct hns3_tx_spare *tx_spare = ring->tx_spare;
993
994 if (!tx_spare ||
995 tx_spare->last_to_clean == tx_spare->next_to_clean)
996 return;
997
998 /* This smp_store_release() pairs with smp_load_acquire() in
999 * hns3_tx_spare_space() called in xmit process.
1000 */
1001 smp_store_release(&tx_spare->last_to_clean,
1002 tx_spare->next_to_clean);
1003 }
1004
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1005 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1006 struct sk_buff *skb,
1007 u32 space)
1008 {
1009 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1010 skb_headlen(skb);
1011
1012 if (len > ring->tx_copybreak)
1013 return false;
1014
1015 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1016 hns3_ring_stats_update(ring, tx_spare_full);
1017 return false;
1018 }
1019
1020 return true;
1021 }
1022
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1023 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1024 struct sk_buff *skb,
1025 u32 space)
1026 {
1027 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1028 (!skb_has_frag_list(skb) &&
1029 skb_shinfo(skb)->nr_frags < tx_sgl))
1030 return false;
1031
1032 if (space < HNS3_MAX_SGL_SIZE) {
1033 hns3_ring_stats_update(ring, tx_spare_full);
1034 return false;
1035 }
1036
1037 return true;
1038 }
1039
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1040 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1041 {
1042 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1043 struct net_device *netdev = ring_to_netdev(ring);
1044 struct hns3_nic_priv *priv = netdev_priv(netdev);
1045 struct hns3_tx_spare *tx_spare;
1046 struct page *page;
1047 dma_addr_t dma;
1048 int order;
1049
1050 if (!alloc_size)
1051 return;
1052
1053 order = get_order(alloc_size);
1054 if (order > MAX_PAGE_ORDER) {
1055 if (net_ratelimit())
1056 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1057 return;
1058 }
1059
1060 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1061 GFP_KERNEL);
1062 if (!tx_spare) {
1063 /* The driver still work without the tx spare buffer */
1064 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1065 goto devm_kzalloc_error;
1066 }
1067
1068 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1069 GFP_KERNEL, order);
1070 if (!page) {
1071 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1072 goto alloc_pages_error;
1073 }
1074
1075 dma = dma_map_page(ring_to_dev(ring), page, 0,
1076 PAGE_SIZE << order, DMA_TO_DEVICE);
1077 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1078 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1079 goto dma_mapping_error;
1080 }
1081
1082 tx_spare->dma = dma;
1083 tx_spare->buf = page_address(page);
1084 tx_spare->len = PAGE_SIZE << order;
1085 ring->tx_spare = tx_spare;
1086 ring->tx_copybreak = priv->tx_copybreak;
1087 return;
1088
1089 dma_mapping_error:
1090 put_page(page);
1091 alloc_pages_error:
1092 devm_kfree(ring_to_dev(ring), tx_spare);
1093 devm_kzalloc_error:
1094 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1095 }
1096
1097 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1098 * before calling below function to allocate tx buffer.
1099 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1100 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1101 unsigned int size, dma_addr_t *dma,
1102 u32 *cb_len)
1103 {
1104 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1105 u32 ntu = tx_spare->next_to_use;
1106
1107 size = ALIGN(size, dma_get_cache_alignment());
1108 *cb_len = size;
1109
1110 /* Tx spare buffer wraps back here because the end of
1111 * freed tx buffer is not enough.
1112 */
1113 if (ntu + size > tx_spare->len) {
1114 *cb_len += (tx_spare->len - ntu);
1115 ntu = 0;
1116 }
1117
1118 tx_spare->next_to_use = ntu + size;
1119 if (tx_spare->next_to_use == tx_spare->len)
1120 tx_spare->next_to_use = 0;
1121
1122 *dma = tx_spare->dma + ntu;
1123
1124 return tx_spare->buf + ntu;
1125 }
1126
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1127 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1128 {
1129 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1130
1131 if (len > tx_spare->next_to_use) {
1132 len -= tx_spare->next_to_use;
1133 tx_spare->next_to_use = tx_spare->len - len;
1134 } else {
1135 tx_spare->next_to_use -= len;
1136 }
1137 }
1138
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1139 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1140 struct hns3_desc_cb *cb)
1141 {
1142 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1143 u32 ntc = tx_spare->next_to_clean;
1144 u32 len = cb->length;
1145
1146 tx_spare->next_to_clean += len;
1147
1148 if (tx_spare->next_to_clean >= tx_spare->len) {
1149 tx_spare->next_to_clean -= tx_spare->len;
1150
1151 if (tx_spare->next_to_clean) {
1152 ntc = 0;
1153 len = tx_spare->next_to_clean;
1154 }
1155 }
1156
1157 /* This tx spare buffer is only really reclaimed after calling
1158 * hns3_tx_spare_update(), so it is still safe to use the info in
1159 * the tx buffer to do the dma sync or sg unmapping after
1160 * tx_spare->next_to_clean is moved forword.
1161 */
1162 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1163 dma_addr_t dma = tx_spare->dma + ntc;
1164
1165 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1166 DMA_TO_DEVICE);
1167 } else {
1168 struct sg_table *sgt = tx_spare->buf + ntc;
1169
1170 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1171 DMA_TO_DEVICE);
1172 }
1173 }
1174
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1175 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1176 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1177 {
1178 u32 l4_offset, hdr_len;
1179 union l3_hdr_info l3;
1180 union l4_hdr_info l4;
1181 u32 l4_paylen;
1182 int ret;
1183
1184 if (!skb_is_gso(skb))
1185 return 0;
1186
1187 ret = skb_cow_head(skb, 0);
1188 if (unlikely(ret < 0))
1189 return ret;
1190
1191 l3.hdr = skb_network_header(skb);
1192 l4.hdr = skb_transport_header(skb);
1193
1194 /* Software should clear the IPv4's checksum field when tso is
1195 * needed.
1196 */
1197 if (l3.v4->version == 4)
1198 l3.v4->check = 0;
1199
1200 /* tunnel packet */
1201 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1202 SKB_GSO_GRE_CSUM |
1203 SKB_GSO_UDP_TUNNEL |
1204 SKB_GSO_UDP_TUNNEL_CSUM)) {
1205 /* reset l3&l4 pointers from outer to inner headers */
1206 l3.hdr = skb_inner_network_header(skb);
1207 l4.hdr = skb_inner_transport_header(skb);
1208
1209 /* Software should clear the IPv4's checksum field when
1210 * tso is needed.
1211 */
1212 if (l3.v4->version == 4)
1213 l3.v4->check = 0;
1214 }
1215
1216 /* normal or tunnel packet */
1217 l4_offset = l4.hdr - skb->data;
1218
1219 /* remove payload length from inner pseudo checksum when tso */
1220 l4_paylen = skb->len - l4_offset;
1221
1222 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1223 hdr_len = sizeof(*l4.udp) + l4_offset;
1224 csum_replace_by_diff(&l4.udp->check,
1225 (__force __wsum)htonl(l4_paylen));
1226 } else {
1227 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1228 csum_replace_by_diff(&l4.tcp->check,
1229 (__force __wsum)htonl(l4_paylen));
1230 }
1231
1232 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1233
1234 /* find the txbd field values */
1235 *paylen_fdop_ol4cs = skb->len - hdr_len;
1236 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1237
1238 /* offload outer UDP header checksum */
1239 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1240 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1241
1242 /* get MSS for TSO */
1243 *mss = skb_shinfo(skb)->gso_size;
1244
1245 trace_hns3_tso(skb);
1246
1247 return 0;
1248 }
1249
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1250 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1251 u8 *il4_proto)
1252 {
1253 union l3_hdr_info l3;
1254 unsigned char *l4_hdr;
1255 unsigned char *exthdr;
1256 u8 l4_proto_tmp;
1257 __be16 frag_off;
1258
1259 /* find outer header point */
1260 l3.hdr = skb_network_header(skb);
1261 l4_hdr = skb_transport_header(skb);
1262
1263 if (skb->protocol == htons(ETH_P_IPV6)) {
1264 exthdr = l3.hdr + sizeof(*l3.v6);
1265 l4_proto_tmp = l3.v6->nexthdr;
1266 if (l4_hdr != exthdr)
1267 ipv6_skip_exthdr(skb, exthdr - skb->data,
1268 &l4_proto_tmp, &frag_off);
1269 } else if (skb->protocol == htons(ETH_P_IP)) {
1270 l4_proto_tmp = l3.v4->protocol;
1271 } else {
1272 return -EINVAL;
1273 }
1274
1275 *ol4_proto = l4_proto_tmp;
1276
1277 /* tunnel packet */
1278 if (!skb->encapsulation) {
1279 *il4_proto = 0;
1280 return 0;
1281 }
1282
1283 /* find inner header point */
1284 l3.hdr = skb_inner_network_header(skb);
1285 l4_hdr = skb_inner_transport_header(skb);
1286
1287 if (l3.v6->version == 6) {
1288 exthdr = l3.hdr + sizeof(*l3.v6);
1289 l4_proto_tmp = l3.v6->nexthdr;
1290 if (l4_hdr != exthdr)
1291 ipv6_skip_exthdr(skb, exthdr - skb->data,
1292 &l4_proto_tmp, &frag_off);
1293 } else if (l3.v4->version == 4) {
1294 l4_proto_tmp = l3.v4->protocol;
1295 }
1296
1297 *il4_proto = l4_proto_tmp;
1298
1299 return 0;
1300 }
1301
1302 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1303 * and it is udp packet, which has a dest port as the IANA assigned.
1304 * the hardware is expected to do the checksum offload, but the
1305 * hardware will not do the checksum offload when udp dest port is
1306 * 4789, 4790 or 6081.
1307 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1308 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1309 {
1310 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1311 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
1312 union l4_hdr_info l4;
1313
1314 /* device version above V3(include V3), the hardware can
1315 * do this checksum offload.
1316 */
1317 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1318 return false;
1319
1320 l4.hdr = skb_transport_header(skb);
1321
1322 if (!(!skb->encapsulation &&
1323 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1324 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1325 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1326 return false;
1327
1328 return true;
1329 }
1330
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1331 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1332 u32 *ol_type_vlan_len_msec)
1333 {
1334 u32 l2_len, l3_len, l4_len;
1335 unsigned char *il2_hdr;
1336 union l3_hdr_info l3;
1337 union l4_hdr_info l4;
1338
1339 l3.hdr = skb_network_header(skb);
1340 l4.hdr = skb_transport_header(skb);
1341
1342 /* compute OL2 header size, defined in 2 Bytes */
1343 l2_len = l3.hdr - skb->data;
1344 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1345
1346 /* compute OL3 header size, defined in 4 Bytes */
1347 l3_len = l4.hdr - l3.hdr;
1348 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1349
1350 il2_hdr = skb_inner_mac_header(skb);
1351 /* compute OL4 header size, defined in 4 Bytes */
1352 l4_len = il2_hdr - l4.hdr;
1353 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1354
1355 /* define outer network header type */
1356 if (skb->protocol == htons(ETH_P_IP)) {
1357 if (skb_is_gso(skb))
1358 hns3_set_field(*ol_type_vlan_len_msec,
1359 HNS3_TXD_OL3T_S,
1360 HNS3_OL3T_IPV4_CSUM);
1361 else
1362 hns3_set_field(*ol_type_vlan_len_msec,
1363 HNS3_TXD_OL3T_S,
1364 HNS3_OL3T_IPV4_NO_CSUM);
1365 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1366 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1367 HNS3_OL3T_IPV6);
1368 }
1369
1370 if (ol4_proto == IPPROTO_UDP)
1371 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1372 HNS3_TUN_MAC_IN_UDP);
1373 else if (ol4_proto == IPPROTO_GRE)
1374 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1375 HNS3_TUN_NVGRE);
1376 }
1377
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1378 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1379 u32 *type_cs_vlan_tso)
1380 {
1381 if (l3.v4->version == 4) {
1382 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1383 HNS3_L3T_IPV4);
1384
1385 /* the stack computes the IP header already, the only time we
1386 * need the hardware to recompute it is in the case of TSO.
1387 */
1388 if (skb_is_gso(skb))
1389 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1390 } else if (l3.v6->version == 6) {
1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1392 HNS3_L3T_IPV6);
1393 }
1394 }
1395
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1396 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1397 u32 l4_proto, u32 *type_cs_vlan_tso)
1398 {
1399 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1400 switch (l4_proto) {
1401 case IPPROTO_TCP:
1402 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1403 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1404 HNS3_L4T_TCP);
1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1406 l4.tcp->doff);
1407 break;
1408 case IPPROTO_UDP:
1409 if (hns3_tunnel_csum_bug(skb)) {
1410 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1411
1412 return ret ? ret : skb_checksum_help(skb);
1413 }
1414
1415 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1417 HNS3_L4T_UDP);
1418 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1419 (sizeof(struct udphdr) >> 2));
1420 break;
1421 case IPPROTO_SCTP:
1422 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1423 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1424 HNS3_L4T_SCTP);
1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1426 (sizeof(struct sctphdr) >> 2));
1427 break;
1428 default:
1429 /* drop the skb tunnel packet if hardware don't support,
1430 * because hardware can't calculate csum when TSO.
1431 */
1432 if (skb_is_gso(skb))
1433 return -EDOM;
1434
1435 /* the stack computes the IP header already,
1436 * driver calculate l4 checksum when not TSO.
1437 */
1438 return skb_checksum_help(skb);
1439 }
1440
1441 return 0;
1442 }
1443
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1444 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1445 u8 il4_proto, u32 *type_cs_vlan_tso,
1446 u32 *ol_type_vlan_len_msec)
1447 {
1448 unsigned char *l2_hdr = skb->data;
1449 u32 l4_proto = ol4_proto;
1450 union l4_hdr_info l4;
1451 union l3_hdr_info l3;
1452 u32 l2_len, l3_len;
1453
1454 l4.hdr = skb_transport_header(skb);
1455 l3.hdr = skb_network_header(skb);
1456
1457 /* handle encapsulation skb */
1458 if (skb->encapsulation) {
1459 /* If this is a not UDP/GRE encapsulation skb */
1460 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1461 /* drop the skb tunnel packet if hardware don't support,
1462 * because hardware can't calculate csum when TSO.
1463 */
1464 if (skb_is_gso(skb))
1465 return -EDOM;
1466
1467 /* the stack computes the IP header already,
1468 * driver calculate l4 checksum when not TSO.
1469 */
1470 return skb_checksum_help(skb);
1471 }
1472
1473 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1474
1475 /* switch to inner header */
1476 l2_hdr = skb_inner_mac_header(skb);
1477 l3.hdr = skb_inner_network_header(skb);
1478 l4.hdr = skb_inner_transport_header(skb);
1479 l4_proto = il4_proto;
1480 }
1481
1482 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1483
1484 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1485 l2_len = l3.hdr - l2_hdr;
1486 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1487
1488 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1489 l3_len = l4.hdr - l3.hdr;
1490 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1491
1492 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1493 }
1494
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1495 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1496 struct sk_buff *skb)
1497 {
1498 struct hnae3_handle *handle = tx_ring->tqp->handle;
1499 struct hnae3_ae_dev *ae_dev;
1500 struct vlan_ethhdr *vhdr;
1501 int rc;
1502
1503 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1504 skb_vlan_tag_present(skb)))
1505 return 0;
1506
1507 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1508 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1509 * will cause RAS error.
1510 */
1511 ae_dev = hns3_get_ae_dev(handle);
1512 if (unlikely(skb_vlan_tagged_multi(skb) &&
1513 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1514 handle->port_base_vlan_state ==
1515 HNAE3_PORT_BASE_VLAN_ENABLE))
1516 return -EINVAL;
1517
1518 if (skb->protocol == htons(ETH_P_8021Q) &&
1519 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1520 /* When HW VLAN acceleration is turned off, and the stack
1521 * sets the protocol to 802.1q, the driver just need to
1522 * set the protocol to the encapsulated ethertype.
1523 */
1524 skb->protocol = vlan_get_protocol(skb);
1525 return 0;
1526 }
1527
1528 if (skb_vlan_tag_present(skb)) {
1529 /* Based on hw strategy, use out_vtag in two layer tag case,
1530 * and use inner_vtag in one tag case.
1531 */
1532 if (skb->protocol == htons(ETH_P_8021Q) &&
1533 handle->port_base_vlan_state ==
1534 HNAE3_PORT_BASE_VLAN_DISABLE)
1535 rc = HNS3_OUTER_VLAN_TAG;
1536 else
1537 rc = HNS3_INNER_VLAN_TAG;
1538
1539 skb->protocol = vlan_get_protocol(skb);
1540 return rc;
1541 }
1542
1543 rc = skb_cow_head(skb, 0);
1544 if (unlikely(rc < 0))
1545 return rc;
1546
1547 vhdr = skb_vlan_eth_hdr(skb);
1548 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1549 & VLAN_PRIO_MASK);
1550
1551 skb->protocol = vlan_get_protocol(skb);
1552 return 0;
1553 }
1554
1555 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1556 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1557 {
1558 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1559
1560 /* Kindly note, due to backward compatibility of the TX descriptor,
1561 * HW checksum of the non-IP packets and GSO packets is handled at
1562 * different place in the following code
1563 */
1564 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1565 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1566 return false;
1567
1568 return true;
1569 }
1570
1571 struct hns3_desc_param {
1572 u32 paylen_ol4cs;
1573 u32 ol_type_vlan_len_msec;
1574 u32 type_cs_vlan_tso;
1575 u16 mss_hw_csum;
1576 u16 inner_vtag;
1577 u16 out_vtag;
1578 };
1579
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1580 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1581 {
1582 pa->paylen_ol4cs = skb->len;
1583 pa->ol_type_vlan_len_msec = 0;
1584 pa->type_cs_vlan_tso = 0;
1585 pa->mss_hw_csum = 0;
1586 pa->inner_vtag = 0;
1587 pa->out_vtag = 0;
1588 }
1589
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1590 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1591 struct sk_buff *skb,
1592 struct hns3_desc_param *param)
1593 {
1594 int ret;
1595
1596 ret = hns3_handle_vtags(ring, skb);
1597 if (unlikely(ret < 0)) {
1598 hns3_ring_stats_update(ring, tx_vlan_err);
1599 return ret;
1600 } else if (ret == HNS3_INNER_VLAN_TAG) {
1601 param->inner_vtag = skb_vlan_tag_get(skb);
1602 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1603 VLAN_PRIO_MASK;
1604 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1605 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1606 param->out_vtag = skb_vlan_tag_get(skb);
1607 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1608 VLAN_PRIO_MASK;
1609 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1610 1);
1611 }
1612 return 0;
1613 }
1614
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1615 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1616 struct sk_buff *skb,
1617 struct hns3_desc_cb *desc_cb,
1618 struct hns3_desc_param *param)
1619 {
1620 u8 ol4_proto, il4_proto;
1621 int ret;
1622
1623 if (hns3_check_hw_tx_csum(skb)) {
1624 /* set checksum start and offset, defined in 2 Bytes */
1625 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1626 skb_checksum_start_offset(skb) >> 1);
1627 hns3_set_field(param->ol_type_vlan_len_msec,
1628 HNS3_TXD_CSUM_OFFSET_S,
1629 skb->csum_offset >> 1);
1630 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1631 return 0;
1632 }
1633
1634 skb_reset_mac_len(skb);
1635
1636 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1637 if (unlikely(ret < 0)) {
1638 hns3_ring_stats_update(ring, tx_l4_proto_err);
1639 return ret;
1640 }
1641
1642 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1643 ¶m->type_cs_vlan_tso,
1644 ¶m->ol_type_vlan_len_msec);
1645 if (unlikely(ret < 0)) {
1646 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1647 return ret;
1648 }
1649
1650 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1651 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1652 if (unlikely(ret < 0)) {
1653 hns3_ring_stats_update(ring, tx_tso_err);
1654 return ret;
1655 }
1656 return 0;
1657 }
1658
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1659 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1660 struct sk_buff *skb, struct hns3_desc *desc,
1661 struct hns3_desc_cb *desc_cb)
1662 {
1663 struct hns3_desc_param param;
1664 int ret;
1665
1666 hns3_init_desc_data(skb, ¶m);
1667 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1668 if (unlikely(ret < 0))
1669 return ret;
1670
1671 desc_cb->send_bytes = skb->len;
1672
1673 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1674 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1675 if (ret)
1676 return ret;
1677 }
1678
1679 /* Set txbd */
1680 desc->tx.ol_type_vlan_len_msec =
1681 cpu_to_le32(param.ol_type_vlan_len_msec);
1682 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1683 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1684 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1685 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1686 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1687
1688 return 0;
1689 }
1690
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1691 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1692 unsigned int size)
1693 {
1694 #define HNS3_LIKELY_BD_NUM 1
1695
1696 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1697 unsigned int frag_buf_num, k;
1698 int sizeoflast;
1699
1700 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1701 desc->addr = cpu_to_le64(dma);
1702 desc->tx.send_size = cpu_to_le16(size);
1703 desc->tx.bdtp_fe_sc_vld_ra_ri =
1704 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1705
1706 trace_hns3_tx_desc(ring, ring->next_to_use);
1707 ring_ptr_move_fw(ring, next_to_use);
1708 return HNS3_LIKELY_BD_NUM;
1709 }
1710
1711 frag_buf_num = hns3_tx_bd_count(size);
1712 sizeoflast = size % HNS3_MAX_BD_SIZE;
1713 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1714
1715 /* When frag size is bigger than hardware limit, split this frag */
1716 for (k = 0; k < frag_buf_num; k++) {
1717 /* now, fill the descriptor */
1718 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1719 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1720 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1721 desc->tx.bdtp_fe_sc_vld_ra_ri =
1722 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1723
1724 trace_hns3_tx_desc(ring, ring->next_to_use);
1725 /* move ring pointer to next */
1726 ring_ptr_move_fw(ring, next_to_use);
1727
1728 desc = &ring->desc[ring->next_to_use];
1729 }
1730
1731 return frag_buf_num;
1732 }
1733
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1734 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1735 unsigned int type)
1736 {
1737 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1738 struct device *dev = ring_to_dev(ring);
1739 unsigned int size;
1740 dma_addr_t dma;
1741
1742 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1743 struct sk_buff *skb = (struct sk_buff *)priv;
1744
1745 size = skb_headlen(skb);
1746 if (!size)
1747 return 0;
1748
1749 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1750 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1751 /* Head data has been filled in hns3_handle_tx_bounce(),
1752 * just return 0 here.
1753 */
1754 return 0;
1755 } else {
1756 skb_frag_t *frag = (skb_frag_t *)priv;
1757
1758 size = skb_frag_size(frag);
1759 if (!size)
1760 return 0;
1761
1762 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1763 }
1764
1765 if (unlikely(dma_mapping_error(dev, dma))) {
1766 hns3_ring_stats_update(ring, sw_err_cnt);
1767 return -ENOMEM;
1768 }
1769
1770 desc_cb->priv = priv;
1771 desc_cb->length = size;
1772 desc_cb->dma = dma;
1773 desc_cb->type = type;
1774
1775 return hns3_fill_desc(ring, dma, size);
1776 }
1777
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1778 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1779 unsigned int bd_num)
1780 {
1781 unsigned int size;
1782 int i;
1783
1784 size = skb_headlen(skb);
1785 while (size > HNS3_MAX_BD_SIZE) {
1786 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1787 size -= HNS3_MAX_BD_SIZE;
1788
1789 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1790 return bd_num;
1791 }
1792
1793 if (size) {
1794 bd_size[bd_num++] = size;
1795 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1796 return bd_num;
1797 }
1798
1799 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1800 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1801 size = skb_frag_size(frag);
1802 if (!size)
1803 continue;
1804
1805 while (size > HNS3_MAX_BD_SIZE) {
1806 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1807 size -= HNS3_MAX_BD_SIZE;
1808
1809 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1810 return bd_num;
1811 }
1812
1813 bd_size[bd_num++] = size;
1814 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1815 return bd_num;
1816 }
1817
1818 return bd_num;
1819 }
1820
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1821 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1822 u8 max_non_tso_bd_num, unsigned int bd_num,
1823 unsigned int recursion_level)
1824 {
1825 #define HNS3_MAX_RECURSION_LEVEL 24
1826
1827 struct sk_buff *frag_skb;
1828
1829 /* If the total len is within the max bd limit */
1830 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1831 !skb_has_frag_list(skb) &&
1832 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1833 return skb_shinfo(skb)->nr_frags + 1U;
1834
1835 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1836 return UINT_MAX;
1837
1838 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1839 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1840 return bd_num;
1841
1842 skb_walk_frags(skb, frag_skb) {
1843 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1844 bd_num, recursion_level + 1);
1845 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1846 return bd_num;
1847 }
1848
1849 return bd_num;
1850 }
1851
hns3_gso_hdr_len(struct sk_buff * skb)1852 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1853 {
1854 if (!skb->encapsulation)
1855 return skb_tcp_all_headers(skb);
1856
1857 return skb_inner_tcp_all_headers(skb);
1858 }
1859
1860 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1861 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1862 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1863 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1864 * than MSS except the last max_non_tso_bd_num - 1 frags.
1865 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1866 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1867 unsigned int bd_num, u8 max_non_tso_bd_num)
1868 {
1869 unsigned int tot_len = 0;
1870 unsigned int i;
1871
1872 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1873 tot_len += bd_size[i];
1874
1875 /* ensure the first max_non_tso_bd_num frags is greater than
1876 * mss + header
1877 */
1878 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1879 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1880 return true;
1881
1882 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1883 * than mss except the last one.
1884 */
1885 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1886 tot_len -= bd_size[i];
1887 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1888
1889 if (tot_len < skb_shinfo(skb)->gso_size)
1890 return true;
1891 }
1892
1893 return false;
1894 }
1895
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1896 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1897 {
1898 u32 i;
1899
1900 for (i = 0; i < MAX_SKB_FRAGS; i++)
1901 size[i] = skb_frag_size(&shinfo->frags[i]);
1902 }
1903
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1904 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1905 struct sk_buff *skb,
1906 unsigned int bd_num)
1907 {
1908 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1909 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1910 */
1911 if (bd_num == UINT_MAX) {
1912 hns3_ring_stats_update(ring, over_max_recursion);
1913 return -ENOMEM;
1914 }
1915
1916 /* The skb->len has exceeded the hw limitation, linearization
1917 * will not help.
1918 */
1919 if (skb->len > HNS3_MAX_TSO_SIZE ||
1920 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1921 hns3_ring_stats_update(ring, hw_limitation);
1922 return -ENOMEM;
1923 }
1924
1925 if (__skb_linearize(skb)) {
1926 hns3_ring_stats_update(ring, sw_err_cnt);
1927 return -ENOMEM;
1928 }
1929
1930 return 0;
1931 }
1932
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1933 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1934 struct net_device *netdev,
1935 struct sk_buff *skb)
1936 {
1937 struct hns3_nic_priv *priv = netdev_priv(netdev);
1938 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1939 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1940 unsigned int bd_num;
1941
1942 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1943 if (unlikely(bd_num > max_non_tso_bd_num)) {
1944 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1945 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1946 max_non_tso_bd_num)) {
1947 trace_hns3_over_max_bd(skb);
1948 goto out;
1949 }
1950
1951 if (hns3_skb_linearize(ring, skb, bd_num))
1952 return -ENOMEM;
1953
1954 bd_num = hns3_tx_bd_count(skb->len);
1955
1956 hns3_ring_stats_update(ring, tx_copy);
1957 }
1958
1959 out:
1960 if (likely(ring_space(ring) >= bd_num))
1961 return bd_num;
1962
1963 netif_stop_subqueue(netdev, ring->queue_index);
1964 smp_mb(); /* Memory barrier before checking ring_space */
1965
1966 /* Start queue in case hns3_clean_tx_ring has just made room
1967 * available and has not seen the queue stopped state performed
1968 * by netif_stop_subqueue above.
1969 */
1970 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1971 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1972 netif_start_subqueue(netdev, ring->queue_index);
1973 return bd_num;
1974 }
1975
1976 hns3_ring_stats_update(ring, tx_busy);
1977
1978 return -EBUSY;
1979 }
1980
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1981 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1982 {
1983 struct device *dev = ring_to_dev(ring);
1984 unsigned int i;
1985
1986 for (i = 0; i < ring->desc_num; i++) {
1987 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1988 struct hns3_desc_cb *desc_cb;
1989
1990 memset(desc, 0, sizeof(*desc));
1991
1992 /* check if this is where we started */
1993 if (ring->next_to_use == next_to_use_orig)
1994 break;
1995
1996 /* rollback one */
1997 ring_ptr_move_bw(ring, next_to_use);
1998
1999 desc_cb = &ring->desc_cb[ring->next_to_use];
2000
2001 if (!desc_cb->dma)
2002 continue;
2003
2004 /* unmap the descriptor dma address */
2005 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2006 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2007 DMA_TO_DEVICE);
2008 else if (desc_cb->type &
2009 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2010 hns3_tx_spare_rollback(ring, desc_cb->length);
2011 else if (desc_cb->length)
2012 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2013 DMA_TO_DEVICE);
2014
2015 desc_cb->length = 0;
2016 desc_cb->dma = 0;
2017 desc_cb->type = DESC_TYPE_UNKNOWN;
2018 }
2019 }
2020
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2021 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2022 struct sk_buff *skb, unsigned int type)
2023 {
2024 struct sk_buff *frag_skb;
2025 int i, ret, bd_num = 0;
2026
2027 ret = hns3_map_and_fill_desc(ring, skb, type);
2028 if (unlikely(ret < 0))
2029 return ret;
2030
2031 bd_num += ret;
2032
2033 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2034 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2035
2036 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2037 if (unlikely(ret < 0))
2038 return ret;
2039
2040 bd_num += ret;
2041 }
2042
2043 skb_walk_frags(skb, frag_skb) {
2044 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2045 DESC_TYPE_FRAGLIST_SKB);
2046 if (unlikely(ret < 0))
2047 return ret;
2048
2049 bd_num += ret;
2050 }
2051
2052 return bd_num;
2053 }
2054
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2055 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2056 {
2057 #define HNS3_BYTES_PER_64BIT 8
2058
2059 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2060 int offset = 0;
2061
2062 /* make sure everything is visible to device before
2063 * excuting tx push or updating doorbell
2064 */
2065 dma_wmb();
2066
2067 do {
2068 int idx = (ring->next_to_use - num + ring->desc_num) %
2069 ring->desc_num;
2070
2071 u64_stats_update_begin(&ring->syncp);
2072 ring->stats.tx_push++;
2073 u64_stats_update_end(&ring->syncp);
2074 memcpy(&desc[offset], &ring->desc[idx],
2075 sizeof(struct hns3_desc));
2076 offset++;
2077 } while (--num);
2078
2079 __iowrite64_copy(ring->tqp->mem_base, desc,
2080 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2081 HNS3_BYTES_PER_64BIT);
2082 }
2083
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2084 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2085 {
2086 #define HNS3_MEM_DOORBELL_OFFSET 64
2087
2088 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2089
2090 /* make sure everything is visible to device before
2091 * excuting tx push or updating doorbell
2092 */
2093 dma_wmb();
2094
2095 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2096 &bd_num, 1);
2097 u64_stats_update_begin(&ring->syncp);
2098 ring->stats.tx_mem_doorbell += ring->pending_buf;
2099 u64_stats_update_end(&ring->syncp);
2100 }
2101
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2102 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2103 bool doorbell)
2104 {
2105 struct net_device *netdev = ring_to_netdev(ring);
2106 struct hns3_nic_priv *priv = netdev_priv(netdev);
2107
2108 /* when tx push is enabled, the packet whose number of BD below
2109 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2110 */
2111 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2112 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2113 /* This smp_store_release() pairs with smp_load_acquire() in
2114 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2115 * is updated.
2116 */
2117 smp_store_release(&ring->last_to_use, ring->next_to_use);
2118 hns3_tx_push_bd(ring, num);
2119 return;
2120 }
2121
2122 ring->pending_buf += num;
2123
2124 if (!doorbell) {
2125 hns3_ring_stats_update(ring, tx_more);
2126 return;
2127 }
2128
2129 /* This smp_store_release() pairs with smp_load_acquire() in
2130 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2131 */
2132 smp_store_release(&ring->last_to_use, ring->next_to_use);
2133
2134 if (ring->tqp->mem_base)
2135 hns3_tx_mem_doorbell(ring);
2136 else
2137 writel(ring->pending_buf,
2138 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2139
2140 ring->pending_buf = 0;
2141 }
2142
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2143 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2144 struct hns3_desc *desc)
2145 {
2146 struct hnae3_handle *h = hns3_get_handle(netdev);
2147
2148 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2149 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2150 return;
2151
2152 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2153 }
2154
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2155 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2156 struct sk_buff *skb)
2157 {
2158 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2159 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2160 unsigned int size = skb_headlen(skb);
2161 dma_addr_t dma;
2162 int bd_num = 0;
2163 u32 cb_len;
2164 void *buf;
2165 int ret;
2166
2167 if (skb->len <= ring->tx_copybreak) {
2168 size = skb->len;
2169 type = DESC_TYPE_BOUNCE_ALL;
2170 }
2171
2172 /* hns3_can_use_tx_bounce() is called to ensure the below
2173 * function can always return the tx buffer.
2174 */
2175 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2176
2177 ret = skb_copy_bits(skb, 0, buf, size);
2178 if (unlikely(ret < 0)) {
2179 hns3_tx_spare_rollback(ring, cb_len);
2180 hns3_ring_stats_update(ring, copy_bits_err);
2181 return ret;
2182 }
2183
2184 desc_cb->priv = skb;
2185 desc_cb->length = cb_len;
2186 desc_cb->dma = dma;
2187 desc_cb->type = type;
2188
2189 bd_num += hns3_fill_desc(ring, dma, size);
2190
2191 if (type == DESC_TYPE_BOUNCE_HEAD) {
2192 ret = hns3_fill_skb_to_desc(ring, skb,
2193 DESC_TYPE_BOUNCE_HEAD);
2194 if (unlikely(ret < 0))
2195 return ret;
2196
2197 bd_num += ret;
2198 }
2199
2200 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2201 DMA_TO_DEVICE);
2202
2203 hns3_ring_stats_update(ring, tx_bounce);
2204
2205 return bd_num;
2206 }
2207
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2208 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2209 struct sk_buff *skb)
2210 {
2211 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2212 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2213 struct sg_table *sgt;
2214 int bd_num = 0;
2215 dma_addr_t dma;
2216 u32 cb_len, i;
2217 int nents;
2218
2219 if (skb_has_frag_list(skb))
2220 nfrag = HNS3_MAX_TSO_BD_NUM;
2221
2222 /* hns3_can_use_tx_sgl() is called to ensure the below
2223 * function can always return the tx buffer.
2224 */
2225 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2226 &dma, &cb_len);
2227
2228 /* scatterlist follows by the sg table */
2229 sgt->sgl = (struct scatterlist *)(sgt + 1);
2230 sg_init_table(sgt->sgl, nfrag);
2231 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2232 if (unlikely(nents < 0)) {
2233 hns3_tx_spare_rollback(ring, cb_len);
2234 hns3_ring_stats_update(ring, skb2sgl_err);
2235 return -ENOMEM;
2236 }
2237
2238 sgt->orig_nents = nents;
2239 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2240 DMA_TO_DEVICE);
2241 if (unlikely(!sgt->nents)) {
2242 hns3_tx_spare_rollback(ring, cb_len);
2243 hns3_ring_stats_update(ring, map_sg_err);
2244 return -ENOMEM;
2245 }
2246
2247 desc_cb->priv = skb;
2248 desc_cb->length = cb_len;
2249 desc_cb->dma = dma;
2250 desc_cb->type = DESC_TYPE_SGL_SKB;
2251
2252 for (i = 0; i < sgt->nents; i++)
2253 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2254 sg_dma_len(sgt->sgl + i));
2255 hns3_ring_stats_update(ring, tx_sgl);
2256
2257 return bd_num;
2258 }
2259
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2260 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2261 struct sk_buff *skb)
2262 {
2263 u32 space;
2264
2265 if (!ring->tx_spare)
2266 goto out;
2267
2268 space = hns3_tx_spare_space(ring);
2269
2270 if (hns3_can_use_tx_sgl(ring, skb, space))
2271 return hns3_handle_tx_sgl(ring, skb);
2272
2273 if (hns3_can_use_tx_bounce(ring, skb, space))
2274 return hns3_handle_tx_bounce(ring, skb);
2275
2276 out:
2277 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2278 }
2279
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2280 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2281 struct sk_buff *skb,
2282 struct hns3_desc_cb *desc_cb,
2283 int next_to_use_head)
2284 {
2285 int ret;
2286
2287 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2288 desc_cb);
2289 if (unlikely(ret < 0))
2290 goto fill_err;
2291
2292 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2293 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2294 * need to be notified to the hw.
2295 */
2296 ret = hns3_handle_desc_filling(ring, skb);
2297 if (likely(ret > 0))
2298 return ret;
2299
2300 fill_err:
2301 hns3_clear_desc(ring, next_to_use_head);
2302 return ret;
2303 }
2304
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2305 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2306 {
2307 struct hns3_nic_priv *priv = netdev_priv(netdev);
2308 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2309 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2310 struct netdev_queue *dev_queue;
2311 int pre_ntu, ret;
2312 bool doorbell;
2313
2314 /* Hardware can only handle short frames above 32 bytes */
2315 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2316 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2317
2318 hns3_ring_stats_update(ring, sw_err_cnt);
2319
2320 return NETDEV_TX_OK;
2321 }
2322
2323 /* Prefetch the data used later */
2324 prefetch(skb->data);
2325
2326 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2327 if (unlikely(ret <= 0)) {
2328 if (ret == -EBUSY) {
2329 hns3_tx_doorbell(ring, 0, true);
2330 return NETDEV_TX_BUSY;
2331 }
2332
2333 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2334 goto out_err_tx_ok;
2335 }
2336
2337 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2338 if (unlikely(ret <= 0))
2339 goto out_err_tx_ok;
2340
2341 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2342 (ring->desc_num - 1);
2343
2344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2345 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2346
2347 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2348 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2349 trace_hns3_tx_desc(ring, pre_ntu);
2350
2351 skb_tx_timestamp(skb);
2352
2353 /* Complete translate all packets */
2354 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2355 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2356 netdev_xmit_more());
2357 hns3_tx_doorbell(ring, ret, doorbell);
2358
2359 return NETDEV_TX_OK;
2360
2361 out_err_tx_ok:
2362 dev_kfree_skb_any(skb);
2363 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2364 return NETDEV_TX_OK;
2365 }
2366
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2367 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2368 {
2369 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2370 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2371 struct hnae3_handle *h = hns3_get_handle(netdev);
2372 struct sockaddr *mac_addr = p;
2373 int ret;
2374
2375 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2376 return -EADDRNOTAVAIL;
2377
2378 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2379 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2380 netdev_info(netdev, "already using mac address %s\n",
2381 format_mac_addr_sa);
2382 return 0;
2383 }
2384
2385 /* For VF device, if there is a perm_addr, then the user will not
2386 * be allowed to change the address.
2387 */
2388 if (!hns3_is_phys_func(h->pdev) &&
2389 !is_zero_ether_addr(netdev->perm_addr)) {
2390 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2391 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2392 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2393 format_mac_addr_perm, format_mac_addr_sa);
2394 return -EPERM;
2395 }
2396
2397 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2398 if (ret) {
2399 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2400 return ret;
2401 }
2402
2403 eth_hw_addr_set(netdev, mac_addr->sa_data);
2404
2405 return 0;
2406 }
2407
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2408 static int hns3_nic_do_ioctl(struct net_device *netdev,
2409 struct ifreq *ifr, int cmd)
2410 {
2411 struct hnae3_handle *h = hns3_get_handle(netdev);
2412
2413 if (!netif_running(netdev))
2414 return -EINVAL;
2415
2416 if (!h->ae_algo->ops->do_ioctl)
2417 return -EOPNOTSUPP;
2418
2419 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2420 }
2421
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2422 static int hns3_nic_set_features(struct net_device *netdev,
2423 netdev_features_t features)
2424 {
2425 netdev_features_t changed = netdev->features ^ features;
2426 struct hns3_nic_priv *priv = netdev_priv(netdev);
2427 struct hnae3_handle *h = priv->ae_handle;
2428 bool enable;
2429 int ret;
2430
2431 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2432 enable = !!(features & NETIF_F_GRO_HW);
2433 ret = h->ae_algo->ops->set_gro_en(h, enable);
2434 if (ret)
2435 return ret;
2436 }
2437
2438 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2439 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2440 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2441 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2442 if (ret)
2443 return ret;
2444 }
2445
2446 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2447 enable = !!(features & NETIF_F_NTUPLE);
2448 h->ae_algo->ops->enable_fd(h, enable);
2449 }
2450
2451 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2452 h->ae_algo->ops->cls_flower_active(h)) {
2453 netdev_err(netdev,
2454 "there are offloaded TC filters active, cannot disable HW TC offload\n");
2455 return -EINVAL;
2456 }
2457
2458 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2459 h->ae_algo->ops->enable_vlan_filter) {
2460 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2461 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2462 if (ret)
2463 return ret;
2464 }
2465
2466 return 0;
2467 }
2468
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2469 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2470 struct net_device *dev,
2471 netdev_features_t features)
2472 {
2473 #define HNS3_MAX_HDR_LEN 480U
2474 #define HNS3_MAX_L4_HDR_LEN 60U
2475
2476 size_t len;
2477
2478 if (skb->ip_summed != CHECKSUM_PARTIAL)
2479 return features;
2480
2481 if (skb->encapsulation)
2482 len = skb_inner_transport_offset(skb);
2483 else
2484 len = skb_transport_offset(skb);
2485
2486 /* Assume L4 is 60 byte as TCP is the only protocol with a
2487 * a flexible value, and it's max len is 60 bytes.
2488 */
2489 len += HNS3_MAX_L4_HDR_LEN;
2490
2491 /* Hardware only supports checksum on the skb with a max header
2492 * len of 480 bytes.
2493 */
2494 if (len > HNS3_MAX_HDR_LEN)
2495 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2496
2497 return features;
2498 }
2499
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2500 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2501 struct hns3_enet_ring *ring, bool is_tx)
2502 {
2503 unsigned int start;
2504
2505 do {
2506 start = u64_stats_fetch_begin(&ring->syncp);
2507 if (is_tx) {
2508 stats->tx_bytes += ring->stats.tx_bytes;
2509 stats->tx_packets += ring->stats.tx_pkts;
2510 stats->tx_dropped += ring->stats.sw_err_cnt;
2511 stats->tx_dropped += ring->stats.tx_vlan_err;
2512 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2513 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2514 stats->tx_dropped += ring->stats.tx_tso_err;
2515 stats->tx_dropped += ring->stats.over_max_recursion;
2516 stats->tx_dropped += ring->stats.hw_limitation;
2517 stats->tx_dropped += ring->stats.copy_bits_err;
2518 stats->tx_dropped += ring->stats.skb2sgl_err;
2519 stats->tx_dropped += ring->stats.map_sg_err;
2520 stats->tx_errors += ring->stats.sw_err_cnt;
2521 stats->tx_errors += ring->stats.tx_vlan_err;
2522 stats->tx_errors += ring->stats.tx_l4_proto_err;
2523 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2524 stats->tx_errors += ring->stats.tx_tso_err;
2525 stats->tx_errors += ring->stats.over_max_recursion;
2526 stats->tx_errors += ring->stats.hw_limitation;
2527 stats->tx_errors += ring->stats.copy_bits_err;
2528 stats->tx_errors += ring->stats.skb2sgl_err;
2529 stats->tx_errors += ring->stats.map_sg_err;
2530 } else {
2531 stats->rx_bytes += ring->stats.rx_bytes;
2532 stats->rx_packets += ring->stats.rx_pkts;
2533 stats->rx_dropped += ring->stats.l2_err;
2534 stats->rx_errors += ring->stats.l2_err;
2535 stats->rx_errors += ring->stats.l3l4_csum_err;
2536 stats->rx_crc_errors += ring->stats.l2_err;
2537 stats->multicast += ring->stats.rx_multicast;
2538 stats->rx_length_errors += ring->stats.err_pkt_len;
2539 }
2540 } while (u64_stats_fetch_retry(&ring->syncp, start));
2541 }
2542
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2543 static void hns3_nic_get_stats64(struct net_device *netdev,
2544 struct rtnl_link_stats64 *stats)
2545 {
2546 struct hns3_nic_priv *priv = netdev_priv(netdev);
2547 int queue_num = priv->ae_handle->kinfo.num_tqps;
2548 struct hnae3_handle *handle = priv->ae_handle;
2549 struct rtnl_link_stats64 ring_total_stats;
2550 struct hns3_enet_ring *ring;
2551 int idx;
2552
2553 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2554 return;
2555
2556 handle->ae_algo->ops->update_stats(handle);
2557
2558 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2559 for (idx = 0; idx < queue_num; idx++) {
2560 /* fetch the tx stats */
2561 ring = &priv->ring[idx];
2562 hns3_fetch_stats(&ring_total_stats, ring, true);
2563
2564 /* fetch the rx stats */
2565 ring = &priv->ring[idx + queue_num];
2566 hns3_fetch_stats(&ring_total_stats, ring, false);
2567 }
2568
2569 stats->tx_bytes = ring_total_stats.tx_bytes;
2570 stats->tx_packets = ring_total_stats.tx_packets;
2571 stats->rx_bytes = ring_total_stats.rx_bytes;
2572 stats->rx_packets = ring_total_stats.rx_packets;
2573
2574 stats->rx_errors = ring_total_stats.rx_errors;
2575 stats->multicast = ring_total_stats.multicast;
2576 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2577 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2578 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2579
2580 stats->tx_errors = ring_total_stats.tx_errors;
2581 stats->rx_dropped = ring_total_stats.rx_dropped;
2582 stats->tx_dropped = ring_total_stats.tx_dropped;
2583 stats->collisions = netdev->stats.collisions;
2584 stats->rx_over_errors = netdev->stats.rx_over_errors;
2585 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2586 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2587 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2588 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2589 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2590 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2591 stats->tx_window_errors = netdev->stats.tx_window_errors;
2592 stats->rx_compressed = netdev->stats.rx_compressed;
2593 stats->tx_compressed = netdev->stats.tx_compressed;
2594 }
2595
hns3_setup_tc(struct net_device * netdev,void * type_data)2596 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2597 {
2598 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2599 struct hnae3_knic_private_info *kinfo;
2600 u8 tc = mqprio_qopt->qopt.num_tc;
2601 u16 mode = mqprio_qopt->mode;
2602 u8 hw = mqprio_qopt->qopt.hw;
2603 struct hnae3_handle *h;
2604
2605 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2606 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2607 return -EOPNOTSUPP;
2608
2609 if (tc > HNAE3_MAX_TC)
2610 return -EINVAL;
2611
2612 if (!netdev)
2613 return -EINVAL;
2614
2615 h = hns3_get_handle(netdev);
2616 kinfo = &h->kinfo;
2617
2618 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2619
2620 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2621 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2622 }
2623
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2624 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2625 struct flow_cls_offload *flow)
2626 {
2627 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2628 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2629
2630 switch (flow->command) {
2631 case FLOW_CLS_REPLACE:
2632 if (h->ae_algo->ops->add_cls_flower)
2633 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2634 break;
2635 case FLOW_CLS_DESTROY:
2636 if (h->ae_algo->ops->del_cls_flower)
2637 return h->ae_algo->ops->del_cls_flower(h, flow);
2638 break;
2639 default:
2640 break;
2641 }
2642
2643 return -EOPNOTSUPP;
2644 }
2645
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2646 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2647 void *cb_priv)
2648 {
2649 struct hns3_nic_priv *priv = cb_priv;
2650
2651 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2652 return -EOPNOTSUPP;
2653
2654 switch (type) {
2655 case TC_SETUP_CLSFLOWER:
2656 return hns3_setup_tc_cls_flower(priv, type_data);
2657 default:
2658 return -EOPNOTSUPP;
2659 }
2660 }
2661
2662 static LIST_HEAD(hns3_block_cb_list);
2663
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2664 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2665 void *type_data)
2666 {
2667 struct hns3_nic_priv *priv = netdev_priv(dev);
2668 int ret;
2669
2670 switch (type) {
2671 case TC_SETUP_QDISC_MQPRIO:
2672 ret = hns3_setup_tc(dev, type_data);
2673 break;
2674 case TC_SETUP_BLOCK:
2675 ret = flow_block_cb_setup_simple(type_data,
2676 &hns3_block_cb_list,
2677 hns3_setup_tc_block_cb,
2678 priv, priv, true);
2679 break;
2680 default:
2681 return -EOPNOTSUPP;
2682 }
2683
2684 return ret;
2685 }
2686
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2687 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2688 __be16 proto, u16 vid)
2689 {
2690 struct hnae3_handle *h = hns3_get_handle(netdev);
2691 int ret = -EIO;
2692
2693 if (h->ae_algo->ops->set_vlan_filter)
2694 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2695
2696 return ret;
2697 }
2698
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2699 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2700 __be16 proto, u16 vid)
2701 {
2702 struct hnae3_handle *h = hns3_get_handle(netdev);
2703 int ret = -EIO;
2704
2705 if (h->ae_algo->ops->set_vlan_filter)
2706 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2707
2708 return ret;
2709 }
2710
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2711 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2712 u8 qos, __be16 vlan_proto)
2713 {
2714 struct hnae3_handle *h = hns3_get_handle(netdev);
2715 int ret = -EIO;
2716
2717 netif_dbg(h, drv, netdev,
2718 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2719 vf, vlan, qos, ntohs(vlan_proto));
2720
2721 if (h->ae_algo->ops->set_vf_vlan_filter)
2722 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2723 qos, vlan_proto);
2724
2725 return ret;
2726 }
2727
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2728 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2729 {
2730 struct hnae3_handle *handle = hns3_get_handle(netdev);
2731
2732 if (hns3_nic_resetting(netdev))
2733 return -EBUSY;
2734
2735 if (!handle->ae_algo->ops->set_vf_spoofchk)
2736 return -EOPNOTSUPP;
2737
2738 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2739 }
2740
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2741 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2742 {
2743 struct hnae3_handle *handle = hns3_get_handle(netdev);
2744
2745 if (!handle->ae_algo->ops->set_vf_trust)
2746 return -EOPNOTSUPP;
2747
2748 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2749 }
2750
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2751 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2752 {
2753 struct hnae3_handle *h = hns3_get_handle(netdev);
2754 int ret;
2755
2756 if (hns3_nic_resetting(netdev))
2757 return -EBUSY;
2758
2759 if (!h->ae_algo->ops->set_mtu)
2760 return -EOPNOTSUPP;
2761
2762 netif_dbg(h, drv, netdev,
2763 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2764
2765 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2766 if (ret)
2767 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2768 ret);
2769 else
2770 WRITE_ONCE(netdev->mtu, new_mtu);
2771
2772 return ret;
2773 }
2774
hns3_get_timeout_queue(struct net_device * ndev)2775 static int hns3_get_timeout_queue(struct net_device *ndev)
2776 {
2777 unsigned int i;
2778
2779 /* Find the stopped queue the same way the stack does */
2780 for (i = 0; i < ndev->num_tx_queues; i++) {
2781 struct netdev_queue *q;
2782 unsigned long trans_start;
2783
2784 q = netdev_get_tx_queue(ndev, i);
2785 trans_start = READ_ONCE(q->trans_start);
2786 if (netif_xmit_stopped(q) &&
2787 time_after(jiffies,
2788 (trans_start + ndev->watchdog_timeo))) {
2789 #ifdef CONFIG_BQL
2790 struct dql *dql = &q->dql;
2791
2792 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2793 dql->last_obj_cnt, dql->num_queued,
2794 dql->adj_limit, dql->num_completed);
2795 #endif
2796 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2797 q->state,
2798 jiffies_to_msecs(jiffies - trans_start));
2799 break;
2800 }
2801 }
2802
2803 return i;
2804 }
2805
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2806 static void hns3_dump_queue_stats(struct net_device *ndev,
2807 struct hns3_enet_ring *tx_ring,
2808 int timeout_queue)
2809 {
2810 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2811 struct hns3_nic_priv *priv = netdev_priv(ndev);
2812
2813 netdev_info(ndev,
2814 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2815 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2816 tx_ring->next_to_clean, napi->state);
2817
2818 netdev_info(ndev,
2819 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2820 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2821 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2822
2823 netdev_info(ndev,
2824 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2825 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2826 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2827
2828 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2829 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2830 }
2831
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2832 static void hns3_dump_queue_reg(struct net_device *ndev,
2833 struct hns3_enet_ring *tx_ring)
2834 {
2835 netdev_info(ndev,
2836 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2837 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2838 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2839 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2840 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2841 readl(tx_ring->tqp_vector->mask_addr));
2842 netdev_info(ndev,
2843 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2844 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2845 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2846 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2847 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2848 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2849 hns3_tqp_read_reg(tx_ring,
2850 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2851 }
2852
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2853 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2854 {
2855 struct hns3_nic_priv *priv = netdev_priv(ndev);
2856 struct hnae3_handle *h = hns3_get_handle(ndev);
2857 struct hns3_enet_ring *tx_ring;
2858 u32 timeout_queue;
2859
2860 timeout_queue = hns3_get_timeout_queue(ndev);
2861 if (timeout_queue >= ndev->num_tx_queues) {
2862 netdev_info(ndev,
2863 "no netdev TX timeout queue found, timeout count: %llu\n",
2864 priv->tx_timeout_count);
2865 return false;
2866 }
2867
2868 priv->tx_timeout_count++;
2869
2870 tx_ring = &priv->ring[timeout_queue];
2871 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2872
2873 /* When mac received many pause frames continuous, it's unable to send
2874 * packets, which may cause tx timeout
2875 */
2876 if (h->ae_algo->ops->get_mac_stats) {
2877 struct hns3_mac_stats mac_stats;
2878
2879 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2880 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2881 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2882 }
2883
2884 hns3_dump_queue_reg(ndev, tx_ring);
2885
2886 return true;
2887 }
2888
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2889 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2890 {
2891 struct hns3_nic_priv *priv = netdev_priv(ndev);
2892 struct hnae3_handle *h = priv->ae_handle;
2893
2894 if (!hns3_get_tx_timeo_queue_info(ndev))
2895 return;
2896
2897 /* request the reset, and let the hclge to determine
2898 * which reset level should be done
2899 */
2900 if (h->ae_algo->ops->reset_event)
2901 h->ae_algo->ops->reset_event(h->pdev, h);
2902 }
2903
2904 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2905 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2906 u16 rxq_index, u32 flow_id)
2907 {
2908 struct hnae3_handle *h = hns3_get_handle(dev);
2909 struct flow_keys fkeys;
2910
2911 if (!h->ae_algo->ops->add_arfs_entry)
2912 return -EOPNOTSUPP;
2913
2914 if (skb->encapsulation)
2915 return -EPROTONOSUPPORT;
2916
2917 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2918 return -EPROTONOSUPPORT;
2919
2920 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2921 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2922 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2923 fkeys.basic.ip_proto != IPPROTO_UDP))
2924 return -EPROTONOSUPPORT;
2925
2926 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2927 }
2928 #endif
2929
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2930 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2931 struct ifla_vf_info *ivf)
2932 {
2933 struct hnae3_handle *h = hns3_get_handle(ndev);
2934
2935 if (!h->ae_algo->ops->get_vf_config)
2936 return -EOPNOTSUPP;
2937
2938 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2939 }
2940
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2941 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2942 int link_state)
2943 {
2944 struct hnae3_handle *h = hns3_get_handle(ndev);
2945
2946 if (!h->ae_algo->ops->set_vf_link_state)
2947 return -EOPNOTSUPP;
2948
2949 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2950 }
2951
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2952 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2953 int min_tx_rate, int max_tx_rate)
2954 {
2955 struct hnae3_handle *h = hns3_get_handle(ndev);
2956
2957 if (!h->ae_algo->ops->set_vf_rate)
2958 return -EOPNOTSUPP;
2959
2960 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2961 false);
2962 }
2963
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2964 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2965 {
2966 struct hnae3_handle *h = hns3_get_handle(netdev);
2967 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2968
2969 if (!h->ae_algo->ops->set_vf_mac)
2970 return -EOPNOTSUPP;
2971
2972 if (is_multicast_ether_addr(mac)) {
2973 hnae3_format_mac_addr(format_mac_addr, mac);
2974 netdev_err(netdev,
2975 "Invalid MAC:%s specified. Could not set MAC\n",
2976 format_mac_addr);
2977 return -EINVAL;
2978 }
2979
2980 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2981 }
2982
2983 #define HNS3_INVALID_DSCP 0xff
2984 #define HNS3_DSCP_SHIFT 2
2985
hns3_get_skb_dscp(struct sk_buff * skb)2986 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2987 {
2988 __be16 protocol = skb->protocol;
2989 u8 dscp = HNS3_INVALID_DSCP;
2990
2991 if (protocol == htons(ETH_P_8021Q))
2992 protocol = vlan_get_protocol(skb);
2993
2994 if (protocol == htons(ETH_P_IP))
2995 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
2996 else if (protocol == htons(ETH_P_IPV6))
2997 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
2998
2999 return dscp;
3000 }
3001
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)3002 static u16 hns3_nic_select_queue(struct net_device *netdev,
3003 struct sk_buff *skb,
3004 struct net_device *sb_dev)
3005 {
3006 struct hnae3_handle *h = hns3_get_handle(netdev);
3007 u8 dscp;
3008
3009 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3010 !h->ae_algo->ops->get_dscp_prio)
3011 goto out;
3012
3013 dscp = hns3_get_skb_dscp(skb);
3014 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3015 goto out;
3016
3017 skb->priority = h->kinfo.dscp_prio[dscp];
3018 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3019 skb->priority = 0;
3020
3021 out:
3022 return netdev_pick_tx(netdev, skb, sb_dev);
3023 }
3024
3025 static const struct net_device_ops hns3_nic_netdev_ops = {
3026 .ndo_open = hns3_nic_net_open,
3027 .ndo_stop = hns3_nic_net_stop,
3028 .ndo_start_xmit = hns3_nic_net_xmit,
3029 .ndo_tx_timeout = hns3_nic_net_timeout,
3030 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3031 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3032 .ndo_change_mtu = hns3_nic_change_mtu,
3033 .ndo_set_features = hns3_nic_set_features,
3034 .ndo_features_check = hns3_features_check,
3035 .ndo_get_stats64 = hns3_nic_get_stats64,
3036 .ndo_setup_tc = hns3_nic_setup_tc,
3037 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3038 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3039 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3040 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3041 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3042 .ndo_set_vf_trust = hns3_set_vf_trust,
3043 #ifdef CONFIG_RFS_ACCEL
3044 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3045 #endif
3046 .ndo_get_vf_config = hns3_nic_get_vf_config,
3047 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3048 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3049 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3050 .ndo_select_queue = hns3_nic_select_queue,
3051 };
3052
hns3_is_phys_func(struct pci_dev * pdev)3053 bool hns3_is_phys_func(struct pci_dev *pdev)
3054 {
3055 u32 dev_id = pdev->device;
3056
3057 switch (dev_id) {
3058 case HNAE3_DEV_ID_GE:
3059 case HNAE3_DEV_ID_25GE:
3060 case HNAE3_DEV_ID_25GE_RDMA:
3061 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3062 case HNAE3_DEV_ID_50GE_RDMA:
3063 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3064 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3065 case HNAE3_DEV_ID_200G_RDMA:
3066 return true;
3067 case HNAE3_DEV_ID_VF:
3068 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3069 return false;
3070 default:
3071 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3072 dev_id);
3073 }
3074
3075 return false;
3076 }
3077
hns3_disable_sriov(struct pci_dev * pdev)3078 static void hns3_disable_sriov(struct pci_dev *pdev)
3079 {
3080 /* If our VFs are assigned we cannot shut down SR-IOV
3081 * without causing issues, so just leave the hardware
3082 * available but disabled
3083 */
3084 if (pci_vfs_assigned(pdev)) {
3085 dev_warn(&pdev->dev,
3086 "disabling driver while VFs are assigned\n");
3087 return;
3088 }
3089
3090 pci_disable_sriov(pdev);
3091 }
3092
3093 /* hns3_probe - Device initialization routine
3094 * @pdev: PCI device information struct
3095 * @ent: entry in hns3_pci_tbl
3096 *
3097 * hns3_probe initializes a PF identified by a pci_dev structure.
3098 * The OS initialization, configuring of the PF private structure,
3099 * and a hardware reset occur.
3100 *
3101 * Returns 0 on success, negative on failure
3102 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3103 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3104 {
3105 struct hnae3_ae_dev *ae_dev;
3106 int ret;
3107
3108 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3109 if (!ae_dev)
3110 return -ENOMEM;
3111
3112 ae_dev->pdev = pdev;
3113 ae_dev->flag = ent->driver_data;
3114 pci_set_drvdata(pdev, ae_dev);
3115
3116 ret = hnae3_register_ae_dev(ae_dev);
3117 if (ret)
3118 pci_set_drvdata(pdev, NULL);
3119
3120 return ret;
3121 }
3122
3123 /**
3124 * hns3_clean_vf_config
3125 * @pdev: pointer to a pci_dev structure
3126 * @num_vfs: number of VFs allocated
3127 *
3128 * Clean residual vf config after disable sriov
3129 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3130 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3131 {
3132 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3133
3134 if (ae_dev->ops->clean_vf_config)
3135 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3136 }
3137
3138 /* hns3_remove - Device removal routine
3139 * @pdev: PCI device information struct
3140 */
hns3_remove(struct pci_dev * pdev)3141 static void hns3_remove(struct pci_dev *pdev)
3142 {
3143 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3144
3145 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3146 hns3_disable_sriov(pdev);
3147
3148 hnae3_unregister_ae_dev(ae_dev);
3149 pci_set_drvdata(pdev, NULL);
3150 }
3151
3152 /**
3153 * hns3_pci_sriov_configure
3154 * @pdev: pointer to a pci_dev structure
3155 * @num_vfs: number of VFs to allocate
3156 *
3157 * Enable or change the number of VFs. Called when the user updates the number
3158 * of VFs in sysfs.
3159 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3160 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3161 {
3162 int ret;
3163
3164 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3165 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3166 return -EINVAL;
3167 }
3168
3169 if (num_vfs) {
3170 ret = pci_enable_sriov(pdev, num_vfs);
3171 if (ret)
3172 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3173 else
3174 return num_vfs;
3175 } else if (!pci_vfs_assigned(pdev)) {
3176 int num_vfs_pre = pci_num_vf(pdev);
3177
3178 pci_disable_sriov(pdev);
3179 hns3_clean_vf_config(pdev, num_vfs_pre);
3180 } else {
3181 dev_warn(&pdev->dev,
3182 "Unable to free VFs because some are assigned to VMs.\n");
3183 }
3184
3185 return 0;
3186 }
3187
hns3_shutdown(struct pci_dev * pdev)3188 static void hns3_shutdown(struct pci_dev *pdev)
3189 {
3190 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3191
3192 hnae3_unregister_ae_dev(ae_dev);
3193 pci_set_drvdata(pdev, NULL);
3194
3195 if (system_state == SYSTEM_POWER_OFF)
3196 pci_set_power_state(pdev, PCI_D3hot);
3197 }
3198
hns3_suspend(struct device * dev)3199 static int __maybe_unused hns3_suspend(struct device *dev)
3200 {
3201 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3202
3203 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3204 dev_info(dev, "Begin to suspend.\n");
3205 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3206 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3207 }
3208
3209 return 0;
3210 }
3211
hns3_resume(struct device * dev)3212 static int __maybe_unused hns3_resume(struct device *dev)
3213 {
3214 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3215
3216 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3217 dev_info(dev, "Begin to resume.\n");
3218 if (ae_dev->ops && ae_dev->ops->reset_done)
3219 ae_dev->ops->reset_done(ae_dev);
3220 }
3221
3222 return 0;
3223 }
3224
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3225 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3226 pci_channel_state_t state)
3227 {
3228 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3229 pci_ers_result_t ret;
3230
3231 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3232
3233 if (state == pci_channel_io_perm_failure)
3234 return PCI_ERS_RESULT_DISCONNECT;
3235
3236 if (!ae_dev || !ae_dev->ops) {
3237 dev_err(&pdev->dev,
3238 "Can't recover - error happened before device initialized\n");
3239 return PCI_ERS_RESULT_NONE;
3240 }
3241
3242 if (ae_dev->ops->handle_hw_ras_error)
3243 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3244 else
3245 return PCI_ERS_RESULT_NONE;
3246
3247 return ret;
3248 }
3249
hns3_slot_reset(struct pci_dev * pdev)3250 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3251 {
3252 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3253 const struct hnae3_ae_ops *ops;
3254 enum hnae3_reset_type reset_type;
3255 struct device *dev = &pdev->dev;
3256
3257 if (!ae_dev || !ae_dev->ops)
3258 return PCI_ERS_RESULT_NONE;
3259
3260 ops = ae_dev->ops;
3261 /* request the reset */
3262 if (ops->reset_event && ops->get_reset_level &&
3263 ops->set_default_reset_request) {
3264 if (ae_dev->hw_err_reset_req) {
3265 reset_type = ops->get_reset_level(ae_dev,
3266 &ae_dev->hw_err_reset_req);
3267 ops->set_default_reset_request(ae_dev, reset_type);
3268 dev_info(dev, "requesting reset due to PCI error\n");
3269 ops->reset_event(pdev, NULL);
3270 }
3271
3272 return PCI_ERS_RESULT_RECOVERED;
3273 }
3274
3275 return PCI_ERS_RESULT_DISCONNECT;
3276 }
3277
hns3_reset_prepare(struct pci_dev * pdev)3278 static void hns3_reset_prepare(struct pci_dev *pdev)
3279 {
3280 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3281
3282 dev_info(&pdev->dev, "FLR prepare\n");
3283 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3284 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3285 }
3286
hns3_reset_done(struct pci_dev * pdev)3287 static void hns3_reset_done(struct pci_dev *pdev)
3288 {
3289 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3290
3291 dev_info(&pdev->dev, "FLR done\n");
3292 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3293 ae_dev->ops->reset_done(ae_dev);
3294 }
3295
3296 static const struct pci_error_handlers hns3_err_handler = {
3297 .error_detected = hns3_error_detected,
3298 .slot_reset = hns3_slot_reset,
3299 .reset_prepare = hns3_reset_prepare,
3300 .reset_done = hns3_reset_done,
3301 };
3302
3303 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3304
3305 static struct pci_driver hns3_driver = {
3306 .name = hns3_driver_name,
3307 .id_table = hns3_pci_tbl,
3308 .probe = hns3_probe,
3309 .remove = hns3_remove,
3310 .shutdown = hns3_shutdown,
3311 .driver.pm = &hns3_pm_ops,
3312 .sriov_configure = hns3_pci_sriov_configure,
3313 .err_handler = &hns3_err_handler,
3314 };
3315
3316 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3317 static void hns3_set_default_feature(struct net_device *netdev)
3318 {
3319 struct hnae3_handle *h = hns3_get_handle(netdev);
3320 struct pci_dev *pdev = h->pdev;
3321 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3322
3323 netdev->priv_flags |= IFF_UNICAST_FLT;
3324
3325 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3326 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3327 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3328 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3329 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3330 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3331
3332 if (hnae3_ae_dev_gro_supported(ae_dev))
3333 netdev->features |= NETIF_F_GRO_HW;
3334
3335 if (hnae3_ae_dev_fd_supported(ae_dev))
3336 netdev->features |= NETIF_F_NTUPLE;
3337
3338 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3339 netdev->features |= NETIF_F_GSO_UDP_L4;
3340
3341 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3342 netdev->features |= NETIF_F_HW_CSUM;
3343 else
3344 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3345
3346 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3347 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3348
3349 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3350 netdev->features |= NETIF_F_HW_TC;
3351
3352 netdev->hw_features |= netdev->features;
3353 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3354 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3355
3356 netdev->vlan_features |= netdev->features &
3357 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3358 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3359 NETIF_F_HW_TC);
3360
3361 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3362
3363 /* The device_version V3 hardware can't offload the checksum for IP in
3364 * GRE packets, but can do it for NvGRE. So default to disable the
3365 * checksum and GSO offload for GRE.
3366 */
3367 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3368 netdev->features &= ~NETIF_F_GSO_GRE;
3369 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3370 }
3371 }
3372
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3373 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3374 struct hns3_desc_cb *cb)
3375 {
3376 unsigned int order = hns3_page_order(ring);
3377 struct page *p;
3378
3379 if (ring->page_pool) {
3380 p = page_pool_dev_alloc_frag(ring->page_pool,
3381 &cb->page_offset,
3382 hns3_buf_size(ring));
3383 if (unlikely(!p))
3384 return -ENOMEM;
3385
3386 cb->priv = p;
3387 cb->buf = page_address(p);
3388 cb->dma = page_pool_get_dma_addr(p);
3389 cb->type = DESC_TYPE_PP_FRAG;
3390 cb->reuse_flag = 0;
3391 return 0;
3392 }
3393
3394 p = dev_alloc_pages(order);
3395 if (!p)
3396 return -ENOMEM;
3397
3398 cb->priv = p;
3399 cb->page_offset = 0;
3400 cb->reuse_flag = 0;
3401 cb->buf = page_address(p);
3402 cb->length = hns3_page_size(ring);
3403 cb->type = DESC_TYPE_PAGE;
3404 page_ref_add(p, USHRT_MAX - 1);
3405 cb->pagecnt_bias = USHRT_MAX;
3406
3407 return 0;
3408 }
3409
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3410 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3411 struct hns3_desc_cb *cb, int budget)
3412 {
3413 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3414 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3415 napi_consume_skb(cb->priv, budget);
3416 else if (!HNAE3_IS_TX_RING(ring)) {
3417 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3418 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3419 else if (cb->type & DESC_TYPE_PP_FRAG)
3420 page_pool_put_full_page(ring->page_pool, cb->priv,
3421 false);
3422 }
3423 memset(cb, 0, sizeof(*cb));
3424 }
3425
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3426 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3427 {
3428 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3429 cb->length, ring_to_dma_dir(ring));
3430
3431 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3432 return -EIO;
3433
3434 return 0;
3435 }
3436
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3437 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3438 struct hns3_desc_cb *cb)
3439 {
3440 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3441 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3442 ring_to_dma_dir(ring));
3443 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3444 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3445 ring_to_dma_dir(ring));
3446 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3447 DESC_TYPE_SGL_SKB))
3448 hns3_tx_spare_reclaim_cb(ring, cb);
3449 }
3450
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3451 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3452 {
3453 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3454 ring->desc[i].addr = 0;
3455 ring->desc_cb[i].refill = 0;
3456 }
3457
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3458 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3459 int budget)
3460 {
3461 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3462
3463 if (!ring->desc_cb[i].dma)
3464 return;
3465
3466 hns3_buffer_detach(ring, i);
3467 hns3_free_buffer(ring, cb, budget);
3468 }
3469
hns3_free_buffers(struct hns3_enet_ring * ring)3470 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3471 {
3472 int i;
3473
3474 for (i = 0; i < ring->desc_num; i++)
3475 hns3_free_buffer_detach(ring, i, 0);
3476 }
3477
3478 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3479 static void hns3_free_desc(struct hns3_enet_ring *ring)
3480 {
3481 int size = ring->desc_num * sizeof(ring->desc[0]);
3482
3483 hns3_free_buffers(ring);
3484
3485 if (ring->desc) {
3486 dma_free_coherent(ring_to_dev(ring), size,
3487 ring->desc, ring->desc_dma_addr);
3488 ring->desc = NULL;
3489 }
3490 }
3491
hns3_alloc_desc(struct hns3_enet_ring * ring)3492 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3493 {
3494 int size = ring->desc_num * sizeof(ring->desc[0]);
3495
3496 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3497 &ring->desc_dma_addr, GFP_KERNEL);
3498 if (!ring->desc)
3499 return -ENOMEM;
3500
3501 return 0;
3502 }
3503
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3504 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3505 struct hns3_desc_cb *cb)
3506 {
3507 int ret;
3508
3509 ret = hns3_alloc_buffer(ring, cb);
3510 if (ret || ring->page_pool)
3511 goto out;
3512
3513 ret = hns3_map_buffer(ring, cb);
3514 if (ret)
3515 goto out_with_buf;
3516
3517 return 0;
3518
3519 out_with_buf:
3520 hns3_free_buffer(ring, cb, 0);
3521 out:
3522 return ret;
3523 }
3524
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3525 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3526 {
3527 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3528
3529 if (ret)
3530 return ret;
3531
3532 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3533 ring->desc_cb[i].page_offset);
3534 ring->desc_cb[i].refill = 1;
3535
3536 return 0;
3537 }
3538
3539 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3540 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3541 {
3542 int i, j, ret;
3543
3544 for (i = 0; i < ring->desc_num; i++) {
3545 ret = hns3_alloc_and_attach_buffer(ring, i);
3546 if (ret)
3547 goto out_buffer_fail;
3548
3549 if (!(i % HNS3_RESCHED_BD_NUM))
3550 cond_resched();
3551 }
3552
3553 return 0;
3554
3555 out_buffer_fail:
3556 for (j = i - 1; j >= 0; j--)
3557 hns3_free_buffer_detach(ring, j, 0);
3558 return ret;
3559 }
3560
3561 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3562 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3563 struct hns3_desc_cb *res_cb)
3564 {
3565 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3566 ring->desc_cb[i] = *res_cb;
3567 ring->desc_cb[i].refill = 1;
3568 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3569 ring->desc_cb[i].page_offset);
3570 ring->desc[i].rx.bd_base_info = 0;
3571 }
3572
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3573 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3574 {
3575 ring->desc_cb[i].reuse_flag = 0;
3576 ring->desc_cb[i].refill = 1;
3577 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3578 ring->desc_cb[i].page_offset);
3579 ring->desc[i].rx.bd_base_info = 0;
3580
3581 dma_sync_single_for_device(ring_to_dev(ring),
3582 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3583 hns3_buf_size(ring),
3584 DMA_FROM_DEVICE);
3585 }
3586
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3587 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3588 int *bytes, int *pkts, int budget)
3589 {
3590 /* This smp_load_acquire() pairs with smp_store_release() in
3591 * hns3_tx_doorbell().
3592 */
3593 int ltu = smp_load_acquire(&ring->last_to_use);
3594 int ntc = ring->next_to_clean;
3595 struct hns3_desc_cb *desc_cb;
3596 bool reclaimed = false;
3597 struct hns3_desc *desc;
3598
3599 while (ltu != ntc) {
3600 desc = &ring->desc[ntc];
3601
3602 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3603 BIT(HNS3_TXD_VLD_B))
3604 break;
3605
3606 desc_cb = &ring->desc_cb[ntc];
3607
3608 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3609 DESC_TYPE_BOUNCE_HEAD |
3610 DESC_TYPE_SGL_SKB)) {
3611 (*pkts)++;
3612 (*bytes) += desc_cb->send_bytes;
3613 }
3614
3615 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3616 hns3_free_buffer_detach(ring, ntc, budget);
3617
3618 if (++ntc == ring->desc_num)
3619 ntc = 0;
3620
3621 /* Issue prefetch for next Tx descriptor */
3622 prefetch(&ring->desc_cb[ntc]);
3623 reclaimed = true;
3624 }
3625
3626 if (unlikely(!reclaimed))
3627 return false;
3628
3629 /* This smp_store_release() pairs with smp_load_acquire() in
3630 * ring_space called by hns3_nic_net_xmit.
3631 */
3632 smp_store_release(&ring->next_to_clean, ntc);
3633
3634 hns3_tx_spare_update(ring);
3635
3636 return true;
3637 }
3638
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3639 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3640 {
3641 struct net_device *netdev = ring_to_netdev(ring);
3642 struct hns3_nic_priv *priv = netdev_priv(netdev);
3643 struct netdev_queue *dev_queue;
3644 int bytes, pkts;
3645
3646 bytes = 0;
3647 pkts = 0;
3648
3649 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3650 return;
3651
3652 ring->tqp_vector->tx_group.total_bytes += bytes;
3653 ring->tqp_vector->tx_group.total_packets += pkts;
3654
3655 u64_stats_update_begin(&ring->syncp);
3656 ring->stats.tx_bytes += bytes;
3657 ring->stats.tx_pkts += pkts;
3658 u64_stats_update_end(&ring->syncp);
3659
3660 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3661 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3662
3663 if (unlikely(netif_carrier_ok(netdev) &&
3664 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3665 /* Make sure that anybody stopping the queue after this
3666 * sees the new next_to_clean.
3667 */
3668 smp_mb();
3669 if (netif_tx_queue_stopped(dev_queue) &&
3670 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3671 netif_tx_wake_queue(dev_queue);
3672 ring->stats.restart_queue++;
3673 }
3674 }
3675 }
3676
hns3_desc_unused(struct hns3_enet_ring * ring)3677 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3678 {
3679 int ntc = ring->next_to_clean;
3680 int ntu = ring->next_to_use;
3681
3682 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3683 return ring->desc_num;
3684
3685 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3686 }
3687
3688 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3689 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3690 int cleand_count)
3691 {
3692 struct hns3_desc_cb *desc_cb;
3693 struct hns3_desc_cb res_cbs;
3694 int i, ret;
3695
3696 for (i = 0; i < cleand_count; i++) {
3697 desc_cb = &ring->desc_cb[ring->next_to_use];
3698 if (desc_cb->reuse_flag) {
3699 hns3_ring_stats_update(ring, reuse_pg_cnt);
3700
3701 hns3_reuse_buffer(ring, ring->next_to_use);
3702 } else {
3703 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3704 if (ret) {
3705 hns3_ring_stats_update(ring, sw_err_cnt);
3706
3707 hns3_rl_err(ring_to_netdev(ring),
3708 "alloc rx buffer failed: %d\n",
3709 ret);
3710
3711 writel(i, ring->tqp->io_base +
3712 HNS3_RING_RX_RING_HEAD_REG);
3713 return true;
3714 }
3715 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3716
3717 hns3_ring_stats_update(ring, non_reuse_pg);
3718 }
3719
3720 ring_ptr_move_fw(ring, next_to_use);
3721 }
3722
3723 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3724 return false;
3725 }
3726
hns3_can_reuse_page(struct hns3_desc_cb * cb)3727 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3728 {
3729 return page_count(cb->priv) == cb->pagecnt_bias;
3730 }
3731
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3732 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3733 struct hns3_enet_ring *ring,
3734 int pull_len,
3735 struct hns3_desc_cb *desc_cb)
3736 {
3737 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3738 u32 frag_offset = desc_cb->page_offset + pull_len;
3739 int size = le16_to_cpu(desc->rx.size);
3740 u32 frag_size = size - pull_len;
3741 void *frag = napi_alloc_frag(frag_size);
3742
3743 if (unlikely(!frag)) {
3744 hns3_ring_stats_update(ring, frag_alloc_err);
3745
3746 hns3_rl_err(ring_to_netdev(ring),
3747 "failed to allocate rx frag\n");
3748 return -ENOMEM;
3749 }
3750
3751 desc_cb->reuse_flag = 1;
3752 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3753 skb_add_rx_frag(skb, i, virt_to_page(frag),
3754 offset_in_page(frag), frag_size, frag_size);
3755
3756 hns3_ring_stats_update(ring, frag_alloc);
3757 return 0;
3758 }
3759
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3760 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3761 struct hns3_enet_ring *ring, int pull_len,
3762 struct hns3_desc_cb *desc_cb)
3763 {
3764 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3765 u32 frag_offset = desc_cb->page_offset + pull_len;
3766 int size = le16_to_cpu(desc->rx.size);
3767 u32 truesize = hns3_buf_size(ring);
3768 u32 frag_size = size - pull_len;
3769 int ret = 0;
3770 bool reused;
3771
3772 if (ring->page_pool) {
3773 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3774 frag_size, truesize);
3775 return;
3776 }
3777
3778 /* Avoid re-using remote or pfmem page */
3779 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3780 goto out;
3781
3782 reused = hns3_can_reuse_page(desc_cb);
3783
3784 /* Rx page can be reused when:
3785 * 1. Rx page is only owned by the driver when page_offset
3786 * is zero, which means 0 @ truesize will be used by
3787 * stack after skb_add_rx_frag() is called, and the rest
3788 * of rx page can be reused by driver.
3789 * Or
3790 * 2. Rx page is only owned by the driver when page_offset
3791 * is non-zero, which means page_offset @ truesize will
3792 * be used by stack after skb_add_rx_frag() is called,
3793 * and 0 @ truesize can be reused by driver.
3794 */
3795 if ((!desc_cb->page_offset && reused) ||
3796 ((desc_cb->page_offset + truesize + truesize) <=
3797 hns3_page_size(ring) && desc_cb->page_offset)) {
3798 desc_cb->page_offset += truesize;
3799 desc_cb->reuse_flag = 1;
3800 } else if (desc_cb->page_offset && reused) {
3801 desc_cb->page_offset = 0;
3802 desc_cb->reuse_flag = 1;
3803 } else if (frag_size <= ring->rx_copybreak) {
3804 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3805 if (!ret)
3806 return;
3807 }
3808
3809 out:
3810 desc_cb->pagecnt_bias--;
3811
3812 if (unlikely(!desc_cb->pagecnt_bias)) {
3813 page_ref_add(desc_cb->priv, USHRT_MAX);
3814 desc_cb->pagecnt_bias = USHRT_MAX;
3815 }
3816
3817 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3818 frag_size, truesize);
3819
3820 if (unlikely(!desc_cb->reuse_flag))
3821 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3822 }
3823
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3824 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3825 {
3826 __be16 type = skb->protocol;
3827 struct tcphdr *th;
3828 u32 depth = 0;
3829
3830 while (eth_type_vlan(type)) {
3831 struct vlan_hdr *vh;
3832
3833 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3834 return -EFAULT;
3835
3836 vh = (struct vlan_hdr *)(skb->data + depth);
3837 type = vh->h_vlan_encapsulated_proto;
3838 depth += VLAN_HLEN;
3839 }
3840
3841 skb_set_network_header(skb, depth);
3842
3843 if (type == htons(ETH_P_IP)) {
3844 const struct iphdr *iph = ip_hdr(skb);
3845
3846 depth += sizeof(struct iphdr);
3847 skb_set_transport_header(skb, depth);
3848 th = tcp_hdr(skb);
3849 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3850 iph->daddr, 0);
3851 } else if (type == htons(ETH_P_IPV6)) {
3852 const struct ipv6hdr *iph = ipv6_hdr(skb);
3853
3854 depth += sizeof(struct ipv6hdr);
3855 skb_set_transport_header(skb, depth);
3856 th = tcp_hdr(skb);
3857 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3858 &iph->daddr, 0);
3859 } else {
3860 hns3_rl_err(skb->dev,
3861 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3862 be16_to_cpu(type), depth);
3863 return -EFAULT;
3864 }
3865
3866 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3867 if (th->cwr)
3868 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3869
3870 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3871 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3872
3873 skb->csum_start = (unsigned char *)th - skb->head;
3874 skb->csum_offset = offsetof(struct tcphdr, check);
3875 skb->ip_summed = CHECKSUM_PARTIAL;
3876
3877 trace_hns3_gro(skb);
3878
3879 return 0;
3880 }
3881
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3882 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3883 struct sk_buff *skb, u32 ptype, u16 csum)
3884 {
3885 if (ptype == HNS3_INVALID_PTYPE ||
3886 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3887 return;
3888
3889 hns3_ring_stats_update(ring, csum_complete);
3890 skb->ip_summed = CHECKSUM_COMPLETE;
3891 skb->csum = csum_unfold((__force __sum16)csum);
3892 }
3893
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3894 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3895 u32 ol_info, u32 ptype)
3896 {
3897 int l3_type, l4_type;
3898 int ol4_type;
3899
3900 if (ptype != HNS3_INVALID_PTYPE) {
3901 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3902 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3903
3904 return;
3905 }
3906
3907 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3908 HNS3_RXD_OL4ID_S);
3909 switch (ol4_type) {
3910 case HNS3_OL4_TYPE_MAC_IN_UDP:
3911 case HNS3_OL4_TYPE_NVGRE:
3912 skb->csum_level = 1;
3913 fallthrough;
3914 case HNS3_OL4_TYPE_NO_TUN:
3915 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3916 HNS3_RXD_L3ID_S);
3917 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3918 HNS3_RXD_L4ID_S);
3919 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3920 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3921 l3_type == HNS3_L3_TYPE_IPV6) &&
3922 (l4_type == HNS3_L4_TYPE_UDP ||
3923 l4_type == HNS3_L4_TYPE_TCP ||
3924 l4_type == HNS3_L4_TYPE_SCTP))
3925 skb->ip_summed = CHECKSUM_UNNECESSARY;
3926 break;
3927 default:
3928 break;
3929 }
3930 }
3931
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3932 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3933 u32 l234info, u32 bd_base_info, u32 ol_info,
3934 u16 csum)
3935 {
3936 struct net_device *netdev = ring_to_netdev(ring);
3937 struct hns3_nic_priv *priv = netdev_priv(netdev);
3938 u32 ptype = HNS3_INVALID_PTYPE;
3939
3940 skb->ip_summed = CHECKSUM_NONE;
3941
3942 skb_checksum_none_assert(skb);
3943
3944 if (!(netdev->features & NETIF_F_RXCSUM))
3945 return;
3946
3947 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3948 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3949 HNS3_RXD_PTYPE_S);
3950
3951 hns3_checksum_complete(ring, skb, ptype, csum);
3952
3953 /* check if hardware has done checksum */
3954 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3955 return;
3956
3957 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3958 BIT(HNS3_RXD_OL3E_B) |
3959 BIT(HNS3_RXD_OL4E_B)))) {
3960 skb->ip_summed = CHECKSUM_NONE;
3961 hns3_ring_stats_update(ring, l3l4_csum_err);
3962
3963 return;
3964 }
3965
3966 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3967 }
3968
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3969 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3970 {
3971 if (skb_has_frag_list(skb))
3972 napi_gro_flush(&ring->tqp_vector->napi, false);
3973
3974 napi_gro_receive(&ring->tqp_vector->napi, skb);
3975 }
3976
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3977 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3978 struct hns3_desc *desc, u32 l234info,
3979 u16 *vlan_tag)
3980 {
3981 struct hnae3_handle *handle = ring->tqp->handle;
3982 struct pci_dev *pdev = ring->tqp->handle->pdev;
3983 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3984
3985 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3986 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3987 if (!(*vlan_tag & VLAN_VID_MASK))
3988 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3989
3990 return (*vlan_tag != 0);
3991 }
3992
3993 #define HNS3_STRP_OUTER_VLAN 0x1
3994 #define HNS3_STRP_INNER_VLAN 0x2
3995 #define HNS3_STRP_BOTH 0x3
3996
3997 /* Hardware always insert VLAN tag into RX descriptor when
3998 * remove the tag from packet, driver needs to determine
3999 * reporting which tag to stack.
4000 */
4001 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
4002 HNS3_RXD_STRP_TAGP_S)) {
4003 case HNS3_STRP_OUTER_VLAN:
4004 if (handle->port_base_vlan_state !=
4005 HNAE3_PORT_BASE_VLAN_DISABLE)
4006 return false;
4007
4008 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4009 return true;
4010 case HNS3_STRP_INNER_VLAN:
4011 if (handle->port_base_vlan_state !=
4012 HNAE3_PORT_BASE_VLAN_DISABLE)
4013 return false;
4014
4015 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4016 return true;
4017 case HNS3_STRP_BOTH:
4018 if (handle->port_base_vlan_state ==
4019 HNAE3_PORT_BASE_VLAN_DISABLE)
4020 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4021 else
4022 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4023
4024 return true;
4025 default:
4026 return false;
4027 }
4028 }
4029
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4030 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4031 {
4032 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4033 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4034 ring->desc_cb[ring->next_to_clean].refill = 0;
4035 ring->next_to_clean += 1;
4036
4037 if (unlikely(ring->next_to_clean == ring->desc_num))
4038 ring->next_to_clean = 0;
4039 }
4040
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4041 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4042 unsigned char *va)
4043 {
4044 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4045 struct net_device *netdev = ring_to_netdev(ring);
4046 struct sk_buff *skb;
4047
4048 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4049 skb = ring->skb;
4050 if (unlikely(!skb)) {
4051 hns3_rl_err(netdev, "alloc rx skb fail\n");
4052 hns3_ring_stats_update(ring, sw_err_cnt);
4053
4054 return -ENOMEM;
4055 }
4056
4057 trace_hns3_rx_desc(ring);
4058 prefetchw(skb->data);
4059
4060 ring->pending_buf = 1;
4061 ring->frag_num = 0;
4062 ring->tail_skb = NULL;
4063 if (length <= HNS3_RX_HEAD_SIZE) {
4064 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4065
4066 /* We can reuse buffer as-is, just make sure it is reusable */
4067 if (dev_page_is_reusable(desc_cb->priv))
4068 desc_cb->reuse_flag = 1;
4069 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4070 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4071 false);
4072 else /* This page cannot be reused so discard it */
4073 __page_frag_cache_drain(desc_cb->priv,
4074 desc_cb->pagecnt_bias);
4075
4076 hns3_rx_ring_move_fw(ring);
4077 return 0;
4078 }
4079
4080 if (ring->page_pool)
4081 skb_mark_for_recycle(skb);
4082
4083 hns3_ring_stats_update(ring, seg_pkt_cnt);
4084
4085 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4086 __skb_put(skb, ring->pull_len);
4087 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4088 desc_cb);
4089 hns3_rx_ring_move_fw(ring);
4090
4091 return 0;
4092 }
4093
hns3_add_frag(struct hns3_enet_ring * ring)4094 static int hns3_add_frag(struct hns3_enet_ring *ring)
4095 {
4096 struct sk_buff *skb = ring->skb;
4097 struct sk_buff *head_skb = skb;
4098 struct sk_buff *new_skb;
4099 struct hns3_desc_cb *desc_cb;
4100 struct hns3_desc *desc;
4101 u32 bd_base_info;
4102
4103 do {
4104 desc = &ring->desc[ring->next_to_clean];
4105 desc_cb = &ring->desc_cb[ring->next_to_clean];
4106 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4107 /* make sure HW write desc complete */
4108 dma_rmb();
4109 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4110 return -ENXIO;
4111
4112 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4113 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4114 if (unlikely(!new_skb)) {
4115 hns3_rl_err(ring_to_netdev(ring),
4116 "alloc rx fraglist skb fail\n");
4117 return -ENXIO;
4118 }
4119
4120 if (ring->page_pool)
4121 skb_mark_for_recycle(new_skb);
4122
4123 ring->frag_num = 0;
4124
4125 if (ring->tail_skb) {
4126 ring->tail_skb->next = new_skb;
4127 ring->tail_skb = new_skb;
4128 } else {
4129 skb_shinfo(skb)->frag_list = new_skb;
4130 ring->tail_skb = new_skb;
4131 }
4132 }
4133
4134 if (ring->tail_skb) {
4135 head_skb->truesize += hns3_buf_size(ring);
4136 head_skb->data_len += le16_to_cpu(desc->rx.size);
4137 head_skb->len += le16_to_cpu(desc->rx.size);
4138 skb = ring->tail_skb;
4139 }
4140
4141 dma_sync_single_for_cpu(ring_to_dev(ring),
4142 desc_cb->dma + desc_cb->page_offset,
4143 hns3_buf_size(ring),
4144 DMA_FROM_DEVICE);
4145
4146 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4147 trace_hns3_rx_desc(ring);
4148 hns3_rx_ring_move_fw(ring);
4149 ring->pending_buf++;
4150 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4151
4152 return 0;
4153 }
4154
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4155 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4156 struct sk_buff *skb, u32 l234info,
4157 u32 bd_base_info, u32 ol_info, u16 csum)
4158 {
4159 struct net_device *netdev = ring_to_netdev(ring);
4160 struct hns3_nic_priv *priv = netdev_priv(netdev);
4161 u32 l3_type;
4162
4163 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4164 HNS3_RXD_GRO_SIZE_M,
4165 HNS3_RXD_GRO_SIZE_S);
4166 /* if there is no HW GRO, do not set gro params */
4167 if (!skb_shinfo(skb)->gso_size) {
4168 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4169 csum);
4170 return 0;
4171 }
4172
4173 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4174 HNS3_RXD_GRO_COUNT_M,
4175 HNS3_RXD_GRO_COUNT_S);
4176
4177 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4178 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4179 HNS3_RXD_PTYPE_S);
4180
4181 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4182 } else {
4183 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4184 HNS3_RXD_L3ID_S);
4185 }
4186
4187 if (l3_type == HNS3_L3_TYPE_IPV4)
4188 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4189 else if (l3_type == HNS3_L3_TYPE_IPV6)
4190 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4191 else
4192 return -EFAULT;
4193
4194 return hns3_gro_complete(skb, l234info);
4195 }
4196
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4197 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4198 struct sk_buff *skb, u32 rss_hash,
4199 u32 l234info, u32 ol_info)
4200 {
4201 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4202 struct net_device *netdev = ring_to_netdev(ring);
4203 struct hns3_nic_priv *priv = netdev_priv(netdev);
4204
4205 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4206 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4207 HNS3_RXD_PTYPE_S);
4208
4209 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4210 } else {
4211 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4212 HNS3_RXD_L3ID_S);
4213 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4214 HNS3_RXD_L4ID_S);
4215
4216 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4217 l3_type == HNS3_L3_TYPE_IPV6) {
4218 if (l4_type == HNS3_L4_TYPE_UDP ||
4219 l4_type == HNS3_L4_TYPE_TCP ||
4220 l4_type == HNS3_L4_TYPE_SCTP)
4221 rss_type = PKT_HASH_TYPE_L4;
4222 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4223 l4_type == HNS3_L4_TYPE_ICMP)
4224 rss_type = PKT_HASH_TYPE_L3;
4225 }
4226 }
4227
4228 skb_set_hash(skb, rss_hash, rss_type);
4229 }
4230
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4231 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4232 struct hns3_desc *desc, struct sk_buff *skb,
4233 u32 bd_base_info)
4234 {
4235 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4236 struct hnae3_handle *h = hns3_get_handle(netdev);
4237 u32 nsec = le32_to_cpu(desc->ts_nsec);
4238 u32 sec = le32_to_cpu(desc->ts_sec);
4239
4240 if (h->ae_algo->ops->get_rx_hwts)
4241 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4242 }
4243 }
4244
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4245 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4246 struct hns3_desc *desc, struct sk_buff *skb,
4247 u32 l234info)
4248 {
4249 struct net_device *netdev = ring_to_netdev(ring);
4250
4251 /* Based on hw strategy, the tag offloaded will be stored at
4252 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4253 * in one layer tag case.
4254 */
4255 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4256 u16 vlan_tag;
4257
4258 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4259 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4260 vlan_tag);
4261 }
4262 }
4263
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4264 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4265 {
4266 struct net_device *netdev = ring_to_netdev(ring);
4267 enum hns3_pkt_l2t_type l2_frame_type;
4268 u32 bd_base_info, l234info, ol_info;
4269 struct hns3_desc *desc;
4270 unsigned int len;
4271 int pre_ntc, ret;
4272 u16 csum;
4273
4274 /* bdinfo handled below is only valid on the last BD of the
4275 * current packet, and ring->next_to_clean indicates the first
4276 * descriptor of next packet, so need - 1 below.
4277 */
4278 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4279 (ring->desc_num - 1);
4280 desc = &ring->desc[pre_ntc];
4281 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4282 l234info = le32_to_cpu(desc->rx.l234_info);
4283 ol_info = le32_to_cpu(desc->rx.ol_info);
4284 csum = le16_to_cpu(desc->csum);
4285
4286 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4287
4288 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4289
4290 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4291 BIT(HNS3_RXD_L2E_B))))) {
4292 u64_stats_update_begin(&ring->syncp);
4293 if (l234info & BIT(HNS3_RXD_L2E_B))
4294 ring->stats.l2_err++;
4295 else
4296 ring->stats.err_pkt_len++;
4297 u64_stats_update_end(&ring->syncp);
4298
4299 return -EFAULT;
4300 }
4301
4302 len = skb->len;
4303
4304 /* Do update ip stack process */
4305 skb->protocol = eth_type_trans(skb, netdev);
4306
4307 /* This is needed in order to enable forwarding support */
4308 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4309 bd_base_info, ol_info, csum);
4310 if (unlikely(ret)) {
4311 hns3_ring_stats_update(ring, rx_err_cnt);
4312 return ret;
4313 }
4314
4315 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4316 HNS3_RXD_DMAC_S);
4317
4318 u64_stats_update_begin(&ring->syncp);
4319 ring->stats.rx_pkts++;
4320 ring->stats.rx_bytes += len;
4321
4322 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4323 ring->stats.rx_multicast++;
4324
4325 u64_stats_update_end(&ring->syncp);
4326
4327 ring->tqp_vector->rx_group.total_bytes += len;
4328
4329 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4330 l234info, ol_info);
4331 return 0;
4332 }
4333
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4334 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4335 {
4336 struct sk_buff *skb = ring->skb;
4337 struct hns3_desc_cb *desc_cb;
4338 struct hns3_desc *desc;
4339 unsigned int length;
4340 u32 bd_base_info;
4341 int ret;
4342
4343 desc = &ring->desc[ring->next_to_clean];
4344 desc_cb = &ring->desc_cb[ring->next_to_clean];
4345
4346 prefetch(desc);
4347
4348 if (!skb) {
4349 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4350 /* Check valid BD */
4351 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4352 return -ENXIO;
4353
4354 dma_rmb();
4355 length = le16_to_cpu(desc->rx.size);
4356
4357 ring->va = desc_cb->buf + desc_cb->page_offset;
4358
4359 dma_sync_single_for_cpu(ring_to_dev(ring),
4360 desc_cb->dma + desc_cb->page_offset,
4361 hns3_buf_size(ring),
4362 DMA_FROM_DEVICE);
4363
4364 /* Prefetch first cache line of first page.
4365 * Idea is to cache few bytes of the header of the packet.
4366 * Our L1 Cache line size is 64B so need to prefetch twice to make
4367 * it 128B. But in actual we can have greater size of caches with
4368 * 128B Level 1 cache lines. In such a case, single fetch would
4369 * suffice to cache in the relevant part of the header.
4370 */
4371 net_prefetch(ring->va);
4372
4373 ret = hns3_alloc_skb(ring, length, ring->va);
4374 skb = ring->skb;
4375
4376 if (ret < 0) /* alloc buffer fail */
4377 return ret;
4378 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4379 ret = hns3_add_frag(ring);
4380 if (ret)
4381 return ret;
4382 }
4383 } else {
4384 ret = hns3_add_frag(ring);
4385 if (ret)
4386 return ret;
4387 }
4388
4389 /* As the head data may be changed when GRO enable, copy
4390 * the head data in after other data rx completed
4391 */
4392 if (skb->len > HNS3_RX_HEAD_SIZE)
4393 memcpy(skb->data, ring->va,
4394 ALIGN(ring->pull_len, sizeof(long)));
4395
4396 ret = hns3_handle_bdinfo(ring, skb);
4397 if (unlikely(ret)) {
4398 dev_kfree_skb_any(skb);
4399 return ret;
4400 }
4401
4402 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4403 return 0;
4404 }
4405
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4406 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4407 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4408 {
4409 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4410 int unused_count = hns3_desc_unused(ring);
4411 bool failure = false;
4412 int recv_pkts = 0;
4413 int err;
4414
4415 unused_count -= ring->pending_buf;
4416
4417 while (recv_pkts < budget) {
4418 /* Reuse or realloc buffers */
4419 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4420 failure = failure ||
4421 hns3_nic_alloc_rx_buffers(ring, unused_count);
4422 unused_count = 0;
4423 }
4424
4425 /* Poll one pkt */
4426 err = hns3_handle_rx_bd(ring);
4427 /* Do not get FE for the packet or failed to alloc skb */
4428 if (unlikely(!ring->skb || err == -ENXIO)) {
4429 goto out;
4430 } else if (likely(!err)) {
4431 rx_fn(ring, ring->skb);
4432 recv_pkts++;
4433 }
4434
4435 unused_count += ring->pending_buf;
4436 ring->skb = NULL;
4437 ring->pending_buf = 0;
4438 }
4439
4440 out:
4441 /* sync head pointer before exiting, since hardware will calculate
4442 * FBD number with head pointer
4443 */
4444 if (unused_count > 0)
4445 failure = failure ||
4446 hns3_nic_alloc_rx_buffers(ring, unused_count);
4447
4448 return failure ? budget : recv_pkts;
4449 }
4450
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4451 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4452 {
4453 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4454 struct dim_sample sample = {};
4455
4456 if (!rx_group->coal.adapt_enable)
4457 return;
4458
4459 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4460 rx_group->total_bytes, &sample);
4461 net_dim(&rx_group->dim, &sample);
4462 }
4463
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4464 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4465 {
4466 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4467 struct dim_sample sample = {};
4468
4469 if (!tx_group->coal.adapt_enable)
4470 return;
4471
4472 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4473 tx_group->total_bytes, &sample);
4474 net_dim(&tx_group->dim, &sample);
4475 }
4476
hns3_nic_common_poll(struct napi_struct * napi,int budget)4477 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4478 {
4479 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4480 struct hns3_enet_ring *ring;
4481 int rx_pkt_total = 0;
4482
4483 struct hns3_enet_tqp_vector *tqp_vector =
4484 container_of(napi, struct hns3_enet_tqp_vector, napi);
4485 bool clean_complete = true;
4486 int rx_budget = budget;
4487
4488 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4489 napi_complete(napi);
4490 return 0;
4491 }
4492
4493 /* Since the actual Tx work is minimal, we can give the Tx a larger
4494 * budget and be more aggressive about cleaning up the Tx descriptors.
4495 */
4496 hns3_for_each_ring(ring, tqp_vector->tx_group)
4497 hns3_clean_tx_ring(ring, budget);
4498
4499 /* make sure rx ring budget not smaller than 1 */
4500 if (tqp_vector->num_tqps > 1)
4501 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4502
4503 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4504 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4505 hns3_rx_skb);
4506 if (rx_cleaned >= rx_budget)
4507 clean_complete = false;
4508
4509 rx_pkt_total += rx_cleaned;
4510 }
4511
4512 tqp_vector->rx_group.total_packets += rx_pkt_total;
4513
4514 if (!clean_complete)
4515 return budget;
4516
4517 if (napi_complete(napi) &&
4518 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4519 hns3_update_rx_int_coalesce(tqp_vector);
4520 hns3_update_tx_int_coalesce(tqp_vector);
4521
4522 hns3_mask_vector_irq(tqp_vector, 1);
4523 }
4524
4525 return rx_pkt_total;
4526 }
4527
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4528 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4529 struct hnae3_ring_chain_node **head,
4530 bool is_tx)
4531 {
4532 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4533 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4534 struct hnae3_ring_chain_node *cur_chain = *head;
4535 struct pci_dev *pdev = tqp_vector->handle->pdev;
4536 struct hnae3_ring_chain_node *chain;
4537 struct hns3_enet_ring *ring;
4538
4539 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4540
4541 if (cur_chain) {
4542 while (cur_chain->next)
4543 cur_chain = cur_chain->next;
4544 }
4545
4546 while (ring) {
4547 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4548 if (!chain)
4549 return -ENOMEM;
4550 if (cur_chain)
4551 cur_chain->next = chain;
4552 else
4553 *head = chain;
4554 chain->tqp_index = ring->tqp->tqp_index;
4555 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4556 bit_value);
4557 hnae3_set_field(chain->int_gl_idx,
4558 HNAE3_RING_GL_IDX_M,
4559 HNAE3_RING_GL_IDX_S, field_value);
4560
4561 cur_chain = chain;
4562
4563 ring = ring->next;
4564 }
4565
4566 return 0;
4567 }
4568
4569 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4570 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4571 {
4572 struct pci_dev *pdev = tqp_vector->handle->pdev;
4573 struct hnae3_ring_chain_node *cur_chain = NULL;
4574 struct hnae3_ring_chain_node *chain;
4575
4576 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4577 goto err_free_chain;
4578
4579 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4580 goto err_free_chain;
4581
4582 return cur_chain;
4583
4584 err_free_chain:
4585 while (cur_chain) {
4586 chain = cur_chain->next;
4587 devm_kfree(&pdev->dev, cur_chain);
4588 cur_chain = chain;
4589 }
4590
4591 return NULL;
4592 }
4593
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4594 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4595 struct hnae3_ring_chain_node *head)
4596 {
4597 struct pci_dev *pdev = tqp_vector->handle->pdev;
4598 struct hnae3_ring_chain_node *chain_tmp, *chain;
4599
4600 chain = head;
4601
4602 while (chain) {
4603 chain_tmp = chain->next;
4604 devm_kfree(&pdev->dev, chain);
4605 chain = chain_tmp;
4606 }
4607 }
4608
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4609 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4610 struct hns3_enet_ring *ring)
4611 {
4612 ring->next = group->ring;
4613 group->ring = ring;
4614
4615 group->count++;
4616 }
4617
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4618 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4619 {
4620 struct pci_dev *pdev = priv->ae_handle->pdev;
4621 struct hns3_enet_tqp_vector *tqp_vector;
4622 int num_vectors = priv->vector_num;
4623 int numa_node;
4624 int vector_i;
4625
4626 numa_node = dev_to_node(&pdev->dev);
4627
4628 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4629 tqp_vector = &priv->tqp_vector[vector_i];
4630 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4631 &tqp_vector->affinity_mask);
4632 }
4633 }
4634
hns3_rx_dim_work(struct work_struct * work)4635 static void hns3_rx_dim_work(struct work_struct *work)
4636 {
4637 struct dim *dim = container_of(work, struct dim, work);
4638 struct hns3_enet_ring_group *group = container_of(dim,
4639 struct hns3_enet_ring_group, dim);
4640 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4641 struct dim_cq_moder cur_moder =
4642 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4643
4644 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4645 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4646
4647 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4648 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4649 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4650 }
4651
4652 dim->state = DIM_START_MEASURE;
4653 }
4654
hns3_tx_dim_work(struct work_struct * work)4655 static void hns3_tx_dim_work(struct work_struct *work)
4656 {
4657 struct dim *dim = container_of(work, struct dim, work);
4658 struct hns3_enet_ring_group *group = container_of(dim,
4659 struct hns3_enet_ring_group, dim);
4660 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4661 struct dim_cq_moder cur_moder =
4662 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4663
4664 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4665 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4666
4667 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4668 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4669 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4670 }
4671
4672 dim->state = DIM_START_MEASURE;
4673 }
4674
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4675 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4676 {
4677 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4678 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4679 }
4680
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4681 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4682 {
4683 struct hnae3_handle *h = priv->ae_handle;
4684 struct hns3_enet_tqp_vector *tqp_vector;
4685 int ret;
4686 int i;
4687
4688 hns3_nic_set_cpumask(priv);
4689
4690 for (i = 0; i < priv->vector_num; i++) {
4691 tqp_vector = &priv->tqp_vector[i];
4692 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4693 tqp_vector->num_tqps = 0;
4694 hns3_nic_init_dim(tqp_vector);
4695 }
4696
4697 for (i = 0; i < h->kinfo.num_tqps; i++) {
4698 u16 vector_i = i % priv->vector_num;
4699 u16 tqp_num = h->kinfo.num_tqps;
4700
4701 tqp_vector = &priv->tqp_vector[vector_i];
4702
4703 hns3_add_ring_to_group(&tqp_vector->tx_group,
4704 &priv->ring[i]);
4705
4706 hns3_add_ring_to_group(&tqp_vector->rx_group,
4707 &priv->ring[i + tqp_num]);
4708
4709 priv->ring[i].tqp_vector = tqp_vector;
4710 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4711 tqp_vector->num_tqps++;
4712 }
4713
4714 for (i = 0; i < priv->vector_num; i++) {
4715 struct hnae3_ring_chain_node *vector_ring_chain;
4716
4717 tqp_vector = &priv->tqp_vector[i];
4718
4719 tqp_vector->rx_group.total_bytes = 0;
4720 tqp_vector->rx_group.total_packets = 0;
4721 tqp_vector->tx_group.total_bytes = 0;
4722 tqp_vector->tx_group.total_packets = 0;
4723 tqp_vector->handle = h;
4724
4725 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4726 if (!vector_ring_chain) {
4727 ret = -ENOMEM;
4728 goto map_ring_fail;
4729 }
4730
4731 ret = h->ae_algo->ops->map_ring_to_vector(h,
4732 tqp_vector->vector_irq, vector_ring_chain);
4733
4734 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4735
4736 if (ret)
4737 goto map_ring_fail;
4738
4739 netif_napi_add(priv->netdev, &tqp_vector->napi,
4740 hns3_nic_common_poll);
4741 }
4742
4743 return 0;
4744
4745 map_ring_fail:
4746 while (i--)
4747 netif_napi_del(&priv->tqp_vector[i].napi);
4748
4749 return ret;
4750 }
4751
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4752 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4753 {
4754 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4755 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4756 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4757
4758 /* initialize the configuration for interrupt coalescing.
4759 * 1. GL (Interrupt Gap Limiter)
4760 * 2. RL (Interrupt Rate Limiter)
4761 * 3. QL (Interrupt Quantity Limiter)
4762 *
4763 * Default: enable interrupt coalescing self-adaptive and GL
4764 */
4765 tx_coal->adapt_enable = 1;
4766 rx_coal->adapt_enable = 1;
4767
4768 tx_coal->int_gl = HNS3_INT_GL_50K;
4769 rx_coal->int_gl = HNS3_INT_GL_50K;
4770
4771 rx_coal->flow_level = HNS3_FLOW_LOW;
4772 tx_coal->flow_level = HNS3_FLOW_LOW;
4773
4774 if (ae_dev->dev_specs.int_ql_max) {
4775 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4776 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4777 }
4778 }
4779
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4780 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4781 {
4782 struct hnae3_handle *h = priv->ae_handle;
4783 struct hns3_enet_tqp_vector *tqp_vector;
4784 struct hnae3_vector_info *vector;
4785 struct pci_dev *pdev = h->pdev;
4786 u16 tqp_num = h->kinfo.num_tqps;
4787 u16 vector_num;
4788 int ret = 0;
4789 u16 i;
4790
4791 /* RSS size, cpu online and vector_num should be the same */
4792 /* Should consider 2p/4p later */
4793 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4794
4795 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4796 GFP_KERNEL);
4797 if (!vector)
4798 return -ENOMEM;
4799
4800 /* save the actual available vector number */
4801 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4802
4803 priv->vector_num = vector_num;
4804 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4805 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4806 GFP_KERNEL);
4807 if (!priv->tqp_vector) {
4808 ret = -ENOMEM;
4809 goto out;
4810 }
4811
4812 for (i = 0; i < priv->vector_num; i++) {
4813 tqp_vector = &priv->tqp_vector[i];
4814 tqp_vector->idx = i;
4815 tqp_vector->mask_addr = vector[i].io_addr;
4816 tqp_vector->vector_irq = vector[i].vector;
4817 hns3_vector_coalesce_init(tqp_vector, priv);
4818 }
4819
4820 out:
4821 devm_kfree(&pdev->dev, vector);
4822 return ret;
4823 }
4824
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4825 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4826 {
4827 group->ring = NULL;
4828 group->count = 0;
4829 }
4830
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4831 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4832 {
4833 struct hnae3_ring_chain_node *vector_ring_chain;
4834 struct hnae3_handle *h = priv->ae_handle;
4835 struct hns3_enet_tqp_vector *tqp_vector;
4836 int i;
4837
4838 for (i = 0; i < priv->vector_num; i++) {
4839 tqp_vector = &priv->tqp_vector[i];
4840
4841 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4842 continue;
4843
4844 /* Since the mapping can be overwritten, when fail to get the
4845 * chain between vector and ring, we should go on to deal with
4846 * the remaining options.
4847 */
4848 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4849 if (!vector_ring_chain)
4850 dev_warn(priv->dev, "failed to get ring chain\n");
4851
4852 h->ae_algo->ops->unmap_ring_from_vector(h,
4853 tqp_vector->vector_irq, vector_ring_chain);
4854
4855 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4856
4857 hns3_clear_ring_group(&tqp_vector->rx_group);
4858 hns3_clear_ring_group(&tqp_vector->tx_group);
4859 netif_napi_del(&priv->tqp_vector[i].napi);
4860 }
4861 }
4862
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4863 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4864 {
4865 struct hnae3_handle *h = priv->ae_handle;
4866 struct pci_dev *pdev = h->pdev;
4867 int i, ret;
4868
4869 for (i = 0; i < priv->vector_num; i++) {
4870 struct hns3_enet_tqp_vector *tqp_vector;
4871
4872 tqp_vector = &priv->tqp_vector[i];
4873 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4874 if (ret)
4875 return;
4876 }
4877
4878 devm_kfree(&pdev->dev, priv->tqp_vector);
4879 }
4880
hns3_update_tx_spare_buf_config(struct hns3_nic_priv * priv)4881 static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv)
4882 {
4883 #define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024)
4884 #define HNS3_MAX_PACKET_SIZE (64 * 1024)
4885
4886 struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev);
4887 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4888 struct hnae3_handle *handle = priv->ae_handle;
4889
4890 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
4891 return;
4892
4893 if (!(domain && iommu_is_dma_domain(domain)))
4894 return;
4895
4896 priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE;
4897 priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE;
4898
4899 if (priv->tx_copybreak < priv->min_tx_copybreak)
4900 priv->tx_copybreak = priv->min_tx_copybreak;
4901 if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size)
4902 handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size;
4903 }
4904
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4905 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4906 unsigned int ring_type)
4907 {
4908 int queue_num = priv->ae_handle->kinfo.num_tqps;
4909 struct hns3_enet_ring *ring;
4910 int desc_num;
4911
4912 if (ring_type == HNAE3_RING_TYPE_TX) {
4913 ring = &priv->ring[q->tqp_index];
4914 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4915 ring->queue_index = q->tqp_index;
4916 ring->tx_copybreak = priv->tx_copybreak;
4917 ring->last_to_use = 0;
4918 } else {
4919 ring = &priv->ring[q->tqp_index + queue_num];
4920 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4921 ring->queue_index = q->tqp_index;
4922 ring->rx_copybreak = priv->rx_copybreak;
4923 }
4924
4925 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4926
4927 ring->tqp = q;
4928 ring->desc = NULL;
4929 ring->desc_cb = NULL;
4930 ring->dev = priv->dev;
4931 ring->desc_dma_addr = 0;
4932 ring->buf_size = q->buf_size;
4933 ring->desc_num = desc_num;
4934 ring->next_to_use = 0;
4935 ring->next_to_clean = 0;
4936 }
4937
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4938 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4939 struct hns3_nic_priv *priv)
4940 {
4941 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4942 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4943 }
4944
hns3_get_ring_config(struct hns3_nic_priv * priv)4945 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4946 {
4947 struct hnae3_handle *h = priv->ae_handle;
4948 struct pci_dev *pdev = h->pdev;
4949 int i;
4950
4951 priv->ring = devm_kzalloc(&pdev->dev,
4952 array3_size(h->kinfo.num_tqps,
4953 sizeof(*priv->ring), 2),
4954 GFP_KERNEL);
4955 if (!priv->ring)
4956 return -ENOMEM;
4957
4958 for (i = 0; i < h->kinfo.num_tqps; i++)
4959 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4960
4961 return 0;
4962 }
4963
hns3_put_ring_config(struct hns3_nic_priv * priv)4964 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4965 {
4966 if (!priv->ring)
4967 return;
4968
4969 devm_kfree(priv->dev, priv->ring);
4970 priv->ring = NULL;
4971 }
4972
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4973 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4974 {
4975 struct page_pool_params pp_params = {
4976 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
4977 .order = hns3_page_order(ring),
4978 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4979 (PAGE_SIZE << hns3_page_order(ring)),
4980 .nid = dev_to_node(ring_to_dev(ring)),
4981 .dev = ring_to_dev(ring),
4982 .dma_dir = DMA_FROM_DEVICE,
4983 .offset = 0,
4984 .max_len = PAGE_SIZE << hns3_page_order(ring),
4985 };
4986
4987 ring->page_pool = page_pool_create(&pp_params);
4988 if (IS_ERR(ring->page_pool)) {
4989 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4990 PTR_ERR(ring->page_pool));
4991 ring->page_pool = NULL;
4992 }
4993 }
4994
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)4995 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4996 {
4997 int ret;
4998
4999 if (ring->desc_num <= 0 || ring->buf_size <= 0)
5000 return -EINVAL;
5001
5002 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
5003 sizeof(ring->desc_cb[0]), GFP_KERNEL);
5004 if (!ring->desc_cb) {
5005 ret = -ENOMEM;
5006 goto out;
5007 }
5008
5009 ret = hns3_alloc_desc(ring);
5010 if (ret)
5011 goto out_with_desc_cb;
5012
5013 if (!HNAE3_IS_TX_RING(ring)) {
5014 if (page_pool_enabled)
5015 hns3_alloc_page_pool(ring);
5016
5017 ret = hns3_alloc_ring_buffers(ring);
5018 if (ret)
5019 goto out_with_desc;
5020 } else {
5021 hns3_init_tx_spare_buffer(ring);
5022 }
5023
5024 return 0;
5025
5026 out_with_desc:
5027 hns3_free_desc(ring);
5028 out_with_desc_cb:
5029 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5030 ring->desc_cb = NULL;
5031 out:
5032 return ret;
5033 }
5034
hns3_fini_ring(struct hns3_enet_ring * ring)5035 void hns3_fini_ring(struct hns3_enet_ring *ring)
5036 {
5037 hns3_free_desc(ring);
5038 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5039 ring->desc_cb = NULL;
5040 ring->next_to_clean = 0;
5041 ring->next_to_use = 0;
5042 ring->last_to_use = 0;
5043 ring->pending_buf = 0;
5044 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5045 dev_kfree_skb_any(ring->skb);
5046 ring->skb = NULL;
5047 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5048 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5049
5050 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5051 DMA_TO_DEVICE);
5052 free_pages((unsigned long)tx_spare->buf,
5053 get_order(tx_spare->len));
5054 devm_kfree(ring_to_dev(ring), tx_spare);
5055 ring->tx_spare = NULL;
5056 }
5057
5058 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5059 page_pool_destroy(ring->page_pool);
5060 ring->page_pool = NULL;
5061 }
5062 }
5063
hns3_buf_size2type(u32 buf_size)5064 static int hns3_buf_size2type(u32 buf_size)
5065 {
5066 int bd_size_type;
5067
5068 switch (buf_size) {
5069 case 512:
5070 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5071 break;
5072 case 1024:
5073 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5074 break;
5075 case 2048:
5076 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5077 break;
5078 case 4096:
5079 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5080 break;
5081 default:
5082 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5083 }
5084
5085 return bd_size_type;
5086 }
5087
hns3_init_ring_hw(struct hns3_enet_ring * ring)5088 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5089 {
5090 dma_addr_t dma = ring->desc_dma_addr;
5091 struct hnae3_queue *q = ring->tqp;
5092
5093 if (!HNAE3_IS_TX_RING(ring)) {
5094 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5095 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5096 (u32)((dma >> 31) >> 1));
5097
5098 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5099 hns3_buf_size2type(ring->buf_size));
5100 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5101 ring->desc_num / 8 - 1);
5102 } else {
5103 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5104 (u32)dma);
5105 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5106 (u32)((dma >> 31) >> 1));
5107
5108 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5109 ring->desc_num / 8 - 1);
5110 }
5111 }
5112
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5113 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5114 {
5115 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5116 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5117 int i;
5118
5119 for (i = 0; i < tc_info->num_tc; i++) {
5120 int j;
5121
5122 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5123 struct hnae3_queue *q;
5124
5125 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5126 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5127 }
5128 }
5129 }
5130
hns3_init_all_ring(struct hns3_nic_priv * priv)5131 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5132 {
5133 struct hnae3_handle *h = priv->ae_handle;
5134 int ring_num = h->kinfo.num_tqps * 2;
5135 int i, j;
5136 int ret;
5137
5138 hns3_update_tx_spare_buf_config(priv);
5139 for (i = 0; i < ring_num; i++) {
5140 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5141 if (ret) {
5142 dev_err(priv->dev,
5143 "Alloc ring memory fail! ret=%d\n", ret);
5144 goto out_when_alloc_ring_memory;
5145 }
5146
5147 u64_stats_init(&priv->ring[i].syncp);
5148 cond_resched();
5149 }
5150
5151 return 0;
5152
5153 out_when_alloc_ring_memory:
5154 for (j = i - 1; j >= 0; j--)
5155 hns3_fini_ring(&priv->ring[j]);
5156
5157 return -ENOMEM;
5158 }
5159
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5160 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5161 {
5162 struct hnae3_handle *h = priv->ae_handle;
5163 int i;
5164
5165 for (i = 0; i < h->kinfo.num_tqps; i++) {
5166 hns3_fini_ring(&priv->ring[i]);
5167 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5168 }
5169 }
5170
5171 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5172 static int hns3_init_mac_addr(struct net_device *netdev)
5173 {
5174 struct hns3_nic_priv *priv = netdev_priv(netdev);
5175 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5176 struct hnae3_handle *h = priv->ae_handle;
5177 u8 mac_addr_temp[ETH_ALEN] = {0};
5178 int ret = 0;
5179
5180 if (h->ae_algo->ops->get_mac_addr)
5181 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5182
5183 /* Check if the MAC address is valid, if not get a random one */
5184 if (!is_valid_ether_addr(mac_addr_temp)) {
5185 eth_hw_addr_random(netdev);
5186 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5187 dev_warn(priv->dev, "using random MAC address %s\n",
5188 format_mac_addr);
5189 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5190 eth_hw_addr_set(netdev, mac_addr_temp);
5191 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5192 } else {
5193 return 0;
5194 }
5195
5196 if (h->ae_algo->ops->set_mac_addr)
5197 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5198
5199 return ret;
5200 }
5201
hns3_init_phy(struct net_device * netdev)5202 static int hns3_init_phy(struct net_device *netdev)
5203 {
5204 struct hnae3_handle *h = hns3_get_handle(netdev);
5205 int ret = 0;
5206
5207 if (h->ae_algo->ops->mac_connect_phy)
5208 ret = h->ae_algo->ops->mac_connect_phy(h);
5209
5210 return ret;
5211 }
5212
hns3_uninit_phy(struct net_device * netdev)5213 static void hns3_uninit_phy(struct net_device *netdev)
5214 {
5215 struct hnae3_handle *h = hns3_get_handle(netdev);
5216
5217 if (h->ae_algo->ops->mac_disconnect_phy)
5218 h->ae_algo->ops->mac_disconnect_phy(h);
5219 }
5220
hns3_client_start(struct hnae3_handle * handle)5221 static int hns3_client_start(struct hnae3_handle *handle)
5222 {
5223 if (!handle->ae_algo->ops->client_start)
5224 return 0;
5225
5226 return handle->ae_algo->ops->client_start(handle);
5227 }
5228
hns3_client_stop(struct hnae3_handle * handle)5229 static void hns3_client_stop(struct hnae3_handle *handle)
5230 {
5231 if (!handle->ae_algo->ops->client_stop)
5232 return;
5233
5234 handle->ae_algo->ops->client_stop(handle);
5235 }
5236
hns3_info_show(struct hns3_nic_priv * priv)5237 static void hns3_info_show(struct hns3_nic_priv *priv)
5238 {
5239 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5240 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5241
5242 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5243 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5244 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5245 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5246 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5247 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5248 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5249 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5250 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5251 kinfo->tc_info.num_tc);
5252 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5253 }
5254
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5255 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5256 enum dim_cq_period_mode mode, bool is_tx)
5257 {
5258 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
5259 struct hnae3_handle *handle = priv->ae_handle;
5260 int i;
5261
5262 if (is_tx) {
5263 priv->tx_cqe_mode = mode;
5264
5265 for (i = 0; i < priv->vector_num; i++)
5266 priv->tqp_vector[i].tx_group.dim.mode = mode;
5267 } else {
5268 priv->rx_cqe_mode = mode;
5269
5270 for (i = 0; i < priv->vector_num; i++)
5271 priv->tqp_vector[i].rx_group.dim.mode = mode;
5272 }
5273
5274 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5275 u32 new_mode;
5276 u64 reg;
5277
5278 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5279 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5280 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5281
5282 writel(new_mode, handle->kinfo.io_base + reg);
5283 }
5284 }
5285
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5286 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5287 enum dim_cq_period_mode tx_mode,
5288 enum dim_cq_period_mode rx_mode)
5289 {
5290 hns3_set_cq_period_mode(priv, tx_mode, true);
5291 hns3_set_cq_period_mode(priv, rx_mode, false);
5292 }
5293
hns3_state_init(struct hnae3_handle * handle)5294 static void hns3_state_init(struct hnae3_handle *handle)
5295 {
5296 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
5297 struct net_device *netdev = handle->kinfo.netdev;
5298 struct hns3_nic_priv *priv = netdev_priv(netdev);
5299
5300 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5301
5302 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5303 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5304
5305 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5306 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5307
5308 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5309 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5310
5311 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5312 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5313 }
5314
hns3_state_uninit(struct hnae3_handle * handle)5315 static void hns3_state_uninit(struct hnae3_handle *handle)
5316 {
5317 struct hns3_nic_priv *priv = handle->priv;
5318
5319 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5320 }
5321
hns3_client_init(struct hnae3_handle * handle)5322 static int hns3_client_init(struct hnae3_handle *handle)
5323 {
5324 struct pci_dev *pdev = handle->pdev;
5325 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5326 u16 alloc_tqps, max_rss_size;
5327 struct hns3_nic_priv *priv;
5328 struct net_device *netdev;
5329 int ret;
5330
5331 ae_dev->handle = handle;
5332
5333 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5334 &max_rss_size);
5335 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5336 if (!netdev)
5337 return -ENOMEM;
5338
5339 priv = netdev_priv(netdev);
5340 priv->dev = &pdev->dev;
5341 priv->netdev = netdev;
5342 priv->ae_handle = handle;
5343 priv->tx_timeout_count = 0;
5344 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5345 priv->min_tx_copybreak = 0;
5346 priv->min_tx_spare_buf_size = 0;
5347 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5348
5349 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5350
5351 handle->kinfo.netdev = netdev;
5352 handle->priv = (void *)priv;
5353
5354 hns3_init_mac_addr(netdev);
5355
5356 hns3_set_default_feature(netdev);
5357
5358 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5359 netdev->priv_flags |= IFF_UNICAST_FLT;
5360 netdev->netdev_ops = &hns3_nic_netdev_ops;
5361 SET_NETDEV_DEV(netdev, &pdev->dev);
5362 hns3_ethtool_set_ops(netdev);
5363
5364 /* Carrier off reporting is important to ethtool even BEFORE open */
5365 netif_carrier_off(netdev);
5366
5367 ret = hns3_get_ring_config(priv);
5368 if (ret) {
5369 ret = -ENOMEM;
5370 goto out_get_ring_cfg;
5371 }
5372
5373 hns3_nic_init_coal_cfg(priv);
5374
5375 ret = hns3_nic_alloc_vector_data(priv);
5376 if (ret) {
5377 ret = -ENOMEM;
5378 goto out_alloc_vector_data;
5379 }
5380
5381 ret = hns3_nic_init_vector_data(priv);
5382 if (ret) {
5383 ret = -ENOMEM;
5384 goto out_init_vector_data;
5385 }
5386
5387 ret = hns3_init_all_ring(priv);
5388 if (ret) {
5389 ret = -ENOMEM;
5390 goto out_init_ring;
5391 }
5392
5393 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5394 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5395
5396 ret = hns3_init_phy(netdev);
5397 if (ret)
5398 goto out_init_phy;
5399
5400 /* the device can work without cpu rmap, only aRFS needs it */
5401 ret = hns3_set_rx_cpu_rmap(netdev);
5402 if (ret)
5403 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5404
5405 ret = hns3_nic_init_irq(priv);
5406 if (ret) {
5407 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5408 hns3_free_rx_cpu_rmap(netdev);
5409 goto out_init_irq_fail;
5410 }
5411
5412 ret = hns3_client_start(handle);
5413 if (ret) {
5414 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5415 goto out_client_start;
5416 }
5417
5418 hns3_dcbnl_setup(handle);
5419
5420 ret = hns3_dbg_init(handle);
5421 if (ret) {
5422 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5423 ret);
5424 goto out_client_start;
5425 }
5426
5427 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5428
5429 hns3_state_init(handle);
5430
5431 ret = register_netdev(netdev);
5432 if (ret) {
5433 dev_err(priv->dev, "probe register netdev fail!\n");
5434 goto out_reg_netdev_fail;
5435 }
5436
5437 if (netif_msg_drv(handle))
5438 hns3_info_show(priv);
5439
5440 return ret;
5441
5442 out_reg_netdev_fail:
5443 hns3_state_uninit(handle);
5444 hns3_dbg_uninit(handle);
5445 hns3_client_stop(handle);
5446 out_client_start:
5447 hns3_free_rx_cpu_rmap(netdev);
5448 hns3_nic_uninit_irq(priv);
5449 out_init_irq_fail:
5450 hns3_uninit_phy(netdev);
5451 out_init_phy:
5452 hns3_uninit_all_ring(priv);
5453 out_init_ring:
5454 hns3_nic_uninit_vector_data(priv);
5455 out_init_vector_data:
5456 hns3_nic_dealloc_vector_data(priv);
5457 out_alloc_vector_data:
5458 priv->ring = NULL;
5459 out_get_ring_cfg:
5460 priv->ae_handle = NULL;
5461 free_netdev(netdev);
5462 return ret;
5463 }
5464
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5465 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5466 {
5467 struct net_device *netdev = handle->kinfo.netdev;
5468 struct hns3_nic_priv *priv = netdev_priv(netdev);
5469
5470 if (netdev->reg_state != NETREG_UNINITIALIZED)
5471 unregister_netdev(netdev);
5472
5473 hns3_client_stop(handle);
5474
5475 hns3_uninit_phy(netdev);
5476
5477 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5478 netdev_warn(netdev, "already uninitialized\n");
5479 goto out_netdev_free;
5480 }
5481
5482 hns3_free_rx_cpu_rmap(netdev);
5483
5484 hns3_nic_uninit_irq(priv);
5485
5486 hns3_clear_all_ring(handle, true);
5487
5488 hns3_nic_uninit_vector_data(priv);
5489
5490 hns3_nic_dealloc_vector_data(priv);
5491
5492 hns3_uninit_all_ring(priv);
5493
5494 hns3_put_ring_config(priv);
5495
5496 out_netdev_free:
5497 hns3_dbg_uninit(handle);
5498 free_netdev(netdev);
5499 }
5500
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5501 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5502 {
5503 struct net_device *netdev = handle->kinfo.netdev;
5504
5505 if (!netdev)
5506 return;
5507
5508 if (linkup) {
5509 netif_tx_wake_all_queues(netdev);
5510 netif_carrier_on(netdev);
5511 if (netif_msg_link(handle))
5512 netdev_info(netdev, "link up\n");
5513 } else {
5514 netif_carrier_off(netdev);
5515 netif_tx_stop_all_queues(netdev);
5516 if (netif_msg_link(handle))
5517 netdev_info(netdev, "link down\n");
5518 }
5519 }
5520
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5521 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5522 {
5523 while (ring->next_to_clean != ring->next_to_use) {
5524 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5525 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5526 ring_ptr_move_fw(ring, next_to_clean);
5527 }
5528
5529 ring->pending_buf = 0;
5530 }
5531
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5532 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5533 {
5534 struct hns3_desc_cb res_cbs;
5535 int ret;
5536
5537 while (ring->next_to_use != ring->next_to_clean) {
5538 /* When a buffer is not reused, it's memory has been
5539 * freed in hns3_handle_rx_bd or will be freed by
5540 * stack, so we need to replace the buffer here.
5541 */
5542 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5543 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5544 if (ret) {
5545 hns3_ring_stats_update(ring, sw_err_cnt);
5546 /* if alloc new buffer fail, exit directly
5547 * and reclear in up flow.
5548 */
5549 netdev_warn(ring_to_netdev(ring),
5550 "reserve buffer map failed, ret = %d\n",
5551 ret);
5552 return ret;
5553 }
5554 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5555 }
5556 ring_ptr_move_fw(ring, next_to_use);
5557 }
5558
5559 /* Free the pending skb in rx ring */
5560 if (ring->skb) {
5561 dev_kfree_skb_any(ring->skb);
5562 ring->skb = NULL;
5563 ring->pending_buf = 0;
5564 }
5565
5566 return 0;
5567 }
5568
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5569 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5570 {
5571 while (ring->next_to_use != ring->next_to_clean) {
5572 /* When a buffer is not reused, it's memory has been
5573 * freed in hns3_handle_rx_bd or will be freed by
5574 * stack, so only need to unmap the buffer here.
5575 */
5576 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5577 hns3_unmap_buffer(ring,
5578 &ring->desc_cb[ring->next_to_use]);
5579 ring->desc_cb[ring->next_to_use].dma = 0;
5580 }
5581
5582 ring_ptr_move_fw(ring, next_to_use);
5583 }
5584 }
5585
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5586 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5587 {
5588 struct net_device *ndev = h->kinfo.netdev;
5589 struct hns3_nic_priv *priv = netdev_priv(ndev);
5590 u32 i;
5591
5592 for (i = 0; i < h->kinfo.num_tqps; i++) {
5593 struct hns3_enet_ring *ring;
5594
5595 ring = &priv->ring[i];
5596 hns3_clear_tx_ring(ring);
5597
5598 ring = &priv->ring[i + h->kinfo.num_tqps];
5599 /* Continue to clear other rings even if clearing some
5600 * rings failed.
5601 */
5602 if (force)
5603 hns3_force_clear_rx_ring(ring);
5604 else
5605 hns3_clear_rx_ring(ring);
5606 }
5607 }
5608
hns3_nic_reset_all_ring(struct hnae3_handle * h)5609 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5610 {
5611 struct net_device *ndev = h->kinfo.netdev;
5612 struct hns3_nic_priv *priv = netdev_priv(ndev);
5613 struct hns3_enet_ring *rx_ring;
5614 int i, j;
5615 int ret;
5616
5617 ret = h->ae_algo->ops->reset_queue(h);
5618 if (ret)
5619 return ret;
5620
5621 for (i = 0; i < h->kinfo.num_tqps; i++) {
5622 hns3_init_ring_hw(&priv->ring[i]);
5623
5624 /* We need to clear tx ring here because self test will
5625 * use the ring and will not run down before up
5626 */
5627 hns3_clear_tx_ring(&priv->ring[i]);
5628 priv->ring[i].next_to_clean = 0;
5629 priv->ring[i].next_to_use = 0;
5630 priv->ring[i].last_to_use = 0;
5631
5632 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5633 hns3_init_ring_hw(rx_ring);
5634 ret = hns3_clear_rx_ring(rx_ring);
5635 if (ret)
5636 return ret;
5637
5638 /* We can not know the hardware head and tail when this
5639 * function is called in reset flow, so we reuse all desc.
5640 */
5641 for (j = 0; j < rx_ring->desc_num; j++)
5642 hns3_reuse_buffer(rx_ring, j);
5643
5644 rx_ring->next_to_clean = 0;
5645 rx_ring->next_to_use = 0;
5646 }
5647
5648 hns3_init_tx_ring_tc(priv);
5649
5650 return 0;
5651 }
5652
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5653 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5654 {
5655 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5656 struct net_device *ndev = kinfo->netdev;
5657 struct hns3_nic_priv *priv = netdev_priv(ndev);
5658
5659 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5660 return 0;
5661
5662 if (!netif_running(ndev))
5663 return 0;
5664
5665 return hns3_nic_net_stop(ndev);
5666 }
5667
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5668 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5669 {
5670 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5671 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5672 int ret = 0;
5673
5674 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5675 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5676 return -EFAULT;
5677 }
5678
5679 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5680
5681 if (netif_running(kinfo->netdev)) {
5682 ret = hns3_nic_net_open(kinfo->netdev);
5683 if (ret) {
5684 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5685 netdev_err(kinfo->netdev,
5686 "net up fail, ret=%d!\n", ret);
5687 return ret;
5688 }
5689 }
5690
5691 return ret;
5692 }
5693
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5694 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5695 {
5696 struct net_device *netdev = handle->kinfo.netdev;
5697 struct hns3_nic_priv *priv = netdev_priv(netdev);
5698 int ret;
5699
5700 /* Carrier off reporting is important to ethtool even BEFORE open */
5701 netif_carrier_off(netdev);
5702
5703 ret = hns3_get_ring_config(priv);
5704 if (ret)
5705 return ret;
5706
5707 ret = hns3_nic_alloc_vector_data(priv);
5708 if (ret)
5709 goto err_put_ring;
5710
5711 ret = hns3_nic_init_vector_data(priv);
5712 if (ret)
5713 goto err_dealloc_vector;
5714
5715 ret = hns3_init_all_ring(priv);
5716 if (ret)
5717 goto err_uninit_vector;
5718
5719 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5720
5721 /* the device can work without cpu rmap, only aRFS needs it */
5722 ret = hns3_set_rx_cpu_rmap(netdev);
5723 if (ret)
5724 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5725
5726 ret = hns3_nic_init_irq(priv);
5727 if (ret) {
5728 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5729 hns3_free_rx_cpu_rmap(netdev);
5730 goto err_init_irq_fail;
5731 }
5732
5733 if (!hns3_is_phys_func(handle->pdev))
5734 hns3_init_mac_addr(netdev);
5735
5736 ret = hns3_client_start(handle);
5737 if (ret) {
5738 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5739 goto err_client_start_fail;
5740 }
5741
5742 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5743
5744 return ret;
5745
5746 err_client_start_fail:
5747 hns3_free_rx_cpu_rmap(netdev);
5748 hns3_nic_uninit_irq(priv);
5749 err_init_irq_fail:
5750 hns3_uninit_all_ring(priv);
5751 err_uninit_vector:
5752 hns3_nic_uninit_vector_data(priv);
5753 err_dealloc_vector:
5754 hns3_nic_dealloc_vector_data(priv);
5755 err_put_ring:
5756 hns3_put_ring_config(priv);
5757
5758 return ret;
5759 }
5760
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5761 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5762 {
5763 struct net_device *netdev = handle->kinfo.netdev;
5764 struct hns3_nic_priv *priv = netdev_priv(netdev);
5765
5766 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5767 hns3_nic_net_stop(netdev);
5768
5769 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5770 netdev_warn(netdev, "already uninitialized\n");
5771 return 0;
5772 }
5773
5774 hns3_free_rx_cpu_rmap(netdev);
5775 hns3_nic_uninit_irq(priv);
5776 hns3_clear_all_ring(handle, true);
5777 hns3_reset_tx_queue(priv->ae_handle);
5778
5779 hns3_nic_uninit_vector_data(priv);
5780
5781 hns3_nic_dealloc_vector_data(priv);
5782
5783 hns3_uninit_all_ring(priv);
5784
5785 hns3_put_ring_config(priv);
5786
5787 return 0;
5788 }
5789
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5790 int hns3_reset_notify(struct hnae3_handle *handle,
5791 enum hnae3_reset_notify_type type)
5792 {
5793 int ret = 0;
5794
5795 switch (type) {
5796 case HNAE3_UP_CLIENT:
5797 ret = hns3_reset_notify_up_enet(handle);
5798 break;
5799 case HNAE3_DOWN_CLIENT:
5800 ret = hns3_reset_notify_down_enet(handle);
5801 break;
5802 case HNAE3_INIT_CLIENT:
5803 ret = hns3_reset_notify_init_enet(handle);
5804 break;
5805 case HNAE3_UNINIT_CLIENT:
5806 ret = hns3_reset_notify_uninit_enet(handle);
5807 break;
5808 default:
5809 break;
5810 }
5811
5812 return ret;
5813 }
5814
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5815 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5816 bool rxfh_configured)
5817 {
5818 int ret;
5819
5820 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5821 rxfh_configured);
5822 if (ret) {
5823 dev_err(&handle->pdev->dev,
5824 "Change tqp num(%u) fail.\n", new_tqp_num);
5825 return ret;
5826 }
5827
5828 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5829 if (ret)
5830 return ret;
5831
5832 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5833 if (ret)
5834 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5835
5836 return ret;
5837 }
5838
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5839 int hns3_set_channels(struct net_device *netdev,
5840 struct ethtool_channels *ch)
5841 {
5842 struct hnae3_handle *h = hns3_get_handle(netdev);
5843 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5844 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5845 u32 new_tqp_num = ch->combined_count;
5846 u16 org_tqp_num;
5847 int ret;
5848
5849 if (hns3_nic_resetting(netdev))
5850 return -EBUSY;
5851
5852 if (ch->rx_count || ch->tx_count)
5853 return -EINVAL;
5854
5855 if (kinfo->tc_info.mqprio_active) {
5856 dev_err(&netdev->dev,
5857 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5858 return -EINVAL;
5859 }
5860
5861 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5862 new_tqp_num < 1) {
5863 dev_err(&netdev->dev,
5864 "Change tqps fail, the tqp range is from 1 to %u",
5865 hns3_get_max_available_channels(h));
5866 return -EINVAL;
5867 }
5868
5869 if (kinfo->rss_size == new_tqp_num)
5870 return 0;
5871
5872 netif_dbg(h, drv, netdev,
5873 "set channels: tqp_num=%u, rxfh=%d\n",
5874 new_tqp_num, rxfh_configured);
5875
5876 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5877 if (ret)
5878 return ret;
5879
5880 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5881 if (ret)
5882 return ret;
5883
5884 org_tqp_num = h->kinfo.num_tqps;
5885 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5886 if (ret) {
5887 int ret1;
5888
5889 netdev_warn(netdev,
5890 "Change channels fail, revert to old value\n");
5891 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5892 if (ret1) {
5893 netdev_err(netdev,
5894 "revert to old channel fail\n");
5895 return ret1;
5896 }
5897
5898 return ret;
5899 }
5900
5901 return 0;
5902 }
5903
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5904 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5905 {
5906 struct hns3_nic_priv *priv = netdev_priv(ndev);
5907
5908 if (!if_running)
5909 return;
5910
5911 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5912 return;
5913
5914 netif_carrier_off(ndev);
5915 netif_tx_disable(ndev);
5916
5917 hns3_disable_irqs_and_tqps(ndev);
5918
5919 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5920 * during reset process, because driver may not be able
5921 * to disable the ring through firmware when downing the netdev.
5922 */
5923 if (!hns3_nic_resetting(ndev))
5924 hns3_nic_reset_all_ring(priv->ae_handle);
5925
5926 hns3_reset_tx_queue(priv->ae_handle);
5927 }
5928
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5929 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5930 {
5931 struct hns3_nic_priv *priv = netdev_priv(ndev);
5932 struct hnae3_handle *h = priv->ae_handle;
5933
5934 if (!if_running)
5935 return;
5936
5937 if (hns3_nic_resetting(ndev))
5938 return;
5939
5940 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5941 return;
5942
5943 if (hns3_nic_reset_all_ring(priv->ae_handle))
5944 return;
5945
5946 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5947
5948 hns3_enable_irqs_and_tqps(ndev);
5949
5950 netif_tx_wake_all_queues(ndev);
5951
5952 if (h->ae_algo->ops->get_status(h))
5953 netif_carrier_on(ndev);
5954 }
5955
5956 static const struct hns3_hw_error_info hns3_hw_err[] = {
5957 { .type = HNAE3_PPU_POISON_ERROR,
5958 .msg = "PPU poison" },
5959 { .type = HNAE3_CMDQ_ECC_ERROR,
5960 .msg = "IMP CMDQ error" },
5961 { .type = HNAE3_IMP_RD_POISON_ERROR,
5962 .msg = "IMP RD poison" },
5963 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5964 .msg = "ROCEE AXI RESP error" },
5965 };
5966
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5967 static void hns3_process_hw_error(struct hnae3_handle *handle,
5968 enum hnae3_hw_error_type type)
5969 {
5970 u32 i;
5971
5972 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5973 if (hns3_hw_err[i].type == type) {
5974 dev_err(&handle->pdev->dev, "Detected %s!\n",
5975 hns3_hw_err[i].msg);
5976 break;
5977 }
5978 }
5979 }
5980
5981 static const struct hnae3_client_ops client_ops = {
5982 .init_instance = hns3_client_init,
5983 .uninit_instance = hns3_client_uninit,
5984 .link_status_change = hns3_link_status_change,
5985 .reset_notify = hns3_reset_notify,
5986 .process_hw_error = hns3_process_hw_error,
5987 };
5988
5989 /* hns3_init_module - Driver registration routine
5990 * hns3_init_module is the first routine called when the driver is
5991 * loaded. All it does is register with the PCI subsystem.
5992 */
hns3_init_module(void)5993 static int __init hns3_init_module(void)
5994 {
5995 int ret;
5996
5997 pr_debug("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5998 pr_debug("%s: %s\n", hns3_driver_name, hns3_copyright);
5999
6000 client.type = HNAE3_CLIENT_KNIC;
6001 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
6002 hns3_driver_name);
6003
6004 client.ops = &client_ops;
6005
6006 INIT_LIST_HEAD(&client.node);
6007
6008 hns3_dbg_register_debugfs(hns3_driver_name);
6009
6010 ret = hnae3_register_client(&client);
6011 if (ret)
6012 goto err_reg_client;
6013
6014 ret = pci_register_driver(&hns3_driver);
6015 if (ret)
6016 goto err_reg_driver;
6017
6018 return ret;
6019
6020 err_reg_driver:
6021 hnae3_unregister_client(&client);
6022 err_reg_client:
6023 hns3_dbg_unregister_debugfs();
6024 return ret;
6025 }
6026 module_init(hns3_init_module);
6027
6028 /* hns3_exit_module - Driver exit cleanup routine
6029 * hns3_exit_module is called just before the driver is removed
6030 * from memory.
6031 */
hns3_exit_module(void)6032 static void __exit hns3_exit_module(void)
6033 {
6034 hnae3_acquire_unload_lock();
6035 pci_unregister_driver(&hns3_driver);
6036 hnae3_unregister_client(&client);
6037 hns3_dbg_unregister_debugfs();
6038 hnae3_release_unload_lock();
6039 }
6040 module_exit(hns3_exit_module);
6041
6042 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6043 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6044 MODULE_LICENSE("GPL");
6045 MODULE_ALIAS("pci:hns-nic");
6046